R8A66173SP

R8A66173SP 4-CH 12-BIT PWM GENERATOR REJ03F0264-0100 Rev.1.00 Jan.24.2008 DESCRIPTION R8A66173 has four 12-bit PWM (Pulse Width Modulation) circuits which are built by using the CMOS process. This IC controls PWM waveform by adjusting the “H” width according to serial data sent from MCU (Micro Controller Unit) or other device. Each channel can be independently controlled. High-resolution digital-analog (D-A) converter can be formed easily by connecting a low-pass filter (LPF) circuit to the output pins of this circuit. R8A66173 is the succession product of M66242. FEATURES ● Built-in four 12-bit high-resolution PWM circuits ● Easy D-A conversion – Quick output waveform smoothing Control by 1.22mV possible per step (VCC=5V range) ● Serial data input ●“H” level width setting type ● 4 channels controlled independently ● All 4 channels reset by reset input (R), High-impedance status after reset ● All 4 channels controlled by output control input (OC) ● Settings take effect after ongoing cycle is completed ● Output : CMOS 3-state output Output current Io=±4mA (Vcc=5.0V range), Io=±2mA (Vcc=3.3V range) ● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V, single power supply) ● Wide operating temperature range: Ta=-40oC~+85 oC APPLICATION ● Analog signal control in televisions and audio systems ● Control of lamps, heaters and motors ● For software servo in home appliances and industrial machinery PIN CONFIGURATION (TOP VIEW) CHIP SELECT RESET WRITE CONTROL SERIAL DATA INPUT WRITE CLOCK OUTPUT CONTROL CS R WR SIN Sc LK OC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc PWM1 PWM2 OUTPUT PWM3 PWM4 XOUT XIN CLOCK OUTPUT CLOCK INPUT REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 1 of 12 R8A66173SP BLOCK DIAGRAM (EACH CHANNEL) 14 Vcc Upper byte register SIN SCLK 4 5 8-bit PWM circuit PWM register 12-bit PWM circuit 4-bit-rate multiplier 13 Input register PWM1 Low er byte register CS WR R OC 1 3 2 6 12 11 PWM2 PWM3 PWM4 Control circuit 1/2 divider To other channels 10 Oscillation circuit 8 9 7 XIN XOUT GND FUNCTION The PWM output waveform of each channel is controlled by taking in PWM data from MCU or other device via serial data input SIN. 12-bit PWM data is input being divided between upper 8-bits (upper byte) and lower 4-bits. The lower 4-bit data is combined with command data such as channel designation and input as 8-bit data (lower byte). The lower byte should be written first, and then the upper byte. Even if only the upper byte is to be changed, rewrite from the lower byte. The PWM waveform changes according to the new setting from the next cycle. One cycle of PWM waveform (=4096 divisions; 12-bit resolution) are divided into 16 (24) subsections t. Each subsection consists of 256 (=28; 8-bit resolution) minimum bits τ(=2/fXIN**). One subsection t consists of an 8-bit PWM waveform (basic waveform). The “H” width of this waveform is determined according to the upper 8-bits of PWM data. One cycle has 16 subsections t, each of which has this basic waveform. Among them, those which are designated by the 4-bit-rate multiplier are conditioned to have a “H” width that is longer by τ. The lower 4-bits of PWM data are used to specify those subsections (tm). The waveform of other subsections remains unchanged. The PWM waveform (12-bit resolution) is a combination of two types of waveforms which are different in “H” width, as described above. When output control input OC is “H”, the output of every 4-channel turns high-impedance from the next cycle. When reset input R is “L”, the output of every channel turns high-impedance as soon as the ongoing cycle is completed, and PWM data of all channels is reset. If R input is changed from “L” to “H”, the next cycle starts, however, the output of the channels remains high-impedance. To enable output, rewrite input data for each channel. **)fXIN: Clock XIN repeat frequency REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 2 of 12 R8A66173SP PIN DESCRIPTIONS Pin R CS WR SIN SCLK Name Reset input Chip select input Write control input Serial data input Write clock input Input/Output Functions Input "L" : All 4-channels put in high-impedance state. Input Input Input Input Input Output "L" : Communication with MCU becomes possible. WR, SIN and SCLK put in enable state. "L": Serial data written. "L"-to-"H" edge: Written data stored in upper or lower byte register. Inputs 8-bit serial data from MCU synchronously with SCLK clock. Inputs sync clock pulses for 8-bit serial data writing. "H": All 4-channels put in high-impedance state. Outputs PWM waveform. (CMOS 3-state output) Input/output signals generated by clock signal generation circuit. Oscillation frequency is determined by connecting ceramic or quartz resonator between XIN and XOUT. The frequency of internal clock (PWM timing clock) signals is the 1/2 divider of the frequency input from clock input XIN. When external clock signals are used, connect clock generator to XIN pin and leave XOUT open. OC Output control input PWM1∼ PWM4 PWM outputs 1∼4 XIN Clock input Input XOUT Clock output Output (1) Upper byte register b7 b6 b5 b4 b3 b2 b1 b0 PWM output "H" w idth setting bits (Upper 8 bits ： b11∼b4) (2) Lower byte register b7 b6 b5 b4 b3 b2 b1 b0 Write data designation bit 0 : Low er byte only 1 : Both low er and upper bytes PWM output select bits 00 : PWM1 01 : PWM2 10 : PWM3 11 : PWM4 Output control select bit 0 : Output disable   (b7∼b4 and b0 are ignored.) 1 : Output enable PWM output "H" w idth setting bits (Low er 4 bits ： b3∼b0) Fig. 1 Upper and Lower Byte Register Makeup Table 1 Mode Selection Mode PWM data setting (output enable) Output disable Lower 4-bit data setting 12-bit data setting b7 b7 X b6 b6 X Input serial data Lower byte data b5 b4 1 b2 b5 b4 1 b2 XX 0 b2 Upper byte data b1 b1 b1 0 1 X − b7 b6 b5 b4 − b3 b2 b1 b0 REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 3 of 12 R8A66173SP Table 2 Patterns of Lower 4-bits and Subsections whose "H" Width is increased PWM register b3∼b0 0000 0001 0010 0100 1000 1111 Subsection tm whose H width is increased by τ ( m = 0∼15) Nothing m=8 m = 4, 12 m = 2, 6, 10, 14 m = 1, 3, 5, 7, 9, 11, 13, 15 m = 1∼15 (m≠0) Number of Subsections 0 1 2 4 8 15 Upper byte register b7 0 1 0 0 1 0 1 b0 0 Low er byte register b7 0 1 1 0 ? ? ? b0 ? PWM register b11 4A616 0 1 0 0 1 0 1 b4 0 b3 0 1 1 b0 0 Determines "H" w idth of basic w aveform (In this case, "H" w idth is 4A 16=74) Determines subsections tm w hose "H" w idth is increased by the minimum bit w idth of τ ( Refer to Table 2.) (In this case, m=2, 4, 6, 10, 12 and 14.) τ Basic w aveform τ ×74 τ ×74 τ= f XIN    (Exp. When f XIN is 4MHz. τ =0.5µs)  2 One subsection t=τ ×256 (8-bit resolution) Output w aveform τ ×74 τ τ ×74 Designated subsection tm (In this case, m=2, 4, 6, 10, 12 and 14.) τ ×75 t0 ∼ t4 Subsection t5 t6 t7 t8 t9 t10 t11 t12 t13 ∼ t15 One cycle Fig.2 PWM Waveform Output Example (Input data:4A616) OPERATION Serial Data Input When chip select CS is “L” and write control input WR is ”L”, data input to SIN at the edge where write clock input SCLK status shifts from “L” to “H” is written.(See Fig.3.) At the edge where WR rises from “L” to “H”, the latest 8-bit data writing is completed, and input data is stored in lower (or upper) byte register .When writing on the lower byte or writing on both upper and lower bytes is completed, data on the lower byte register or, in the latter case, data on both lower and upper byte registers is written on the PWM register of the channel designated by lower bytes b2 and b1. All setting process ends with this writing, and PWM waveform changes according to the setting from the next cycle. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 4 of 12 R8A66173SP PWM Waveform Output (1)12-bit PWM output One PWM waveform cycle is divided into 16(=24) subsections t, and each subsection is further divided into 256(=28) minimum resolution bits τ(=2/fXIN). The “H” width of subsection t basic waveform is determined by the upper 8-bits of PWM data. (In Fig.2 above, ”H” width is 4A16=74×τ) Among these 16 subsections t, subsections tm designated by the lower 4-bits of PWM data have “H” width that is longer by τ. (In Fig.2 above, the “H” width of designated 6 subsections (m =2, 4, 6, 10, 12 and 14) is 4B16=75×τ.) The “H” width of undesignated subsections remains unchanged. As explained above, one cycle of waveform is a combination of two waveforms different in the “H” width. (In Fig. 2 above, one cycle consists of 10 subsections whose “H” width is 74×τ and 6 subsections whose “H” width is 75×τ) Note: It is impossible to set one whole cycle to “H” level. (2)8-bit PWM output As can be seen from the 12-bit PWM waveform output process as described above, 8-bit resolution PWM waveform can be output by fixing the lower 4-bits of PWM data to 00002. All subsections from t0 to t15 have the “H” width as determined by the upper 8-bits of PWM data. Note: It is impossible to set one whole cycle to “H” level. Output Control (1)Serial data input By using data on lower byte register b3 (output control selection bit), output of each channel can be controlled independently. The state of the selected PWM output changes after the completion of the ongoing cycle. When b3 is set 0, lower byte register b0 (write data designation bit) is reset. Do not write on upper byte in this case. (2)Output control input The status of all 4-channel outputs during a cycle is determined depending on the status of output control input OC at the start of the cycle. (See Fig. 6.) Even when output is in a high-impedance state, data on each PWM register is retained, and data can be rewritten. (3)Reset When reset input R turns “L”, all operation is reset as soon as the ongoing cycle is completed. The outputs of all 4-channels turn high-impedance. The PWM register of each channel is reset. When R is shifted from “L” to “H”, a next cycle starts, and data writing becomes possible. However, outputs stay in the high-impedance state. (See Fig. 6) To resume output, write input data for each channel. Initial State After power-on, outputs and PWM register data are unstable. (1)Reset Reset input R is kept on “L” level for more than one cycle (2.048ms when fXIN is 4 MHz) or more, this integrated circuit is put in a reset state. If stabilization needs more time, e.g. when a quartz resonator is used, keep R on “L” level for an adequate period of time. (2)Serial data input When starting using this integrated circuit without resetting, input false lower byte data (b0=0) to stabilize lower byte register b0 data, and then input normal data. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 5 of 12 R8A66173SP WR SIN b0 b1 b2 b3 b4 b5 b6 b7 SCLK PWM output Ongoing cycle Next cycle Fig.3 Serial Data Write Timing PWM Setting Data 000 16 τ 001 16 τ 002 16 τ 003 16 τ τ τ τ 00E 16 00F 16 τ 010 16 τ 011 16 τ 012 16 τ 013 16 τ×150 963 16 τ×255 FFD 16 τ FFE 16 τ FFF 16 τ t0 ∼ τ τ×150 t4 t5 t6 t7 t8 1 cycle T= t9 t10 t11 t12 t13 ∼ t15   2 ×212 fXIN Fig.4 12-bit PWM Waveform Output Example REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 6 of 12 R8A66173SP PWM Setting Data 00016 τ 01016 τ×2 02016 τ×2 τ×2 τ×2 τ×2 τ×2 τ×2 τ τ τ τ τ τ τ×254 FE016 τ×255 FF016 t0 τ×254 τ×254 τ×254 τ×254 τ×254 τ×254 τ×255 τ×255 τ×255 τ×255 τ×255 τ×255 t1 t2 t3 1 cycle t13 t14 t15 Fig.5 8-bit PWM Waveform Output Example R OC CS WR SIN DATA internal signal "Φ" (cycle start signal) PWM output High-impedance 1 cycle High-impedance Fig.6 Output Control Timing Chart REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 7 of 12 R8A66173SP Start Reset R="L" Set low er byte WR="L" 1 Set upper byte b0=? A 0 WR="L" NO Setting complete? YES Output enable OC="L", or low er byte b3=1 PWM output Change setting? NO Stop YES Repeat A Fig.7 PWM Setting Flow Chart REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 8 of 12 R8A66173SP ABSOLUTE MAXIMUM RATINGS (Ta= -40 C~85 C unless otherwise noted) Symbol Vcc VI VO IO Icc Pd Tstg Parameter Supply voltage Input voltage Output voltage Output current Supply/GND current Power dissipation Storage temperature Vcc, GND Conditions Ratings -0.5 ~ +7.0 -0.5 ~ Vcc+0.5 -0.5 ~ Vcc+0.5 ±15 ±40 150 -65 ~ 150 Unit V V V mA mA mW o o o C RECOMMENDED OPERATING CONDITIONS (Ta=-40 C ~ 85 C unless otherwise noted) Symbol Vcc GND VI VO Topr Supply voltage Supply voltage Input voltage Output voltage Operating temperature range 0 0 -40 Parameter 5.0V support 3.3V support Limits Min. 4.5 3.0 Typ. 5.0 3.3 0 Vcc Vcc 85 Max. 5.5 3.6 Unit V V V V V o o o C ELECTRICAL CHARACTERISTICS ■5.0V version support specifications (Ta=-40 Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC Parameter “H” input voltage “L” input voltage “H” output voltage “L” output voltage “H” input current “L” input current Off-state “H” output current Off-state “L” output current Quiescent supply current XIN Other input XIN Other input PWM1~4 PWM1~4 IOH=-4mA IOL=4mA VI=Vcc VI=GND VO=Vcc VO=GND VI=Vcc, GND, Output open o o C ~ 85 oC, Vcc=4.5V ~ 5.5V, unless otherwise noted) Limits Min. 0.8Vcc 0.75Vcc 0.2Vcc 0.25Vcc Vcc-0.5 0.5 1.0 -1.0 5.0 -5.0 40 Typ. Max. V V V V V V µA µA µA µA µA Unit Test conditions ■3.3V version support specifications (Ta=-40 Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC Parameter “H” input voltage “L” input voltage “H” output voltage “L” output voltage “H” input current “L” input current Off-state “H” output current Off-state “L” output current Quiescent supply current XIN Other input XIN Other input PWM1~4 PWM1~4 C ~ 85 oC, Vcc=3.0V ~ 3.6V, unless otherwise noted) Limits Min. 0.8Vcc 0.75Vcc 0.2Vcc 0.25Vcc Typ. Max. V V V V V 0.5 1.0 -1.0 5.0 -5.0 40 V µA µA µA µA µA Unit Test conditions IOH=-2mA IOL=2mA VI=Vcc VI=GND VO=Vcc VO=GND VI=Vcc, GND, Output open Vcc-0.5 REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 9 of 12 R8A66173SP SWITCHING CHARACTERISTICS (Ta=-40 oC ~ 85 oC, Vcc=5.0V±0.5V or 3.3V±0.3V, unless otherwise noted) Symbol fmax tPLH tPHL Parameter Maximum clock frequency Output "L-H", "H-L" propagation time XIN XIN-PWM1~4 CL=50pF (Note 1) Test conditions 5.0V specification Min. Typ. Max. 16 100 100 3.3V specification Min. Typ. Max. 12.5 100 100 MHz ns ns Unit TIMING REQUIREMENTS (Ta=-40 C ~ 85 C, Vcc=5.0V±0.5V or 3.3V±0.3V, unless otherwise noted) Symbol tc(X) tw(XH) tw(XL) tw(S) twRH tsu(CS) tsu(WR) tsu(S) th(CS) th(WR) th(S) th(SCLK) tr tf Parameter XIN cycle time XIN “H” pulse width XIN “L” pulse width SCLK pulse width WR “H” hold time CS "L" setup time before WR WR "L" setup time before SCLK SIN setup time before SCLK CS "L" hold time after WR WR "L" hold time after SCLK SIN hold time after SCLK SCLK hold time after WR Input rise time Input fall time Test conditions 5.0V specification Min. 62.5 32.5 30 30 6tc(x) 30 30 50 30 10 10 30 25 25 Typ. Max. 3.3V specification Min. 80 40 40 40 6tc(x) 40 40 60 40 20 20 40 25 25 Typ. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit o o Note 1. Test Circuit INPUT Vcc OUTPUT P.G. 50Ω DUT CL GND (1) The pulse generator (PG) has the following characteristics. : tr=3ns, tf=3ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 10 of 12 R8A66173SP TIMING CHARTS tsu(CS) th(CS) Vcc CS 50% 50% 0V tWRH Vcc WR 50% tsu(WR) tw (S) tw (S) 50% 50% th(WR) th(SCLK) 50% 0V Vcc SCLK 50% 50% tsu(S) th(S) 50% 50% 0V Vcc SIN 50% 50% 0V tc(X) tw (XH) tw (XL) Vcc XIN 50% 50% 50% 0V Φ (internal clock) tPLH tPHL V OH PWM1~4 50% 50% V OL Note 2. (1)Shaded portions indicate that switching is possible during those periods. (2)PWM outputs 1 to 4 change synchronously with internal clock signals Φ. The frequency of these signals is the 1/2 divider of the frequency input from XIN. APPLICATION EXAMPLE (Combination with electronic control for amplifier system) Electronic control CD FM DAT AV Pow er amplifier Graphic equalizer Speaker Control microcomputer Buffer/Low -pass filter PWM MCU R8A66173SP REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 11 of 12 R8A66173SP PACKAGE OUTLINE Package 14pin SOP RENESAS Code PRSP0014DG-A Previous Code 14P2X-B All trademarks and registered trademarks are the property of their respective owners. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 12 of 12