R8CL35A

REJ09B0441-0010 R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, 16 R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/Lx SERIES Preliminary All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.0.10 Revision Date: Jul 30, 2008 w ww.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/L35A Group, R8C/L35B Group, R8C/L36A Group, R8C/L36B Group, R8C/L38A Group, R8C/L38B Group, R8C/L3AA Group, R8C/L3AB Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Title Document No. R8C/L35A Group, REJ03B0243 R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Shortsheet R8C/L35A Group, This hardware Hardware manual Hardware specifications (pin assignments, R8C/L36A Group, manual memory maps, peripheral function R8C/L38A Group, specifications, electrical characteristics, timing R8C/L3AA Group, charts) and operation description Note: Refer to the application notes for details on R8C/L35B Group, R8C/L36B Group, using peripheral functions. R8C/L38B Group, R8C/L3AB Group Hardware Manual Software manual Description of CPU instruction set R8C/Tiny Series REJ09B0001 Software Manual Available from the Renesas Application note Information on using peripheral functions and Technology Corp. website. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Shortsheet Description Hardware overview 2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234 3. Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) b6 XXX6 0 b5 XXX5 0 Bit Name b1 b0 Address XXXXh Bit b7 Symbol XXX7 After Reset 0 Bit b0 b1 b4 XXX4 0 b3 — 0 b2 — 0 b1 XXX1 0 Function b0 XXX0 0 *1 Symbol XXX0 XXX bit XXX1 b2 b3 b4 b5 b6 b7 — — XXX4 XXX5 XXX6 XXX7 0 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Reserved bit Set to 0. XXX bit Function varies according to the operating mode. R/W R/W R/W XXX bit 0: XXX 1: XXX — R/W R/W W R/W R *2 *3 *1 R/W: Read and write. R: Read only. W: Write only. −: Nothing is assigned. *2 • Reserved bit Reserved bit. Set to specified value. *3 • Nothing is assigned. Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. • Do not set to a value. Operation is not guaranteed when a value is set. • Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes. 4. List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment Bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Special Function Register Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners. Table of Contents SFR Page Reference ........................................................................................................................... B - 1 1. Overview ......................................................................................................................................... 1 1.1 1.1.1 1.1.2 1.1.3 1.2 1.3 1.4 1.5 2. Features ..................................................................................................................................................... 1 Applications .......................................................................................................................................... 1 Differences between Groups ................................................................................................................. 2 Specifications ........................................................................................................................................ 3 Product Lists .............................................................................................................................................. 6 Block Diagrams ...................................................................................................................................... 14 Pin Assignments ...................................................................................................................................... 18 Pin Functions ........................................................................................................................................... 26 Central Processing Unit (CPU) ..................................................................................................... 28 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10 Data Registers (R0, R1, R2, and R3) ...................................................................................................... Address Registers (A0 and A1) ............................................................................................................... Frame Base Register (FB) ....................................................................................................................... Interrupt Table Register (INTB) .............................................................................................................. Program Counter (PC) ............................................................................................................................. User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. Static Base Register (SB) ........................................................................................................................ Flag Register (FLG) ................................................................................................................................ Carry Flag (C) ..................................................................................................................................... Debug Flag (D) ................................................................................................................................... Zero Flag (Z) ....................................................................................................................................... Sign Flag (S) ....................................................................................................................................... Register Bank Select Flag (B) ............................................................................................................ Overflow Flag (O) .............................................................................................................................. Interrupt Enable Flag (I) ..................................................................................................................... Stack Pointer Select Flag (U) .............................................................................................................. Processor Interrupt Priority Level (IPL) ............................................................................................. Reserved Bit ........................................................................................................................................ 29 29 29 29 29 29 29 29 29 29 29 29 29 29 30 30 30 30 3. 4. 5. Memory ......................................................................................................................................... 31 Special Function Registers (SFRs) ............................................................................................... 32 Resets ........................................................................................................................................... 48 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.2.1 5.2.2 5.3 5.4 5.5 5.6 Registers .................................................................................................................................................. Processor Mode Register 0 (PM0) ...................................................................................................... Reset Source Determination Register (RSTFR) ................................................................................. Option Function Select Register (OFS) .............................................................................................. Option Function Select Register 2 (OFS2) ......................................................................................... Hardware Reset ....................................................................................................................................... When Power Supply is Stable ............................................................................................................. Power On ............................................................................................................................................ Power-On Reset Function ....................................................................................................................... Voltage Monitor 0 Reset ......................................................................................................................... Watchdog Timer Reset ............................................................................................................................ Software Reset ......................................................................................................................................... A-1 51 51 51 52 53 54 54 54 56 57 58 58 5.7 5.8 6. Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 59 Reset Source Determination Function ..................................................................................................... 59 Voltage Detection Circuit .............................................................................................................. 60 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.3 6.3.1 6.3.2 6.3.3 6.4 6.5 6.6 7. Introduction ............................................................................................................................................. Registers .................................................................................................................................................. Voltage Monitor Circuit/Comparator A Control Register (CMPA) ................................................... Voltage Monitor Circuit Edge Select Register (VCAC) .................................................................... Voltage Detect Register (VCA1) ........................................................................................................ Voltage Detect Register 2 (VCA2) ..................................................................................................... Voltage Detection 1 Level Select Register (VD1LS) ......................................................................... Voltage Monitor 0 Circuit Control Register (VW0C) ........................................................................ Voltage Monitor 1 Circuit Control Register (VW1C) ........................................................................ Voltage Monitor 2 Circuit Control Register (VW2C) ........................................................................ Option Function Select Register (OFS) .............................................................................................. VCC Input Voltage .................................................................................................................................. Monitoring Vdet0 ............................................................................................................................... Monitoring Vdet1 ............................................................................................................................... Monitoring Vdet2 ............................................................................................................................... Voltage Monitor 0 Reset ......................................................................................................................... Voltage Monitor 1 Interrupt .................................................................................................................... Voltage Monitor 2 Interrupt .................................................................................................................... 60 64 64 65 65 66 67 68 69 70 71 72 72 72 72 73 74 76 I/O Ports ........................................................................................................................................ 78 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 7.4.14 7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 I/O Port Functions ................................................................................................................................... 79 Effect on Peripheral Functions ................................................................................................................ 79 Pins Other than I/O Ports ......................................................................................................................... 79 Registers .................................................................................................................................................. 85 Port Pi Direction Register (PDi) (i = 0 to 7, 10 to 13) ........................................................................ 85 Port Pi Register (Pi) (i = 0 to 7, 10 to 13) ........................................................................................... 86 Timer RA Pin Select Register (TRASR) ............................................................................................ 87 Timer RB/RC Pin Select Register (TRBRCSR) ................................................................................. 88 Timer RC Pin Select Register 0 (TRCPSR0) ..................................................................................... 89 Timer RC Pin Select Register 1 (TRCPSR1) ..................................................................................... 90 Timer RD Pin Select Register 0 (TRDPSR0) ..................................................................................... 91 Timer RD Pin Select Register 1 (TRDPSR1) ..................................................................................... 92 Timer RG Pin Select Register (TRGPSR) .......................................................................................... 93 UART0 Pin Select Register (U0SR) ................................................................................................... 93 UART1 Pin Select Register (U1SR) ................................................................................................... 94 UART2 Pin Select Register 0 (U2SR0) .............................................................................................. 95 UART2 Pin Select Register 1 (U2SR1) .............................................................................................. 96 SSU/IIC Pin Select Register (SSUIICSR) .......................................................................................... 97 Key Input Pin Select Register (KISR) ................................................................................................ 98 INT Interrupt Input Pin Select Register (INTSR) ............................................................................... 99 Port Pi Pull-Up Control Register (PiPUR) (i = 0 to 7) ....................................................................... 99 Port Pj Pull-Up Control Register (PjPUR) (j = 10 to 13) ................................................................. 100 Port P10 Drive Capacity Control Register (P10DRR) ...................................................................... 100 Port P11 Drive Capacity Control Register (P11DRR) ...................................................................... 101 Input Threshold Control Register 0 (VLT0) ..................................................................................... 101 A-2 7.4.22 Input Threshold Control Register 1 (VLT1) ..................................................................................... 7.4.23 Input Threshold Control Register 2 (VLT2) ..................................................................................... 7.5 Port Settings .......................................................................................................................................... 7.6 Unassigned Pin Handling ...................................................................................................................... 8. 9. 102 103 104 123 Bus .............................................................................................................................................. 124 Clock Generation Circuit ............................................................................................................. 126 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.2.11 9.2.12 9.3 9.4 9.4.1 9.4.2 9.5 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.6.9 9.6.10 9.6.11 9.7 9.7.1 9.8 9.8.1 9.8.2 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ System Clock Control Register 0 (CM0) .......................................................................................... System Clock Control Register 1 (CM1) .......................................................................................... System Clock Control Register 3 (CM3) .......................................................................................... Oscillation Stop Detection Register (OCD) ...................................................................................... High-Speed On-Chip Oscillator Control Register 7 (FRA7) ............................................................ High-Speed On-Chip Oscillator Control Register 0 (FRA0) ............................................................ High-Speed On-Chip Oscillator Control Register 1 (FRA1) ............................................................ High-Speed On-Chip Oscillator Control Register 2 (FRA2) ............................................................ High-Speed On-Chip Oscillator Control Register 4 (FRA4) ............................................................ High-Speed On-Chip Oscillator Control Register 5 (FRA5) ............................................................ High-Speed On-Chip Oscillator Control Register 6 (FRA6) ............................................................ High-Speed On-Chip Oscillator Control Register 3 (FRA3) ............................................................ XIN Clock ............................................................................................................................................. On-Chip Oscillator Clock ...................................................................................................................... Low-Speed On-Chip Oscillator Clock .............................................................................................. High-Speed On-Chip Oscillator Clock ............................................................................................. XCIN Clock ........................................................................................................................................... CPU Clock and Peripheral Function Clock ........................................................................................... System Clock .................................................................................................................................... CPU Clock ........................................................................................................................................ Peripheral Function Clock (f1, f2, f4, f8, and f32) ........................................................................... fOCO ................................................................................................................................................. fOCO40M ......................................................................................................................................... fOCO-F ............................................................................................................................................. fOCO-S ............................................................................................................................................. fOCO128 ........................................................................................................................................... fC-LCD ............................................................................................................................................. fC, fC2, fC4, and fC32 ...................................................................................................................... fOCO-WDT ...................................................................................................................................... Oscillation Stop Detection Function ..................................................................................................... How to Use Oscillation Stop Detection Function ............................................................................. Notes on Clock Generation Circuit ....................................................................................................... Oscillation Stop Detection Function ................................................................................................. Oscillation Circuit Constants ............................................................................................................ 126 129 129 130 131 132 132 133 133 134 135 135 135 135 136 137 137 137 138 139 139 139 139 139 139 139 140 140 140 140 140 141 141 143 143 143 10. Power Control ............................................................................................................................. 144 10.1 Introduction ........................................................................................................................................... 144 10.2 Registers ................................................................................................................................................ 146 10.2.1 System Clock Control Register 0 (CM0) .......................................................................................... 146 A-3 10.2.2 System Clock Control Register 1 (CM1) .......................................................................................... 10.2.3 System Clock Control Register 3 (CM3) .......................................................................................... 10.2.4 Oscillation Stop Detection Register (OCD) ...................................................................................... 10.2.5 High-Speed On-Chip Oscillator Control Register 0 (FRA0) ............................................................ 10.2.6 Voltage Detect Register 2 (VCA2) ................................................................................................... 10.2.7 Power-Off Mode Control Register 0 (POMCR0) ............................................................................. 10.3 Standard Operating Mode ..................................................................................................................... 10.3.1 High-Speed Clock Mode .................................................................................................................. 10.3.2 Low-Speed Clock Mode ................................................................................................................... 10.3.3 High-Speed On-Chip Oscillator Mode ............................................................................................. 10.3.4 Low-Speed On-Chip Oscillator Mode .............................................................................................. 10.4 Wait Mode ............................................................................................................................................. 10.4.1 Peripheral Function Clock Stop Function ......................................................................................... 10.4.2 Entering Wait Mode .......................................................................................................................... 10.4.3 Pin Status in Wait Mode ................................................................................................................... 10.4.4 Exiting Wait Mode ............................................................................................................................ 10.5 Stop Mode ............................................................................................................................................. 10.5.1 Entering Stop Mode .......................................................................................................................... 10.5.2 Pin Status in Stop Mode .................................................................................................................... 10.5.3 Exiting Stop Mode ............................................................................................................................ 10.6 Power-Off Mode .................................................................................................................................... 10.6.1 Pin Handling in Power-Off Mode ..................................................................................................... 10.6.2 Entering Power-Off Mode ................................................................................................................ 10.6.3 Pin Status in Power-Off Mode .......................................................................................................... 10.6.4 Exiting Power-Off Mode .................................................................................................................. 10.7 Reducing Power Consumption .............................................................................................................. 10.7.1 Voltage Detection Circuit ................................................................................................................. 10.7.2 Ports .................................................................................................................................................. 10.7.3 Clocks ............................................................................................................................................... 10.7.4 Wait Mode, Stop Mode, and Power-Off Mode ................................................................................ 10.7.5 Stopping Peripheral Function Clocks ............................................................................................... 10.7.6 Timers ............................................................................................................................................... 10.7.7 A/D Converter ................................................................................................................................... 10.7.8 Clock Synchronous Serial Interface ................................................................................................. 10.7.9 Reducing Internal Power Consumption ............................................................................................ 10.7.10 Stopping Flash Memory .................................................................................................................... 10.7.11 Low-Current-Consumption Read Mode ........................................................................................... 10.8 Notes on Power Control ........................................................................................................................ 10.8.1 Stop Mode ......................................................................................................................................... 10.8.2 Wait Mode ........................................................................................................................................ 10.8.3 Power-Off Mode ............................................................................................................................... 11. 147 148 149 150 151 152 153 154 154 154 154 155 155 155 155 156 159 159 159 160 161 161 161 161 162 163 163 163 163 163 163 163 164 164 164 165 166 167 167 167 167 Protection .................................................................................................................................... 168 11.1 Register .................................................................................................................................................. 168 11.1.1 Protect Register (PRCR) ................................................................................................................... 168 12. Interrupts ..................................................................................................................................... 169 12.1 Introduction ........................................................................................................................................... 169 12.1.1 Types of Interrupts ............................................................................................................................ 169 A-4 12.1.2 Software Interrupts ........................................................................................................................... 170 12.1.3 Special Interrupts .............................................................................................................................. 171 12.1.4 Peripheral Function Interrupts .......................................................................................................... 171 12.1.5 Interrupts and Interrupt Vectors ........................................................................................................ 172 12.2 Registers ................................................................................................................................................ 174 12.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) .................................................................................................................... 174 12.2.2 Interrupt Control Register (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC, TRGIC) .................................................. 175 12.2.3 INTi Interrupt Control Register (INTiIC) (i = 0 to 7) ....................................................................... 176 12.3 Interrupt Control .................................................................................................................................... 177 12.3.1 I Flag ................................................................................................................................................. 177 12.3.2 IR Bit ................................................................................................................................................. 177 12.3.3 Bits ILVL2 to ILVL0, IPL ................................................................................................................ 177 12.3.4 Interrupt Sequence ............................................................................................................................ 178 12.3.5 Interrupt Response Time ................................................................................................................... 179 12.3.6 IPL Change when Interrupt Request is Acknowledged .................................................................... 179 12.3.7 Saving Registers ............................................................................................................................... 180 12.3.8 Returning from Interrupt Routine ..................................................................................................... 182 12.3.9 Interrupt Priority ............................................................................................................................... 182 12.3.10 Interrupt Priority Level Selection Circuit ......................................................................................... 183 12.4 INT Interrupt ......................................................................................................................................... 184 12.4.1 INTi Interrupt (i = 0 to 7) .................................................................................................................. 184 12.4.2 INT Interrupt Input Pin Select Register (INTSR) ............................................................................. 185 12.4.3 External Input Enable Register 0 (INTEN) ...................................................................................... 186 12.4.4 External Input Enable Register 1 (INTEN1) .................................................................................... 187 12.4.5 INT Input Filter Select Register 0 (INTF) ........................................................................................ 188 12.4.6 INT Input Filter Select Register 1 (INTF1) ...................................................................................... 188 12.4.7 INTi Input Filter (i = 0 to 7) .............................................................................................................. 189 12.5 Key Input Interrupt ................................................................................................................................ 190 12.5.1 Key Input Pin Select Register (KISR) .............................................................................................. 192 12.5.2 Key Input Enable Register 0 (KIEN) ................................................................................................ 193 12.5.3 Key Input Enable Register 1 (KIEN1) .............................................................................................. 194 12.6 Address Match Interrupt ........................................................................................................................ 195 12.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1) ...................................................... 196 12.6.2 Address Match Interrupt Register i (RMADi) (i = 0 or 1) ................................................................ 196 12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources) ............................ 197 12.8 Notes on Interrupts ................................................................................................................................ 199 12.8.1 Reading Address 00000h .................................................................................................................. 199 12.8.2 SP Setting .......................................................................................................................................... 199 12.8.3 External Interrupt, Key Input Interrupt ............................................................................................. 199 12.8.4 Changing Interrupt Sources .............................................................................................................. 200 12.8.5 Rewriting Interrupt Control Register ................................................................................................ 201 13. 13.1 13.2 ID Code Areas ............................................................................................................................ 202 Introduction ........................................................................................................................................... 202 Functions ............................................................................................................................................... 203 A-5 13.3 Forced Erase Function ........................................................................................................................... 13.4 Standard Serial I/O Mode Disabled Function ....................................................................................... 13.5 Notes on ID Code Areas ........................................................................................................................ 13.5.1 Setting Example of ID Code Areas ................................................................................................... 14. 204 204 205 205 Option Function Select Area ....................................................................................................... 206 206 207 207 208 209 209 14.1 Introduction ........................................................................................................................................... 14.2 Registers ................................................................................................................................................ 14.2.1 Option Function Select Register (OFS) ............................................................................................ 14.2.2 Option Function Select Register 2 (OFS2) ....................................................................................... 14.3 Notes on Option Function Select Area .................................................................................................. 14.3.1 Setting Example of Option Function Select Area ............................................................................. 15. Watchdog Timer .......................................................................................................................... 210 15.1 Introduction ........................................................................................................................................... 210 15.2 Registers ................................................................................................................................................ 212 15.2.1 Processor Mode Register 1 (PM1) .................................................................................................... 212 15.2.2 Watchdog Timer Reset Register (WDTR) ........................................................................................ 212 15.2.3 Watchdog Timer Start Register (WDTS) ......................................................................................... 212 15.2.4 Watchdog Timer Control Register (WDTC) .................................................................................... 213 15.2.5 Count Source Protection Mode Register (CSPR) ............................................................................. 213 15.2.6 Option Function Select Register (OFS) ............................................................................................ 214 15.2.7 Option Function Select Register 2 (OFS2) ....................................................................................... 215 15.3 Functional Description ......................................................................................................................... 216 15.3.1 Common Items for Multiple Modes ................................................................................................. 216 15.3.2 Count Source Protection Mode Disabled .......................................................................................... 217 15.3.3 Count Source Protection Mode Enabled ........................................................................................... 218 16. DTC ............................................................................................................................................ 219 16.1 Overview ............................................................................................................................................... 219 16.2 Registers ................................................................................................................................................ 220 16.2.1 DTC Control Register j (DTCCRj) (j = 0 to 23) ............................................................................... 221 16.2.2 DTC Block Size Register j (DTBLSj) (j = 0 to 23) .......................................................................... 221 16.2.3 DTC Transfer Count Register j (DTCCTj) (j = 0 to 23) ................................................................... 222 16.2.4 DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23) ...................................................... 222 16.2.5 DTC Source Address Register j (DTSARj) (j = 0 to 23) .................................................................. 222 16.2.6 DTC Destination Register j (DTDARj) (j = 0 to 23) ........................................................................ 222 16.2.7 DTC Activation Enable Registers i (DTCENi) (i = 0 to 6) .............................................................. 223 16.2.8 DTC Activation Control Register (DTCTL) .................................................................................... 224 16.3 Function Description ............................................................................................................................. 225 16.3.1 Overview ........................................................................................................................................... 225 16.3.2 Activation Sources ............................................................................................................................ 225 16.3.3 Control Data Allocation and DTC Vector Table .............................................................................. 227 16.3.4 Normal Mode .................................................................................................................................... 231 16.3.5 Repeat Mode ..................................................................................................................................... 232 16.3.6 Chain Transfers ................................................................................................................................. 233 16.3.7 Interrupt Sources ............................................................................................................................... 233 16.3.8 Operation Timings ............................................................................................................................ 234 16.3.9 Number of DTC Execution Cycles ................................................................................................... 235 A-6 16.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags .......................................... 16.4 Notes on DTC ........................................................................................................................................ 16.4.1 DTC activation source ...................................................................................................................... 16.4.2 DTCENi (i = 0 to 6) Registers .......................................................................................................... 16.4.3 Peripheral Modules ........................................................................................................................... 17. 18. 236 237 237 237 237 Timers ......................................................................................................................................... 238 Timer RA ..................................................................................................................................... 240 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ Timer RA Control Register (TRACR) .............................................................................................. Timer RA I/O Control Register (TRAIOC) ...................................................................................... Timer RA Mode Register (TRAMR) ................................................................................................ Timer RA Prescaler Register (TRAPRE) ......................................................................................... Timer RA Register (TRA) ................................................................................................................ Timer RA Pin Select Register (TRASR) .......................................................................................... Timer Mode ........................................................................................................................................... Timer RA I/O Control Register (TRAIOC) in Timer Mode ............................................................ Timer Write Control during Count Operation .................................................................................. Pulse Output Mode ................................................................................................................................ Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode ................................................. Event Counter Mode ............................................................................................................................. Timer RA I/O Control Register (TRAIOC) in Event Counter Mode ............................................... Pulse Width Measurement Mode .......................................................................................................... Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement Mode ............................ Operating Example ........................................................................................................................... Pulse Period Measurement Mode .......................................................................................................... Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement Mode ........................... Operating Example ........................................................................................................................... Notes on Timer RA ............................................................................................................................... 240 241 241 241 242 242 243 243 244 244 245 246 247 248 249 250 251 252 253 254 255 256 18.1 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.3 18.3.1 18.3.2 18.4 18.4.1 18.5 18.5.1 18.6 18.6.1 18.6.2 18.7 18.7.1 18.7.2 18.8 19. Timer RB ..................................................................................................................................... 257 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ Timer RB Control Register (TRBCR) .............................................................................................. Timer RB One-Shot Control Register (TRBOCR) ........................................................................... Timer RB I/O Control Register (TRBIOC) ...................................................................................... Timer RB Mode Register (TRBMR) ................................................................................................ Timer RB Prescaler Register (TRBPRE) .......................................................................................... Timer RB Secondary Register (TRBSC) .......................................................................................... Timer RB Primary Register (TRBPR) .............................................................................................. Timer RB/RC Pin Select Register (TRBRCSR) ............................................................................... Timer Mode ........................................................................................................................................... Timer RB I/O Control Register (TRBIOC) in Timer Mode ............................................................. Timer Write Control during Count Operation .................................................................................. Programmable Waveform Generation Mode ........................................................................................ Timer RB I/O Control Register (TRBIOC) in Programmable Waveform Generation Mode .......... Operating Example ........................................................................................................................... A-7 257 258 258 258 259 259 260 260 261 261 262 262 263 265 266 267 19.1 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 19.3 19.3.1 19.3.2 19.4 19.4.1 19.4.2 19.5 Programmable One-shot Generation Mode ........................................................................................... 268 19.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode ............ 269 19.5.2 Operating Example ........................................................................................................................... 270 19.5.3 One-Shot Trigger Selection .............................................................................................................. 271 19.6 Programmable Wait One-Shot Generation Mode ................................................................................. 272 19.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode ... 273 19.6.2 Operating Example ........................................................................................................................... 274 19.7 Notes on Timer RB ................................................................................................................................ 275 19.7.1 Timer Mode ...................................................................................................................................... 275 19.7.2 Programmable Waveform Generation Mode .................................................................................... 275 19.7.3 Programmable One-Shot Generation Mode ..................................................................................... 276 19.7.4 Programmable Wait One-shot Generation Mode ............................................................................. 276 20. Timer RC ..................................................................................................................................... 277 277 279 280 281 282 282 283 284 284 285 285 286 286 287 287 288 289 290 291 291 292 294 295 297 299 300 301 302 304 305 306 307 308 310 312 20.1 Introduction ........................................................................................................................................... 20.2 Registers ................................................................................................................................................ 20.2.1 Module Standby Control Register (MSTCR) ................................................................................... 20.2.2 Timer RC Mode Register (TRCMR) ................................................................................................ 20.2.3 Timer RC Control Register 1 (TRCCR1) ......................................................................................... 20.2.4 Timer RC Interrupt Enable Register (TRCIER) ............................................................................... 20.2.5 Timer RC Status Register (TRCSR) ................................................................................................. 20.2.6 Timer RC I/O Control Register 0 (TRCIOR0) ................................................................................. 20.2.7 Timer RC I/O Control Register 1 (TRCIOR1) ................................................................................. 20.2.8 Timer RC Counter (TRC) ................................................................................................................. 20.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) .......... 20.2.10 Timer RC Control Register 2 (TRCCR2) ......................................................................................... 20.2.11 Timer RC Digital Filter Function Select Register (TRCDF) ............................................................ 20.2.12 Timer RC Output Master Enable Register (TRCOER) .................................................................... 20.2.13 Timer RC Trigger Control Register (TRCADCR) ........................................................................... 20.2.14 Timer RB/RC Pin Select Register (TRBRCSR) ............................................................................... 20.2.15 Timer RC Pin Select Register 0 (TRCPSR0) ................................................................................... 20.2.16 Timer RC Pin Select Register 1 (TRCPSR1) ................................................................................... 20.3 Common Items for Multiple Modes ...................................................................................................... 20.3.1 Count Source ..................................................................................................................................... 20.3.2 Buffer Operation ............................................................................................................................... 20.3.3 Digital Filter ...................................................................................................................................... 20.3.4 Forced Cutoff of Pulse Output .......................................................................................................... 20.4 Timer Mode (Input Capture Function) .................................................................................................. 20.4.1 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Input Capture Function) ............... 20.4.2 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Input Capture Function) ............... 20.4.3 Operating Example ........................................................................................................................... 20.5 Timer Mode (Output Compare Function) ............................................................................................. 20.5.1 Timer RC Control Register 1 (TRCCR1) in Timer Mode (Output Compare Function) .................. 20.5.2 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Output Compare Function) .......... 20.5.3 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Output Compare Function) .......... 20.5.4 Operating Example ........................................................................................................................... 20.5.5 Changing Output Pins in Registers TRCGRC and TRCGRD .......................................................... 20.6 PWM Mode ........................................................................................................................................... 20.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode ................................................................ A-8 20.6.2 Timer RC Control Register 2 (TRCCR2) in PWM Mode ................................................................ 313 20.6.3 Operating Example ........................................................................................................................... 314 20.7 PWM2 Mode ......................................................................................................................................... 316 20.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode .............................................................. 318 20.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode .............................................................. 319 20.7.3 Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode ................................. 319 20.7.4 Operating Example ........................................................................................................................... 320 20.8 Timer RC Interrupt ................................................................................................................................ 323 20.9 Notes on Timer RC ................................................................................................................................ 324 20.9.1 TRC Register .................................................................................................................................... 324 20.9.2 TRCSR Register .............................................................................................................................. 324 20.9.3 TRCCR1 Register ............................................................................................................................. 324 20.9.4 Count Source Switching ................................................................................................................... 324 20.9.5 Input Capture Function ..................................................................................................................... 324 20.9.6 TRCMR Register in PWM2 Mode ................................................................................................... 324 21. Timer RD ..................................................................................................................................... 325 21.1 Introduction ........................................................................................................................................... 325 21.2 Common Items for Multiple Modes ...................................................................................................... 327 21.2.1 Count Sources ................................................................................................................................... 327 21.2.2 Buffer Operation ............................................................................................................................... 328 21.2.3 Synchronous Operation ..................................................................................................................... 330 21.2.4 Pulse Output Forced Cutoff .............................................................................................................. 331 21.3 Input Capture Function .......................................................................................................................... 333 21.3.1 Module Standby Control Register (MSTCR) ................................................................................... 335 21.3.2 Timer RD Control Expansion Register (TRDECR) ......................................................................... 335 21.3.3 Timer RD Start Register (TRDSTR) for Input Capture Function .................................................... 336 21.3.4 Timer RD Mode Register (TRDMR) for Input Capture Function .................................................... 336 21.3.5 Timer RD PWM Mode Register (TRDPMR) for Input Capture Function ....................................... 337 21.3.6 Timer RD Function Control Register (TRDFCR) for Input Capture Function ................................ 337 21.3.7 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) for Input Capture Function ........................................................................................................................................................... 338 21.3.8 Timer RD Control Register i (TRDCRi) (i = 0 or 1) for Input Capture Function ............................ 339 21.3.9 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) for Input Capture Function .............. 340 21.3.10 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) for Input Capture Function ............... 341 21.3.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) for Input Capture Function ............................... 342 21.3.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) for Input Capture Function ............. 343 21.3.13 Timer RD Counter i (TRDi) (i = 0 or 1) for Input Capture Function ............................................... 343 21.3.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) for Input Capture Function ............................................................................................. 344 21.3.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 345 21.3.16 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 346 21.3.17 Operating Example ........................................................................................................................... 347 21.3.18 Digital Filter ...................................................................................................................................... 348 21.4 Output Compare Function ..................................................................................................................... 349 21.4.1 Module Standby Control Register (MSTCR) ................................................................................... 351 21.4.2 Timer RD Control Expansion Register (TRDECR) ......................................................................... 352 21.4.3 Timer RD Trigger Control Register (TRDADCR) ........................................................................... 352 21.4.4 Timer RD Start Register (TRDSTR) for Output Compare Function ................................................ 353 A-9 Timer RD Mode Register (TRDMR) for Output Compare Function ............................................... Timer RD PWM Mode Register (TRDPMR) for Output Compare Function .................................. Timer RD Function Control Register (TRDFCR) for Output Compare Function ........................... Timer RD Output Master Enable Register 1 (TRDOER1) for Output Compare Function .............. Timer RD Output Master Enable Register 2 (TRDOER2) for Output Compare Function .............. Timer RD Output Control Register (TRDOCR) for Output Compare Function .............................. Timer RD Control Register i (TRDCRi) (i = 0 or 1) for Output Compare Function ....................... Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) for Output Compare Function .......... Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) for Output Compare Function .......... Timer RD Status Register i (TRDSRi) (i = 0 or 1) for Output Compare Function .......................... Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) for Output Compare Function ........ Timer RD Counter i (TRDi) (i = 0 or 1) for Output Compare Function .......................................... Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) for Output Compare Function ........................................................................................ 21.4.18 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 21.4.19 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 21.4.20 Operating Example ........................................................................................................................... 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi ..................................... 21.4.22 A/D Trigger Generation .................................................................................................................... 21.5 PWM Mode ........................................................................................................................................... 21.5.1 Module Standby Control Register (MSTCR) ................................................................................... 21.5.2 Timer RD Control Expansion Register (TRDECR) ......................................................................... 21.5.3 Timer RD Trigger Control Register (TRDADCR) ........................................................................... 21.5.4 Timer RD Start Register (TRDSTR) in PWM Mode ....................................................................... 21.5.5 Timer RD Mode Register (TRDMR) in PWM Mode ....................................................................... 21.5.6 Timer RD PWM Mode Register (TRDPMR) in PWM Mode .......................................................... 21.5.7 Timer RD Function Control Register (TRDFCR) in PWM Mode ................................................... 21.5.8 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM Mode ...................................... 21.5.9 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM Mode ...................................... 21.5.10 Timer RD Output Control Register (TRDOCR) in PWM Mode ...................................................... 21.5.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in PWM Mode ............................................... 21.5.12 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM Mode .................................................. 21.5.13 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM Mode ................................ 21.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or 1) in PWM Mode ........................................................................................................................................................... 21.5.15 Timer RD Counter i (TRDi) (i = 0 or 1) in PWM Mode .................................................................. 21.5.16 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM Mode ................................................................................................................ 21.5.17 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 21.5.18 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 21.5.19 Operating Example ........................................................................................................................... 21.5.20 A/D Trigger Generation .................................................................................................................... 21.6 Reset Synchronous PWM Mode ........................................................................................................... 21.6.1 Module Standby Control Register (MSTCR) ................................................................................... 21.6.2 Timer RD Control Expansion Register (TRDECR) ......................................................................... 21.6.3 Timer RD Trigger Control Register (TRDADCR) ........................................................................... 21.6.4 Timer RD Start Register (TRDSTR) in Reset Synchronous PWM Mode ....................................... 21.6.5 Timer RD Mode Register (TRDMR) in Reset Synchronous PWM Mode ....................................... 21.6.6 Timer RD Function Control Register (TRDFCR) in Reset Synchronous PWM Mode ................... 21.4.5 21.4.6 21.4.7 21.4.8 21.4.9 21.4.10 21.4.11 21.4.12 21.4.13 21.4.14 21.4.15 21.4.16 21.4.17 354 354 355 356 356 357 358 359 360 361 362 362 363 364 365 366 367 369 370 372 373 373 374 374 375 375 376 376 377 377 378 379 379 380 381 382 383 384 386 387 389 390 390 391 391 392 A - 10 Timer RD Output Master Enable Register 1 (TRDOER1) in Reset Synchronous PWM Mode ...... 393 Timer RD Output Master Enable Register 2 (TRDOER2) in Reset Synchronous PWM Mode ...... 393 Timer RD Control Register 0 (TRDCR0) in Reset Synchronous PWM Mode ................................ 394 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Reset Synchronous PWM Mode .................. 395 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Reset Synchronous PWM Mode 396 Timer RD Counter 0 (TRD0) in Reset Synchronous PWM Mode ................................................... 396 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) in Reset Synchronous PWM Mode ................................................................................ 397 21.6.14 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 398 21.6.15 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 399 21.6.16 Operating Example ........................................................................................................................... 400 21.6.17 A/D Trigger Generation .................................................................................................................... 401 21.7 Complementary PWM Mode ................................................................................................................ 402 21.7.1 Module Standby Control Register (MSTCR) ................................................................................... 404 21.7.2 Timer RD Control Expansion Register (TRDECR) ......................................................................... 404 21.7.3 Timer RD Trigger Control Register (TRDADCR) ........................................................................... 405 21.7.4 Timer RD Start Register (TRDSTR) in Complementary PWM Mode ............................................ 406 21.7.5 Timer RD Mode Register (TRDMR) in Complementary PWM Mode ............................................ 406 21.7.6 Timer RD Function Control Register (TRDFCR) in Complementary PWM Mode ........................ 407 21.7.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Complementary PWM Mode ........... 408 21.7.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Complementary PWM Mode ........... 408 21.7.9 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Complementary PWM Mode .................... 409 21.7.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Complementary PWM Mode ....................... 410 21.7.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Complementary PWM Mode ..... 411 21.7.12 Timer RD Counter 0 (TRD0) in Complementary PWM Mode ........................................................ 411 21.7.13 Timer RD Counter 1 (TRD1) in Complementary PWM Mode ........................................................ 412 21.7.14 Timer RD General Registers Ai, Bi, C1, and Di (TRDGRAi, TRDGRBi, TRDGRC1, TRDGRDi) (i = 0 or 1) in Complementary PWM Mode ..................................................................................... 412 21.7.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 414 21.7.16 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 415 21.7.17 Operating Example ........................................................................................................................... 416 21.7.18 Transfer Timing from Buffer Register .............................................................................................. 418 21.7.19 A/D Trigger Generation .................................................................................................................... 418 21.8 PWM3 Mode ......................................................................................................................................... 419 21.8.1 Module Standby Control Register (MSTCR) ................................................................................... 421 21.8.2 Timer RD Control Expansion Register (TRDECR) ......................................................................... 421 21.8.3 Timer RD Trigger Control Register (TRDADCR) ........................................................................... 422 21.8.4 Timer RD Start Register (TRDSTR) in PWM3 Mode ..................................................................... 423 21.8.5 Timer RD Mode Register (TRDMR) in PWM3 Mode ..................................................................... 423 21.8.6 Timer RD Function Control Register (TRDFCR) in PWM3 Mode ................................................. 424 21.8.7 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM3 Mode .................................... 425 21.8.8 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM3 Mode .................................... 425 21.8.9 Timer RD Output Control Register (TRDOCR) in PWM3 Mode .................................................... 426 21.8.10 Timer RD Control Register 0 (TRDCR0) in PWM3 Mode .............................................................. 427 21.8.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM3 Mode ................................................ 428 21.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode .............................. 429 21.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode ................................................................................. 429 21.8.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM3 Mode .............................................................................................................. 430 21.6.7 21.6.8 21.6.9 21.6.10 21.6.11 21.6.12 21.6.13 A - 11 21.8.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 21.8.16 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 21.8.17 Operating Example ........................................................................................................................... 21.8.18 A/D Trigger Generation .................................................................................................................... 21.9 Timer RD Interrupt ................................................................................................................................ 21.10 Notes on Timer RD ............................................................................................................................... 21.10.1 TRDSTR Register ............................................................................................................................. 21.10.2 TRDi Register (i = 0 or 1) ................................................................................................................. 21.10.3 TRDSRi Register (i = 0 or 1) ............................................................................................................ 21.10.4 Count Source Switching ................................................................................................................... 21.10.5 Input Capture Function ..................................................................................................................... 21.10.6 Reset Synchronous PWM Mode ....................................................................................................... 21.10.7 Complementary PWM Mode ............................................................................................................ 21.10.8 Count Source fOCO40M .................................................................................................................. 22. 432 433 434 435 436 438 438 438 439 439 439 439 440 443 Timer RE ..................................................................................................................................... 444 Introduction ........................................................................................................................................... Real-Time Clock Mode ......................................................................................................................... Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode ......................................... Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode ......................................... Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode ............................................... Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode ................................ Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode .............................................. Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode .............................................. Timer RE Count Source Select Register (TRECSR) in Real-Time Clock Mode ............................. Operating Example ........................................................................................................................... Output Compare Mode .......................................................................................................................... Timer RE Counter Data Register (TRESEC) in Output Compare Mode ......................................... Timer RE Compare Data Register (TREMIN) in Output Compare Mode ....................................... Timer RE Control Register 1 (TRECR1) in Output Compare Mode ............................................... Timer RE Control Register 2 (TRECR2) in Output Compare Mode ............................................... Timer RE Count Source Select Register (TRECSR) in Output Compare Mode .............................. Operating Example ........................................................................................................................... Notes on Timer RE ................................................................................................................................ Reset .................................................................................................................................................. Starting and Stopping Count ............................................................................................................. Register Setting ................................................................................................................................. Time Reading Procedure in Real-Time Clock Mode ....................................................................... 444 445 447 447 448 448 449 450 451 452 453 454 454 455 455 456 457 458 458 458 458 460 22.1 22.2 22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.2.6 22.2.7 22.2.8 22.3 22.3.1 22.3.2 22.3.3 22.3.4 22.3.5 22.3.6 22.4 22.4.1 22.4.2 22.4.3 22.4.4 23. Timer RG .................................................................................................................................... 461 461 463 463 464 465 466 467 468 469 23.1 Introduction ........................................................................................................................................... 23.2 Registers ................................................................................................................................................ 23.2.1 Timer RG Mode Register (TRGMR) ................................................................................................ 23.2.2 Timer RG Count Control Register (TRGCNTC) ............................................................................. 23.2.3 Timer RG Control Register (TRGCR) .............................................................................................. 23.2.4 Timer RG Interrupt Enable Register (TRGIER) ............................................................................... 23.2.5 Timer RG Status Register (TRGSR) ................................................................................................ 23.2.6 Timer RG I/O Control Register (TRGIOR) ...................................................................................... 23.2.7 Timer RG Counter (TRG) ................................................................................................................. A - 12 23.2.8 23.2.9 23.3 23.3.1 23.3.2 23.3.3 23.4 23.4.1 23.4.2 23.4.3 23.4.4 23.5 23.5.1 23.5.2 23.5.3 23.5.4 23.6 23.6.1 23.6.2 23.7 23.7.1 23.7.2 23.7.3 23.8 23.9 23.9.1 24. Timer RG General Register A, B, C, D (TRGGRA, TRGGRB, TRGGRC, TRGGRD) ................. Timer RG Pin Select Register (TRGPSR) ........................................................................................ Common Items for Multiple Modes ...................................................................................................... Count Sources ................................................................................................................................... Buffer Operation ............................................................................................................................... Digital Filter ...................................................................................................................................... Timer Mode (Input Capture Function) .................................................................................................. Timer RG I/O Control Register (TRGIOR) in Timer Mode (Input Capture Function) ................... Procedure Example for Setting Input Capture Operation ................................................................. Input Capture Signal Timing ............................................................................................................ Operating Example ........................................................................................................................... Timer Mode (Output Compare Function) ............................................................................................. Timer RG I/O Control Register (TRGIOR) in Timer Mode (Output Compare Function) ............... Procedure Example for Setting Waveform Output by Compare Match ........................................... Output-Compare Output Timing ...................................................................................................... Operating Example ........................................................................................................................... PWM Mode ........................................................................................................................................... Procedure Example for Setting PWM Mode .................................................................................... Operating Example ........................................................................................................................... Phase Counting Mode ........................................................................................................................... Timer RG Control Register (TRGCR) in Phase Counting Mode ..................................................... Procedure Example for Setting Phase Counting Mode .................................................................... Operating Example ........................................................................................................................... Timer RG Interrupt ................................................................................................................................ Notes on Timer RG ............................................................................................................................... Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ........................................... 470 471 472 472 473 475 476 477 478 478 479 480 481 482 482 483 484 485 485 488 489 489 490 492 493 493 Serial Interface (UARTi (i = 0 or 1)) ............................................................................................ 494 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ UARTi Transmit/Receive Mode Register (UiMR) (i = 0 or 1) ........................................................ UARTi Bit Rate Register (UiBRG) (i = 0 or 1) ................................................................................ UARTi Transmit Buffer Register (UiTB) (i = 0 or 1) ...................................................................... UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1) .................................................... UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1) .................................................... UARTi Receive Buffer Register (UiRB) (i = 0 or 1) ....................................................................... UART0 Pin Select Register (U0SR) ................................................................................................. UART1 Pin Select Register (U1SR) ................................................................................................. Clock Synchronous Serial I/O Mode ..................................................................................................... Polarity Select Function .................................................................................................................... LSB First/MSB First Select Function ............................................................................................... Continuous Receive Mode ................................................................................................................ Clock Asynchronous Serial I/O (UART) Mode .................................................................................... Bit Rate ............................................................................................................................................. Notes on Serial Interface (UARTi (i = 0 or 1)) ..................................................................................... 494 496 496 496 497 498 498 499 500 501 502 506 506 507 508 513 514 24.1 24.2 24.2.1 24.2.2 24.2.3 24.2.4 24.2.5 24.2.6 24.2.7 24.2.8 24.3 24.3.1 24.3.2 24.3.3 24.4 24.4.1 24.5 25. 25.1 25.2 Serial Interface (UART2) ............................................................................................................ 515 Introduction ........................................................................................................................................... 515 Registers ................................................................................................................................................ 517 A - 13 25.2.1 UART2 Transmit/Receive Mode Register (U2MR) ......................................................................... 25.2.2 UART2 Bit Rate Register (U2BRG) ................................................................................................ 25.2.3 UART2 Transmit Buffer Register (U2TB) ....................................................................................... 25.2.4 UART2 Transmit/Receive Control Register 0 (U2C0) .................................................................... 25.2.5 UART2 Transmit/Receive Control Register 1 (U2C1) .................................................................... 25.2.6 UART2 Receive Buffer Register (U2RB) ........................................................................................ 25.2.7 UART2 Digital Filter Function Select Register (URXDF) .............................................................. 25.2.8 UART2 Special Mode Register 5 (U2SMR5) .................................................................................. 25.2.9 UART2 Special Mode Register 4 (U2SMR4) .................................................................................. 25.2.10 UART2 Special Mode Register 3 (U2SMR3) .................................................................................. 25.2.11 UART2 Special Mode Register 2 (U2SMR2) .................................................................................. 25.2.12 UART2 Special Mode Register (U2SMR) ....................................................................................... 25.2.13 UART2 Pin Select Register 0 (U2SR0) ............................................................................................ 25.2.14 UART2 Pin Select Register 1 (U2SR1) ............................................................................................ 25.3 Clock Synchronous Serial I/O Mode ..................................................................................................... 25.3.1 Measure for Dealing with Communication Errors ........................................................................... 25.3.2 CLK Polarity Select Function ........................................................................................................... 25.3.3 LSB First/MSB First Select Function ............................................................................................... 25.3.4 Continuous Receive Mode ................................................................................................................ 25.3.5 Serial Data Logic Switching Function .............................................................................................. 25.3.6 CTS/RTS Function ............................................................................................................................ 25.4 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 25.4.1 Bit Rate ............................................................................................................................................. 25.4.2 Measure for Dealing with Communication Errors ........................................................................... 25.4.3 LSB First/MSB First Select Function ............................................................................................... 25.4.4 Serial Data Logic Switching Function .............................................................................................. 25.4.5 TXD and RXD I/O Polarity Inverse Function .................................................................................. 25.4.6 CTS/RTS Function ............................................................................................................................ 25.4.7 RXD2 Digital Filter Select Function ................................................................................................ 25.5 Special Mode 1 (I2C Mode) .................................................................................................................. 25.5.1 Detection of Start and Stop Conditions ............................................................................................ 25.5.2 Output of Start and Stop Conditions ................................................................................................. 25.5.3 Arbitration ......................................................................................................................................... 25.5.4 Transfer Clock .................................................................................................................................. 25.5.5 SDA Output ...................................................................................................................................... 25.5.6 SDA Input ......................................................................................................................................... 25.5.7 ACK and NACK ............................................................................................................................... 25.5.8 Initialization of Transmission/Reception .......................................................................................... 25.6 Multiprocessor Communication Function ............................................................................................. 25.6.1 Multiprocessor Transmission ............................................................................................................ 25.6.2 Multiprocessor Reception ................................................................................................................. 25.6.3 RXD2 Digital Filter Select Function ................................................................................................ 25.7 Notes on Serial Interface (UART2) ....................................................................................................... 25.7.1 Clock Synchronous Serial I/O Mode ................................................................................................ 25.7.2 Clock Asynchronous Serial I/O (UART) Mode ............................................................................... 25.7.3 Special Mode 1 (I2C Mode) .............................................................................................................. 26. 26.1 517 517 518 519 520 521 522 522 523 523 524 524 525 526 527 531 531 532 532 533 534 535 539 540 540 541 541 542 542 543 549 550 551 551 551 552 552 552 553 556 557 559 560 560 561 561 Clock Synchronous Serial Interface ............................................................................................ 562 Mode Selection ...................................................................................................................................... 562 A - 14 27. Synchronous Serial Communication Unit (SSU) ........................................................................ 563 563 565 565 566 567 567 568 568 569 570 571 572 573 574 574 576 577 578 579 579 580 582 586 587 588 590 592 593 27.1 Introduction ........................................................................................................................................... 27.2 Registers ................................................................................................................................................ 27.2.1 Module Standby Control Register (MSTCR) ................................................................................... 27.2.2 SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 27.2.3 SS Bit Counter Register (SSBR) ...................................................................................................... 27.2.4 SS Transmit Data Register (SSTDR) ................................................................................................ 27.2.5 SS Receive Data Register (SSRDR) ................................................................................................. 27.2.6 SS Control Register H (SSCRH) ...................................................................................................... 27.2.7 SS Control Register L (SSCRL) ....................................................................................................... 27.2.8 SS Mode Register (SSMR) ............................................................................................................... 27.2.9 SS Enable Register (SSER) .............................................................................................................. 27.2.10 SS Status Register (SSSR) ................................................................................................................ 27.2.11 SS Mode Register 2 (SSMR2) .......................................................................................................... 27.3 Common Items for Multiple Modes ...................................................................................................... 27.3.1 Transfer Clock .................................................................................................................................. 27.3.2 SS Shift Register (SSTRSR) ............................................................................................................. 27.3.3 Interrupt Requests ............................................................................................................................. 27.3.4 Communication Modes and Pin Functions ....................................................................................... 27.4 Clock Synchronous Communication Mode .......................................................................................... 27.4.1 Initialization in Clock Synchronous Communication Mode ............................................................ 27.4.2 Data Transmission ............................................................................................................................ 27.4.3 Data Reception .................................................................................................................................. 27.5 Operation in 4-Wire Bus Communication Mode .................................................................................. 27.5.1 Initialization in 4-Wire Bus Communication Mode ......................................................................... 27.5.2 Data Transmission ............................................................................................................................ 27.5.3 Data Reception .................................................................................................................................. 27.5.4 SCS Pin Control and Arbitration ...................................................................................................... 27.6 Notes on Synchronous Serial Communication Unit .............................................................................. 28. I2C bus Interface ......................................................................................................................... 594 594 597 597 597 598 598 599 600 601 602 603 604 604 605 605 606 607 607 28.1 Introduction ........................................................................................................................................... 28.2 Registers ................................................................................................................................................ 28.2.1 Module Standby Control Register (MSTCR) ................................................................................... 28.2.2 SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 28.2.3 IIC bus Transmit Data Register (ICDRT) ......................................................................................... 28.2.4 IIC bus Receive Data Register (ICDRR) .......................................................................................... 28.2.5 IIC bus Control Register 1 (ICCR1) ................................................................................................. 28.2.6 IIC bus Control Register 2 (ICCR2) ................................................................................................. 28.2.7 IIC bus Mode Register (ICMR) ........................................................................................................ 28.2.8 IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 28.2.9 IIC bus Status Register (ICSR) ......................................................................................................... 28.2.10 Slave Address Register (SAR) .......................................................................................................... 28.2.11 IIC bus Shift Register (ICDRS) ........................................................................................................ 28.3 Common Items for Multiple Modes ...................................................................................................... 28.3.1 Transfer Clock .................................................................................................................................. 28.3.2 Interrupt Requests ............................................................................................................................. 28.4 I2C bus Interface Mode ......................................................................................................................... 28.4.1 I2C bus Format ................................................................................................................................. A - 15 28.4.2 28.4.3 28.4.4 28.4.5 28.5 28.5.1 28.5.2 28.5.3 28.6 28.7 28.8 28.9 29. Master Transmit Operation ............................................................................................................... Master Receive Operation ................................................................................................................ Slave Transmit Operation ................................................................................................................. Slave Receive Operation ................................................................................................................... Clock Synchronous Serial Mode ........................................................................................................... Clock Synchronous Serial Format .................................................................................................... Transmit Operation ........................................................................................................................... Receive Operation ............................................................................................................................. Register Setting Examples ..................................................................................................................... Noise Canceller ..................................................................................................................................... Bit Synchronization Circuit ................................................................................................................... Notes on I2C bus Interface .................................................................................................................... 608 610 613 616 618 618 619 620 621 625 626 627 Hardware LIN .............................................................................................................................. 628 Introduction ........................................................................................................................................... Input/Output Pins .................................................................................................................................. Registers ................................................................................................................................................ LIN Control Register 2 (LINCR2) .................................................................................................... LIN Control Register (LINCR) ......................................................................................................... LIN Status Register (LINST) ............................................................................................................ Functional Description .......................................................................................................................... Master Mode ..................................................................................................................................... Slave Mode ....................................................................................................................................... Bus Collision Detection Function ..................................................................................................... Hardware LIN End Processing ......................................................................................................... Interrupt Requests .................................................................................................................................. Notes on Hardware LIN ........................................................................................................................ 628 629 629 629 630 630 631 631 634 638 639 640 641 29.1 29.2 29.3 29.3.1 29.3.2 29.3.3 29.4 29.4.1 29.4.2 29.4.3 29.4.4 29.5 29.6 30. A/D Converter ............................................................................................................................. 642 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ On-Chip Reference Voltage Control Register (OCVREFCR) ......................................................... A/D Register i (ADi) (i = 0 to 7) ...................................................................................................... A/D Mode Register (ADMOD) ........................................................................................................ A/D Input Select Register (ADINSEL) ............................................................................................ A/D Control Register 0 (ADCON0) ................................................................................................. A/D Control Register 1 (ADCON1) ................................................................................................. Common Items for Multiple Modes ...................................................................................................... Input/Output Pins .............................................................................................................................. A/D Conversion Cycles .................................................................................................................... A/D Conversion Start Conditions ..................................................................................................... A/D Conversion Result ..................................................................................................................... Low-Current-Consumption Function ............................................................................................... Extended Analog Input Pins ............................................................................................................. A/D Open-Circuit Detection Assist Function ................................................................................... One-Shot Mode ..................................................................................................................................... Repeat Mode 0 ....................................................................................................................................... Repeat Mode 1 ....................................................................................................................................... Single Sweep Mode ............................................................................................................................... A - 16 642 644 644 645 646 647 648 648 649 649 649 651 653 653 653 653 655 656 657 659 30.1 30.2 30.2.1 30.2.2 30.2.3 30.2.4 30.2.5 30.2.6 30.3 30.3.1 30.3.2 30.3.3 30.3.4 30.3.5 30.3.6 30.3.7 30.4 30.5 30.6 30.7 30.8 30.9 30.10 30.11 31. Repeat Sweep Mode .............................................................................................................................. Internal Equivalent Circuit of Analog Input .......................................................................................... Output Impedance of Sensor during A/D Conversion .......................................................................... Notes on A/D Converter ........................................................................................................................ 661 663 664 665 D/A Converter ............................................................................................................................. 666 666 668 668 668 31.1 Introduction ........................................................................................................................................... 31.2 Registers ................................................................................................................................................ 31.2.1 D/Ai Register (DAi) (i = 0 or 1) ....................................................................................................... 31.2.2 D/A Control Register (DACON) ...................................................................................................... 32. Comparator A ............................................................................................................................. 669 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ Voltage Monitor Circuit/Comparator A Control Register (CMPA) ................................................. Voltage Monitor Circuit Edge Select Register (VCAC) .................................................................. Voltage Detect Register 1 (VCA1) ................................................................................................... Voltage Detect Register 2 (VCA2) ................................................................................................... Voltage Monitor 1 Circuit Control Register (VW1C) ................................................................... Voltage Monitor 2 Circuit Control Register (VW2C) ..................................................................... Monitoring Comparison Results ........................................................................................................... Monitoring Comparator A1 .............................................................................................................. Monitoring Comparator A2 .............................................................................................................. Functional Description .......................................................................................................................... Comparator A1 ................................................................................................................................. Comparator A2 ................................................................................................................................. Comparator A1 and Comparator A2 Interrupts ..................................................................................... Non-Maskable Interrupts .................................................................................................................. Maskable Interrupts .......................................................................................................................... 669 671 671 672 672 673 674 675 676 676 676 677 677 680 683 683 683 32.1 32.2 32.2.1 32.2.2 32.2.3 32.2.4 32.2.5 32.2.6 32.3 32.3.1 32.3.2 32.4 32.4.1 32.4.2 32.5 32.5.1 32.5.2 33. Comparator B ............................................................................................................................. 684 Introduction ........................................................................................................................................... Registers ................................................................................................................................................ Comparator B Control Register 0 (INTCMP) .................................................................................. External Input Enable Register 0 (INTEN) ...................................................................................... INT Input Filter Select Register 0 (INTF) ........................................................................................ Functional Description .......................................................................................................................... Comparator Bi Digital Filter (i = 1 or 3) .......................................................................................... Comparator B1 and Comparator B3 Interrupts ..................................................................................... 684 686 686 686 687 688 689 690 33.1 33.2 33.2.1 33.2.2 33.2.3 33.3 33.3.1 33.4 34. LCD Drive Control Circuit ........................................................................................................... 691 692 694 694 695 696 696 697 697 34.1 Introduction ........................................................................................................................................... 34.2 Registers ................................................................................................................................................ 34.2.1 LCD Control Register (LCR0) ......................................................................................................... 34.2.2 LCD Bias Control Register (LCR1) ................................................................................................. 34.2.3 LCD Display Control Register (LCR2) ............................................................................................ 34.2.4 LCD Clock Control Register (LCR3) ............................................................................................... 34.2.5 LCD Port Select Register 0 (LSE0) .................................................................................................. 34.2.6 LCD Port Select Register 1 (LSE1) .................................................................................................. A - 17 34.2.7 LCD Port Select Register 2 (LSE2) .................................................................................................. 34.2.8 LCD Port Select Register 3 (LSE3) .................................................................................................. 34.2.9 LCD Port Select Register 4 (LSE4) .................................................................................................. 34.2.10 LCD Port Select Register 5 (LSE5) .................................................................................................. 34.2.11 LCD Port Select Register 6 (LSE6) .................................................................................................. 34.2.12 LCD Port Select Register 7 (LSE7) .................................................................................................. 34.3 Data Registers ........................................................................................................................................ 34.4 LCD Drive Control ................................................................................................................................ 34.4.1 Segment Output Pin Selection .......................................................................................................... 34.4.2 LCD Clock Selection ........................................................................................................................ 34.4.3 LCD Data Display Control ............................................................................................................... 34.4.4 Bias Control ...................................................................................................................................... 34.4.5 LCD Data Display ............................................................................................................................ 34.4.6 Pin Status in Stop Mode .................................................................................................................... 34.4.7 Pin Status in Power-Off Mode .......................................................................................................... 34.5 LCD Drive Waveform ........................................................................................................................... 34.5.1 Segment Panel Control Waveform ................................................................................................... 34.5.2 Dot Matrix Panel Control Waveform ............................................................................................... 34.6 Notes on LCD Drive Control Circuit .................................................................................................... 34.6.1 Voltage Multiplier ............................................................................................................................. 34.6.2 When Division Resistors are Connected Externally ......................................................................... 35. 698 698 699 699 700 700 701 703 704 704 704 704 705 705 706 707 707 713 719 719 719 Flash Memory ............................................................................................................................. 720 720 721 723 723 724 724 725 726 728 730 732 733 733 733 734 735 736 737 747 747 747 747 747 748 750 750 35.1 Introduction ........................................................................................................................................... 35.2 Memory Map ......................................................................................................................................... 35.3 Functions to Prevent Flash Memory from being Rewritten .................................................................. 35.3.1 ID Code Check Function .................................................................................................................. 35.3.2 ROM Code Protect Function ............................................................................................................ 35.3.3 Option Function Select Register (OFS) ............................................................................................ 35.4 CPU Rewrite Mode ............................................................................................................................... 35.4.1 Flash Memory Status Register (FST) ............................................................................................... 35.4.2 Flash Memory Control Register 0 (FMR0) ...................................................................................... 35.4.3 Flash Memory Control Register 1 (FMR1) ...................................................................................... 35.4.4 Flash Memory Control Register 2 (FMR2) ...................................................................................... 35.4.5 EW0 Mode ........................................................................................................................................ 35.4.6 EW1 Mode ........................................................................................................................................ 35.4.7 Suspend Operation ............................................................................................................................ 35.4.8 How to Set and Exit Each Mode ....................................................................................................... 35.4.9 BGO (BackGround Operation) Function .......................................................................................... 35.4.10 Data Protect Function ....................................................................................................................... 35.4.11 Software Commands ......................................................................................................................... 35.4.12 Status Register .................................................................................................................................. 35.4.13 Sequence Status ................................................................................................................................ 35.4.14 Erase Status ....................................................................................................................................... 35.4.15 Program Status .................................................................................................................................. 35.4.16 Suspend Status .................................................................................................................................. 35.4.17 Full Status Check .............................................................................................................................. 35.5 Standard Serial I/O Mode ...................................................................................................................... 35.5.1 ID Code Check Function .................................................................................................................. A - 18 35.6 Parallel I/O Mode .................................................................................................................................. 35.6.1 ROM Code Protect Function ............................................................................................................ 35.7 Notes on Flash Memory ........................................................................................................................ 35.7.1 CPU Rewrite Mode ........................................................................................................................... 36. 37. 753 753 754 754 Electrical Characteristics ............................................................................................................ 757 Usage Notes ............................................................................................................................... 758 758 758 758 759 759 759 759 760 760 760 760 761 762 763 763 763 763 764 764 764 764 765 766 766 766 767 767 768 768 768 768 768 768 768 769 769 769 770 770 770 770 37.1 Notes on Clock Generation Circuit ....................................................................................................... 37.1.1 Oscillation Stop Detection Function ................................................................................................. 37.1.2 Oscillation Circuit Constants ............................................................................................................ 37.2 Notes on Power Control ........................................................................................................................ 37.2.1 Stop Mode ......................................................................................................................................... 37.2.2 Wait Mode ........................................................................................................................................ 37.2.3 Power-Off Mode ............................................................................................................................... 37.3 Notes on Interrupts ................................................................................................................................ 37.3.1 Reading Address 00000h .................................................................................................................. 37.3.2 SP Setting .......................................................................................................................................... 37.3.3 External Interrupt, Key Input Interrupt ............................................................................................. 37.3.4 Changing Interrupt Sources .............................................................................................................. 37.3.5 Rewriting Interrupt Control Register ................................................................................................ 37.4 Notes on ID Code Areas ........................................................................................................................ 37.4.1 Setting Example of ID Code Areas ................................................................................................... 37.5 Notes on Option Function Select Area .................................................................................................. 37.5.1 Setting Example of Option Function Select Area ............................................................................. 37.6 Notes on DTC ........................................................................................................................................ 37.6.1 DTC activation source ...................................................................................................................... 37.6.2 DTCENi (i = 0 to 6) Registers .......................................................................................................... 37.6.3 Peripheral Modules ........................................................................................................................... 37.7 Notes on Timer RA ............................................................................................................................... 37.8 Notes on Timer RB ................................................................................................................................ 37.8.1 Timer Mode ...................................................................................................................................... 37.8.2 Programmable Waveform Generation Mode .................................................................................... 37.8.3 Programmable One-Shot Generation Mode ..................................................................................... 37.8.4 Programmable Wait One-shot Generation Mode ............................................................................. 37.9 Notes on Timer RC ................................................................................................................................ 37.9.1 TRC Register .................................................................................................................................... 37.9.2 TRCSR Register .............................................................................................................................. 37.9.3 TRCCR1 Register ............................................................................................................................. 37.9.4 Count Source Switching ................................................................................................................... 37.9.5 Input Capture Function ..................................................................................................................... 37.9.6 TRCMR Register in PWM2 Mode ................................................................................................... 37.10 Notes on Timer RD ............................................................................................................................... 37.10.1 TRDSTR Register ............................................................................................................................. 37.10.2 TRDi Register (i = 0 or 1) ................................................................................................................. 37.10.3 TRDSRi Register (i = 0 or 1) ............................................................................................................ 37.10.4 Count Source Switching ................................................................................................................... 37.10.5 Input Capture Function ..................................................................................................................... 37.10.6 Reset Synchronous PWM Mode ....................................................................................................... A - 19 37.10.7 Complementary PWM Mode ............................................................................................................ 37.10.8 Count Source fOCO40M .................................................................................................................. 37.11 Notes on Timer RE ................................................................................................................................ 37.11.1 Reset .................................................................................................................................................. 37.11.2 Starting and Stopping Count ............................................................................................................. 37.11.3 Register Setting ................................................................................................................................. 37.11.4 Time Reading Procedure in Real-Time Clock Mode ....................................................................... 37.12 Notes on Timer RG ............................................................................................................................... 37.12.1 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ........................................... 37.13 Notes on Serial Interface (UARTi (i = 0 or 1)) ..................................................................................... 37.14 Notes on Serial Interface (UART2) ....................................................................................................... 37.14.1 Clock Synchronous Serial I/O Mode ................................................................................................ 37.14.2 Clock Asynchronous Serial I/O (UART) Mode ............................................................................... 37.14.3 Special Mode 1 (I2C Mode) .............................................................................................................. 37.15 Notes on Synchronous Serial Communication Unit .............................................................................. 37.16 Notes on I2C bus Interface .................................................................................................................... 37.17 Notes on Hardware LIN ........................................................................................................................ 37.18 Notes on A/D Converter ........................................................................................................................ 37.19 Notes on LCD Drive Control Circuit .................................................................................................... 37.19.1 Voltage Multiplier ............................................................................................................................. 37.19.2 When Division Resistors are Connected Externally ......................................................................... 37.20 Notes on Flash Memory ........................................................................................................................ 37.20.1 CPU Rewrite Mode ........................................................................................................................... 37.21 Notes on Noise ..................................................................................................................................... 37.21.1 Inserting Bypass Capacitor between Pins VCC and VSS as Countermeasure against Noise and Latch-up ............................................................................................................................................ 37.21.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 38. 771 774 775 775 775 775 777 778 778 778 779 779 780 780 781 781 781 781 782 782 782 783 783 786 786 786 Notes on On-Chip Debugger ...................................................................................................... 787 Appendix 1. Package Dimensions ........................................................................................................ 788 Appendix 2. Connection Examples with M16C Flash Starter ............................................................... 792 Appendix 3. Connection Examples with E8a Emulator ........................................................................ 797 Appendix 4. Examples of Oscillation Evaluation Circuit ....................................................................... 802 Index ..................................................................................................................................................... 807 A - 20 SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register Flash Memory Ready Interrupt Control Register INT7 Interrupt Control Register INT6 Interrupt Control Register INT5 Interrupt Control Register INT4 Interrupt Control Register Timer RC Interrupt Control Register Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register Timer RE Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU Interrupt Control Register / IIC bus Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Symbol FMRDYIC INT7IC INT6IC INT5IC INT4IC TRCIC TRD0IC TRD1IC TREIC S2TIC S2RIC KUPIC ADIC SSUIC/IICIC Page 175 176 176 176 176 175 175 175 174 174 174 174 174 175 Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register PM0 PM1 CM0 CM1 MSTCR 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register CM3 PRCR RSTFR OCD WDTR WDTS WDTC 51 212 129, 146 130, 147 280, 335, 351, 372, 389, 404, 421, 565, 597 131, 148 168 51 132, 149 212 212 213 S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC TRBIC INT1IC INT3IC 174 174 174 174 176 174 174 176 176 High-Speed On-Chip Oscillator Control Register 7 FRA7 132 Count Source Protection Mode Register CSPR 213 INT0 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register INT0IC U2BCNIC 176 174 Power-Off Mode Control Register 0 POMCR0 152 High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 On-Chip Reference Voltage Control Register FRA0 FRA1 FRA2 OCVREFCR 133, 150 133 134 644 High-Speed On-Chip Oscillator Control Register 4 FRA4 High-Speed On-Chip Oscillator Control Register 5 FRA5 High-Speed On-Chip Oscillator Control Register 6 FRA6 135 135 135 Timer RG Interrupt Control Register TRGIC 175 High-Speed On-Chip Oscillator Control Register 3 FRA3 Voltage Monitor Circuit/Comparator A Control CMPA Register Voltage Monitor Circuit Edge Select Register VCAC Voltage Detect Register 1 Voltage Detect Register 2 VCA1 VCA2 135 64, 671 65, 672 65, 672 66, 151, 673 67 68 69, 674 70, 675 Voltage Monitor 1 / Comparator A1 Interrupt Control Register Voltage Monitor 2 / Comparator A2 Interrupt Control Register VCMP1IC VCMP2IC 174 174 Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register VD1LS VW0C VW1C VW2C Note: 1. Blank spaces are reserved. No access is allowed. B-1 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register DTC Activation Control Register Symbol DTCTL Page 224 DTC Activation Enable Register 0 DTC Activation Enable Register 1 DTC Activation Enable Register 2 DTC Activation Enable Register 3 DTC Activation Enable Register 4 DTC Activation Enable Register 5 DTC Activation Enable Register 6 DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN4 DTCEN5 DTCEN6 223 223 223 223 223 223 223 UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register UART2 Digital Filter Function Select Register U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF 496 496 497 498 498 499 517 517 518 519 520 521 522 UART2 Special Mode Register 5 UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register U2SMR5 U2SMR4 U2SMR3 U2SMR2 U2SMR 522 523 523 524 524 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Page 645 645 645 645 645 645 645 645 A/D Mode Register A/D Input Select Register A/D Control Register 0 A/D Control Register 1 D/A0 Register D/A1 Register ADMOD ADINSEL ADCON0 ADCON1 DA0 DA1 646 647 648 648 668 668 D/A Control Register DACON 668 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 86 86 85 85 86 86 85 85 86 86 85 85 86 86 85 85 Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register P10 P11 PD10 PD11 P12 P13 PD12 PD13 86 86 85 85 86 86 85 85 Note: 1. Blank spaces are reserved. No access is allowed. B-2 Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register Symbol TRACR TRAIOC 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register 2 LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC Page 241 241, 244, 247, 249, 251, 254 242 242 243 629 630 630 258 258 259, 262, 266, 269, 273 259 260 260 261 Address Register 0130h Timer RC Control Register 2 0131h Timer RC Digital Filter Function Select Register 0132h Timer RC Output Master Enable Register 0133h Timer RC Trigger Control Register 0134h 0135h Timer RD Control Expansion Register 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h Timer RD Trigger Control Register Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1 Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Timer RD General Register A0 Timer RD General Register B0 Timer RD General Register C0 Timer RD General Register D0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 Timer RD General Register A1 Timer RD General Register B1 Timer RD General Register C1 Timer RD General Register D1 Symbol TRCCR2 TRCDF TRCOER TRCADCR TRDECR TRDADCR TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1 TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 Page 286, 313, 319 286, 319 287 287 335, 352, 373, 390, 404, 421 352, 373, 390, 422 336, 353, 374, 391, 406, 423 336, 354, 374, 391, 406, 423 337, 354, 375 337, 355, 375, 392, 407, 424 356, 376, 393, 408, 425 356, 376, 393, 408, 425 357, 377, 426 338 338 339, 358, 377, 394, 409, 427 340, 359 341, 360 342, 361, 378, 395, 410, 428 343, 362, 379, 396, 411, 429 379 343, 362, 380, 396, 411, 429 344, 363, 381, 397, 412, 430 344, 363, 381, 397, 412, 430 344, 363, 381, 397, 430 344, 363, 381, 397, 412, 430 339, 358, 377, 409 340, 359 341, 360 342, 361, 378, 395, 410, 428 343, 362, 379, 396, 411, 429 379 343, 362, 380, 412 344, 363, 381, 397, 412, 430 344, 363, 381, 397, 412, 430 344, 363, 381, 397, 412, 430 344, 363, 381, 397, 412, 430 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register TRBMR TRBPRE TRBSC TRBPR Timer RE Second Data Register / Timer RE Counter Data Register Timer RE Minute Data Register / Timer RE Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD 447, 454 447, 454 448 448 449, 455 450, 455 451, 456 281 282, 304, 312, 318 282 283 284, 299, 305 284, 300, 306 285 285 285 285 285 Note: 1. Blank spaces are reserved. No access is allowed. 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh B-3 Address 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register Symbol U1MR U1BRG U1TB U1C0 U1C1 U1RB Page 496 496 497 498 498 499 Address Register 0190h 0191h 0192h 0193h SS Bit Counter Register 0194h SS Transmit Data Register L / IIC bus Transmit Data Register 0195h SS Transmit Data Register H 0196h SS Receive Data Register L / IIC bus Receive Data Register 0197h SS Receive Data Register H 0198h SS Control Register H / IIC bus Control Register 1 0199h SS Control Register L / IIC bus Control Register 2 019Ah SS Mode Register / IIC bus Mode Register 019Bh SS Enable Register / IIC bus Interrupt Enable Register SS Status Register / IIC bus Status Register SS Mode Register 2 / Slave Address Register Symbol Page Timer RG Mode Register Timer RG Count Control Register Timer RG Control Register Timer RG Interrupt Enable Register Timer RG Status Register Timer RG I/O Control Register Timer RG Counter Timer RG General Register A Timer RG General Register B Timer RG General Register C Timer RG General Register D Timer RA Pin Select Register Timer RB/RC Pin Select Register Timer RC Pin Select Register 0 Timer RC Pin Select Register 1 Timer RD Pin Select Register 0 TRGMR TRGCNTC TRGCR TRGIER TRGSR TRGIOR TRG TRGGRA TRGGRB TRGGRC TRGGRD TRASR TRBRCSR TRCPSR0 TRCPSR1 TRDPSR0 463 464 465, 489 466 467 468, 477, 481 469 470 470 470 470 87, 243 88, 261, 288 89, 289 90, 290 91, 345, 364, 382, 398, 414, 432 92, 346, 365, 383, 399, 415, 433 93 93, 500 94, 501 95, 525 96, 526 97, 566, 597 98, 192 99, 185 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh SSBR SSTDR/ ICDRT SSTDRH SSRDR/ ICDRR SSRDRH SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR 567 567, 598 567 568, 598 568 568, 599 569, 600 570, 601 571, 602 572, 603 573, 604 0185h Timer RD Pin Select Register 1 TRDPSR1 Flash Memory Status Register Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2 FST FMR0 FMR1 FMR2 726 728 730 732 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh Timer RG Pin Select Register UART0 Pin Select Register UART1 Pin Select Register UART2 Pin Select Register 0 UART2 Pin Select Register 1 SSU/IIC Pin Select Register Key Input Pin Select Register INT Interrupt Input Pin Select Register TRGPSR U0SR U1SR U2SR0 U2SR1 SSUIICSR KISR INTSR Note: 1. Blank spaces are reserved. No access is allowed. Address Match Interrupt Register 0 RMAD0 196 Address Match Interrupt Enable Register 0 Address Match Interrupt Register 1 AIER0 RMAD1 196 196 Address Match Interrupt Enable Register 1 AIER1 196 B-4 Address 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh Register Symbol Page Port P0 Pull-Up Control Register Port P1 Pull-Up Control Register Port P2 Pull-Up Control Register Port P3 Pull-Up Control Register Port P4 Pull-Up Control Register Port P5 Pull-Up Control Register Port P6 Pull-Up Control Register Port P7 Pull-Up Control Register P0PUR P1PUR P2PUR P3PUR P4PUR P5PUR P6PUR P7PUR 99 99 99 99 99 99 99 99 Port P10 Pull-Up Control Register Port P11 Pull-Up Control Register Port P12 Pull-Up Control Register Port P13 Pull-Up Control Register P10PUR P11PUR P12PUR P13PUR 100 100 100 100 Port P10 Drive Capacity Control Register Port P11 Drive Capacity Control Register P10DRR P11DRR 100 101 Input Threshold Control Register 0 Input Threshold Control Register 1 Input Threshold Control Register 2 Comparator B Control Register 0 External Input Enable Register 0 External Input Enable Register 1 INT Input Filter Select Register 0 INT Input Filter Select Register 1 Key Input Enable Register 0 Key Input Enable Register 1 VLT0 VLT1 VLT2 INTCMP INTEN INTEN1 INTF INTF1 KIEN KIEN1 101 102 103 686 186, 686 187 188, 687 188 193 194 Note: 1. Blank spaces are reserved. No access is allowed. Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Register LCD Control Register LCD Bias Control Register LCD Display Control Register LCD Clock Control Register Symbol LCR0 LCR1 LCR2 LCR3 Page 694 695 696 696 LCD Port Select Register 0 LCD Port Select Register 1 LCD Port Select Register 2 LCD Port Select Register 3 LCD Port Select Register 4 LCD Port Select Register 5 LCD Port Select Register 6 LCD Port Select Register 7 LSE0 LSE1 LSE2 LSE3 LSE4 LSE5 LSE6 LSE7 697 697 698 698 699 699 700 700 LCD Display Data Register LRA0L LRA1L LRA2L LRA3L LRA4L LRA5L LRA6L LRA7L LRA8L LRA9L LRA10L LRA11L LRA12L LRA13L LRA14L LRA15L LRA16L LRA17L LRA18L LRA19L LRA20L LRA21L LRA22L LRA23L LRA24L LRA25L LRA26L LRA27L LRA28L LRA29L LRA30L LRA31L LRA32L LRA33L LRA34L LRA35L LRA36L LRA37L LRA38L LRA39L LRA40L LRA41L LRA42L LRA43L LRA44L LRA45L LRA46L LRA47L 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 B-5 Address Register 0240h LCD Display Data Register 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h LCD Display Control Data Register 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh Symbol LRA48L LRA49L LRA50L LRA51L LRA52L LRA53L LRA54L LRA55L LRA56L LRA57L LRA58L LRA59L LRA60L LRA61L LRA62L LRA63L LRA64L LRA65L LRA66L LRA67L LRA68L LRA69L LRA70L LRA71L LRA72L LRA73L LRA74L LRA75L LRA76L LRA77L LRA78L LRA79L LRA80L LRA81L LRA82L LRA83L LRA84L LRA85L LRA86L LRA87L LRA88L LRA89L LRA90L LRA91L LRA92L LRA93L LRA94L LRA95L LRA0H LRA1H LRA2H LRA3H LRA4H LRA5H LRA6H LRA7H LRA8H LRA9H LRA10H LRA11H LRA12H LRA13H LRA14H LRA15H Page 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 701 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 Address Register 0280h LCD Display Control Data Register 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh Symbol LRA16H LRA17H LRA18H LRA19H LRA20H LRA21H LRA22H LRA23H LRA24H LRA25H LRA26H LRA27H LRA28H LRA29H LRA30H LRA31H LRA32H LRA33H LRA34H LRA35H LRA36H LRA37H LRA38H LRA39H LRA40H LRA41H LRA42H LRA43H LRA44H LRA45H LRA46H LRA47H LRA48H LRA49H LRA50H LRA51H LRA52H LRA53H LRA54H LRA55H LRA56H LRA57H LRA58H LRA59H LRA60H LRA61H LRA62H LRA63H LRA64H LRA65H LRA66H LRA67H LRA68H LRA69H LRA70H LRA71H LRA72H LRA73H LRA74H LRA75H LRA76H LRA77H LRA78H LRA79H Page 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 Note: 1. Blank spaces are reserved. No access is allowed. B-6 Address Register 02C0h LCD Display Control Data Register 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh Symbol LRA80H LRA81H LRA82H LRA83H LRA84H LRA85H LRA86H LRA87H LRA88H LRA89H LRA90H LRA91H LRA92H LRA93H LRA94H LRA95H Page 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 702 Note: 1. Blank spaces are reserved. No access is allowed. Address 2C00h 2C01h 2C02h 2C03h 2C04h 2C05h 2C06h 2C07h 2C08h 2C09h 2C0Ah : : 2C3Ah 2C3Bh 2C3Ch 2C3Dh 2C3Eh 2C3Fh 2C40h 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh 2C50h 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh Register DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Control Data 0 Symbol Page DTCD0 DTC Control Data 1 DTCD1 DTC Control Data 2 DTCD2 DTC Control Data 3 DTCD3 DTC Control Data 4 DTCD4 DTC Control Data 5 DTCD5 B-7 Address 2C70h 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh 2C90h 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh Register DTC Control Data 6 Symbol DTCD6 Page DTC Control Data 7 DTCD7 DTC Control Data 8 DTCD8 DTC Control Data 9 DTCD9 DTC Control Data 10 DTCD10 DTC Control Data 11 DTCD11 DTC Control Data 12 DTCD12 DTC Control Data 13 DTCD13 Address 2CB0h 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh 2CD0h 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh Register DTC Control Data 14 Symbol DTCD14 Page DTC Control Data 15 DTCD15 DTC Control Data 16 DTCD16 DTC Control Data 17 DTCD17 DTC Control Data 18 DTCD18 DTC Control Data 19 DTCD19 DTC Control Data 20 DTCD20 DTC Control Data 21 DTCD21 Note: 1. Blank spaces are reserved. No access is allowed. B-8 Address 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h 2D01h : 0FFDBh : 0FFFFh Register DTC Control Data 22 Symbol DTCD22 Page DTC Control Data 23 DTCD23 Option Function Select Register 2 Option Function Select Register OFS2 OFS 53, 208, 215 52, 71, 207, 214, 724 Note: 1. Blank spaces are reserved. No access is allowed. B-9 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group RENESAS MCU 1. 1.1 Overview Features The R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, and R8C/L3AB Group of single-chip MCUs incorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency and supports a 1 Mbyte address space, allowing execution of instructions at high speed. In addition, the CPU core integrates a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow for additional power control. These MCUs use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce the number of system components. 1.1.1 Applications Household appliances, office equipment, audio equipment, consumer products, etc. REJ09B0441-0010 Rev.0.10 Page 1 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 1.1.2 Differences between Groups Tables 1.1 and 1.2 list the differences between the groups, and Table 1.3 lists the I/O ports provided for each group. Figures 1.13 to 1.17 show the pin assignment for each group, and Tables 1.7 to 1.14 list product information. The explanations in the chapters which follow apply to the R8C/L3AA Group only. Note the differences shown below. Table 1.1 Item Data flash Differences between Groups (1) Function R8C/L35A Group, R8C/L36A Group R8C/L35B Group, R8C/L36B Group R8C/L38A Group, R8C/L3AA Group R8C/L38B Group, R8C/L3AB Group Provided Not provided 1 KB × 4 blocks with BGO (background operation) function Table 1.2 Item I/O Ports Interrupts Timers Differences between Groups (2) Function Programmable I/O ports High current drive ports INT interrupt pins Key input interrupt pins Timer RA pins (I/O: 1, output: 1) Timer RB pin (output: 1) Timer RD pin (I/O: 8) Timer RE pin (output: 1) Timer RG pin (I/O: 2, output: 2) Analog input pin LCD power supply Common output pins Segment output pins R8C/L35A Group R8C/L35B Group 41 pins 5 pins 5 pins 4 pins 1 pin (I/O pin only) None None None None 12 pins 3 pins (VL1, VL2, VL4) Max. 4 pins Max. 24 pins Not supported 52-pin LQFP R8C/L36A Group R8C/L36B Group 52 pins 8 pins 8 pins 4 pins 2 pins 1 pin None 1 pin None 12 pins 4 pins (VL1 to VL4) Max. 8 pins Max. 32 pins Supported 64-pin LQFP R8C/L38A Group R8C/L38B Group 68 pins 8 pins 8 pins 8 pins 2 pins 1 pin 8 pins 1 pin None 16 pins 4 pins (VL1 to VL4) Max. 8 pins Max. 48 pins Supported 80-pin LQFP R8C/L3AA Group R8C/L3AB Group 88 pins 16 pins 8 pins 8 pins 2 pins 1 pin 8 pins 1 pin 4 pins 20 pins 4 pins (VL1 to VL4) Max. 8 pins Max. 56 pins Supported 100-pin LQFP/ 100-pin QFP A/D Converter LCD Drive Control Circuit Other Pin Function Packages WKUP1 Note: 1. I/O ports are shared with I/O functions, such as interrupts or timers. Refer to Tables 1.15 to 1.17, Pin Name Information by Pin Number, for details. Table 1.3 Programmable I/O Port Programmable I/O Ports Provided for Each Group R8C/L35A Group R8C/L35B Group Total: 41 I/O pins bit 7 bit 6 √ − √ − √ − − √ − − − − bit 5 √ − √ − √ − − √ − − − − bit 4 √ − √ − √ − − √ − √ − − bit 3 √ − − √ √ − − − − √ √ √ bit 2 √ − − √ √ − − − − √ √ √ bit 1 √ − − √ √ − − − − √ √ √ bit 0 √ − − √ √ − − − − √ √ √ bit 7 √ − √ √ √ − − √ − √ − − √ − √ − √ − − √ − − − − R8C/L36A Group R8C/L36B Group Total: 52 I/O pins bit 6 √ − √ √ √ − − √ − √ − − bit 5 √ − √ √ √ − − √ − √ − − bit 4 √ − √ √ √ − − √ − √ − − bit 3 √ − − √ √ − − √ − √ √ √ bit 2 √ − − √ √ − − √ − √ √ √ bit 1 √ − − √ √ − − √ − √ √ √ bit 0 √ − − √ √ − − √ − √ √ √ bit 7 √ − √ √ √ − √ √ − √ − − R8C/L38A Group R8C/L38B Group Total: 68 I/O pins bit 6 √ − √ √ √ − √ √ − √ − − bit 5 √ − √ √ √ − √ √ − √ − − bit 4 √ − √ √ √ − √ √ − √ − − bit 3 √ √ √ √ √ − √ √ − √ √ √ bit 2 √ √ √ √ √ − √ √ − √ √ √ bit 1 √ √ √ √ √ − √ √ − √ √ √ bit 0 √ √ √ √ √ − √ √ − √ √ √ bit 7 √ √ √ √ √ − √ √ √ √ − √ R8C/L3AA Group R8C/L3AB Group Total: 88 I/O pins bit 6 √ √ √ √ √ − √ √ √ √ − √ bit 5 √ √ √ √ √ − √ √ √ √ − √ bit 4 √ √ √ √ √ − √ √ √ √ − √ bit 3 √ √ √ √ √ √ √ √ √ √ √ √ bit 2 √ √ √ √ √ √ √ √ √ √ √ √ bit 1 √ √ √ √ √ √ √ √ √ √ √ √ bit 0 √ √ √ √ √ √ √ √ √ √ √ √ P0 P1 P2 P3 P4 P5 P6 P7 P10 P11 P12 P13 Note: 1. The symbol “√” indicates a programmable I/O port. REJ09B0441-0010 Rev.0.10 Page 2 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 1.1.3 Specifications Tables 1.4 to 1.6 list the specifications. Table 1.4 Item CPU Specifications (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Refer to Tables 1.7 to 1.14 Product Lists. • Power-on reset • Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) Memory Power Supply Voltage Detection I/O Ports Programmable R8C/L35A Group I/O ports R8C/L35B Group R8C/L36A Group R8C/L36B Group R8C/L38A Group R8C/L38B Group R8C/L3AA Group R8C/L3AB Group Clock Clock generation circuits ROM/RAM Data flash Voltage detection circuit • CMOS I/O ports: 41, selectable pull-up resistor • High current drive ports: 5 • CMOS I/O ports: 52, selectable pull-up resistor • High current drive ports: 8 • CMOS I/O ports: 68, selectable pull-up resistor • High current drive ports: 8 • CMOS I/O ports: 88, selectable pull-up resistor • High current drive ports: 16 4 circuits: XIN clock oscillation circuit XCIN clock oscillation circuit (32 kHz) High-speed on-chip oscillator (with frequency adjustment function) Low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Division ratio selectable from 1, 2, 4, 8, and 16 • Low-power-consumption modes: Standard operating mode (high-speed clock, low-speed clock, highspeed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode, power-off mode Real-time clock (timer RE) Interrupts R8C/L35A Group • Number of interrupt vectors: 69 R8C/L35B Group • External Interrupt: 9 (INT × 5, key input × 4) • Priority levels: 7 levels R8C/L36A Group • Number of interrupt vectors: 69 R8C/L36B Group • External Interrupt: 12 (INT × 8, key input × 4) • Priority levels: 7 levels R8C/L38A Group • Number of interrupt vectors: 69 R8C/L38B Group • External Interrupt: 16 (INT × 8, key input × 8) • Priority levels: 7 levels R8C/L3AA Group • Number of interrupt vectors: 69 R8C/L3AB Group • External Interrupt: 16 (INT × 8, key input × 8) • Priority levels: 7 levels Watchdog Timer • 14 bits × 1 (with prescaler) • Selectable reset start function • Selectable low-speed on-chip oscillator for watchdog timer DTC (Data Transfer Controller) • 1 channel • Activation sources: 38 • Transfer modes: 2 (normal mode, repeat mode) REJ09B0441-0010 Rev.0.10 Page 3 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.5 Item Timer Specifications (2) Function Timer RA Specification 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output: 3 pins), PWM2 mode (PWM output: 1 pin) 16 bits × 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output: 6 pins), reset synchronous PWM mode (three-phase waveform output: 6 pins, sawtooth wave modulation), complementary PWM mode (three-phase waveform output: 6 pins, triangular wave modulation), PWM3 mode (PWM output with fixed period: 2 pins) 8 bits × 1 Real-time clock mode (counting of seconds, minutes, hours, days of week), output compare mode 16 bits × 1 Phase-counting mode, timer mode (output compare function, input capture function), PWM mode (output: 1 pin) Clock synchronous serial I/O/UART × 2 channels Clock synchronous serial I/O/UART, I2C mode (I2C-bus), multiprocessor communication function 1 (shared with I2C-bus) 1 (shared with SSU) Hardware LIN: 1 channel (timer RA, UART0 used) 10-bit resolution × 12 channels, including sample and hold function, with sweep mode 10-bit resolution × 12 channels, including sample and hold function, with sweep mode 10-bit resolution × 16 channels, including sample and hold function, with sweep mode 10-bit resolution × 20 channels, including sample and hold function, with sweep mode 8-bit resolution × 2 circuits • 2 circuits (shared with voltage monitor 1 and voltage monitor 2) • External reference voltage input available 2 circuits Common output: Max. 4 pins Bias: 1/2, 1/3 Segment output: Max. 24 pins Duty: static, 1/2, 1/3, 1/4 Common output: Max. 8 pins Segment output: Max. 32 pins (1) Common output: Max. 8 pins Bias: 1/2, 1/3, 1/4 Duty: static, 1/2, 1/3, 1/4, 1/8 Segment output: Max. 48 pins (1) Common output: Max. 8 pins Segment output: Max. 56 pins (1) Voltage multiplier and dedicated regulator integrated Timer RB Timer RC Timer RD Timer RE Timer RG Serial Interface UART0, UART1 UART2 Synchronous Serial Communication Unit (SSU) I2C bus LIN Module A/D R8C/L35A Group Converter R8C/L35B Group R8C/L36A Group R8C/L36B Group R8C/L38A Group R8C/L38B Group R8C/L3AA Group R8C/L3AB Group D/A Converter Comparator A Comparator B R8C/L35A Group LCD Drive R8C/L35B Group Control R8C/L36A Group Circuit R8C/L36B Group R8C/L38A Group R8C/L38B Group R8C/L3AA Group R8C/L3AB Group Notes: 1. This applies when four pins are selected for common output. REJ09B0441-0010 Rev.0.10 Page 4 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.6 Item Flash Memory Specifications (2) Function R8C/L35A Group R8C/L36A Group R8C/L38A Group R8C/L3AA Group Specification • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function • Background operation (BGO) function • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 1,000 times • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V) TBD (VCC = 5.0 V, f(XIN) = 20 MHz) TBD (VCC = 3.0 V, f(XIN) = 10 MHz) TBD (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)) TBD (VCC = 3.0 V, stop mode) TBD (VCC = 3.0 V, power-off mode, timer RE enabled) TBD (VCC = 3.0 V, power-off mode, timer RE disabled) -20 to 85°C (N version) -40 to 85°C (D version) (1) R8C/L35B Group R8C/L36B Group R8C/L38B Group R8C/L3AB Group Operating Frequency/ Supply Voltage Current Consumption Operating Ambient Temperature Note: 1. Specify the D version if D version functions are to be used. REJ09B0441-0010 Rev.0.10 Page 5 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 1.2 Product Lists Tables 1.7 to 1.14 list product information for each group. Figure 1.1 to 1.8 show the Correspondence of Part No., with Memory Size and Package of R8C/Lx Group. Table 1.7 Product List for R8C/L35A Group Internal ROM Capacity Program ROM Data Flash 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 Internal RAM Capacity 6 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A Current of Jul 2008 Remarks N Version Part No. R5F2L357ANFP R5F2L358ANFP R5F2L35AANFP R5F2L35CANFP R5F2L357ADFP R5F2L358ADFP R5F2L35AADFP R5F2L35CADFP (D) (D) (D) (D) (D) (D) (D) (D) D Version (D): Under development Part No. R 5 F 2L 35 C A N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L35A Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Correspondence of Part No., with Memory Size and Package of R8C/L35A Group REJ09B0441-0010 Rev.0.10 Page 6 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.8 Product List for R8C/L35B Group Internal ROM Capacity (D) (D) (D) (D) (D) (D) (D) (D) 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Internal RAM Capacity 6 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A Current of Jul 2008 Remarks N Version Part No. R5F2L357BNFP R5F2L358BNFP R5F2L35ABNFP R5F2L35CBNFP R5F2L357BDFP R5F2L358BDFP R5F2L35ABDFP R5F2L35CBDFP D Version (D): Under development Part No. R 5 F 2L 35 C B N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L35B Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.2 Correspondence of Part No., with Memory Size and Package of R8C/L35B Group REJ09B0441-0010 Rev.0.10 Page 7 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.9 Product List for R8C/L36A Group Internal ROM Capacity Program ROM Data Flash 48 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 Internal RAM Capacity 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A Current of Jul 2008 Remarks N Version Part No. R5F2L367ANFP R5F2L367ANFA R5F2L368ANFP R5F2L368ANFA R5F2L36AANFP R5F2L36AANFA R5F2L36CANFP R5F2L36CANFA R5F2L367ADFP R5F2L367ADFA R5F2L368ADFP R5F2L368ADFA R5F2L36AADFP R5F2L36AADFA R5F2L36CADFP R5F2L36CADFA (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) D Version (D): Under development Part No. R 5 F 2L 36 C A N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L36A Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.3 Correspondence of Part No., with Memory Size and Package of R8C/L36A Group REJ09B0441-0010 Rev.0.10 Page 8 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.10 Product List for R8C/L36B Group Internal ROM Capacity (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) 48 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes 48 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes Internal RAM Capacity 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A Current of Jul 2008 Remarks N Version Part No. R5F2L367BNFP R5F2L367BNFA R5F2L368BNFP R5F2L368BNFA R5F2L36ABNFP R5F2L36ABNFA R5F2L36CBNFP R5F2L36CBNFA R5F2L367BDFP R5F2L367BDFA R5F2L368BDFP R5F2L368BDFA R5F2L36ABDFP R5F2L36ABDFA R5F2L36CBDFP R5F2L36CBDFA D Version (D): Under development Part No. R 5 F 2L 36 C B N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L36B Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.4 Correspondence of Part No., with Memory Size and Package of R8C/L36B Group REJ09B0441-0010 Rev.0.10 Page 9 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.11 Product List for R8C/L38A Group Internal ROM Capacity Program ROM Data Flash 48 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 Internal RAM Capacity 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A Current of Jul 2008 Remarks N Version Part No. R5F2L387ANFP R5F2L387ANFA R5F2L388ANFP R5F2L388ANFA R5F2L38AANFP R5F2L38AANFA R5F2L38CANFP R5F2L38CANFA R5F2L387ADFP R5F2L387ADFA R5F2L388ADFP R5F2L388ADFA R5F2L38AADFP R5F2L38AADFA R5F2L38CADFP R5F2L38CADFA (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) D Version (D): Under development Part No. R 5 F 2L 38 C A N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L38A Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.5 Correspondence of Part No., with Memory Size and Package of R8C/L38A Group REJ09B0441-0010 Rev.0.10 Page 10 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.12 Product List for R8C/L38B Group Internal ROM Capacity (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) 48 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes 48 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes Internal RAM Capacity 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A PLQP0080KB-A PLQP0080JA-A Current of Jul 2008 Remarks N Version Part No. R5F2L387BNFP R5F2L387BNFA R5F2L388BNFP R5F2L388BNFA R5F2L38ABNFP R5F2L38ABNFA R5F2L38CBNFP R5F2L38CBNFA R5F2L387BDFP R5F2L387BDFA R5F2L388BDFP R5F2L388BDFA R5F2L38ABDFP R5F2L38ABDFA R5F2L38CBDFP R5F2L38CBDFA D Version (D): Under development Part No. R 5 F 2L 38 C B N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L38B Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.6 Correspondence of Part No., with Memory Size and Package of R8C/L38B Group REJ09B0441-0010 Rev.0.10 Page 11 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.13 Product List for R8C/L3AA Group Internal ROM Capacity Program ROM Data Flash 48 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 Internal RAM Capacity 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B Current of Jul 2008 Remarks N Version Part No. R5F2L3A7ANFP R5F2L3A7ANFA R5F2L3A8ANFP R5F2L3A8ANFA R5F2L3AAANFP R5F2L3AAANFA R5F2L3ACANFP R5F2L3ACANFA R5F2L3A7ADFP R5F2L3A7ADFA R5F2L3A8ADFP R5F2L3A8ADFA R5F2L3AAADFP R5F2L3AAADFA R5F2L3ACADFP R5F2L3ACADFA (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) D Version (D): Under development Part No. R 5 F 2L 3A C A N FP Package type: FP: LQFP (0.50 mm pin pitch) FA: LQFP (0.65 mm pin pitch) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L3AA Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.7 Correspondence of Part No., with Memory Size and Package of R8C/L3AA Group REJ09B0441-0010 Rev.0.10 Page 12 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.14 Product List for R8C/L3AB Group Internal ROM Capacity (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) 48 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes 48 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes Internal RAM Capacity 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 6 Kbytes 8 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes 10 Kbytes Package Type PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B PLQP0100KB-A PRQP0100JD-B Current of Jul 2008 Remarks N Version Part No. R5F2L3A7BNFP R5F2L3A7BNFA R5F2L3A8BNFP R5F2L3A8BNFA R5F2L3AABNFP R5F2L3AABNFA R5F2L3ACBNFP R5F2L3ACBNFA R5F2L3A7BDFP R5F2L3A7BDFA R5F2L3A8BDFP R5F2L3A8BDFA R5F2L3AABDFP R5F2L3AABDFA R5F2L3ACBDFP R5F2L3ACBDFA D Version (D): Under development Part No. R 5 F 2L 3A C B N FP Package type: FP: LQFP (0.50 mm pin pitch) FA: LQFP (0.65 mm pin pitch) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L3AB Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.8 Correspondence of Part No., with Memory Size and Package of R8C/L3AB Group REJ09B0441-0010 Rev.0.10 Page 13 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 1.3 Block Diagrams Figure 1.9 shows a Block Diagram of R8C/L35A and R8C/L35B Groups. Figure 1.10 shows a Block Diagram of R8C/L36A and R8C/L36B Groups. Figure 1.11 shows a Block Diagram of R8C/L38A and R8C/L38B Groups. Figure 1.12 shows a Block Diagram of R8C/L3AA and R8C/L3AB Groups. 8 4 4 8 I/O ports Port P0 Port P2 Port P3 Port P4 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) UART or clock synchronous serial I/O (8 bits × 3) I C bus or SSU (8 bits × 1) 2 System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Port P7 4 LIN module DTC Port P11 Watchdog timer (14 bits) Comparator A LCD drive control circuit Common output: Max. 4 pins Segment output: Max. 24 pins 5 Port P12 A/D converter (10 bits × 12 channels) Comparator B 4 D/A converter (8 bits × 2 channels) R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory Port P13 ROM (1) 4 RAM (2) Multiplier Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. Figure 1.9 Block Diagram of R8C/L35A and R8C/L35B Groups REJ09B0441-0010 Rev.0.10 Page 14 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 8 4 8 8 I/O ports Port P0 Port P2 Port P3 Port P4 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Port P7 8 LIN module DTC Port P11 Watchdog timer (14 bits) Comparator A LCD drive control circuit Common output: Max. 8 pins Segment output: Max. 32 pins 8 Port P12 A/D converter (10 bits × 12 channels) Comparator B 4 D/A converter (8 bits × 2 channels) R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory Port P13 ROM (1) 4 RAM (2) Multiplier Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. Figure 1.10 Block Diagram of R8C/L36A and R8C/L36B Groups REJ09B0441-0010 Rev.0.10 Page 15 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 8 4 8 8 8 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P6 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Port P7 8 LIN module DTC Port P11 Watchdog timer (14 bits) Comparator A LCD drive control circuit Common output: Max. 8 pins Segment output: Max. 48 pins 8 Port P12 A/D converter (10 bits × 16 channels) Comparator B 4 D/A converter (8 bits × 2 channels) R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory Port P13 ROM (1) 4 RAM (2) Multiplier Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. Figure 1.11 Block Diagram of R8C/L38A and R8C/L38B Groups REJ09B0441-0010 Rev.0.10 Page 16 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 8 8 8 8 8 4 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Port P7 Port P10 8 8 LIN module DTC Port P11 Watchdog timer (14 bits) Comparator A LCD drive control circuit Common output: Max. 8 pins Segment output: Max. 56 pins 8 Port P12 A/D converter (10 bits × 20 channels) Comparator B 4 D/A converter (8 bits × 2 channels) R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory Port P13 ROM (1) 8 RAM (2) Multiplier Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. Figure 1.12 Block Diagram of R8C/L3AA and R8C/L3AB Groups REJ09B0441-0010 Rev.0.10 Page 17 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 1.4 Pin Assignments Figures 1.13 to 1.17 show pin assignments (top view). Tables 1.15 to 1.17 list the pin name information by pin number. 39 38 37 36 35 34 33 32 31 30 29 28 27 P0_5/SEG5/AN9 P0_4/SEG4/AN8 P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 VL1 VL2 CL2/P12_3 CL1/P12_2 VL4 P13_3/AN3/CLK0/LVCMP2 P13_2/AN2/RXD0/LVCMP1 40 41 42 43 44 45 46 47 48 49 50 51 52 P0_6/SEG6/AN10 P0_7/SEG7/AN11 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 26 25 24 23 R8C/L35A Group R8C/L35B Group PLQP0052JA-A (52P6A-A) (top view) 22 21 20 19 18 17 16 15 14 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB P7_4/COM3 P7_5/COM2 P7_6/COM1 P7_7/COM0 P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.13 Pin Assignment (Top View) of PLQP0052JA-A Package REJ09B0441-0010 Rev.0.10 Page 18 of 809 Jul 30, 2008 P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0 WKUP0 VREF MODE XCIN XCOUT RESET P12_1/XOUT VSS/AVSS P12_0/XIN VCC/AVCC P11_4/TRAIO/(INT4/RXD0) Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P0_5/SEG5/AN9 P0_4/SEG4/AN8 P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 VL1 VL2 VL3 CL2/P12_3 CL1/P12_2 VL4 P13_3/AN3/CLK0/LVCMP2 P13_2/AN2/RXD0/LVCMP1 P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0/WKUP1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P0_6/SEG6/AN10 P0_7/SEG7/AN11 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P3_4/SEG28/INT4 P3_5/SEG29/INT5 P3_6/SEG30/INT6 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 32 31 30 29 28 R8C/L36A Group R8C/L36B Group PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) (top view) 27 26 25 24 23 22 21 20 19 18 17 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB P7_0/SEG52/COM7 P7_1/SEG53/COM6 P7_2/SEG54/COM5 P7_3/SEG55/COM4 P7_4/COM3 P7_5/COM2 P7_6/COM1 P7_7/COM0 P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.14 Pin Assignment (Top View) of PLQP0064KB-A and PLQP0064GA-A Packages REJ09B0441-0010 Rev.0.10 Page 19 of 809 Jul 30, 2008 WKUP0 VREF MODE XCIN XCOUT RESET P12_1/XOUT VSS/AVSS P12_0/XIN VCC/AVCC P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P11_5/TRAO/(INT5) P11_4/TRAIO/(INT4/RXD0) P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P2_0/SEG16/KI0 P1_3/SEG11/AN15 P1_2/SEG10/AN14 P1_1/SEG9/AN13 P1_0/SEG8/AN12 P0_7/SEG7/AN11 P0_6/SEG6/AN10 P0_5/SEG5/AN9 P0_4/SEG4/AN8 P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 VL1 VL2 VL3 CL2/P12_3 CL1/P12_2 VL4 P13_3/AN3/CLK0/LVCMP2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P2_1/SEG17/KI1 P2_2/SEG18/KI2 P2_3/SEG19/KI3 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P3_4/SEG28/INT4 P3_5/SEG29/INT5 P3_6/SEG30/INT6 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG 40 39 38 37 36 35 34 R8C/L38A Group R8C/L38B Group PLQP0080KB-A (80P6Q-A) PLQP0080JA-A (FP-80W/FP-80WV) (top view) 33 32 31 30 29 28 27 26 25 24 23 22 21 P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB P6_0/SEG44/TRDIOA0/TRDCLK P6_1/SEG45/TRDIOB0 P6_2/SEG46/TRDIOC0 P6_3/SEG47/TRDIOD0 P6_4/SEG48/TRDIOA1 P6_5/SEG49/TRDIOB1 P6_6/SEG50/TRDIOC1 P6_7/SEG51/TRDIOD1 P7_0/SEG52/COM7 P7_1/SEG53/COM6 P7_2/SEG54/COM5 P7_3/SEG55/COM4 P7_4/COM3 P7_5/COM2 P7_6/COM1 P7_7/COM0 P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.15 Pin Assignment (Top View) of PLQP0080KB-A and PLQP0080JA-A Packages REJ09B0441-0010 Rev.0.10 Page 20 of 809 Jul 30, 2008 P13_2/AN2/RXD0/LVCMP1 P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0/WKUP1 WKUP0 VREF MODE XCIN XCOUT RESET P12_1/XOUT VSS/AVSS P12_0/XIN VCC/AVCC P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P11_5/TRAO/(INT5) P11_4/TRAIO/(INT4/RXD0) P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_6/SEG14 P1_5/SEG13 P1_4/SEG12 P1_3/SEG11/AN15 P1_2/SEG10/AN14 P1_1/SEG9/AN13 P1_0/SEG8/AN12 P0_7/SEG7/AN11 P0_6/SEG6/AN10 P0_5/SEG5/AN9 P0_4/SEG4/AN8 P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 VL1 VL2 VL3 CL2/P12_3 CL1/P12_2 VL4 P13_7/AN19/TRGCLKB P13_6/AN18/TRGIOB P13_5/AN17/TRGCLKA P13_4/AN16/TRGIOA 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P1_7/SEG15 P2_0/SEG16/KI0 P2_1/SEG17/KI1 P2_2/SEG18/KI2 P2_3/SEG19/KI3 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P3_4/SEG28/INT4 P3_5/SEG29/INT5 P3_6/SEG30/INT6 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB 50 49 48 47 46 45 44 43 42 R8C/L3AA Group R8C/L3AB Group PLQP0100KB-A (100P6Q-A) (top view) 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P5_0/SEG40 P5_1/SEG41 P5_2/SEG42 P5_3/SEG43 P6_0/SEG44/TRDIOA0/TRDCLK P6_1/SEG45/TRDIOB0 P6_2/SEG46/TRDIOC0 P6_3/SEG47/TRDIOD0 P6_4/SEG48/TRDIOA1 P6_5/SEG49/TRDIOB1 P6_6/SEG50/TRDIOC1 P6_7/SEG51/TRDIOD1 P7_0/SEG52/COM7 P7_1/SEG53/COM6 P7_2/SEG54/COM5 P7_3/SEG55/COM4 P7_4/COM3 P7_5/COM2 P7_6/COM1 P7_7/COM0 P10_0/(TRDIOA0/TRDCLK/KI0) P10_1/(TRDIOB0/KI1) P10_2/(TRDIOC0/KI2) P10_3/(TRDIOD0/KI3) P10_4/(TRDIOA1/KI4) Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.16 Pin Assignment (Top View) of PLQP0100KB-A Package REJ09B0441-0010 Rev.0.10 Page 21 of 809 Jul 30, 2008 P13_3/AN3/CLK0/LVCMP2 P13_2/AN2/RXD0/LVCMP1 P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0/WKUP1 WKUP0 VREF MODE XCIN XCOUT RESET P12_1/XOUT VSS/AVSS P12_0/XIN VCC/AVCC P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P11_5/TRAO/(INT5) P11_4/TRAIO/(INT4/RXD0) P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P11_0/SCL/SSCK/(CLK2/INT0) /IVREF1/LVCOUT1 P10_7/(TRDIOD1/KI7) P10_6/(TRDIOC1/KI6) P10_5/(TRDIOB1/KI5) Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview P1_3/SEG11/AN15 P1_2/SEG10/AN14 P1_1/SEG9/AN13 P1_0/SEG8/AN12 P0_7/SEG7/AN11 P0_6/SEG6/AN10 P0_5/SEG5/AN9 P0_4/SEG4/AN8 P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 VL1 VL2 VL3 CL2/P12_3 CL1/P12_2 VL4 P13_7/AN19/TRGCLKB P13_6/AN18/TRGIOB P1_4/SEG12 P1_5/SEG13 P1_6/SEG14 P1_7/SEG15 P2_0/SEG16/KI0 P2_1/SEG17/KI1 P2_2/SEG18/KI2 P2_3/SEG19/KI3 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P3_4/SEG28/INT4 P3_5/SEG29/INT5 P3_6/SEG30/INT6 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB P5_0/SEG40 P5_1/SEG41 80 79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 R8C/L3AA Group R8C/L3AB Group PRQP0100JD-B (100P6F-A) (top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P5_2/SEG42 P5_3/SEG43 P6_0/SEG44/TRDIOA0/TRDCLK P6_1/SEG45/TRDIOB0 P6_2/SEG46/TRDIOC0 P6_3/SEG47/TRDIOD0 P6_4/SEG48/TRDIOA1 P6_5/SEG49/TRDIOB1 P6_6/SEG50/TRDIOC1 P6_7/SEG51/TRDIOD1 P7_0/SEG52/COM7 P7_1/SEG53/COM6 P7_2/SEG54/COM5 P7_3/SEG55/COM4 P7_4/COM3 P7_5/COM2 P7_6/COM1 P7_7/COM0 P10_0/(TRDIOA0/TRDCLK/KI0) P10_1/(TRDIOB0/KI1) Figure 1.17 Pin Assignment (Top View) of PRQP0100JD-B Package REJ09B0441-0010 Rev.0.10 Page 22 of 809 P13_5/AN17/TRGCLKA P13_4/AN16/TRGIOA P13_3/AN3/CLK0/LVCMP2 P13_2/AN2/RXD0/LVCMP1 P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0/WKUP1 WKUP0 VREF MODE XCIN XCOUT RESET P12_1/XOUT VSS/AVSS P12_0/XIN VCC/AVCC P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P11_5/TRAO/(INT5) P11_4/TRAIO/(INT4/RXD0) P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P11_0/SCL/SSCK/(CLK2/INT0) /IVREF1/LVCOUT1 P10_7/(TRDIOD1/KI7) P10_6/(TRDIOC1/KI6) P10_5/(TRDIOB1/KI5) P10_4/(TRDIOA1/KI4) P10_3/(TRDIOD0/KI3) P10_2/(TRDIOC0/KI2) Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.15 Pin Name Information by Pin Number (1) I/O Pin Functions for Peripheral Modules A/D Converter, D/A Converter, 2C Serial I SSU Comparators A, B, Timer Interface bus Voltage Detection Circuit CLK0 RXD0 TXD0 AN3/LVCMP2 AN2/LVCMP1 AN1/DA1/LVREF AN0/DA0 Pin Number L3AA L38A L36A L35A L3AB L38B L36B L35B (Note 2) 1 [3] 2 [4] 3 [5] 4 [6] 5 [7] 6 [8] 7 [9] 8 [10] 9 [11] 10 [12] 11 [13] 12 [14] 13 [15] 14 [16] 15 [17] 16 [18] 17 [19] 18 [20] 19 [21] 20 [22] 21 [23] 22 [24] 23 [25] 24 [26] 25 [27] 26 [28] 27 [29] 28 [30] 29 [31] 30 [32] 31 [33] 32 [34] 33 [35] 34 [36] 35 [37] 36 [38] 37 [39] 38 [40] 39 [41] 22 23 24 25 26 27 28 29 30 19 20 21 22 23 24 25 26 18 19 20 21 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 13 14 15 16 17 51 52 1 2 3 4 5 6 7 8 9 10 11 12 WKUP1(3) WKUP0 VREF MODE XCIN XCOUT RESET XOUT VSS/ AVSS XIN VCC/ AVCC P12_1 Control Pin Port Interrupt LCD drive control circuit P13_3 P13_2 P13_1 P13_0 P12_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 (INT7) (INT6) (INT5) (INT4) (INT3) (INT2) (INT1) (INT0) (KI7) (KI6) (KI5) (KI4) (KI3) (KI2) (KI1) (KI0) TREO TRBO TRAO TRAIO (RXD0) (CTS2/RTS2) (RXD2/SCL2/ TXD2/SDA2) (RXD2/SCL2/ TXD2/SDA2) (CLK2) (TRDIOD1) (TRDIOC1) (TRDIOB1) (TRDIOA1) (TRDIOD0) (TRDIOC0) (TRDIOB0) (TRDIOA0/ TRDCLK) SCS SSO SSI SSCK SCL SDA (ADTRG) IVCMP3 IVREF3 IVCMP1/LVCOUT2 IVREF1/LVCOUT1 COM0 COM1 COM2 COM3 SEG55/ COM4 SEG54/ COM5 SEG53/ COM6 SEG52/ COM7 SEG51 TRDIOD1 Notes: 1. The pin in parentheses can be assigned by a program. 2. The number in brackets indicates the pin number for the 100P6F package. 3. 0000The WKUP1 pin is not available in the R8C/L35A and R8C/L35B Groups. REJ09B0441-0010 Rev.0.10 Page 23 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.16 Pin Name Information by Pin Number (2) I/O Pin Functions for Peripheral Modules Control Pin Port Serial Interface A/D Converter, D/A Converter, Comparators A, B, Voltage Detection Circuit Pin Number L3AA L38A L36A L35A L3AB L38B L36B L35B (Note 2) 40 [42] 41 [43] 42 [44] 43 [45] 44 [46] 45 [47] 46 [48] 47 [49] 48 [50] 49 [51] 50 [52] 51 [53] 52 [54] 53 [55] 54 [56] 55 [57] 56 [58] 57 [59] 58 [60] 59 [61] 60 [62] 61 [63] 62 [64] 63 [65] 64 [66] 65 [67] 66 [68] 67 [69] 68 [70] 69 [71] 70 [72] 71 [73] 72 [74] 73 [75] 74 [76] 75 [77] 76 [78] 77 [79] 78 [80] 79 [81] 80 [82] 81 [83] 82 [84] 83 [85] 84 [86] 85 [87] 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 30 31 32 33 34 35 36 37 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 Interrupt Timer SSU I2C bus LCD drive control circuit SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOC0 TRDIOB0 TRDIOA0/ TRDCLK TRCIOD/ TRCIOB TRCIOC/ TRCIOB TRCIOB TRCIOA/ TRCTRG TRCCLK/ TRCTRG CLK1 RXD1 TXD1 TRCTRG ADTRG SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 62 63 64 65 66 67 68 47 48 49 38 39 40 AN15 AN14 AN13 AN12 AN11 AN10 AN9 Notes: 1. The pin in parentheses can be assigned by a program. 2. The number in brackets indicates the pin number for the 100P6F package. REJ09B0441-0010 Rev.0.10 Page 24 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.17 Pin Name Information by Pin Number (3) I/O Pin Functions for Peripheral Modules A/D Converter, D/A Converter, Serial SSU I2C bus Comparators A, B, Interface Voltage Detection Circuit AN8 AN7 AN6 AN5 AN4 Pin Number L3AA L38A L36A L35A L3AB L38B L36B L35B (Note 2) 86 [88] 87 [89] 69 70 50 51 41 42 Control Pin Port Interrupt Timer LCD drive control circuit SEG4 SEG3 SEG2 SEG1 SEG0 VL1 VL2 VL3 CL2 CL1 VL4 88 [90] 89 [91] 90 [92] 91 [93] 92 [94] 93 [95] 94 [96] 95 [97] 96 [98] 97 [99] 98 [100] 99 [1] 100 [2] 71 72 73 74 75 76 77 78 79 52 53 54 55 56 57 58 59 60 43 44 45 46 47 48 49 50 P0_4 P0_3 P0_2 P0_1 P0_0 P12_3 P12_2 P13_7 P13_6 P13_5 P13_4 TRGCLKB TRGIOB TRGCLKA TRGIOA AN19 AN18 AN17 AN16 Notes: 1. The pin in parentheses can be assigned by a program. 2. The number in brackets indicates the pin number for the 100P6F package. REJ09B0441-0010 Rev.0.10 Page 25 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview 1.5 Pin Functions Tables 1.18 and 1.19 list pin functions. Table 1.18 Item Power supply input Analog power supply input Reset input MODE Pin Functions (1) Pin Name VCC, VSS AVCC, AVSS RESET MODE I/O Type − − I I I I I O I O I I I/O O O I I I/O I/O Description Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Driving this pin low resets the MCU. Connect this pin to VCC via a resistor. This pin is provided for input to exit the mode used in power-off mode. Connect to VSS when not using power-off mode. This pin is provided for input to exit the mode used in power-off mode. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic oscillator or a crystal oscillator between pins XIN and XOUT. (1) To use an external clock, input it to the XIN pin and leave the XOUT pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between pins XCIN and XCOUT. (1) To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin External clock input pin External trigger input pin Timer RC I/O pins Timer RD I/O pins Power-off mode exit WKUP0 input WKUP1 XIN clock input XIN clock output XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RC XIN XOUT XCIN XCOUT INT0 to INT7 KI0 to KI7 TRAIO TRAO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD Timer RD TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDCLK Timer RE Timer RG Serial interface TREO TRGCLKA, TRGCLKB TRGIOA, TRGIOB CLK0, CLK1, CLK2 RXD0, RXD1, RXD2 TXD0, TXD1, TXD2 CTS2 RTS2 SCL2 SDA2 I O I I/O I/O I O I O I/O I/O External clock input pin Divided clock output pin Timer RG input pins Timer RG I/O pins Transfer clock I/O pins Serial data input pins Serial data output pins Transmission control input pin Reception control output pin I2C mode clock I/O pin I2C mode data I/O pin I: Input O: Output I/O: Input and output Note: 1. Contact the oscillator manufacturer for oscillation characteristics. REJ09B0441-0010 Rev.0.10 Page 26 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 1. Overview Table 1.19 Item I2C bus Pin Functions (2) Pin Name SCL SDA SSI SCS SSCK SSO I/O Type I/O I/O I/O I/O I/O I/O I I I O I I O I I I I/O Clock I/O pin Data I/O pin Data I/O pin Chip-select signal I/O pin Clock I/O pin Data I/O pin Reference voltage input pin for the A/D converter and the D/A converter A/D converter analog input pins AD external trigger input pin D/A converter output pins Comparator A analog voltage input pins Comparator A reference voltage input pin Comparator A output pins Comparator B analog voltage input pins Comparator B reference voltage input pins Detection target voltage input pin for voltage detection 2 CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. Ports P10_0 to P10_7 and P11_0 to P11_7 can be used as LED drive ports. Description SSU Reference voltage input A/D converter D/A converter Comparator A VREF AN0 to AN11 ADTRG DA0, DA1 LVCMP1, LVCMP2 LVREF LVCOUT1, LVCOUT2 Comparator B Voltage detection circuit I/O ports IVCMP1, IVCMP3 IVREF1, IVREF3 LVCMP2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0, P5_3, P6_0 to P6_7 P7_0 to P7_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_3, P13_0 to P13_7 SEG0 to SEG55 COM0 to COM7 CL1, CL2 Segment output Common output Voltage multiplier capacity connect pins LCD power supply O O O LCD segment output pins LCD common output pins Connect pins for the LCD control voltage multiplier VL1 VL2 to VL4 I/O I Apply the voltage: 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VL4. VL1 can be used as the reference potential input or output pin when setting the voltage multiplier. I: Input O: Output I/O: Input and output Note: 1. Contact the oscillator manufacturer for oscillation characteristics. REJ09B0441-0010 Rev.0.10 Page 27 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register banks. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1) R2 R3 A0 A1 FB b19 b15 b0 Address registers (1) Frame base register (1) INTBH INTBL Interrupt table register The 4 high-order bits of INTB are INTBH and the 16 low-order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit Note: 1. These registers configure a register bank. There are two sets of register banks. Figure 2.1 CPU Registers REJ09B0441-0010 Rev.0.10 Page 28 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the starting address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. REJ09B0441-0010 Rev.0.10 Page 29 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. REJ09B0441-0010 Rev.0.10 Page 30 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 3. Memory 3. Memory Figure 3.1 is a Memory Map of each group. Each group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h 002FFh 00400h SFR (Refer to 4. Special Function Registers (SFRs)) Internal RAM 0XXXXh 0FFD8h Reserved area 0FFDCh 02C00h 02FFFh 03000h SFR (Refer to 4. Special Function Registers (SFRs)) Internal ROM (data flash) (1) 03FFFh 0YYYYh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor Internal ROM (program ROM) 0FFFFh Address break 0FFFFh (Reserved) Reset Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F2L357A***, R5F2L367A***, R5F2L387A***, R5F2L3A7A*** R5F2L358A***, R5F2L368A***, R5F2L388A***, R5F2L3A8A*** R5F2L35AA***, R5F2L36AA***, R5F2L38AA***, R5F2L3AAA*** R5F2L35CA***, R5F2L36CA***, R5F2L38CA***, R5F2L3ACA*** R5F2L357B***, R5F2L367B***, R5F2L387B***, R5F2L3A7B*** R5F2L358B***, R5F2L368B***, R5F2L388B***, R5F2L3A8B*** R5F2L35AB***, R5F2L36AB***, R5F2L38AB***, R5F2L3AAB*** R5F2L35CB***, R5F2L36CB***, R5F2L38CB***, R5F2L3ACB*** Capacity 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Address 0YYYYh 04000h 04000h 04000h 04000h 04000h 04000h 04000h 04000h Address ZZZZZh Internal RAM Capacity 6 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes 10 Kbytes Address 0XXXXh 01BFFh 023FFh Data Flash − 13FFFh 1BFFFh 23FFFh Available 02BFFh 02BFFh 01BFFh 023FFh 02BFFh 02BFFh − 13FFFh 1BFFFh 23FFFh Not available Figure 3.1 Memory Map REJ09B0441-0010 Rev.0.10 Page 31 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.16 list SFR information. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h SFR Information (1) (1) Register Symbol After Reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register PM0 PM1 CM0 CM1 MSTCR CM3 PRCR RSTFR OCD WDTR WDTS WDTC 00h 00h 00100000b 00100000b 00h 00h 00h XXXX00XXb (2) 00000100b XXh XXh 00111111b High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping Count Source Protection Mode Register CSPR 00h 10000000b (3) Power-Off Mode Control Register 0 POMCR0 X0000000b High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 On-Chip Reference Voltage Control Register FRA0 FRA1 FRA2 OCVREFCR 00h When shipping 00h 00h High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 5 High-Speed On-Chip Oscillator Control Register 6 FRA4 FRA5 FRA6 When Shipping When Shipping When Shipping High-Speed On-Chip Oscillator Control Register 3 Voltage Monitor Circuit/Comparator A Control Register Voltage Monitor Circuit Edge Select Register Voltage Detect Register 1 Voltage Detect Register 2 FRA3 CMPA VCAC VCA1 VCA2 When shipping 00h 00h 00001000b 00h (4) 00100000b (5) 00000111b 1100X010b (4) 1100X011b (5) 10001010b Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register VD1LS VW0C 0039h Voltage Monitor 1 Circuit Control Register VW1C X: Undefined Notes: 1. Blank spaces are reserved. No access is allowed. 2. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off mode. Software reset, watchdog timer reset, or oscillation stop detection reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0. REJ09B0441-0010 Rev.0.10 Page 32 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) (1) Symbol VW2C After Reset 10000010b Address Register 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h INT7 Interrupt Control Register 0044h INT6 Interrupt Control Register 0045h INT5 Interrupt Control Register 0046h INT4 Interrupt Control Register 0047h Timer RC Interrupt Control Register 0048h Timer RD0 Interrupt Control Register 0049h Timer RD1 Interrupt Control Register 004Ah Timer RE Interrupt Control Register 004Bh UART2 Transmit Interrupt Control Register 004Ch UART2 Receive Interrupt Control Register 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register (2) 0050h 0051h UART0 Transmit Interrupt Control Register 0052h UART0 Receive Interrupt Control Register 0053h UART1 Transmit Interrupt Control Register 0054h UART1 Receive Interrupt Control Register 0055h INT2 Interrupt Control Register 0056h Timer RA Interrupt Control Register 0057h 0058h Timer RB Interrupt Control Register 0059h INT1 Interrupt Control Register 005Ah INT3 Interrupt Control Register 005Bh 005Ch 005Dh INT0 Interrupt Control Register 005Eh UART2 Bus Collision Detection Interrupt Control Register 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh Timer RG Interrupt Control Register 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage monitor 1 / Comparator A1 Interrupt Control Register 0073h Voltage monitor 2 / Comparator A2 Interrupt Control Register 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh X: Undefined Notes: 1. Blank spaces are reserved. No access is allowed. 2. Selectable by the IICSEL bit in the SSUIICSR register. FMRDYIC INT7IC INT6IC INT5IC INT4IC TRCIC TRD0IC TRD1IC TREIC S2TIC S2RIC KUPIC ADIC SSUIC/IICIC S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC TRBIC INT1IC INT3IC XXXXX000b XX00X000b XX00X000b XX00X000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b INT0IC U2BCNIC XX00X000b XXXXX000b TRGIC XXXXX000b VCMP1IC VCMP2IC XXXXX000b XXXXX000b REJ09B0441-0010 Rev.0.10 Page 33 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh SFR Information (3) (1) Register DTC Activation Control Register Symbol DTCTL After Reset 00h DTC Activation Enable Register 0 DTC Activation Enable Register 1 DTC Activation Enable Register 2 DTC Activation Enable Register 3 DTC Activation Enable Register 4 DTC Activation Enable Register 5 DTC Activation Enable Register 6 DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN4 DTCEN5 DTCEN6 00h 00h 00h 00h 00h 00h 00h UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register UART2 Digital Filter Function Select Register U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h UART2 Special Mode Register 5 UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register U2SMR5 U2SMR4 U2SMR3 U2SMR2 U2SMR 00h 00h 000X0X0Xb X0000000b X0000000b X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. REJ09B0441-0010 Rev.0.10 Page 34 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) (1) Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After Reset XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb Address Register 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D Register 6 00CDh 00CEh A/D Register 7 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register 00D5h A/D Input Select Register 00D6h A/D Control Register 0 00D7h A/D Control Register 1 00D8h D/A 0 Register 00D9h D/A 1 Register 00DAh 00DBh 00DCh D/A Control Register 00DDh 00DEh 00DFh 00E0h Port P0 Register 00E1h Port P1 Register 00E2h Port P0 Direction Register 00E3h Port P1 Direction Register 00E4h Port P2 Register 00E5h Port P3 Register 00E6h Port P2 Direction Register 00E7h Port P3 Direction Register 00E8h Port P4 Register 00E9h Port P5 Register 00EAh Port P4 Direction Register 00EBh Port P5 Direction Register 00ECh Port P6 Register 00EDh Port P7 Register 00EEh Port P6 Direction Register 00EFh Port P7 Direction Register 00F0h 00F1h 00F2h 00F3h 00F4h Port P10 Register 00F5h Port P11 Register 00F6h Port P10 Direction Register 00F7h Port P11 Direction Register 00F8h Port P12 Register 00F9h Port P13 Register 00FAh Port P12 Direction Register 00FBh Port P13 Direction Register 00FCh 00FDh 00FEh 00FFh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. ADMOD ADINSEL ADCON0 ADCON1 DA0 DA1 00h 11000000b 00h 00h 00h 00h DACON 00h P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h P10 P11 PD10 PD11 P12 P13 PD12 PD13 XXh XXh 00h 00h XXh XXh 00h 00h REJ09B0441-0010 Rev.0.10 Page 35 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.5 Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh SFR Information (5) (1) Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register 2 LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After Reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh Timer RE Second Data Register / Timer RE Counter Data Register Timer RE Minute Data Register / Timer RE Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register Timer RC Trigger Control Register Timer RD Control Expansion Register Timer RD Trigger Control Register Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1 TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER TRCADCR TRDECR TRDADCR TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1 XXh XXh XXh XXh XXXXX0XXb XXh 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011000b 00h 01111111b 00h 00h 00h 11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. REJ09B0441-0010 Rev.0.10 Page 36 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) (1) Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 U1MR U1BRG U1TB U1C0 U1C1 U1RB After Reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh Address Register 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt Enable Register 0 0145h Timer RD PWM Mode Output Level Control Register 0 0146h Timer RD Counter 0 0147h 0148h Timer RD General Register A0 0149h 014Ah Timer RD General Register B0 014Bh 014Ch Timer RD General Register C0 014Dh 014Eh Timer RD General Register D0 014Fh 0150h Timer RD Control Register 1 0151h Timer RD I/O Control Register A1 0152h Timer RD I/O Control Register C1 0153h Timer RD Status Register 1 0154h Timer RD Interrupt Enable Register 1 0155h Timer RD PWM Mode Output Level Control Register 1 0156h Timer RD Counter 1 0157h 0158h Timer RD General Register A1 0159h 015Ah Timer RD General Register B1 015Bh 015Ch Timer RD General Register C1 015Dh 015Eh Timer RD General Register D1 015Fh 0160h UART1 Transmit/Receive Mode Register 0161h UART1 Bit Rate Register 0162h UART1 Transmit Buffer Register 0163h 0164h UART1 Transmit/Receive Control Register 0 0165h UART1 Transmit/Receive Control Register 1 0166h UART1 Receive Buffer Register 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h Timer RG Mode Register 0171h Timer RG Count Control Register 0172h Timer RG Control Register 0173h Timer RG Interrupt Enable Register 0174h Timer RG Status Register 0175h Timer RG I/O Control Register 0176h Timer RG Counter 0177h 0178h Timer RG General Register A 0179h 017Ah Timer RG General Register B 017Bh 017Ch Timer RG General Register C 017Dh 017Eh Timer RG General Register D 017Fh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. TRGMR TRGCNTC TRGCR TRGIER TRGSR TRGIOR TRG TRGGRA TRGGRB TRGGRC TRGGRD 01000000b 00h 10000000b 11110000b 11100000b 00h 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh REJ09B0441-0010 Rev.0.10 Page 37 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) (1) Symbol TRASR TRBRCSR TRCPSR0 TRCPSR1 TRDPSR0 TRDPSR1 TRGPSR U0SR U1SR U2SR0 U2SR1 SSUIICSR KISR INTSR After Reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Address Register 0180h Timer RA Pin Select Register 0181h Timer RB/RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h Timer RD Pin Select Register 0 0185h Timer RD Pin Select Register 1 0186h 0187h Timer RG Pin Select Register 0188h UART0 Pin Select Register 0189h UART1 Pin Select Register 018Ah UART2 Pin Select Register 0 018Bh UART2 Pin Select Register 1 018Ch SSU/IIC Pin Select Register 018Dh Key Input Pin Select Register 018Eh INT Interrupt Input Pin Select Register 018Fh 0190h 0191h 0192h 0193h SS Bit Counter Register 0194h SS Transmit Data Register L / IIC bus Transmit Data Register (2) 0195h SS Transmit Data Register H 0196h SS Receive Data Register L / IIC bus Receive Data Register (2) 0197h SS Receive Data Register H (2) 0198h SS Control Register H / IIC bus Control Register 1 (2) 0199h SS Control Register L / IIC bus Control Register 2 (2) 019Ah SS Mode Register / IIC bus Mode Register (2) 019Bh SS Enable Register / IIC bus Interrupt Enable Register (2) 019Ch SS Status Register / IIC bus Status Register (2) 019Dh SS Mode Register 2 / Slave Address Register (2) 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register 01B3h 01B4h Flash Memory Control Register 0 01B5h Flash Memory Control Register 1 01B6h Flash Memory Control Register 2 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh X: Undefined Notes: 1. Blank spaces are reserved. No access is allowed. 2. Selectable by the IICSEL bit in the SSUIICSR register. SSBR SSTDR/ICDRT SSTDRH SSRDR/ICDRR SSRDRH SSCRH/ICCR1 SSCRL/ICCR2 SSMR/ICMR SSER/ICIER SSSR/ICSR SSMR2/SAR 11111000b FFh FFh FFh FFh 00h 01111101b 00010000b/00011000b 00h 00h/0000X000b 00h FST FMR0 FMR1 FMR2 10000X00b 00h 00h 00h REJ09B0441-0010 Rev.0.10 Page 38 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.8 SFR Information (8) (1) Symbol RMAD0 After Reset XXh XXh 0000XXXXb 00h XXh XXh 0000XXXXb 00h Address Register 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Port P0 Pull-Up Control Register 01E1h Port P1 Pull-Up Control Register 01E2h Port P2 Pull-Up Control Register 01E3h Port P3 Pull-Up Control Register 01E4h Port P4 Pull-Up Control Register 01E5h Port P5 Pull-Up Control Register 01E6h Port P6 Pull-Up Control Register 01E7h Port P7 Pull-Up Control Register 01E8h 01E9h 01EAh Port 10 Pull-Up Control Register 01EBh Port 11 Pull-Up Control Register 01ECh Port 12 Pull-Up Control Register 01EDh Port 13 Pull-Up Control Register 01EEh 01EFh 01F0h Port P10 Drive Capacity Control Register 01F1h Port P11 Drive Capacity Control Register 01F2h 01F3h 01F4h 01F5h Input Threshold Control Register 0 01F6h Input Threshold Control Register 1 01F7h Input Threshold Control Register 2 01F8h Comparator B Control Register 0 01F9h 01FAh External Input Enable Register 0 01FBh External Input Enable Register 1 01FCh INT Input Filter Select Register 0 01FDh INT Input Filter Select Register 1 01FEh Key Input Enable Register 0 01FFh Key Input Enable Register 1 X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. AIER0 RMAD1 AIER1 P0PUR P1PUR P2PUR P3PUR P4PUR P5PUR P6PUR P7PUR 00h 00h 00h 00h 00h 00h 00h 00h P10PUR P11PUR P12PUR P13PUR 00h 00h 00h 00h P10DRR P11DRR 00h 00h VLT0 VLT1 VLT2 INTCMP INTEN INTEN1 INTF INTF1 KIEN KIEN1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h REJ09B0441-0010 Rev.0.10 Page 39 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.9 SFR Information (9) (1) Symbol LCR0 LCR1 LCR2 LCR3 00h 00h 00h 00h After Reset Address Register LCD Control Register 0200h LCD Bias Control Register 0201h LCD Display Control Register 0202h LCD Clock Control Register 0203h 0204h 0205h LCD Port Select Register 0 0206h LCD Port Select Register 1 0207h LCD Port Select Register 2 0208h LCD Port Select Register 3 0209h LCD Port Select Register 4 020Ah LCD Port Select Register 5 020Bh LCD Port Select Register 6 020Ch LCD Port Select Register 7 020Dh 020Eh 020Fh LCD Display Data Register 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. LSE0 LSE1 LSE2 LSE3 LSE4 LSE5 LSE6 LSE7 00h 00h 00h 00h 00h 00h 00h 00h LRA0L LRA1L LRA2L LRA3L LRA4L LRA5L LRA6L LRA7L LRA8L LRA9L LRA10L LRA11L LRA12L LRA13L LRA14L LRA15L LRA16L LRA17L LRA18L LRA19L LRA20L LRA21L LRA22L LRA23L LRA24L LRA25L LRA26L LRA27L LRA28L LRA29L LRA30L LRA31L LRA32L LRA33L LRA34L LRA35L LRA36L LRA37L LRA38L LRA39L LRA40L LRA41L LRA42L LRA43L LRA44L LRA45L LRA46L LRA47L XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh REJ09B0441-0010 Rev.0.10 Page 40 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.10 SFR Information (10) (1) Symbol LRA48L LRA49L LRA50L LRA51L LRA52L LRA53L LRA54L LRA55L LRA56L LRA57L LRA58L LRA59L LRA60L LRA61L LRA62L LRA63L LRA64L LRA65L LRA66L LRA67L LRA68L LRA69L LRA70L LRA71L LRA72L LRA73L LRA74L LRA75L LRA76L LRA77L LRA78L LRA79L LRA80L LRA81L LRA82L LRA83L LRA84L LRA85L LRA86L LRA87L LRA88L LRA89L LRA90L LRA91L LRA92L LRA93L LRA94L LRA95L LRA0H LRA1H LRA2H LRA3H LRA4H LRA5H LRA6H LRA7H LRA8H LRA9H LRA10H LRA11H LRA12H LRA13H LRA14H LRA15H After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 0240h LCD Display Data Register 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h LCD Display Control Data Register 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. REJ09B0441-0010 Rev.0.10 Page 41 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.11 SFR Information (11) (1) Symbol LRA16H LRA17H LRA18H LRA19H LRA20H LRA21H LRA22H LRA23H LRA24H LRA25H LRA26H LRA27H LRA28H LRA29H LRA30H LRA31H LRA32H LRA33H LRA34H LRA35H LRA36H LRA37H LRA38H LRA39H LRA40H LRA41H LRA42H LRA43H LRA44H LRA45H LRA46H LRA47H LRA48H LRA49H LRA50H LRA51H LRA52H LRA53H LRA54H LRA55H LRA56H LRA57H LRA58H LRA59H LRA60H LRA61H LRA62H LRA63H LRA64H LRA65H LRA66H LRA67H LRA68H LRA69H LRA70H LRA71H LRA72H LRA73H LRA74H LRA75H LRA76H LRA77H LRA78H LRA79H After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 0280h LCD Display Control Data Register 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. REJ09B0441-0010 Rev.0.10 Page 42 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.12 SFR Information (12) (1) Symbol LRA80H LRA81H LRA82H LRA83H LRA84H LRA85H LRA86H LRA87H LRA88H LRA89H LRA90H LRA91H LRA92H LRA93H LRA94H LRA95H After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 02C0h LCD Display Control Data Register 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. REJ09B0441-0010 Rev.0.10 Page 43 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.13 Address 2C00h 2C01h 2C02h 2C03h 2C04h 2C05h 2C06h 2C07h 2C08h 2C09h 2C0Ah : : 2C3Ah 2C3Bh 2C3Ch 2C3Dh 2C3Eh 2C3Fh 2C40h 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh 2C50h 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh SFR Information (13) (1) Register DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Transfer Vector Area DTC Control Data 0 Symbol XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh After Reset DTCD0 DTC Control Data 1 DTCD1 DTC Control Data 2 DTCD2 DTC Control Data 3 DTCD3 DTC Control Data 4 DTCD4 DTC Control Data 5 DTCD5 X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. REJ09B0441-0010 Rev.0.10 Page 44 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.14 SFR Information (14) (1) Symbol DTCD6 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h DTC Control Data 9 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh 2C90h DTC Control Data 10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC Control Data 13 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. DTCD7 DTCD8 DTCD9 DTCD10 DTCD11 DTCD12 DTCD13 REJ09B0441-0010 Rev.0.10 Page 45 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.15 SFR Information (15) (1) Symbol DTCD14 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC Control Data 17 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh 2CD0h DTC Control Data 18 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h DTC Control Data 19 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h DTC Control Data 20 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h DTC Control Data 21 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh X: Undefined Note: 1. Blank spaces are reserved. No access is allowed. DTCD15 DTCD16 DTCD17 DTCD18 DTCD19 DTCD20 DTCD21 REJ09B0441-0010 Rev.0.10 Page 46 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) Table 4.16 Address 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h 2D01h SFR Information (16) (1) Register DTC Control Data 22 Symbol DTCD22 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh DTC Control Data 23 DTCD23 0FFDBh Option Function Select Register 2 : 0FFFFh Option Function Select Register X: Undefined Notes: 1. Blank spaces are reserved. No access is allowed. 2. This register cannot be changed by a program. Use a flash programmer to write to it. OFS2 OFS (Note 2) (Note 2) REJ09B0441-0010 Rev.0.10 Page 47 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5. Resets The following resets are available: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources and Figure 5.1 shows the Reset Circuit Block Diagram. Table 5.1 Reset Names and Sources Reset Name Hardware reset Power-on reset Voltage monitor 0 reset Watchdog timer reset Software reset Source The input voltage to the RESET pin is held low. VCC rises. VCC falls. (Monitor voltage: Vdet0) Underflow of the watchdog timer Write 1 to the PM03 bit in the PM0 register. RESET Hardware reset VCC Power-on reset circuit Power-on reset Voltage detection circuit Voltage monitor 0 reset Watchdog timer Watchdog timer reset Pins, CPU, and SFRs (1) CPU Software reset Note: 1. The CWR bit in the RSTFR register is set to 0 (cold start-up) after power-on, voltage monitor 0 reset, or exit from power-off mode. This bit remains unchanged at a software reset, watchdog timer reset, or oscillation detection reset. Figure 5.1 Reset Circuit Block Diagram REJ09B0441-0010 Rev.0.10 Page 48 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets Table 5.2 shows the Pin Status while RESET Pin Level is Low. Figure 5.2 shows the CPU Register Status after Reset and Figure 5.3 shows the Reset Sequence. Table 5.2 P0 to P13 WKUP0 XCIN, XCOUT VL1 to LVL4 Pin Status while RESET Pin Level is Low Pin Name Pin Status High impedance High impedance Undefined High impedance b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h b19 b0 Data register (R0) Data register (R1) Data register (R2) Data register (R3) Address register (A0) Address register (A1) Frame base register (FB) 00000h Content of addresses 0FFFEh to 0FFFCh b15 b0 Interrupt table register (INTB) Program counter (PC) 0000h 0000h 0000h b15 b0 User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) 0000h b15 b8 b7 b0 Flag register (FLG) IPL U I OBSZDC Figure 5.2 CPU Register Status after Reset REJ09B0441-0010 Rev.0.10 Page 49 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets fOCO-S RESET pin 10 µs or more required (1) fOCO-S clock × 32 cycles (2) Internal reset signal Activation time of flash memory (CPU clock × 148 cycles) CPU clock × 28 cycles CPU clock 0FFFCh Address (internal address signal) 0FFFDh Content of reset vector Notes: 1. Hardware reset. 2. When the low-level input width of the RESET pin is set to fOCO-S clock × 8 cycles or more, the RESET pin is driven high at the same time as the internal reset signal is held high. 0FFFEh Figure 5.3 Reset Sequence REJ09B0441-0010 Rev.0.10 Page 50 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.1 5.1.1 Registers Processor Mode Register 0 (PM0) b6 — 0 b5 — 0 b4 — 0 b3 PM03 0 b2 — 0 b1 — 0 Function Set to 0. b0 — 0 R/W R/W Address 0004h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name — Reserved bits — — PM03 Software reset bit — — — — Setting this bit to 1 resets the MCU. When read, the content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W — Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register. 5.1.2 Reset Source Determination Register (RSTFR) b6 — X b5 — X b4 — X b3 WDR 0 b2 SWR 0 b1 HWR X b0 CWR X Address 000Bh Bit b7 Symbol — After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 (Note 1) R/W R/W R R R R Symbol Bit Name CWR Cold start-up/warm start-up determine flag (2, 3) HWR Hardware reset detect flag (4) SWR WDR — — — — Software reset detect flag Watchdog timer reset detect flag Reserved bits Function 0: Cold start-up 1: Warm start-up 0: Not detected 1: Detected 0: Not detected 1: Detected 0: Not detected 1: Detected When read, the content is undefined. Notes: 1. The CWR bit is set to 0 (cold start-up) after power-on, voltage monitor 0 reset, or exit from power-off mode. This bit remains unchanged at a hardware reset, software reset, or watchdog timer reset. 2. When 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.) 3. When the VW0C0 bit in the VW0C register is set to 0 (voltage monitor 0 reset disabled), the CWR bit value is undefined. 4. A hardware reset or an exit from power-off mode is detected. REJ09B0441-0010 Rev.0.10 Page 51 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.1.3 Option Function Select Register (OFS) b6 LVDAS 1 b5 b4 b3 b2 VDSEL1 VDSEL0 ROMCP1 ROMCR 1 1 1 1 b1 — 1 b0 WDTON 1 (Note 1) R/W R/W R/W R/W R/W Address 0FFFFh Bit b7 Symbol CSPROINI When shipping 1 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name WDTON Watchdog timer start select bit — Reserved bit ROMCR ROM code protect disable bit ROMCP1 ROM code protect bit VDSEL0 Voltage detection 0 level select bit (2) VDSEL1 Function 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset Set to 1. 0: ROM code protect disabled 1: ROMCP1 bit enabled 0: ROM code protect enabled 1: ROM code protect disabled b5 b4 b6 b7 LVDAS Voltage detection 0 circuit start bit (3) CSPROINI Count source protection mode after reset select bit R/W 0 0: 3.80 V selected (Vdet0_3) R/W 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) 0: Voltage monitor 0 reset enabled after reset R/W 1: Voltage monitor 0 reset disabled after reset 0: Count source protection mode enabled after reset R/W 1: Count source protection mode disabled after reset Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. REJ09B0441-0010 Rev.0.10 Page 52 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.1.4 Option Function Select Register 2 (OFS2) b6 — 1 b5 — 1 b4 — 1 b3 b2 b1 b0 WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 1 1 1 1 (Note 1) Function b1 b0 Address 0FFDBh Bit b7 Symbol — When shipping 1 Bit b0 b1 Symbol Bit Name WDTUFS0 Watchdog timer underflow period set bit WDTUFS1 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh b3 b2 R/W R/W R/W b2 b3 WDTRCS0 Watchdog timer refresh acknowledgement period WDTRCS1 set bit b4 b5 b6 b7 — — — — Reserved bits 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% Set to 1. R/W R/W R/W Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 15.3.1.1 Refresh Acknowledgment Period. REJ09B0441-0010 Rev.0.10 Page 53 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.2 Hardware Reset A reset is applied using the RESET pin. When a low-level signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, the pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Status while RESET Pin Level is Low). When the input level applied to the RESET pin changes from low to high, a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after reset. The internal RAM is not reset. If the RESET pin is pulled low while writing to the internal RAM is in progress, the contents of internal RAM will be undefined. Figure 5.4 shows an Example of Hardware Reset Circuit and Operation and Figure 5.5 shows an Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation. 5.2.1 When Power Supply is Stable (1) Apply a low-level signal to the RESET pin. (2) Wait for 10 µs. (3) Apply a high-level signal to the RESET pin. 5.2.2 Power On (1) Apply a low-level signal to the RESET pin. (2) Let the supply voltage increase until it meets the recommended operating conditions. (3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 36. Electrical Characteristics). (4) Wait for 10 µs. (5) Apply a high-level signal to the RESET pin. REJ09B0441-0010 Rev.0.10 Page 54 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets VCC VCC 0V RESET RESET 1.8 V 0.2 VCC or below 0V td(P-R) + 10 µs or more Note: 1. Refer to 36. Electrical Characteristics. Figure 5.4 Example of Hardware Reset Circuit and Operation Supply voltage detection circuit 5V VCC 1.8 V RESET VCC 0V 5V RESET 0V td(P-R) + 10 µs or more Example when VCC = 5 V Note: 1. Refer to 36. Electrical Characteristics. Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation REJ09B0441-0010 Rev.0.10 Page 55 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.3 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the pins, CPU, and SFRs are reset. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8 VCC or above. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held high and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after power-on reset. After power-on reset, voltage monitor 0 reset is enabled when the LVDAS bit in the OFS register is set to 0 (voltage monitor 0 reset enabled after reset). Figure 5.6 shows an Example of Power-On Reset Circuit and Operation. VCC 4.7 kΩ (reference) RESET Vdet0 trth Vccmin Vpor1 External Power VCC tw(por1) Internal reset signal (low valid) 1 × 32 fOCO-S 1 × 32 fOCO-S trth Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 2. Refer to 36. Electrical Characteristics. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to 1. Figure 5.6 Example of Power-On Reset Circuit and Operation REJ09B0441-0010 Rev.0.10 Page 56 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.4 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. The Vdet0 voltage detection level can be changed by the settings of bits VDSEL0 and VDSEL1 in the OFS register. When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFRs are reset. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held high and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after a reset. The LVDAS bit in the OFS register can be used to select whether voltage monitor 0 reset is enabled or disabled after a reset. The setting of the LVDAS bit is enabled at all resets. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 bits in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to 1. Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6 of address 0FFFFh using a flash programmer. Refer to 5.1.3 Option Function Select Register (OFS) for details of the OFS register. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after voltage monitor 0 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset. Figure 5.7 shows an Example of Voltage Monitor 0 Reset Circuit and Operation. VCC 4.7 kΩ (reference) RESET tw(Vdet0) VCC Vdet0 Vccmin Vpor1 Sampling time (1, 2) Internal reset signal (low valid) 1 × 32 fOCO-S Notes: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (1.8 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 36. Electrical Characteristics. 5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to 1. Figure 5.7 Example of Voltage Monitor 0 Reset Circuit and Operation Jul 30, 2008 REJ09B0441-0010 Rev.0.10 Page 57 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFRs when the watchdog timer underflows. Then the program beginning with the address indicated by the reset vector is executed. The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after watchdog timer reset. The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined. The underflow period and refresh acknowledge period for the watchdog timer can be set by bits WDTUFS0 and WDTUFS1 and bits WDTRCS0 and WDTRCS1 in the OFS2 register, respectively. Refer to 15. Watchdog Timer for details of the watchdog timer. 5.6 Software Reset When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFRs. The program beginning with the address indicated by the reset vector is executed. The low-speed on-chip oscillator clock with no division is automatically selected for the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after software reset. The internal RAM is not reset. REJ09B0441-0010 Rev.0.10 Page 58 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets 5.7 Cold Start-Up/Warm Start-Up Determination Function The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation. The CWR bit is set to 0 (cold start-up) at power-on and also set to 0 at a voltage monitor 0 reset or an exit from power-off mode. When 1 is written to the CWR bit by a program, it is set to 1. This bit remains unchanged at a hardware reset, software reset, or watchdog timer reset. The cold start-up/warm stat-up determination function uses voltage monitor 0 reset. To set the bits associated with voltage monitor 0 reset, follow Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset. Figure 5.8 shows an Operating Example of Cold Start-Up/Warm Start-Up Function 5V VCC Vdet0 0V Set to 1 by a program. Set to 1 by a program. CWR bit in RSTFR register Voltage monitor 0 reset The above applies when the digital filter is not used. Figure 5.8 Operating Example of Cold Start-Up/Warm Start-Up Function 5.8 Reset Source Determination Function The RSTFR register can be used to detect whether a hardware reset, software reset, or watchdog timer reset has occurred. If a hardware reset or an exit from power-off mode occurs, the HWR bit is set to 1 (detected). If a software reset occurs, the SWR bit is set to 1 (detected). If a watchdog timer reset occurs, the WDR bit is set to 1 (detected). REJ09B0441-0010 Rev.0.10 Page 59 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6. Voltage Detection Circuit The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. 6.1 Introduction The detection voltage of voltage detection 0 can be selected among four levels using the OFS register. The detection voltage of voltage detection 1 can be selected among 16 levels using the VD1LS register. As a detection target, the voltage input to VCC and the LVCMP2 pin can be switched for voltage detection 2 only. The voltage monitor 0 reset, and voltage monitor 1 interrupt and voltage monitor 2 interrupt can also be used. Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator A1 and comparator A2. Either voltage monitor 1 and voltage monitor 2 or comparator A1 and comparator A2 can be selected. Table 6.1 VCC monitor Voltage Detection Circuit Specifications Item Voltage to monitor Detection target Voltage Monitor 0 Vdet0 Whether passing through Vdet0 by falling Voltage Monitor 1 Vdet1 Whether passing through Vdet1 by rising or falling Voltage Monitor 2 Vdet2 Whether passing through Vdet2 by rising or falling The input voltage to VCC and the LVCMP2 pin can be switched by the VCA24 bit in the VCA2 register. The detection voltage level varies depending on when VCC is selected or when LVCMP2 is selected. Each value is set as the fixed level. The VCA13 bit in the VCA1 register Whether VCC or LVCMP2 input voltage is higher or lower than Vdet2 None Detection voltage Selectable among 4 levels using the OFS register. Selectable among 16 levels using the VD1LS register. Monitor None The VW1C3 bit in the VW1C register Whether VCC is higher or lower than Vdet1 None Process at voltage detection Reset Interrupts Voltage monitor 0 reset Reset at Vdet0 > VCC; CPU operation restarts at VCC > Vdet0 None Digital filter Switching Supported enable/disable Sampling (fOCO-S divided by n) × 4 (fOCO-S divided by n) × 2 time n: 1, 2, 4, and 8 n: 1, 2, 4, and 8 Voltage monitor 1 interrupt Non-maskable or maskable selectable Interrupt request at: Vdet1 > VCC and/or VCC > Vdet1 Supported Voltage monitor 2 interrupt Non-maskable or maskable selectable Interrupt request at: Vdet2 > VCC (LVCMP2) and/or VCC (LVCMP2) > Vdet2 Supported (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8 REJ09B0441-0010 Rev.0.10 Page 60 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit Shared with comparator A VCA27 VCA24 = 1 LVCMP2 VCC VCA24 = 0 + - Voltage detection 2 signal ≥ Vdet2 VCA1 register b3 VCA13 bit VCA26 Level selection circuit (16 levels) VD1S3 to VD1S0 Voltage detection 1 signal + - ≥ Vdet1 VW1C register b3 VW1C3 bit VCA25 Level selection circuit (4 levels) + Voltage detection 0 signal Internal reference voltage - ≥ Vdet0 VCA13: Bit in VCA1 register VCA24, VCA25, VCA26, VCA27: Bits in VCA2 register VW1C3: Bit in VW1C register VD1S0 to VD1S3: Bits in VD1LS register VDSEL0, VDSEL1: Bits in OFS register VDSEL1 to VDSEL0 Figure 6.1 Block Diagram of Voltage Detection Circuit Table 6.2 Pin Name LVCMP2 Pin Configuration of Voltage Detection Circuit I/O Input Function Detection target voltage pin for voltage detection 2 REJ09B0441-0010 Rev.0.10 Page 61 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit Voltage monitor 0 reset generation circuit VW0F1 to VW0F0 = 00b = 01b = 10b Voltage detection 0 circuit VCA25 fOCO-S 1/2 1/2 1/2 = 11b VW0C1 VCC VDSEL1 to VDSEL0 Level selection + Digital filter Internal reference voltage Voltage detection 0 signal When VCA25 bit is set to 0 (disabled), voltage detection 0 signal is driven high. Voltage monitor 0 reset signal VW0C1 VW0C0 VW0C0, VW0C1, VW0F0, VW0F1: Bits in VW0C register VCA25: Bit in VCA2 register VDSEL0, VDSEL1: Bits in OFS register Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit Voltage monitor 1 interrupt generation circuit VW1F1 to VW1F0 = 00b = 01b = 10b VW1C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA26 bit is set to 0 (voltage detection 1 circuit disabled), VW1C2 bit is set to 0. Voltage detection 1 circuit VCA26 fOCO-S 1/2 VW1C3 1/2 1/2 = 11b VCC VD1S3 to VD1S0 Level selection VCA22 = 0 + VCA21 = 0 Voltage detection 1 signal VW1C1 = 0 Digital filter VW1C1 = 1 Edge selection circuit VW1C2 Watchdog timer interrupt signal Internal reference voltage When VCA26 bit is set to 0 (disabled), voltage detection 1 signal is driven high. VCA1C VW1C7 Voltage monitor 1 interrupt signal VW1C0 Non-maskable interrupt signal Comparator A1 interrupt signal COMPSEL IRQ1SEL Maskable interrupt signal VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register VCA21, VCA22, VCA26: Bits in VCA2 register VD1S0 to VD1S3: Bits in VD1LS register COMPSEL, IRQ1SEL: Bits in CMPA register VCA1C: Bit in VCAC register Figure 6.3 Block Diagram of Voltage Monitor 1 Interrupt Generation Circuit REJ09B0441-0010 Rev.0.10 Page 62 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit Voltage monitor 2 interrupt generation circuit VW2F1 to VW2F0 = 00b = 01b Voltage detection 2 circuit fOCO-S VCA27 VCA24 = 1 LVCMP2 VCC VCA24 = 0 VCA23 = 0 Internal reference voltage When VCA27 bit is set to 0 (disabled), voltage detection 2 signal is driven high. + Voltage detection 2 signal VCA13 VW2C1 = 0 = 10b 1/2 1/2 1/2 = 11b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0. Digital filter VW2C1 = 1 Edge selection circuit VW2C2 Watchdog timer interrupt signal Voltage monitor 2 interrupt signal VCAC2 VW2C6 VW2C0 Non-maskable interrupt signal Watchdog timer block VW2C3 Comparator A2 interrupt signal Watchdog timer underflow signal VW2C3 bit is set to 0 (not detected) by writing 0 by a program. VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C VCA13: Bit in VCA1 register VCA23, VCA24, VCA27: Bits in VCA2 register COMPSEL, IRQ2SEL: Bits in CMPA register VCAC2: Bit in VCAC register COMPSEL IRQ2SEL Maskable interrupt signal Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt Generation Circuit REJ09B0441-0010 Rev.0.10 Page 63 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2 6.2.1 Registers Voltage Monitor Circuit/Comparator A Control Register (CMPA) b6 — 0 b5 IRQ2SEL 0 b4 IRQ1SEL 0 b3 CM2OE 0 b2 CM1OE 0 b1 CM2POR 0 b0 CM1POR 0 R/W R/W Address 0030h Bit b7 Symbol COMPSEL After Reset 0 Bit b0 Symbol CM1POR b1 b2 b3 b4 b5 b6 b7 Function 0: Non-inverted comparator A1 comparison result is output to LVCOUT1. 1: Inverted comparator A1 comparison result is output to LVCOUT1. CM2POR LVCOUT2 output polarity 0: Non-inverted Comparator A2 comparison result is select bit output to LVCOUT2. 1: Inverted comparator A2 comparison result is output to LVCOUT2. CM1OE LVCOUT1 output enable bit 0: Output disabled 1: Output enabled CM2OE LVCOUT2 output enable bit 0: Output disabled 1: Output enabled IRQ1SEL Voltage monitor 1/comparator A1 0: Non-maskable interrupt interrupt type select bit 1: Maskable interrupt IRQ2SEL Voltage monitor 2/comparator A2 0: Non-maskable interrupt interrupt type select bit 1: Maskable interrupt — Reserved bit Set to 0. COMPSEL Voltage monitor/comparator A 0: Bits IRQ1SEL and IRQ2SEL disabled interrupt type selection enable bit 1: Bits IRQ1SEL and IRQ2SEL enabled Bit Name LVCOUT1 output polarity select bit R/W R/W R/W R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 64 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 VCAC2 0 b1 VCAC1 0 b0 — 0 R/W — R/W R/W — Address 0031h Bit b7 Symbol — After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 0 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. VCAC1 Voltage monitor 1 circuit edge select bit (1) 0: One edge 1: Both edges VCAC2 Voltage monitor 2 circuit edge select bit (2) 0: One edge 1: Both edges — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — — Notes: 1. When the VCA1 bit is set to 0 (one edge), the VW1C7 bit in the VW1C register is enabled. Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. When the VCA2 bit is set to 0 (one edge), the VW2C7 bit in the VW2C register is enabled. Set the VW2C7 bit after setting the VCAC2 bit to 0. 6.2.3 Voltage Detect Register (VCA1) b6 — 0 b5 — 0 b4 — 0 b3 VCA13 1 b2 — 0 b1 — 0 b0 — 0 R/W R/W Address 0033h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Set to 0. Reserved bits — — VCA13 Voltage detection 2 signal monitor flag (1) 0: VCC < Vdet2 1: VCC ≥ Vdet2 or voltage detection 2 circuit disabled — Set to 0. Reserved bits — — — R R/W Note: 1. When the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled), the VCA13 bit is enabled. When the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled), the VCA13 bit is set to 1 (VCC ≥ Vdet2). REJ09B0441-0010 Rev.0.10 Page 65 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.4 Voltage Detect Register 2 (VCA2) b2 VCA22 0 0 b1 VCA21 0 0 b0 VCA20 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0034h Bit b7 b6 b5 b4 b3 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 After Reset The LVDAS bit in the OFS register is set to 1. 0 0 0 0 0 After Reset The LVDAS bit in the OFS register is set to 0. 0 0 1 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name VCA20 Internal power low consumption enable bit (1) VCA21 Comparator A1 reference voltage input select bit VCA22 LVCMP1 comparison voltage external input select bit VCA23 Comparator A2 reference voltage input select bit VCA24 LVCMP2 comparison voltage external input select bit VCA25 Voltage detection 0 enable bit (3) VCA26 VCA27 Voltage detection 1/comparator A1 enable bit (4) Voltage detection 2/comparator A2 enable bit (5) Function 0: Low consumption disabled 1: Low consumption enabled (2) 0: Internal reference voltage 1: LVREF pin input voltage 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage 0: Internal reference voltage 1: LVREF pin input voltage 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 10.7 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. REJ09B0441-0010 Rev.0.10 Page 66 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) b6 — 0 b5 — 0 b4 — 0 b3 VD1S3 0 b2 VD1S2 1 b1 VD1S1 1 b0 VD1S0 1 R/W R/W R/W R/W R/W Address 0036h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 Symbol Bit Name VD1S0 Voltage detection 1 level select bit VD1S1 (Reference voltage when the voltage falls) VD1S2 VD1S3 Function b3 b2 b1 b0 b4 b5 b6 b7 — — — — Reserved bits 0 0 0 0: 2.20 V 0 0 0 1: 2.35 V 0 0 1 0: 2.50 V 0 0 1 1: 2.65 V 0 1 0 0: 2.80 V 0 1 0 1: 2.95 V 0 1 1 0: 3.10 V 0 1 1 1: 3.25 V 1 0 0 0: 3.40 V 1 0 0 1: 3.55 V 1 0 1 0: 3.70 V 1 0 1 1: 3.85 V 1 1 0 0: 4.00 V 1 1 0 1: 4.15 V 1 1 1 0: 4.30 V 1 1 1 1: 4.45 V Set to 0. (Vdet1_0) (Vdet1_1) (Vdet1_2) (Vdet1_3) (Vdet1_4) (Vdet1_5) (Vdet1_6) (Vdet1_7) (Vdet1_8) (Vdet1_9) (Vdet1_A) (Vdet1_B) (Vdet1_C) (Vdet1_D) (Vdet1_E) (Vdet1_F) R/W R/W R/W R/W Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VD1LS register. REJ09B0441-0010 Rev.0.10 Page 67 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) b3 — X X b2 — 0 0 b1 VW0C1 1 1 b0 VW0C0 0 1 R/W R/W R/W Address 0038h Bit b7 b6 b5 b4 Symbol — — VW0F1 VW0F0 After Reset The LVDAS bit in the OFS register is set to 1. 1 1 0 0 After Reset The LVDAS bit in the OFS register is set to 0. 1 1 0 0 Bit b0 b1 Symbol Bit Name VW0C0 Voltage monitor 0 reset enable bit (1) b2 b3 b4 b5 b6 b7 Function 0: Disabled 1: Enabled VW0C1 Voltage monitor 0 digital filter disabled mode 0: Digital filter enabled mode select bit (digital filter circuit enabled) 1: Digital filter disabled mode (digital filter circuit disabled) — Reserved bit Set to 0. — Reserved bit When read, the content is undefined. b5 b4 VW0F0 Sampling clock select bit 0 0: fOCO-S divided by 1 VW0F1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 — Reserved bits Set to 1. — R/W R R/W R/W R/W R/W Note: 1. The VW0C0 bit is enabled when the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disabled) when the VCA25 bit in the VCA2 register is set to 0 (voltage detection 0 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure in Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset. Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing to the VW0C register. REJ09B0441-0010 Rev.0.10 Page 68 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) b6 — 0 b5 VW1F1 0 b4 VW1F0 0 b3 VW1C3 1 b2 VW1C2 0 b1 VW1C1 1 b0 VW1C0 0 R/W R/W R/W Address 0039h Bit b7 Symbol VW1C7 After Reset 1 Bit b0 b1 Symbol Bit Name VW1C0 Voltage monitor 1 reset enable bit (1) VW1C1 b2 b3 VW1C2 VW1C3 b4 b5 VW1F0 VW1F1 b6 b7 — VW1C7 Function 0: Disabled 1: Enabled Voltage monitor 0 digital filter 0: Digital filter enabled mode (digital filter circuit enabled) disable mode select bit (2) 1: Digital filter disable mode (digital filter circuit disabled) 0: Not detected Voltage change detection flag (3, 4) 1: Vdet1 passing detected Voltage detection 1 signal monitor flag (3) 0: VCC < Vdet1 1: VCC ≥ Vdet1 or voltage detection 1 circuit disabled b5 b4 Sampling clock select bit 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 Reserved bit Set to 0. Voltage monitor 1 reset 0: When VCC reaches Vdet1 or above. 1: When VCC reaches Vdet1 or below. generation condition select bit (5) R/W R R/W R/W R/W R/W Notes: 1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (voltage detection 1 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure shown in Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. 2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit. 3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). 4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the VCAC1 bit to 0, set the VW1C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW1C register. Rewriting the VW1C register may set the VW1C2 bit to 1. Set the VW1C2 bit to 0 after rewriting the VW1C register. REJ09B0441-0010 Rev.0.10 Page 69 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) b6 — 0 b5 VW2F1 0 b4 VW2F0 0 b3 VW2C3 0 b2 VW2C2 0 b1 VW2C1 1 b0 VW2C0 0 R/W R/W R/W Address 003Ah Bit b7 Symbol VW2C7 After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function VW2C0 Voltage monitor 2 interrupt enable bit (1) 0: Disabled 1: Enabled VW2C1 Voltage monitor 2 digital filter 0: Digital filter enable mode (digital filter circuit enabled) disable mode select bit (2) 1: Digital filter disable mode (digital filter circuit disabled) VW2C2 Voltage change detection flag (3, 4) 0: Not detected 1: Vdet2 passing detected VW2C3 WDT detection monitor flag (4) 0: Not detected 1: Detected b5 b4 VW2F0 Sampling clock select bit 0 0: fOCO-S divided by 1 VW2F1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 — Reserved bit Set to 0. VW2C7 Voltage monitor 2 interrupt 0: When VCC or LVCMP2 reaches Vdet2 or above. generation condition select bit (5) 1: When VCC or LVCMP2 reaches Vdet2 or below. R/W R/W R/W R/W R/W R/W Notes: 1. The VW2C0 is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). To set the VW2C0 bit to 1 (enabled), follow the procedure shown in Table 6.5 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. 2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit. 3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the VCAC2 bit to 0, set the VW2C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0. REJ09B0441-0010 Rev.0.10 Page 70 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.2.9 Option Function Select Register (OFS) b6 LVDAS 1 b5 b4 b3 b2 VDSEL1 VDSEL0 ROMCP1 ROMCR 1 1 1 1 b1 — 1 b0 WDTON 1 (Note 1) R/W R/W R/W R/W R/W Address 0FFFFh Bit b7 Symbol CSPROINI When shipping 1 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name WDTON Watchdog timer start select bit — Reserved bit ROMCR ROM code protect disable bit ROMCP1 ROM code protect bit VDSEL0 Voltage detection 0 level select bit (2) VDSEL1 Function 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset Set to 1. 0: ROM code protect disabled 1: ROMCP1 bit enabled 0: ROM code protect enabled 1: ROM code protect disabled b5 b4 b6 b7 LVDAS Voltage detection 0 circuit start bit (3) CSPROINI Count source protection mode after reset select bit R/W 0 0: 3.80 V selected (Vdet0_3) R/W 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) 0: Voltage monitor 0 reset enabled after reset R/W 1: Voltage monitor 0 reset disabled after reset 0: Count source protection mode enabled after reset R/W 1: Count source protection mode disabled after reset Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. REJ09B0441-0010 Rev.0.10 Page 71 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.3 6.3.1 VCC Input Voltage Monitoring Vdet0 Vdet0 cannot be monitored. 6.3.2 Monitoring Vdet1 Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 36. Electrical Characteristics). (1) Set bits VD1S3 to VD1S0 in the VD1LS register (voltage detection 1 detection voltage). (2) Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage). (3) Set the VCA22 bit in the VCA2 register to 0 (VCC voltage). (4) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). 6.3.3 Monitoring Vdet2 Once the following settings are made, the comparison result of voltage monitor 2 can be monitored by the VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 36. Electrical Characteristics). (1) Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage). (2) Set the VCA24 bit in the VCA2 register to 0 (VCC voltage), or 1 (LVCMP2 pin input voltage). (3) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). REJ09B0441-0010 Rev.0.10 Page 72 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.4 Voltage Monitor 0 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.5 shows an Operating Example of Voltage Monitor 0 Reset. To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). Table 6.3 Step 1 2 3 4 (1) 5 6 7 8 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset When Using Digital Filter When Using No Digital Filter Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled). Wait for td(E-A). Select the sampling clock of the digital filter by Set the VW0C7 bit in the VW0C register to 1. bits VW0F1 to VW0F0 in the VW0C register. Set the VW0C1 bit in the VW0C register to 0 Set the VW0C1 bit in the VW0C register to 1 (digital filter enabled). (digital filter disabled). Set the VW0C2 bit in the VW0C register to 0. Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on). Wait for 4 cycles of the sampling clock of − (No wait time required) the digital filter. Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled). Note: 1. When the VW0C0 bit is set to 0, steps 3 and 4 can be executed simultaneously (with one instruction). VCC Vdet0 Sampling clock of digital filter × 4 cycles VW0C1 bit is set to 0 (digital filter enabled) Internal reset signal 1 × 32 fOCO-S 1 × 32 fOCO-S VW0C1 bit is set to 1 (digital filter disabled) Internal reset signal VW0C1 and VW0C7: Bits in VW0C register The above applies under the following conditions: • VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled) • VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled) When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized. When the internal reset signal level changes from low to high, a program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after reset. Figure 6.5 Operating Example of Voltage Monitor 0 Reset REJ09B0441-0010 Rev.0.10 Page 73 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.5 Voltage Monitor 1 Interrupt Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of Voltage Monitor 1 Interrupt. To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Table 6.4 Step 1 2 3 (1) 4 (1) 5 6 7 (2) 8 9 (3) 10 11 12 13 14 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt When Using Digital Filter When Using No Digital Filter Select the voltage detection 1 detection voltage by bits VD1S3 to VD1S0 in the VD1LS register. Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage). Set the VCA22 bit in the VCA2 register to 0 (VCC voltage). Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). Wait for td(E-A). Set the COMPSEL bit in the CMPA register to 1. Select the interrupt type by the IRQ1SEL in the CMPA register. Select the sampling clock of the digital filter by Set the VW1C1 bit in the VW1C register to 1 bits VW1F1 to VW1F0 in the VW1C register. (digital filter disabled). Set the VW1C1 bit in the VW1C register to 0 − (digital filter enabled). Select the interrupt request timing by the VCAC1 bit in the VCAC register and the VW1C7 bit in the VW1C register. Set the VW1C2 bit in the VW1C register to 0. Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) − (No wait time required) Wait for 2 cycles of the sampling clock of the digital filter Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled) Notes: 1. When the VW1C0 bit is set to 0, steps 2, 3, and 4 can be executed simultaneously (with one instruction). 2. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed simultaneously (with one instruction). 3. When the VW1C0 bit is set to 0, steps 8 and 9 can be executed simultaneously (with one instruction). REJ09B0441-0010 Rev.0.10 Page 74 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit VCC Vdet1 1.8 V (1) 1 VW1C3 bit 0 Sampling clock of digital filter × 2 cycles 1 VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) VW1C2 bit 0 Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Sampling clock of digital filter × 2 cycles Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) 1 VW1C2 bit 0 Voltage monitor 1 interrupt request Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) 1 VW1C2 bit 0 Voltage monitor 1 interrupt request Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. 1 VW1C1 bit is set to 1 (digital filter disabled) and VCAC1 bit is set to 1 (both edges) VW1C2 bit 0 Voltage monitor 1 interrupt request Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) 1 VW1C2 bit 0 Voltage monitor 1 interrupt request Set to 0 when an interrupt request is acknowledged. VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) Set to 0 by a program. 1 VW1C2 bit 0 Voltage monitor 1 interrupt request Set to 0 when an interrupt request is acknowledged. VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register The above applies under the following conditions: • VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled) • VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt enabled) Note: 1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V. Figure 6.6 Operating Example of Voltage Monitor 1 Interrupt REJ09B0441-0010 Rev.0.10 Page 75 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit 6.6 Voltage Monitor 2 Interrupt Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of Voltage Monitor 2 Interrupt. To use the voltage monitor 2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Table 6.5 Step 1 2 (1) 3 (1) 4 5 6 (2) 7 8 (3) 9 10 11 12 13 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt When Using Digital Filter When Using No Digital Filter Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage). Set the VCA24 bit in the VCA2 register to 0 (VCC voltage) or 1 (LCVCMP2 pin input voltage). Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). Wait for td(E-A). Set the COMPSEL bit in the CMPA register to 1. Select the interrupt type by the IRQ2SEL in the CMPA register. Select the sampling clock of the digital filter by Set the VW2C1 bit in the VW2C register to 1 bits VW2F1 to VW2F0 in the VW2C register. (digital filter disabled). Set the VW2C1 bit in the VW2C register to 0 − (digital filter enabled). Select the interrupt request timing by the VCAC2 bit in the VCAC register and the VW2C7 bit in the VW2C register. Set the VW2C2 bit in the VW2C register to 0. Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on). − (No wait time required) Wait for 2 cycles of the sampling clock of the digital filter. Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt enabled). Notes: 1. When the VW2C0 bit is set to 0, steps 1, 2, and 3 can be executed simultaneously (with one instruction). 2. When the VW2C0 bit is set to 0, steps 5 and 6 can be executed simultaneously (with one instruction). 3. When the VW2C0 bit is set to 0, steps 7 and 8 can be executed simultaneously (with one instruction). REJ09B0441-0010 Rev.0.10 Page 76 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit VCC or LVCMP2 Vdet2 1.8 V (1) 1 VW1C3 bit 0 Sampling clock of digital filter × 2 cycles 1 VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) VW2C2 bit 0 Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Sampling clock of digital filter × 2 cycles Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when VCC or LVCMP2 reaches Vdet2 or above) 1 VW2C2 bit 0 Voltage monitor 2 interrupt request Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when VCC or LVCMP2 reaches Vdet2 or below) 1 VW2C2 bit 0 Voltage monitor 2 interrupt request Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. 1 VW2C1 bit is set to 1 (digital filter disabled) and VCAC2 bit is set to 1 (both edges) VW2C2 bit 0 Voltage monitor 2 interrupt request Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when VCC or LVCMP2 reaches Vdet2 or above) 1 VW2C2 bit 0 Voltage monitor 2 interrupt request Set to 0 when an interrupt request is acknowledged. VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when VCC or LVCMP2 reaches Vdet2 or below) 1 VW2C2 bit 0 Voltage monitor 2 interrupt request Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C3, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register The above applies under the following conditions: • VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled) • VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt enabled) Note: 1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V. Figure 6.7 Operating Example of Voltage Monitor 2 Interrupt REJ09B0441-0010 Rev.0.10 Page 77 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7. I/O Ports I/O ports are shared with the LCD ports for the LCD dive control waveform output and the I/O functions for the oscillation circuits, timers, and A/D converter. When these functions are not used, pins can be used as I/O ports. Table 7.1 lists the Overview of I/O Ports. The following explanation applies to the R8C/L33A Group and R8C/L3AB Group, which have the maximum number of I/O ports. For other groups, note that only the pins listed in Table 7.2 are provided. Table 7.1 Port P0 to P4 P5_0 to P5_3 P6, P7 P10, P11 Overview of I/O Ports I/O Format I/O CMOS3 state I/O CMOS3 state I/O CMOS3 state I/O CMOS3 state I/O Setting Set in 1-bit units. Set in 1-bit units. Set in 1-bit units. Set in 1-bit units. Internal Pull-Up Resister (1) Set in 1-bit units. Set in 1-bit units. Set in 1-bit units. Set in 1-bit units. Drive Capacity Switch (2) None None None Set in 1-bit units. Input Level Switch (3) Set in 8-bit units. Set in 4-bit units. Set in 8-bit units. Set in 8-bit units. Set in 1-bit units. Set in 1-bit units. None Set in 4-bit units. P13 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. None Set in 8-bit units. Notes: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers P0PUR to and P13PUR. 2. Whether the drive capacity of the output transistor is set to low or high can be selected by registers P10DRR and P11DRR. 3. The input threshold value can be selected among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC) using registers VLT0 and VLT1. P12_0 to P12_3 I/O CMOS3 state Table 7.2 Programmable I/O Port Programmable I/O Ports Provided for Each Group R8C/L35A Group R8C/L35B Group Total: 41 I/O pins bit 7 bit 6 √ − √ − √ − − √ − − − − R8C/L36A Group R8C/L36B Group Total: 52 I/O pins bit 0 √ − − √ √ − − − − √ √ √ R8C/L38A Group R8C/L38B Group Total: 68 I/O pins bit 0 √ − − √ √ − − √ − √ √ √ R8C/L3AA Group R8C/L3AB Group Total: 88 I/O pins bit 0 √ √ √ √ √ − √ √ − √ √ √ bit 5 √ − √ − √ − − √ − − − − bit 4 √ − √ − √ − − √ − √ − − bit 3 √ − − √ √ − − − − √ √ √ bit 2 √ − − √ √ − − − − √ √ √ bit 1 √ − − √ √ − − − − √ √ √ bit 7 √ − √ √ √ − − √ − √ − − bit 6 √ − √ √ √ − − √ − √ − − bit 5 √ − √ √ √ − − √ − √ − − bit 4 √ − √ √ √ − − √ − √ − − bit 3 √ − − √ √ − − √ − √ √ √ bit 2 √ − − √ √ − − √ − √ √ √ bit 1 √ − − √ √ − − √ − √ √ √ bit 7 √ − √ √ √ − √ √ − √ − − bit 6 √ − √ √ √ − √ √ − √ − − bit 5 √ − √ √ √ − √ √ − √ − − bit 4 √ − √ √ √ − √ √ − √ − − bit 3 √ √ √ √ √ − √ √ − √ √ √ bit 2 √ √ √ √ √ − √ √ − √ √ √ bit 1 √ √ √ √ √ − √ √ − √ √ √ bit 7 √ √ √ √ √ − √ √ √ √ − √ bit 6 √ √ √ √ √ − √ √ √ √ − √ bit 5 √ √ √ √ √ − √ √ √ √ − √ bit 4 √ √ √ √ √ − √ √ √ √ − √ bit 3 √ √ √ √ √ √ √ √ √ √ √ √ bit 2 √ √ √ √ √ √ √ √ √ √ √ √ bit 1 √ √ √ √ √ √ √ √ √ √ √ √ bit 0 √ √ √ √ √ √ √ √ √ √ √ √ P0 P1 P2 P3 P4 P5 P6 P7 P10 P11 P12 P13 √ − √ − √ − − √ − − − − Note: 1. The symbol “√” indicates a programmable I/O port. REJ09B0441-0010 Rev.0.10 Page 78 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.1 I/O Port Functions The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 7, 10 to 13) register controls the input/output of ports P0 to P7 and P10 to P13. The Pi register consists of a port latch to retain output data and a circuit to read the pin status. Figures 7.1 to 7.4 show the I/O Port Configurations, and Table 7.3 lists the I/O Port Functions. Table 7.3 I/O Port Functions Operation When Value of PDi_j Bit in PDi Register (1) Accessing When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode) Pi Register Read Read the pin input level. Read the port latch. Write to the port latch. The value written to Write Write to the port latch. the port latch is output from the pin. Note: 1. i = 0 to 7, 10 to 13; j = 0 to 7 7.2 Effect on Peripheral Functions I/O ports function as I/O ports for peripheral functions (refer to Tables 1.15 to 1.17 Pin Name Information by Pin Number). Table 7.4 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 7, 10 to 13; j = 0 to 7). Refer to the description of each function for information on how to set peripheral functions. Table 7.4 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 7, 10 to 13; j = 0 to 7) I/O of Peripheral Function PDi_j Bit Settings for Shared Pin Function Input Set this bit to 0 (input mode). Output This bit can be set to either 0 or 1 (output regardless of the port setting). 7.3 Pins Other than I/O Ports Figure 7.5 shows the Pin Configuration. REJ09B0441-0010 Rev.0.10 Page 79 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports P0 to P3, P5, and P7 Pull-up selection Direction register LCD port select Data bus Port latch (Note 1) Input level switch function Input to individual peripheral function VL4 VL3 VL2 VL1 VSS Pin select register Analog input of A/D converter P0, P1_0 to P1_3 only P4 and P6 Pull-up selection LCD port select Direction register 1 Pin select register Input to individual peripheral function Data bus Port latch (Note 1) Input level switch function Input to individual peripheral function VL4 VL3 VL2 VL1 VSS Note: 1. symbolizes a parasitic diode. Pin select register Figure 7.1 I/O Port Configuration (1) REJ09B0441-0010 Rev.0.10 Page 80 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Pull-up selection P10 and P11 Drive capacity selection Direction register 1 Pin select register Input to individual peripheral function Data bus Port latch (Note 2) (Note 1) Input level switch function Input to individual peripheral function Pin select register Analog input of comparators A and B P11_0 to P11_3 only P12_2 and P12_3 Pull-up selection Direction register LCD port select Data bus Port latch (Note 1) Input level switch function VL4 VL3 VL2 VL1 VSS Notes: 1. 2. symbolizes a parasitic diode. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.2 I/O Port Configuration (2) REJ09B0441-0010 Rev.0.10 Page 81 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports P12_0/XIN Pull-up selection Direction register (Note 2) Data bus Port latch (Note 1) Input level switch function CM05 CM07 Stop mode CM13 = 0 Input to XIN clock CM13 = 1 Stop mode CM11 RfXIN CM05 CM13 P12_1/XOUT Pull-up selection Direction register (Note 2) Data bus Port latch (Note 1) Input level switch function Notes: 1. 2. symbolizes a parasitic diode. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. CM05, CM07: Bits in CM0 register CM11, CM13: Bits in CM1 register Figure 7.3 I/O Port Configuration (3) REJ09B0441-0010 Rev.0.10 Page 82 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports P13_0 to P13_7 Pull-up selection Direction register 1 Pin select register Input to individual peripheral function Data bus Port latch (Note 2) (Note 1) Input level switch function Input to individual peripheral function Analog input of A/D converter Pin select register Analog input of comparator A P13_2 to P13_4 only Analog input of D/A converter P13_0 and P13_1 only Notes: 1. 2. symbolizes a parasitic diode. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.4 I/O Port Configuration (4) REJ09B0441-0010 Rev.0.10 Page 83 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports XCIN/XCOUT Stop mode (Note 2) CM03 (Note 2) XCOUT (Note 1) XCIN (Note 1) Input to XIN clock RfXCIN VREF Stop mode CM12 (Note 2) A/D converter VREF (Note 1) WKUP0 Power-off mode input signal (Note 1) MODE MODE input signal (Note 1) RESET RESET input signal (Note 1) Notes: 1. 2. symbolizes a parasitic diode. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.5 Pin Configuration REJ09B0441-0010 Rev.0.10 Page 84 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4 7.4.1 Registers Port Pi Direction Register (PDi) (i = 0 to 7, 10 to 13) Address 00E2h (PD0), 00E3h (PD1), 00E6h (PD2), 00E7h (PD3), 00EAh (PD4 (1)), 00EBh (PD5 (2)), 00EEh (PD6), 00EFh (PD7), 00F6h (PD10), 00F7h (PD11), 00FAh (PD12), 00FBh (PD13), Bit b7 b6 b5 b4 b3 b2 Symbol PDi_7 PDi_6 PDi_5 PDi_4 PDi_3 PDi_2 After Reset 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Bit Name Port Pi_0 direction bit Port Pi_1 direction bit Port Pi_2 direction bit Port Pi_3 direction bit Port Pi_4 direction bit Port Pi_5 direction bit Port Pi_6 direction bit Port Pi_7 direction bit b1 PDi_1 0 b0 PDi_0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Function 0: Input mode (function as an input port) 1: Output mode (function as an output port) Notes: 1. Bits PD5_4 to PD5_7 in the PD5 register are unavailable on this MCU. If it is necessary to set bits PD5_4 to PD5_7, set to 0. When read, the content is 0. 2. Bits PD12_4 to PD12_7 in the PD12 register are unavailable on this MCU. If it is necessary to set bits PD12_4 to PD12_7, set to 0. When read, the content is 0. The PDi register selects whether I/O ports are used for input or output. Each bit in the PDi register corresponds to one port. REJ09B0441-0010 Rev.0.10 Page 85 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.2 Port Pi Register (Pi) (i = 0 to 7, 10 to 13) Address 00E0h (P0), 00E1h (P1), 00E4h (P2), 00E5h (P3), 00E8h (P4 (1)), 00E9h (P5 (2)), 00ECh(P6), 00EDh (P7), 00F4h (P10), 00F5h (P11), 00F8h (P12), 00F9h (P13), Bit Symbol After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 b7 Pi_7 X b6 Pi_6 X b5 Pi_5 X Bit Name Port Pi_0 bit Port Pi_1 bit Port Pi_2 bit Port Pi_3 bit Port Pi_4 bit Port Pi_5 bit Port Pi_6 bit Port Pi_7 bit 0: Low level 1: High level b4 Pi_4 X b3 Pi_3 X b2 Pi_2 X b1 Pi_1 X Function b0 Pi_0 X R/W R/W R/W R/W R/W R/W R/W R/W R/W Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Notes: 1. Bits PD5_4 to PD5_7 in the PD5 register are unavailable on this MCU. If it is necessary to set bits PD5_4 to PD5_7, set to 0. When read, the content is 0. 2. Bits PD12_4 to PD12_7 in the PD12 register are unavailable on this MCU. If it is necessary to set bits PD12_4 to PD12_7, set to 0. When read, the content is 0. Data input and output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to retain output data and a circuit to read the pin status. The value written in the port latch is output from the pin. Each bit in the Pi register corresponds to one port. Pi_j Bit (i = 0 to 7, 10 to 13, j = 0 to 7) (Port Pi_0 Bit) The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port which is set to output mode can be controlled by writing to the corresponding bit in this register. REJ09B0441-0010 Rev.0.10 Page 86 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.3 Timer RA Pin Select Register (TRASR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 b0 TRAIOSEL1 TRAIOSEL0 0 0 Function b1 b0 Address 0180h Bit b7 Symbol — After Reset 0 Bit b0 b1 Symbol Bit Name TRAIOSEL0 TRAIO pin select bit TRAIOSEL1 0 0: TRAIO pin not used 0 1: P11_4 assigned R/W R/W R/W b2 b3 b4 b5 b6 b7 — — — — — — 1 0: INT4 assigned 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Note: 1. To use hardware LIN, set 01b to bits TRAIOSEL1 to TRAIOSEL0. To use the I/O pin for timer RA, set the TRASR register. Set this register before setting the timer RA associated registers. Also, do not change the setting value of this register during timer RA operation. REJ09B0441-0010 Rev.0.10 Page 87 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.4 Timer RB/RC Pin Select Register (TRBRCSR) b5 — Address 0181h Bit b7 b6 Symbol TRCTRGSEL1 TRCTRGSEL0 After Reset 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b4 TRCCLKSEL0 b3 — b2 — b1 — b0 — 0 0 0 0 0 0 R/W — Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — TRCCLKSEL0 TRCCLK pin select bit 0: TRCCLK pin not used 1: TRCCLK pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 b6 TRCTRGSEL0 TRCTRG pin select bit 0 0: TRCTRG pin not used TRCTRGSEL1 0 1: P3_7 assigned 1 0: P4_3 assigned 1 1: P4_4 assigned R/W — R/W R/W The register function for timer RB is not implemented. To use the I/O pins for timer RC, set the TRBRCSR register. Set this register before setting the timer RC associated registers. Also, do not change the setting value of the TRCCLKSEL0 bit during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 88 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) b6 — 0 b5 b4 TRCIOBSEL1 TRCIOBSEL0 0 0 b3 — 0 b2 — 0 b1 — 0 b0 TRCIOASEL0 0 R/W R/W — Address 0182h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name TRCIOASEL0 TRCIOA pin select bit — — — TRCIOBSEL0 TRCIOB pin select bit TRCIOBSEL1 Function 0: TRCIOA pin not used 1: TRCIOA pin used Nothing is assigned. If necessary, set to 0. When read, the content is 0. b5 b4 b6 b7 — — 0 0: TRCIOB pin not used 0 1: P4_5 assigned 1 0: P4_6 assigned 1 1: P4_7 assigned Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W — The TRCPSR0 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 89 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.6 Timer RC Pin Select Register 1 (TRCPSR1) b6 — 0 b5 — 0 b4 TRCIODSEL0 0 b3 — 0 b2 — 0 b1 — 0 b0 TRCIOCSEL0 0 R/W R/W — Address 0183h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name TRCIOCSEL0 TRCIOC pin select bit (1) — — — TRCIODSEL0 TRCIOD pin select bit (2) — — — Function 0: TRCIOC pin not used 1: P4_6 assigned Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0: TRCIOD pin not used 1: P4_7 assigned Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W — Notes: 1. When bits TRCIOBSEL1 to TRCIOBSEL0 in the TRCPSR0 register are set to 10b (P4_6 assigned as TRCIOB pin), P4_6 functions as the TRCIOB pin regardless of the content of the TRCIOCSEL0 bit. 2. When bits TRCIOBSEL1 to TRCIOBSEL0 in the TRCPSR0 register are set to 11b (P4_7 assigned as TRCIOB pin), P4_7 functions as the TRCIOB pin regardless of the content of the TRCIODSEL0 bit. The TRCPSR1 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 90 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.7 Timer RD Pin Select Register 0 (TRDPSR0) Bit b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 Address 0184h b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 After Reset Bit b0 b1 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 91 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.8 Timer RD Pin Select Register 1 (TRDPSR1) Bit b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 Address 0185h b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 After Reset Bit b0 b1 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 92 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.9 Timer RG Pin Select Register (TRGPSR) b4 TRGIOASEL0 Address 0187h Bit b7 b6 b5 Symbol TRGCLKBSEL0 TRGCLKASEL0 TRGIOBSEL0 After Reset 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol — — — — TRGIOASEL0 TRGIOBSEL0 b3 — b2 — b1 — b0 — 0 0 0 0 0 R/W — Bit Name Function Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRGIOA pin select bit TRGIOB pin select bit TRGCLKASEL0 TRGCLKA pin select bit TRGCLKBSEL0 TRGCLKB pin select bit 0: TRGIOA pin not used 1: TRGIOA pin used 0: TRGIOB pin not used 1: TRGIOB pin used 0: TRGCLKA pin not used 1: TRGCLKA pin used 0: TRGCLKB pin not used 1: TRGCLKB pin used R/W R/W R/W R/W The TRGPSR register selects which pin is assigned as the timer RG input/output. To use the I/O pins for timer RG, set this register. Set the TRGPSR register before setting the timer RG associated registers. Also, do not change the setting value of this register during timer RG operation. 7.4.10 UART0 Pin Select Register (U0SR) b6 — 0 b5 — 0 b4 CLK0SEL0 0 b3 — 0 b2 b1 b0 RXD0SEL0 RXD0SEL1 TXD0SEL0 0 0 0 R/W R/W — R/W R/W Address 0188h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Function 0: TXD0 pin not used 1: TXD0 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b3 b2 RXD0SEL0 RXD0 pin select bit 0 0: RXD0 pin not used RXD0SEL1 0 1: P13_2 assigned 1 0: P11_4 assigned 1 1: Do not set. CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used 1: CLK0 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — Symbol Bit Name TXD0SEL0 TXD0 pin select bit R/W — The U0SR register selects which pin is assigned as the UART0 input/output. To use the I/O pins for UART0, set this register. Set the U0SR register before setting the UART0 associated registers. Also, do not change the setting value of this register during UART0 operation. REJ09B0441-0010 Rev.0.10 Page 93 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.11 UART1 Pin Select Register (U1SR) b6 — 0 b5 — 0 b4 CLK1SEL0 0 b3 — 0 b2 RXD1SEL0 0 b1 — 0 b0 TXD1SEL0 0 R/W R/W — R/W — R/W — Address 0189h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Function 0: TXD1 pin not used 1: TXD1 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. RXD1SEL0 RXD1 pin select bit 0: RXD1 pin not used 1: RXD1 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. CLK1SEL0 CLK1 pin select bit 0: CLK1 pin not used 1: CLK1 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — Symbol Bit Name TXD1SEL0 TXD1 pin select bit The U1SR register selects which pin is assigned as the UART1 input/output. To use the I/O pins for UART1, set this register. Set the U1SR register before setting the UART1 associated registers. Also, do not change the setting value of this register during UART1 operation. REJ09B0441-0010 Rev.0.10 Page 94 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.12 UART2 Pin Select Register 0 (U2SR0) b6 — 0 b5 b4 RXD2SEL1 RXD2SEL0 0 0 b3 — 0 b2 — 0 b1 b0 TXD2SEL1 TXD2SEL0 0 0 Function b1 b0 Address 018Ah Bit b7 Symbol — After Reset 0 Bit b0 b1 Symbol Bit Name TXD2SEL0 TXD2/SDA2 pin select bit TXD2SEL1 b2 b3 b4 b5 — — RXD2SEL0 RXD2/SCL2 pin select bit RXD2SEL1 0 0: TXD2/SDA2 pin not used 0 1: P11_2 assigned 1 0: P11_1 assigned 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. b5 b4 R/W R/W R/W — R/W R/W b6 b7 — — 0 0: RXD2/SCL2 pin not used 0 1: P11_1 assigned 1 0: P11_2 assigned 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — The U2SR0 register selects which pin is assigned as the UART2 input/output. To use the I/O pins for UART2, set this register. Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. REJ09B0441-0010 Rev.0.10 Page 95 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.13 UART2 Pin Select Register 1 (U2SR1) b6 — 0 b5 — 0 b4 CTS2SEL0 0 b3 — 0 b2 — 0 b1 — 0 b0 CLK2SEL0 0 R/W R/W — Address 018Bh Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name CLK2SEL0 CLK2 pin select bit — — — CTS2SEL0 CTS2/RTS2 pin select bit — — — Function 0: CLK2 pin not used 1: CLK2 pin used Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0: CTS2/RTS2 pin not used 0: CTS2/RTS2 pin used Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W — The U2SR1 register selects which pin is assigned as the UART2 input/output. To use the I/O pins for UART2, set this register. Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. REJ09B0441-0010 Rev.0.10 Page 96 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.14 SSU/IIC Pin Select Register (SSUIICSR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 IICSEL 0 R/W R/W — Address 018Ch Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IICSEL — — — — — — — Bit Name SSU/I2C bus switch bit Function 0: SSU function selected 1: I2C bus function selected Nothing is assigned. If necessary, set to 0. When read, the content is 0. REJ09B0441-0010 Rev.0.10 Page 97 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.15 Key Input Pin Select Register (KISR) b6 KI6SEL0 0 b5 KISEL0 0 b4 KI4SEL0 0 b3 KI3SEL0 0 b2 KI2SEL0 0 b1 KI1SEL0 0 b0 KI0SEL0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 018Dh Bit b7 Symbol KI7SEL0 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name KI0SEL0 KI0 pin select bit KI1SEL0 KI1 pin select bit KI2SEL0 KI2 pin select bit KI3SEL0 KI3 pin select bit KI4SEL0 KI4 pin select bit KI5SEL0 KI5 pin select bit KI6SEL0 KI6 pin select bit KI7SEL0 KI7 pin select bit Function 0: P2_0 assigned 1: P10_0 assigned 0: P2_1 assigned 1: P10_1 assigned 0: P2_2 assigned 1: P10_2 assigned 0: P2_3 assigned 1: P10_3 assigned 0: P2_4 assigned 1: P10_4 assigned 0: P2_5 assigned 1: P10_5 assigned 0: P2_6 assigned 1: P10_6 assigned 0: P2_7 assigned 1: P10_7 assigned The KISR register selects which pin is assigned as the KIi (i = 1 to 7) input. To use the KIi, set this register. Set the KISR register before setting the KIi associated registers. Also, do not change the setting values in this register during KIi operation. REJ09B0441-0010 Rev.0.10 Page 98 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.16 INT Interrupt Input Pin Select Register (INTSR) Address 018Eh Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol INT7SEL0 INT6SEL0 INT5SEL0 INT4SEL0 INT3SEL0 INT2SEL0 INT1SEL0 INT0SEL0 After Reset 0 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name 0: P3_0 assigned 1: P11_0 assigned 0: P3_1 assigned 1: P11_1 assigned 0: P3_2 assigned 1: P11_2 assigned 0: P3_3 assigned 1: P11_3 assigned 0: P3_4 assigned 1: P11_4 assigned 0: P3_5 assigned 1: P11_5 assigned 0: P3_6 assigned 1: P11_6 assigned 0: P3_7 assigned 1: P11_7 assigned Function R/W R/W R/W R/W R/W R/W R/W R/W R/W INT0SEL0 INT0 pin select bit INT1SEL0 INT1 pin select bit INT2SEL0 INT2 pin select bit INT3SEL0 INT3 pin select bit INT4SEL0 INT4 pin select bit INT5SEL0 INT5 pin select bit INT6SEL0 INT6 pin select bit INT7SEL0 INT7 pin select bit The INTSR register selects which pin is assigned as the INTi (i = 1 to 7) input. To use the INTi, set this register. Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this register during INTi operation. 7.4.17 Port Pi Pull-Up Control Register (PiPUR) (i = 0 to 7) Address 01E0h (P0PUR), 01E1h (P1PUR), 01E2h (P2PUR), 01E3h (P3PUR), 01E4h (P4PUR), 01E5h (P5PUR), 01E6h (P6PUR), 01E7h (P7PUR) Bit b7 b6 b5 b4 b3 b2 b1 Symbol PUi7 PUi6 PUi5 PUi4 PUi3 PUi2 PUi1 After Reset 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PUi0 PUi1 PUi2 PUi3 PUi4 PUi5 PUi6 PUi7 Bit Name Port Pi_0 pull-up Port Pi_1 pull-up Port Pi_2 pull-up Port Pi_3 pull-up Port Pi_4 pull-up Port Pi_5 pull-up Port Pi_6 pull-up Port Pi_7 pull-up Function 0: Not pulled up 1: Pulled up (1) b0 PUi0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: 1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up. For ports set to output as I/O pins for peripheral functions, the setting values of the PiPUR register are invalid and no pull-up resistor is connected. REJ09B0441-0010 Rev.0.10 Page 99 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.18 Port Pj Pull-Up Control Register (PjPUR) (j = 10 to 13) b0 PUj0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 01EAh (P10PUR), 01EBh (P11PUR), 01ECh (P12PUR), 01EDh (P13PUR) Bit b7 b6 b5 b4 b3 b2 b1 Symbol PUj7 PUj6 PUj5 PUj4 PUj3 PUi2 PUj1 After Reset 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PUj0 PUj1 PUj2 PUj3 PUj4 PUj5 PUj6 PUj7 Bit Name Port Pj_0 pull-up Port Pj_1 pull-up Port Pj_2 pull-up Port Pj_3 pull-up Port Pj_4 pull-up Port Pj_5 pull-up Port Pj_6 pull-up Port Pj_7 pull-up Function 0: Not pulled up 1: Pulled up (1) Note: 1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up. For ports set to output as I/O pins for peripheral functions, the setting values of the PjPUR register are invalid and no pull-up resistor is connected. 7.4.19 Port P10 Drive Capacity Control Register (P10DRR) Address 01F0h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol P10DRR7 P10DRR6 P10DRR5 P10DRR4 P10DRR3 P10DRR2 P10DRR1 P10DRR0 After Reset 0 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol P10DRR0 P10DRR1 P10DRR2 P10DRR3 P10DRR4 P10DRR5 P10DRR6 P10DRR7 Bit Name P10_0 drive capacity P10_1 drive capacity P10_2 drive capacity P10_3 drive capacity P10_4 drive capacity P10_5 drive capacity P10_6 drive capacity P10_7 drive capacity Function 0: Low 1: High (1) R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: 1. Both high-level output and low-level output are set to high drive capacity. The P10DRR register selects whether the drive capacity of the P10 output transistor is set to low or high. The P10DRRi bit (i = 0 to 7) is used to select whether the drive capacity of the output transistor is set to low or high for each pin. REJ09B0441-0010 Rev.0.10 Page 100 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.20 Port P11 Drive Capacity Control Register (P11DRR) Address 01F1h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol P11DRR7 P11DRR6 P11DRR5 P11DRR4 P11DRR3 P11DRR2 P11DRR1 P11DRR0 After Reset 0 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol P11DRR0 P11DRR1 P11DRR2 P11DRR3 P11DRR4 P11DRR5 P11DRR6 P11DRR7 Bit Name P11_0 drive capacity P11_1 drive capacity P11_2 drive capacity P11_3 drive capacity P11_4 drive capacity P11_5 drive capacity P11_6 drive capacity P11_7 drive capacity Function 0: Low 1: High (1) R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: 1. Both high-level output and low-level output are set to high drive capacity. The P11DRR register selects whether the drive capacity of the P11 output transistor is set to low or high. The P11DRRi bit (i = 0 to 7) is used to select whether the drive capacity of the output transistor is set to low or high for each pin. 7.4.21 Input Threshold Control Register 0 (VLT0) b6 VLT06 0 b5 VLT05 0 b4 VLT04 0 b3 VLT03 0 b2 VLT02 0 b1 VLT01 0 Function b1 b0 Address 01F5h Bit b7 Symbol VLT07 After Reset 0 Bit b0 b1 b0 VLT00 0 R/W R/W R/W Symbol Bit Name VLT00 P0 input level select bit VLT01 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b3 b2 b2 b3 VLT02 VLT03 P1 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b5 b4 R/W R/W b4 b5 VLT04 VLT05 P2 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b7 b6 R/W R/W b6 b7 VLT06 VLT07 P3 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W R/W The VLT0 register selects the voltage level of the input threshold values for ports P0 to P3. Bits VLT00 to VLT07 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). REJ09B0441-0010 Rev.0.10 Page 101 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.22 Input Threshold Control Register 1 (VLT1) b6 VLT16 0 b5 VLT15 0 b4 VLT14 0 b3 VLT13 0 b2 VLT12 0 b1 VLT11 0 Function b1 b0 Address 01F6h Bit b7 Symbol VLT17 After Reset 0 Bit b0 b1 b0 VLT10 0 R/W R/W R/W Symbol Bit Name VLT10 P4 input level select bit VLT11 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b3 b2 b2 b3 VLT12 VLT13 P5_0 and P5_3 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b5 b4 R/W R/W b4 b5 VLT14 VLT15 P6 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b7 b6 R/W R/W b6 b7 VLT16 VLT17 P7 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W R/W The VLT1 register selects the voltage level of the input threshold values for ports P4 to P7. Bits VLT10 to VLT17 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). REJ09B0441-0010 Rev.0.10 Page 102 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.4.23 Input Threshold Control Register 2 (VLT2) b6 VLT16 0 b5 VLT15 0 b4 VLT14 0 b3 VLT13 0 b2 VLT12 0 b1 VLT11 0 Function b1 b0 Address 01F7h Bit b7 Symbol VLT17 After Reset 0 Bit b0 b1 b0 VLT10 0 R/W R/W R/W Symbol Bit Name VLT20 P10 input level select bit VLT21 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b3 b2 b2 b3 VLT22 VLT23 P11 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b5 b4 R/W R/W b4 b5 VLT24 VLT25 P12_0 to P12_3 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. b7 b6 R/W R/W b6 b7 VLT26 VLT27 P13 input level select bit 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W R/W The VLT2 register selects the voltage level of the input threshold values for ports P10 to P13. Bits VLT20 to VLT27 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). REJ09B0441-0010 Rev.0.10 Page 103 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.5 Port Settings Tables 7.5 to 7.23 list the port settings. Table 7.5 Pin Port P0 Register Bit PD0 PD0_i 0 LSE0 LSEi 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 2 X X X 1 X X X 1 X X X 1 X X X 1 X X X 0 X X X 0 X X X 0 X X X 0 ADINSEL CH ADGSEL 1 0 1 0 X X X 0 X X X 0 X X X 1 X X X 1 X X X 0 X X X 0 X X X 1 X X X 1 X X X 0 X X X 1 X X X 0 X X X 1 X X X 0 X X X 1 X X X 0 X X X 1 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 1 X X X 1 X X X 1 X X X 1 — Function Input port (1) Output port LCD drive control output (SEG0) A/D converter input (AN4) (1) Input port (1) Output port LCD drive control output (SEG1) A/D converter input (AN5) (1) Input port (1) Output port LCD drive control output (SEG2) A/D converter input (AN6) (1) Input port (1) Output port LCD drive control output (SEG3) A/D converter input (AN7) (1) Input port (1) Output port LCD drive control output (SEG4) A/D converter input (AN8) (1) Input port (1) Output port LCD drive control output (SEG5) A/D converter input (AN9) (1) Input port (1) Output port LCD drive control output (SEG6) A/D converter input (AN10) (1) Input port (1) Output port LCD drive control output (SEG7) A/D converter input (AN11) (1) Port P0_0 SEG0 AN4 1 i=0 X 0 0 Port P0_1 SEG1 AN5 1 i=1 X 0 0 Port P0_2 SEG2 AN6 1 i=2 X 0 0 Port P0_3 SEG3 AN7 1 i=3 X 0 0 Port P0_4 SEG4 AN8 1 i=4 X 0 0 Port P0_5 SEG5 AN9 1 i=5 X 0 0 Port P0_6 SEG6 AN10 1 i=6 X 0 0 Port P0_7 SEG7 AN11 1 i=7 X 0 X: 0 or 1 Note: 1. Pulled up by setting the corresponding bit in the P0PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 104 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.6 Pin Port P1 Register Bit PD1 PD1_i 0 LSE1 LSEi+8 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 2 X X X 1 X X X 1 X X X 1 X X X 1 ADINSEL CH ADGSEL 1 0 1 0 X X X 0 X X X 0 X X X 1 X X X 1 X X X 0 X X X 1 X X X 0 X X X 1 X X X 0 X X X 0 X X X 0 X X X 0 X X X 1 X X X 1 X X X 1 X X X 1 — Function Input port (1) Output port LCD drive control output (SEG8) A/D converter input (AN12) (1) Input port (1) Output port LCD drive control output (SEG9) A/D converter input (AN13) (1) Input port (1) Output port LCD drive control output (SEG10) A/D converter input (AN14) (1) Input port (1) Output port LCD drive control output (SEG11) A/D converter input (AN15) (1) Input port (1) Output port LCD drive control output (SEG12) Input port (1) Output port LCD drive control output (SEG13) Input port (1) Output port LCD drive control output (SEG14) Input port (1) Output port LCD drive control output (SEG15) Port P1_0 SEG8 AN12 1 i=0 X 0 0 Port P1_1 SEG9 AN13 1 i=1 X 0 0 Port P1_2 SEG10 AN14 1 i=2 X 0 0 Port P1_3 SEG11 AN15 1 i=3 X 0 0 Port P1_4 SEG12 i=4 1 X 0 Port P1_5 SEG13 i=5 1 X 0 Port P1_6 SEG14 i=6 1 X 0 Port P1_7 SEG15 i=7 1 X X: 0 or 1 Note: 1. Pulled up by setting the corresponding bit in the P1PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 105 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.7 Pin Port P2 Register Bit PD2 PD2_i 0 1 i=0 X 0 0 LSE2 KISR LSEi+16 KIiSEL0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 KIEN KIiEN X X X 1 X X X 1 X X X 1 X X X 1 — — — — — — — — — — — — — — — — KIEN1 KIiEN — — — — — — — — — — — — — — — — X X X 1 X X X 1 X X X 1 X X X 1 — Function Input port (1) Output port LCD drive control output (SEG16) KI0 input (1) Input port (1) Output port LCD drive control output (SEG17) KI1 input (1) Input port (1) Output port LCD drive control output (SEG18) KI2 input (1) Input port (1) Output port LCD drive control output (SEG19) KI3 input (1) Input port (1) Output port LCD drive control output (SEG20) KI4 input (1) Input port (1) Output port LCD drive control output (SEG21) KI5 input (1) Input port (1) Output port LCD drive control output (SEG22) KI6 input (1) Input port (1) Output port LCD drive control output (SEG23) KI7 input (1) Port P2_0 SEG16 KI0 Port P2_1 SEG17 KI1 1 i=1 X 0 0 Port P2_2 SEG18 KI2 1 i=2 X 0 0 Port P2_3 SEG19 KI3 1 i=3 X 0 0 Port P2_4 SEG20 KI4 1 i=4 X 0 0 Port P2_5 SEG21 KI5 1 i=5 X 0 0 Port P2_6 SEG22 KI6 1 i=6 X 0 0 Port P2_7 SEG23 KI7 1 i=7 X 0 X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P2PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 106 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.8 Pin Port P3 Register PD3 LSE3 INTSR INTEN INTEN1 ADMOD TRBRCSR TRCMR TRCCR2 Bit ADCAP TRCTRG TRCTRG PWM2 TCEG1 TCEG0 PD3_i LSEi+24 INTiSEL0 INTiEN INTiEN ADCAP1 0 SEL1 SEL0 Function Input port (1) Output port LCD drive control output (SEG24) INT0 input (1) Input port (1) Output port LCD drive control output (SEG25) INT1 input (1) Input port (1) Output port LCD drive control output (SEG26) INT2 input (1) Input port (1) Output port LCD drive control output (SEG27) INT3 input (1) Input port (1) Output port LCD drive control output (SEG28) INT4 input (1) Input port (1) Output port LCD drive control output (SEG29) INT5 input (1) Input port (1) Output port LCD drive control output (SEG30) INT6 input (1) Input port (1) Output port LCD drive control output (SEG31) INT7 input (1) ADTRG input (1) PWM2 mode TRCTRG input (1) 0 Port P3_0 SEG24 INT0 0 0 Port P3_1 SEG25 INT1 0 0 Port P3_2 SEG26 INT2 0 0 Port P3_3 SEG27 INT3 0 0 Port P3_4 SEG28 INT4 0 0 Port P3_5 SEG29 INT5 0 0 Port P3_6 SEG30 INT6 0 0 1 Port P3_7 SEG31 INT7 ADTRG TRCTRG i=7 X 0 0 0 1 i=6 X 1 i=5 X 1 i=4 X 1 i=3 X 1 i=2 X 1 i=1 X 1 i=0 X 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 0 X X X X 1 X X X 1 X X X 1 X X X 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — X X X 1 X X X 1 X X X 1 X X 1 1 1 X — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — X X X X X 0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — X X X X 1 X — X X X X 1 X — X X X X X 0 — X X X X X 1 — X X X X X 0 1 — X X X X X 1 X X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P3PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 107 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.9 Pin Ports P4_0 to 4_2 Register PD4 LSE4 U1SR U1MR Bit PD4_i LSEi+32 CLK1SEL0 RXD1SEL0 TXD1SEL0 SMD2 SMD1 SMD0 CKDIR 0 0 0 0 1 — — — — — — 0 0 0 X X X 0 1 1 X X X X X X X X 0 X X X 0 0 1 X X X X X X X X 0 X X X 1 X 0 X X X X X X X X 1 X X X — Function Input port (1) Output port LCD drive control output (SEG32) TXD1 output (2) X X X X X X X X 1 0 Input port (1) Output port LCD drive control output (SEG33) RXD1 input (1) Input port (1) Output port LCD drive control output (SEG34) CLK1 (external clock) input (1) CLK1 (internal clock) output (2) Port P4_0 SEG32 TXD1 i=0 X 0 0 Port P4_1 SEG33 RXD1 0 0 0 1 0 0 0 1 0 0 — — — — — 0 0 0 1 1 — X X X 1 — — — — — 1 — — — — — — — — — 0 i=1 X 0 0 0 Port P4_2 SEG34 CLK1 X i=2 0 X X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P4PUR register to 1. 2. N-channel open-drain output by setting the MCH bit in the U1C0 register to 1. REJ09B0441-0010 Rev.0.10 Page 108 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.10 Pin Bit Ports P4_3 and 4_4 PD4 LSE4 Register TRBRCSR TRCTRG SEL0 TRCCR1 TRCCLK TCK2 TCK1 SEL0 TCK0 TRCMR TRCCR2 TRCTRG PD4_i LSE35 SEL1 PWM2 TCEG1 TCEG0 — Function Input port (1) Output port LCD drive control output (SEG35) TRCCLK input (1) PWM2 mode TRCTRG input (1) 0 Port P4_3 SEG35 TRCCLK TRCTRG 0 0 1 X 0 LSE4 X X X X 1 X X X X 0 X X X 1 X TRCPSR0 TRCIOA SEL0 X X X 1 X TRCOER EA X X X 0 X TRCMR PWM2 X X X 1 X X X X X 0 TRCIOR0 X X X X 0 1 X X X X 1 X TRCCR2 TCEG 0 i=3 1 X 0 0 Register PD4 TRBRCSR TRCTRG SEL0 Pin Bit TRCTRG PD4_i LSE36 SEL1 IOA2 IOA1 IOA0 TCEG1 Function Input port (1) Output port LCD drive control output (SEG36) Timer waveform (output compare function) Timer mode (input capture function) (1) PWM2 mode TRCTRG input (1) 0 1 X i=4 X 0 0 0 0 1 0 0 0 X X X X X 1 X X X X X 1 0 0 0 1 1 X X X X 0 X X X X X 1 1 0 X X X 0 0 1 X X X X 0 1 X X X X X 1 X X X X X X X X X 0 1 X X X X X X 1 X Port P4_4 SEG36 TRCIOA TRCTRG X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P4PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 109 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.11 Pin Bit Ports P4_5 to 4_7 TRCPSR0 TRCIOBSEL 1 0 Other than 01b Other than 01b Other than 01b Register PD4 LSE4 TRCOER — EB X X X 0 0 0 X TRCOER EB X X X 0 0 0 X X X X EC X X X X X X X 0 0 X TRCMR PWM2 X X X 0 1 1 1 TRCMR PWM2 PWMB PWMC TRCIOR0 IOB 2 X X X X X 0 0 1 1 X X X X X 0 1 X TRCIOR0 IOB 2 X X X X X 0 0 1 X X X X 1 X X X X X 0 1 X X X X X TRCIOR0 IOB 2 X X X X X 0 0 1 X X X X 1 X X X X X 0 1 X X X X X 0 X X X X X 1 X X X X X X 2 X X X X X X X X X 0 0 1 0 X X X X X 1 X X X X X X 2 X X X X X X X X X 0 0 1 0 X X X X X 1 X X TRCIOR1 IOC 1 X X X X X X X X X 0 1 X TRCIOR1 IOD 1 X X X X X X X X X 0 1 X 0 X X X X X X X X X 1 X X Input port (1) Output port LCD drive control output (SEG39) PWM2 mode waveform output PWM mode waveform output Timer waveform output (output compare function) PD4_i LSE37 0 1 X 0 0 1 0 0 0 0 PWMB X X X X 1 0 0 — Function Input port (1) Output port LCD drive control output (SEG37) PWM2 mode waveform output PWM mode waveform output Timer waveform output (output compare function) Port P4_5 SEG37 TRCIOB X i=5 X X 0 0 0 0 0 1 1 1 1 Timer mode (input capture function) (1) Function 0 X X X X X X X X X 1 X X Input port (1) Output port LCD drive control output (SEG38) PWM2 mode waveform output PWM mode waveform output Timer waveform output (output compare function) Register PD4 LSE4 TRCPSR0 TRCPSR1 Pin Bit TRCIOBSEL TRCIOC PD4_i LSE38 SEL0 1 0 0 1 X X X 0 0 1 0 0 0 0 0 0 0 Other than 10b Other than 10b Other than 10b 0 0 0 X X X 0 1 1 1 X X X 0 1 1 1 1 1 1 X X X X 1 0 0 X X X TRCMR X X X X X X X 1 0 0 1 1 1 1 0 0 0 0 Port P4_6 SEG38 TRCIOB TRCIOC i=6 X 0 X X 0 Timer mode (input capture function) (1) PWM mode waveform output Timer waveform (output compare function) Other than 10b Other than 10b Other than 10b Timer mode (input capture function) (1) Function Register PD4 LSE4 TRCPSR0 TRCPSR1 TRCOER EB X X X 0 0 0 X X X X ED X X X X X X X 0 0 X Pin Bit TRCIOBSEL TRCIOD PD4_i LSE39 SEL0 1 0 0 1 X X X 0 0 1 0 0 0 0 0 0 0 Other than 11b Other than 11b Other than 11b PWM2 PWMB PWMD 0 0 0 X X X 0 1 1 1 X X X 0 1 1 1 1 1 1 X X X X 1 0 0 X X X X X X X X X X 1 0 0 1 1 1 1 1 1 1 1 Port P4_7 SEG39 TRCIOB TRCIOD i=7 X 0 X X 0 Timer mode (input capture function) (1) PWM mode waveform output Timer waveform output (output compare function) Other than 11b Other than 11b Other than 11b Timer mode (input capture function) (1) X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P4PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 110 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.12 Pin Port P5 Register Bit PD5 PD5_i 0 1 X 0 LSE5 LSEi+40 0 0 1 0 0 1 0 0 1 0 0 1 — Function Input port (1) Output port LCD drive control output (SEG40) Input port (1) Output port LCD drive control output (SEG41) Input port (1) Output port LCD drive control output (SEG42) Input port (1) Output port LCD drive control output (SEG43) Port P5_0 SEG40 i=0 Port P5_1 SEG41 i=1 1 X 0 Port P5_2 SEG42 i=2 1 X 0 Port P5_3 SEG43 i=3 1 X X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P5PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 111 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.13 Pin Ports P6_0 to P6_3 Register Bit TRDPSR0 TRDIOA0SEL PD6_i LSE44 1 0 LSE5 PD6 TRDOER1 TRDFCR TRDIORA0 IOA1 IOA0 EA0 X X X X X 0 0 TRDOER1 CMD1 CMD0 STCLK PWM3 IOA2 Function Input port (1) Output port LCD drive control output (SEG44) Timer mode (input capture function) (1) External clock input (TRDCLK) (1) PWM3 mode waveform output Timer mode waveform output (output compare function) Function Input port (1) Output port LCD drive control output (SEG45) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM3 mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Function Input port (1) Output port LCD drive control output (SEG46) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Function Input port (1) Output port LCD drive control output (SEG47) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) 0 1 X Port P6_0 SEG44 TRDIOA0 TRDCLK 0 0 1 0 0 0 0 LSE5 Other than 01b Other than 01b 0 0 0 0 1 1 1 1 X X X 0 X 0 0 X X X 0 X 0 0 TRDFCR X X X 0 1 0 0 X X X 1 1 0 1 TRDPMR PWMB0 X X X 1 0 X 0 0 X X X X 0 X X X X X 0 X i=0 0 0 X X Register Pin Bit TRDPSR0 TRDIOB0SEL PD6_i LSE45 1 0 0 1 X 0 0 0 1 0 0 0 0 0 0 LSE5 PD6 0 1 1 X TRDIORB0 IOB1 IOB0 EB0 X X X X 0 0 0 0 0 TRDOER1 CMD1 CMD0 PWM3 IOB2 Other than 01b Other than 01b 0 0 0 0 0 0 1 1 1 1 1 1 X X X 0 1 0 0 0 0 X X X 0 X 1 0 0 0 TRDFCR X X X 1 X X 0 1 1 X X X 0 X X X 1 0 TRDPMR X X X 1 X X X X 0 0 X X X X X X X X X X X X Port P6_1 SEG45 TRDIOB0 i=1 X X X X X Register Pin Bit TRDPSR0 TRDIOC0SEL PD6_i LSE46 1 0 0 1 X 0 0 1 0 0 0 0 0 LSE5 PD6 X X X X 0 1 1 X TRDIORC0 EC0 X X X X 0 0 0 0 TRDOER1 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0 Other than 01b Other than 01b 0 0 0 0 0 1 1 1 1 1 X X X 0 1 0 0 0 X X X 0 X 1 0 0 TRDFCR X X X 1 X X 1 1 X X X 0 X X 1 0 TRDPMR X X X 1 X X X 0 0 X X X X X X X X X X X X Port P6_2 SEG46 TRDIOC0 0 i=2 X X X X Register Pin Bit TRDPSR0 TRDIOD0SEL PD6_i LSE47 1 0 0 1 X 0 0 1 0 0 0 0 0 Other than 01b Other than 01b 0 0 0 0 0 1 1 1 1 1 PD6 X X 0 1 1 X TRDIORC0 ED0 X X X X 0 0 0 0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0 X X X 0 1 0 0 0 X X X 0 X 1 0 0 X X X 1 X X 1 1 X X X 0 X X 1 0 X X X 1 X X X 0 0 X X X X X X X 0 1 X X X X X X X 1 X Port P6_3 SEG47 TRDIOD0 0 i=3 X X X X X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P6PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 112 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.14 Pin Ports P6_4 to P6_7 Register Bit TRDPSR1 TRDIOA1SEL PD6_i LSE48 1 0 LSE6 PD6 TRDOER1 TRDFCR CMD1 CMD0 PWM3 TRDIORA1 — IOA2 IOA1 IOA0 EA1 X X X X 0 0 0 TRDOER1 Function Input port (1) Output port LCD drive control output (SEG48) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output Timer mode waveform output (output compare function) Function Input port (1) Output port LCD drive control output (SEG49) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Function Input port (1) Output port LCD drive control output (SEG50) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Function Input port (1) Output port LCD drive control output (SEG51) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) 0 1 X Port P6_4 SEG48 TRDIOA1 0 0 1 0 0 0 0 LSE6 Other than 01b Other than 01b 0 0 0 0 1 1 1 1 X X X 0 1 0 0 X X X 0 X 1 0 TRDFCR X X X 1 X X 1 TRDPMR PWMB1 X X X 1 X X 0 0 X X X X X X X X X X X X 0 i=4 X X X Register Pin Bit TRDPSR1 TRDIOB1SEL PD6_i LSE49 1 0 0 1 X 0 0 1 0 0 0 0 0 LSE6 PD6 0 1 1 X TRDIORB1 IOB1 IOB0 EB1 X X X X 0 0 0 0 TRDOER1 CMD1 CMD0 PWM3 IOB2 Other than 01b Other than 01b 0 0 0 0 0 1 1 1 1 1 X X X 0 1 0 0 0 X X X 0 X 1 0 0 TRDFCR X X X 1 X X 1 1 X X X 0 X X 1 0 TRDPMR X X X 1 X X X 0 0 X X X X X X X X X X X X Port P6_5 SEG49 TRDIOB1 0 i=5 X X X X Register Pin Bit TRDPSR1 TRDIOC1SEL PD6_i LSE50 1 0 0 0 X 0 0 1 0 0 0 0 0 LSE6 PD6 X X 0 1 1 X TRDIORC1 EC1 X X X X 0 0 0 0 TRDOER1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0 Other than 01b Other than 01b 0 0 0 0 0 1 1 1 1 1 X X X 0 1 0 0 0 X X X 0 X 1 0 0 TRDFCR X X X 1 X X 1 1 X X X 0 X X 1 0 TRDPMR X X X 1 X X X 0 0 X X X X X X X X X X X X Port P6_6 SEG50 TRDIOC1 0 i=6 X X X X Register Pin Bit TRDPSR1 TRDIOC1SEL PD6_i LSE51 1 0 0 0 X 0 0 1 0 0 0 0 0 Other than 01b Other than 01b 0 0 0 0 0 1 1 1 1 1 PD6 X X 0 1 1 X TRDIORD1 ED1 X X X X 0 0 0 0 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0 X X X 0 1 0 0 0 X X X 0 X 1 0 0 X X X 1 X X 1 1 X X X 0 X X 1 0 X X X 1 X X X 0 0 X X X X X X X 0 1 X X X X X X X 1 X Port P6_7 SEG51 TRDIOD1 0 i=7 X X X X X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P6PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 113 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.15 Pin Port P7 Register Bit PD7 PD7_i 0 i=0 1 X 0 i=1 1 X 0 i=2 1 X 0 i=3 1 X 0 i=4 1 X 0 i=5 1 X 0 i=6 1 X 0 i=7 1 X LSE6/ LSE7 LSEi+52 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 LCR0 LDTY 210 X X 0 1 X X 0 1 X X 0 1 X X 0 1 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 X X X 0 — Function Port P7_0 SEG52 COM7 Port P7_1 SEG53 COM6 Port P7_2 SEG54 COM5 Port P7_3 SEG55 COM4 Port P7_4 COM3 Port P7_5 COM2 Port P7_6 COM1 Port P7_7 COM0 Input port (1) Output port LCD drive control output (SEG52) LCD drive control output (COM7) Input port (1) Output port LCD drive control output (SEG53) LCD drive control output (COM6) Input port (1) Output port LCD drive control output (SEG54) LCD drive control output (COM5) Input port (1) Output port LCD drive control output (SEG55) LCD drive control output (COM4) Input port (1) Output port LCD drive control output (COM3) Input port (1) Output port LCD drive control output (COM2) Input port (1) Output port LCD drive control output (COM1) Input port (1) Output port LCD drive control output (COM0) X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P6PUR or P7PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 114 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.16 Pin Ports P10_0 to P10_3 Register Bit Port P10_0 (TRDIOA0 TRDCLK KI0) i=0 Register Pin Bit Port P10_1 (TRDIOB0 KI1) i=1 Register Pin Bit KIEN TRDPSR0 TRDOER1 TRDFCR TRDIORA0 Function TRDIOA0SEL PD10_i KIiSEL0 KIiEN EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA0 1 0 0 X X X X X X X X X X Input port (1) Other than 10b 1 X X X X X X X X X X Output port Other than KI0 input (1) 0 1 1 X X X X X X X X 10b Timer mode (input capture 0 X X 1 0 X 0 0 0 1 1 X X function) (1) External clock input 0 X X 1 0 X X X 1 1 0 0 0 (TRDCLK) (1) X X X 1 0 0 0 0 0 0 X X X PWM3 mode waveform output 0 0 1 Timer mode waveform output X X X 1 0 0 0 0 0 1 (output compare function) 0 1 X PD10 KISR KIEN TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORB0 Function TRDIOB0SEL PD10_i KIiSEL0 KIiEN EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0 1 0 0 X X X X X X X X X X Input port (1) Other than 10b 1 X X X X X X X X X X Output port Other than KI1 input (1) 0 1 1 X X X X X X X X 10b Timer mode (input capture 0 X X 1 0 X 0 0 1 0 1 X X function) (1) Complementary PWM mode X X X 1 0 0 1 X X X X X X waveform output Reset synchronous PWM mode X X X 1 0 0 0 1 X X X X X waveform output X X X 1 0 0 0 0 0 X X X X PWM3 mode waveform output X X X 1 0 0 0 0 1 1 X X X PWM mode waveform output 0 0 1 Timer mode waveform output X X X 1 0 0 0 0 1 0 0 1 X (output compare function) PD10 KISR KIEN TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORC0 Function TRDIOC0SEL PD10_i KIiSEL0 KIiEN EB0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0 1 0 0 X X X X X X X X X X Input port (1) Other than 10b 1 X X X X X X X X X X Output port PD10 KISR 0 Port P10_2 (TRDIOC0 KI2) 0 i=2 X X X X Register PD10 1 X X X X X KISR 1 X X X X X Other than 10b 1 1 1 1 1 0 0 0 0 0 X X 0 0 0 0 X 0 1 0 0 0 X 0 X 1 0 0 X 1 X X 1 1 X 0 X X 1 0 X 1 X X X X X X X X X X KI2 input (1) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Pin Bit KIEN TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIOD0SEL PD10_i KIiSEL0 KIiEN ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0 1 0 X X X 0 0 1 0 1 X TRDIORD0 Function Input port (1) Output port KI3 input (1) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) 0 1 0 Port P10_3 (TRDIOD0 KI3) 0 i=3 X X X X X X 1 X X X X X X X 1 X X X X X Other than 10b Other than 10b 1 1 1 1 1 0 0 0 0 0 X X X X 0 0 0 0 X X X 0 1 0 0 0 X X X 0 X 1 0 0 X X X 1 X X 1 1 X X X 0 X X 1 0 X X X 1 X X X 0 0 X X X X X X X 0 1 X X X X X X X 1 X X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P10PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 115 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.17 Pin Ports P10_4 to P10_7 Register Bit KIEN1 TRDPSR1 TRDOER1 TRDFCR TRDIOA1SEL PD10_i KIiSEL0 KIiEN EA1 CMD1 CMD0 PWM3 1 0 0 X X X X X X Other than 10b 1 X X X X X X Other than 0 1 1 X X X X 10b PD10 KISR TRDIORA1 — IOA2 IOA1 IOA0 Function Input port (1) Output port KI4 input (1) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output Timer mode waveform output (output compare function) X X X 1 X X 0 0 X X X X X X X X X X X X Port P10_4 (TRDIOA1 KI4) 0 i=4 X X X Register PD10 X X X X KISR X X X X 1 1 1 1 0 0 0 0 X 0 0 0 0 1 0 0 0 X 1 0 1 X X 1 Pin Bit Port P10_5 (TRDIOB1 KI5) i=5 Register Pin Bit KIEN TRDPSR1 TRDOER1 TRDFCR TRDPMR Function TRDIOB1SEL PD10_i KIiSEL0 KIiEN EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0 1 0 0 X X X X X X X X X X Input port (1) Other than 10b 1 X X X X X X X X X X Output port Other than KI5 input (1) 0 1 1 X X X X X X X X 10b Timer mode (input capture 0 X X 1 0 X 0 0 1 0 1 X X function) (1) Complementary PWM mode X X X 1 0 0 1 X X X X X X waveform output Reset synchronous PWM mode X X X 1 0 0 0 1 X X X X X waveform output X X X 1 0 0 0 0 1 1 X X X PWM mode waveform output 0 0 1 Timer mode waveform output X X X 1 0 0 0 0 1 0 0 1 X (output compare function) PD10 KISR KIEN TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORC1 Function TRDIOC1SEL PD10_i KIiSEL0 KIiEN EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0 1 0 0 X X X X X X X X X X Input port (1) Other than 10b 1 X X X X X X X X X X Output port 0 1 1 X TRDIORA1 0 Port P10_6 (TRDIOC1 KI6) 0 i=6 X X X X Register PD10 1 X X X X X KISR 1 X X X X X Other than 10b 1 1 1 1 1 0 0 0 0 0 X X 0 0 0 0 X 0 1 0 0 0 X 0 X 1 0 0 X 1 X X 1 1 X 0 X X 1 0 X 1 X X X X X X X X X X KI6 input (1) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Pin Bit KIEN TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIOD1SEL PD10_i KIiSEL0 KIiEN ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0 1 0 X X X 0 0 1 0 1 X TRDIORC1 Function Input port (1) Output port KI7 input (1) Timer mode (input capture function) (1) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) 0 1 0 Port P10_7 (TRDIOD1 KI7) 0 i=7 X X X X X X 1 X X X X X X X 1 X X X X X Other than 10b Other than 10b 1 1 1 1 1 0 0 0 0 0 X X X X 0 0 0 0 X X X 0 1 0 0 0 X X X 0 X 1 0 0 X X X 1 X X 1 1 X X X 0 X X 1 0 X X X 1 X X X 0 0 X X X X X X X 0 1 X X X X X X X 1 X X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P10PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 116 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.18 Ports P11_0 and P11_1 PD11 INTSR INTEN INTCMP ACMR SSUIICSR ICCR1 SSU Associated Register (7) Register U2SR1 U2MR SMD 2 1 0 CKDIR Pin Bit PD11_i INTi INTiEN SEL0 INT1 CP0 CM10E IICSEL ICE SSCK SSCK output input CLK2SEL0 control control Function 0 1 0 Port P11_0 SCL SSCK (CLK2 INT0) IVREF1 LVCOUT1 0 0 0 i=0 0 0 X X X X X X X 1 X X X X X X X 1 X X X X X X X X 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 X 0 X 0 1 X X X 0 X 0 X 0 X 0 X 0 0 X 0 X X 0 1 0 X 0 X 0 X 0 X 0 X 0 X 0 X X 1 0 0 X 0 X 0 X 0 X 0 X 0 0 0 0 0 1 1 0 X X X X X X 0 X X X X X X X 0 X X X X X X X 1 X X X X X X 1 0 X Input port (1) Output port (2) SCL input/output (2) SSCK input (1) SSCK output (2, 5) CLK2 input (1) CLK2 output (2, 6) INT0 input (1) Comparator B1 reference voltage input (IVREF1) Comparator A1 output (LVCOUT1) (2) 0 X X 1 0 0 X X X X X X X X 1 1 0 X X X X Register PD11 INTSR INTEN INTCMP ACMR SSUIICSR SSU Associated Register (7) U2SR0 U2MR SMD 2 1 0 U2SMR Pin Bit PD11_i INTi INTiEN SEL0 INT1 CP0 CM20E IICSEL SSI SSI RXD2 TXD2 output input SEL SEL control control 1 0 1 0 Function IICM 0 1 0 X Port P11_1 SSI (RXD2 SCL2 TXD2 SDA2 INT1) IVCMP1 LVCOUT2 X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 X X 0 0 X X 0 0 0 1 0 0 0 0 1 0 0 0 XX XX X X X X X X X 1 0 0 1 1 X X X X X X X 0 1 X 0 0 X X X X X X 0 1 0 0 0 1 X X Input port (1) Output port (2) SSI input (1) SSI output (2, 5) RXD2 input (1) SCL2 input/output (2, 6) TXD2 output (2, 6) X X Other X X X than X 10b 0 0 01 01 X 0 i=1 X X X X 0 X 0 0 0 XX10 1 1 XX10 0 XX X 0 0 0 X 1 0 X 1 1 X 0 1 0 0 0 X X X 0 0 0 0 0 0 SDA2 input/output (2, 6) INT1 input (1) Comparator B1 input (IVCMP1) Comparator A2 output (LVCOUT2) (2) X X Other X than 10b 0 X X X 1 X 0 0 XX X X X X X: 0 or 1; —: No change in outcome Notes: 1. 2. 3. 4. 5. 6. 7. Pulled up by setting the corresponding bit in the P11PUR register to 1. Output drive capacity high by setting the corresponding bit in the P10DRR register to 1. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit to 0 (standard mode). N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. Synchronous serial communication unit (refer to Table 27.4 Association between Communication Modes and I/O Pins). REJ09B0441-0010 Rev.0.10 Page 117 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.19 Register Ports P11_2 and P11_3 PD11 INTSR INTEN INTCMP — SSUIICSR ICCR1 SSU Associated Register (6) U2SR0 U2MR SMD 2 1 X X X X X X X X 0 X X X X X X X X U2SMR Pin Bit PD11_i INTi INTiEN SEL0 X X X X X X X X X X X X X X X X INT3 CP0 X X X X X X X X — — — — — — — — — IICSEL 1 0 1 0 1 0 0 1 ICE 0 X 0 X 1 X X 0 X 0 X 0 X 0 X X X SSMR2 SSI SSI RXD2 TXD2 output input SEL SEL control control 1 0 1 0 X 0 X 0 X 0 1 X 0 X 0 X 0 X 0 0 0 U2CO CRS X X X X 0 1 X X CRD X X X X 0 0 X X X 0 X 0 X 1 0 X 0 X 0 X 0 X 0 0 0 XX01 Function IICM 0 0 1 1 0 0 Port P11_2 SDA SSO (RXD2 SCL2 TXD2 SDA2 INT2) IVREF3 X X Other X than X X 01b X X X Other X than X X 01b X XX X Other X X than X 01b XX X Other 1 0 than X 01b Other 1 0 than 01b 0 0 0 0 0 0 0 0 Input port (1) Output port (2) SDA input/output (2) SSO input (1) SSO output (2, 3) RXD2 input (1) 0 0 i=2 0 0 1 X X X X X X 1 X X X X X X 1 — — — — — — — — — — — — — — — — 0 1 0 1 0 X X — — — — — — — — — — 0 0 1 1 1 0 0 1 1 X X U2MR SMD 0 1 X 0 0 X X 1 SCL2 input/output (2, 4) TXD2 output (2, 4) 0 X X 1 X 0 0 0 0 Register XX01 XX01 Other X X than 01b 0 X X 1 X X SDA2 input/outpu (2, 4) INT2 input (1) Comparator B3 reference voltage input (IVREF3) Function Input port (1) Output port (2) SCS input (1) SCS output (2, 5) CTS2 input (1) RTS2 output (2) INT3 input (1) Comparator B3 input (IVCMP3) PD11 INTSR INTEN INTCMP U2SR1 CTSSEL0 0 0 X X 1 1 0 0 2 X X X X Pin Bit INTi PD11_i INTiEN SEL0 0 1 X X X X X X 1 0 X X X X X X 1 1 INT3 CP0 X X X X X X 0 1 CSS 1 0 0 0 1 0 0 0 0 0 0 0 1 X 0 0 0 0 — 0 X X X X 1 X X X X Port P11_3 SCS (CTS2 RTS2 INT3) IVCMP3 X X i=3 0 0 0 0 Other than 000b X X X X X X X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P11PUR register to 1. 2. Output drive capacity high by setting the corresponding bit in the P11DRR register to 1. 3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output). 4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. 5. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1. 6. Synchronous serial communication unit (refer to Table 27.4 Association between Communication Modes and I/O Pins). REJ09B0441-0010 Rev.0.10 Page 118 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.20 Pin Ports P11_4 to P11_7 Register Bit INTSR INTEN1 TRASR TRAIOC INTi TRAIOSEL INTiEN PD11_i TOPCR 10 SEL0 0 1 X X X 1 1 X X X X X 1 1 X X 0 0 1 0 1 1 0 — — — — — — — — — — — — 0 0 1 0 0 1 0 X X 0 X 0 0 X PD11 TRAMR TMOD0 2 X X 1 X X 0 X X U0SR RXD0SEL Function Input port (1) Output port (2) TRAIO input (1) INT4 input (1) TRAIO/INT4 input (1) TRAIO pulse output (2) RXD0 input (1) Function Input port (1) Output port (2) TRAO input (1) INT5 input (1) 1 X X X X X X 1 0 X X X X X X 0 Port P11_4 TRAIO (INT4 RXD0) 0 i=4 0 0 X 0 Register PD11 Other than 000b, 001b X X X Other than 000b, 001b 0 X 0 X 1 X Pin Bit INTSR INTEN1 INTi INTiEN PD11_i SEL0 0 X X X 1 X X X 1 1 X 0 TRAIOC — — — TOENA — — — 0 0 1 0 TRBIOC TOCNT Port P11_5 TRAO (INT5) i=5 Register PD11 Pin Bit INTSR INTEN1 INTi INTiEN PD11_i SEL0 0 1 X X X X X X X X X TRBMR TMOD 1 0 0 X 0 0 0 0 X 1 Function Input port (1) Output port (2) Programmable waveform generation mode (2) Programmable one-shot generation mode (2) Programmable wait oneshot generation mode (2) INT6 input (1) Function Input port (1) Output port (2) TREO output (2) INT7 input (1) ADTRG input (1) X X 1 0 Port P11_6 TRBO (INT6) X i=6 X X 0 Register PD11 X X 1 X X 1 — — — — — — — — — — — 0 0 X TRECR1 1 1 0 0 1 0 Pin Bit INTSR INTEN1 INTi INTiEN PD11_i SEL0 0 X X X 1 1 X X X 1 1 1 TOENA 0 0 1 0 0 ADMOD ADCAP 1 0 X X X X 1 X X X X 1 Port P11_7 TREO (INT7 ADTRG) i=7 X 0 0 X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P11PUR register to 1. 2. Output drive capacity high by setting the corresponding bit in the P11DRR register to 1. REJ09B0441-0010 Rev.0.10 Page 119 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.21 Pin Ports P12_0 to P12_3 Register PD12 CM0 CM1 Bit PD12_i CM05 CM07 CM10 CM11 CM13 Circuit Specifications Oscillation Feedback buffer resistor OFF OFF ON ON ON OFF OFF ON ON ON Function 0 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 Input port (1) Output port XIN clock input (1) XIN clock input stop (STOP mode) (1) XIN-XOUT oscillation (on-chip feedback resistor enabled) XIN-XOUT oscillation (on-chip feedback resistor disabled ) XIN-XOUT oscillation stop (on-chip feedback resistor enabled) XIN-XOUT oscillation stop (on-chip feedback resistor disabled ) oscillation stop (STOP mode) Port P12_0 XIN i=4 0 0 0 0 1 1 ON OFF 0 1 0 0 0 1 OFF ON 0 1 0 0 1 1 OFF OFF 0 Register 0 CM0 0 1 X CM1 1 OFF OFF PD12 Pin Bit PD12_i CM05 CM07 CM10 CM11 CM13 Circuit Specifications Oscillation Feedback buffer resistor OFF OFF ON OFF OFF ON Function 0 1 0 1 1 0 X X 0 0 0 0 1 1 0 0 0 1 0 Port P12_1 XOUT 0 0 0 1 1 ON OFF i=1 0 1 0 0 0 1 OFF ON 0 1 0 0 1 1 OFF OFF 0 Pin Port P12_2 CL1 Port P12_3 CL2 Register 0 LSE7 0 1 X 1 — OFF OFF Input port (1) Output port XIN-XOUT oscillation (on-chip feedback resistor enabled) XIN-XOUT oscillation (on-chip feedback resistor disabled ) XIN-XOUT oscillation stop (on-chip feedback resistor enabled) XIN-XOUT oscillation stop (on-chip feedback resistor disabled ) oscillation stop (STOP mode) Function Input port (1) Output port CL1 Input port (1) Output port CL2 PD12 0 Bit i=2 PD12_i LSE60 0 0 1 0 1 X 0 1 0 X 1 X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P12PUR register to 1. i=3 REJ09B0441-0010 Rev.0.10 Page 120 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.22 Pin Ports P13_0 to P13_3 Register Bit ADINSEL DACON CH ADGSEL PD13_i DA0E 2101 0 0 X X X 0 X X X X 0 X X X X 0 X X X X 0 X X X X 0 X 0 0 0 0 1 U0SR TXD0 SEL0 PD13 — Function Input port (1) Output port WKUP1 input (1) A/D converter input (AN0) (1) D/A converter output (DA0) U0MR SMD — 0 X X X X 1 X 0 X Input port (1) Output port A/D converter input (AN1) (1) D/A converter output (DA1) TXD0 output (2) Comparator A1 reference input (LVREF) Comparator A2 reference input (LVREF) Function Port P13_0 AN0 DA0 WKUP1 1 0 i=0 0 0 Register Pin Bit ADINSEL DACON VCA2 CH ADGSEL PD13_i DA1E VCA21 VCA23 2101 0 0 1 0 X X 0 X X X 0 X X X 1 X X X 0 X X X 0 X 0 0 0 1 X X X X X X X X PD13 2 X X X X 0 1 1 X 1 X X X X 0 0 1 X 0 0 0 0 Port P13_1 AN1 DA1 TXD0 LVREF 0 i=1 0 X X X X X 0 X X 1 0 X X X X X 0 1 X 0 0 Register X X X X X 0 — — — — — — — — — — — — — — — X 1 0 U0SR RXD0 SEL X X X PD13 PD13_i ADINSEL CH 2 1 X X 1 X X 0 X X 0 X X ADGSEL VCA2 VCA22 X X X X 1 VCA2 VCA24 Pin Bit — Function 1 X X 0 X X 0 X X 0 X X 1 X X X 0 X 0 X X X 1 X U0MR SMD CKDIR 210 X X X X 0 X X X X X 0 X X X X X 1 X X X X 1 0 X Input port (1) Output port A/D converter input (AN2) (1) RXD0 input (1) Comparator A1 input (LVCMP1) — Function Input port (1) Output port A/D converter input (AN3) (1) CLK0 (external clock input) (1) CLK0 (internal clock) output Comparator A2 input (LVCMP2) 0 Port P13_2 AN2 RXD0 LVCMP1 X X 0 X X 1 i=2 0 0 0 Register Pin Bit ADINSEL CH ADGSEL PD13_i 2101 0 0 1 X X 0 X X X X X 1 X X X X X 1 X X X X X 0 X X X X X 0 X X X PD13 U0SR CLK0 SEL0 0 0 0 1 1 0 X X X X X 1 Port P13_3 AN3 CLK0 LVCMP2 0 i=3 0 X 0 X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P13PUR register to 1. 2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1. REJ09B0441-0010 Rev.0.10 Page 121 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports Table 7.23 Pin Ports P13_4 to P13_7 Register Bit ADINSEL TRGPSR CH ADGSEL TRG PD13_i 2 1 0 1 0 IOASEL PD13 0 1 0 X X 0 X X X X X 0 X X X X X 0 X X X X X 1 X X X X X 0 X X X 0 0 0 1 1 1 TRGIOR IOA 2 1 0 X X X 1 X 0 X X X X X 0 X X X X X 1 X TRGMR PWM X X X 0 1 0 TRGMR Function Input port (1) Output port A/D converter input (AN16) (1) Timer mode (input capture function) (1) PWM mode waveform output Timer mode waveform output (output compare function) Port P13_4 AN16 TRGIOA i=4 0 X X 1 TRGCR TCK Register Pin Bit TRGPSR ADINSEL CH ADGSEL TRG CLKA PD13_i 2 1 0 1 0 SEL PD13 2 X X X 1 X X X 0 X X X MDF X X X Function 0 1 0 Port P13_5 AN17 TRGCLKA X X 0 X X 0 X X 1 X X 1 X X 0 0 0 0 i=5 X X X X X X 1 1 0 1 0 X X X X X X 1 X X X 1 Input port (1) Output port A/D converter input (AN17) (1) TRGCLKA input (other than phasecounting mode) (1) TRGCLKA input (phase-counting mode) (1) Function Input port (1) Output port A/D converter input (AN18) (1) Timer mode (input capture function) (1) Timer mode waveform output (output compare function) Pin Register Bit ADINSEL TRGPSR CH ADGSEL TRG PD13_i 2 1 0 1 0 IOBSEL PD13 0 1 X X 0 X X X 1 X X X 0 X X X 1 X X X 0 X 0 0 0 1 TRGIOR IOB 2 1 0 X X X 1 X X X X 0 X X X X 1 X TRGMR Port P13_6 AN18 TRGIOB 0 i=6 0 X X X X X X 1 0 1 TRGCR TCK Register Pin Bit ADINSEL TRGPSR CH ADGSEL TRG CLKB PD13_i 2 1 0 1 0 SEL PD13 0 1 0 X X 0 X X 1 X X 1 X X 1 X X 0 0 0 0 2 X X X 1 X X X 0 X X X MDF X X X Function Port P13_7 AN19 TRGCLKB i=7 0 X X X X X 1 1 1 1 0 0 X X X X X 1 X X X 1 Input port (1) Output port A/D converter input (AN19) (1) TRGCLKB input (other than phasecounting mode) (1) TRGCLKB input (phase-counting mode) (1) X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P13PUR register to 1. REJ09B0441-0010 Rev.0.10 Page 122 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports 7.6 Unassigned Pin Handling Table 7.24 lists Unassigned Pin Handling. Table 7.24 Unassigned Pin Handling Connection • After setting to input mode, connect each pin to VSS via a resistor (pull-down) or connect each pin to VCC via a resistor (pull-up). (2) • After setting to output mode, leave these pins open. (1, 2) Connect to VCC via a pull-up resistor. (2) Connect to VCC. Connect to VSS. (3) Connect to VCC via a pull-up resistor. (4) Pin Name Ports P0 to P7, Ports P10, P11, 12_2, P12_3 Ports P12_0, P12_1 VREF WKUP0 (3) RESET (4) Notes: 1. If these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. The content of the direction registers may change due to noise or program runaway caused by noise. In order to enhance program reliability, the program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible. 3. When power-off mode is not used. 4. When the power-on reset function is used. MCU Ports P0 to P7, Ports P10, P11 Ports P12_2, P12_3 (Input mode ) : : (Input mode) (Output mode) : : Open Ports P12_0, P12_1 WKUP0 (2) RESET (1) VREF Notes: 1. When the power-on reset function is used. 2. When power-off mode is not used. Figure 7.6 Unassigned Pin Handling REJ09B0441-0010 Rev.0.10 Page 123 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 8. Bus 8. Bus The bus cycles differ when accessing ROM/RAM and when accessing SFR. Table 8.1 lists the Bus Cycles by Access Area. ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. Table 8.2 shows Access Units and Bus Operations. Table 8.1 Bus Cycles by Access Area Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock Access Area SFR/Data flash Program ROM/RAM Note: 1. Data flash is provided only in the following four: the R8C/L35A Group, L36A Group, L38A Group, and L3AA Group. Table 8.2 Area Even address Byte access CPU clock Address Data Odd address Byte access CPU clock Address Data Even address Word access CPU clock Address Data Odd address Word access CPU clock Address Data Odd Data Odd + 1 Data Even Data Even + 1 Data Odd Data Even Data Access Units and Bus Operations SFR, Data flash ROM (program ROM), RAM CPU clock Address Data CPU clock Address Data CPU clock Address Data CPU clock Address Data Odd Data Odd + 1 Data Even Data Even + 1 Data Odd Data Even Data REJ09B0441-0010 Rev.0.10 Page 124 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 8. Bus However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD Timer RD: Registers TRDi (i = 0 or 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi Timer RG: Registers TRG, TRGGRA, and TRGGRB SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2, and U2SMR A/D converter: Registers AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, ADMOD, ADINSEL, ADCON0, and ADCON1 D/A converter: Registers DA0 and DA1 Address match interrupt: Registers RMAD0, AIER0, RMAD1, and AIER1 Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, Data flash, Even address Byte Access” in Table 8.2 Access Units and Bus Operations, and 16-bit data is accessed at a time. REJ09B0441-0010 Rev.0.10 Page 125 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit: • XIN clock oscillation circuit • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator • Low-speed on-chip oscillator for the watchdog timer 9.1 Introduction Table 9.1 lists the Specification Overview of Clock Generation Circuit. Figure 9.1 shows the Clock Generation Circuit and Figure 9.2 shows the Peripheral Function Clock. Table 9.1 Item Applications Specification Overview of Clock Generation Circuit XIN Clock XCIN Clock Oscillation Circuit Oscillation Circuit • CPU clock source • Peripheral function clock source • CPU clock source • Peripheral function clock source On-Chip Oscillator High-Speed Low-Speed On-Chip Oscillator On-Chip Oscillator • CPU clock • CPU clock source source • Peripheral • Peripheral function clock function clock source source • CPU and • CPU and peripheral peripheral function clock function clock source when XIN source when XIN clock stops clock stops oscillating oscillating Approx. 40 MHz (3) Approx. 125 kHz − − Low-Speed On-Chip Oscillator for Watchdog Timer • Watchdog timer clock source Clock frequency 0 to 20 MHz Connectable oscillator • Ceramic resonator • Crystal oscillator 32.768 kHz • Crystal oscillator Approx. 125 kHz − Oscillator XIN, XOUT (1) connect pins Oscillation stop, Usable restart function Oscillator status Stop after reset Others Externally generated clock can be input (2) XCIN, XCOUT Usable Oscillate − (1) Usable Stop − (1) Usable Oscillate − − Usable Stop (4) Oscillate (5) − • Externally − generated clock can be input • On-chip feedback resistor Rf (connected/ not connected selectable) Notes: 1. These pins can be used as P12_0 and P12_1 when using the on-chip oscillator clock as the CPU clock while the XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used. 2. To input an external clock, set the CM05 bit in the CM0 register to 1 (XIN clock stops), the CM11 bit in the CM1 register to 1 (on-chip feedback resistor enabled), and the CM13 bit to 1 (XIN-XOUT pin). 3. The clock frequency is set to up to 20 MHz by a divider when using the high-speed on-chip oscillator as the CPU clock source. 4. This applies when the CSPROINI bit in the OFS register is set to 1 (count source protection mode disabled after reset). 5. This applies when the CSPROINI bit in the OFS register is set to 0 (count source protection mode enabled after reset). REJ09B0441-0010 Rev.0.10 Page 126 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit CM02 CM01 (Receiver) CM03 CM04 = 1 CSPRO Low-speed on-chip oscillator for watchdog timer fOCO-WDT fC-LCD fC fC2 1/4 fC CM04 = 0 (Oscillator) CM02 CM12 FRA00 FRA1 register, FRA3 register High-speed on-chip oscillator Frequency adjustable 1/2 1/2 1/8 fC4 fC32 FRA2 register fOCO40M XCIN XCOUT Divider FRA01 = 1 FRA01 = 0 Low-speed on-chip oscillator On-chip oscillator clock FRA03 = 1 FRA03 = 0 Divider (1/128) Power-on reset circuit fOCO-S Voltage detection circuit fOCO-S b c Oscillation stop detection XIN clock System clock OCD2 = 1 a Divider h CPU clock d e g f1 f2 f4 f8 f32 fOCO-F fOCO fOCO128 Peripheral function clock CM14 CM10 = 1 (stop mode) RESET Power-on reset Software reset Interrupt request WAIT instruction CM30 CM07 CM05 SQ R SQ R CM13 = 0 CM13 = 1 CM13 fC CM07 = 0 CM07 = 1 OCD2 = 0 CM05 CM11 CM02 CM01 XIN XOUT b a 1/2 c 1/2 d 1/2 e 1/2 1/2 g CM06 = 0 CM17 to CM16 = 11b CM06 = 1 CM06 = 0 CM17 to CM16 = 10b CM01, CM02, CM03, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM11, CM12, CM13, CM14, CM16, CM17: Bits in CM1 register CM30: Bit in CM3 register OCD0, OCD1, OCD2: Bits in OCD register FRA00, FRA01, FRA03: Bits in FRA0 register CSPRO: Bit in CSPR register CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b h Detail of divider Oscillation Stop Detection Circuit Forcible discharge when OCD0 = 0 Pulse generation circuit for clock edge detection and charge/ discharge control XIN clock Charge/ discharge circuit OCD1 Oscillation stop detection Interrupt generation circuit Watchdog timer interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt OCD2 bit switch signal CM14 bit switch signal Oscillation stop detection, watchdog timer, voltage monitor 1 interrupt, voltage monitor 2 interrupt Figure 9.1 Clock Generation Circuit REJ09B0441-0010 Rev.0.10 Page 127 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit fC-LCD fC fC2 fC4 fC32 fOCO40M fOCO128 fOCO fOCO-F fOCO-WDT i = 0 to 7 INTi Watchdog timer Timer RA Timer RB Timer RC Timer RD Timer RE Timer RG A/D converter UART2 UART1 UART0 LCD SSU/ I2 C bus f1 f2 f4 f8 f32 CPU clock CPU Figure 9.2 Peripheral Function Clock REJ09B0441-0010 Rev.0.10 Page 128 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2 9.2.1 Registers System Clock Control Register 0 (CM0) b6 CM06 0 b5 CM05 1 b4 CM04 0 b3 CM03 0 b2 CM02 0 b1 CM01 0 b0 — 0 R/W R/W R/W R/W Address 0006h Bit b7 Symbol CM07 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Reserved bit Set to 0. CM01 Peripheral function clock stop bit in b1 b0 0 0: Peripheral function clock does not stop in CM02 wait mode wait mode 0 1: Clocks f1 to f32 stop in wait mode 1 0: Clocks f1 to f32 and fC stop in wait mode 1 1: Clocks f1 to f32, fC, and fC-LCD stop in wait mode CM03 XCIN clock stop bit 0: XCIN clock oscillates 1: XCIN clock stops CM04 XCIN external clock input enable bit 0: External clock input disabled 1: External clock input enabled CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates 1: XIN clock stops (2) CM06 System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled 1: Divide-by-8 mode 0: XIN clock CM07 XIN and XCIN clock select bit (5) 1: XCIN clock R/W R/W R/W R/W R/W Notes: 1. The CM05 bit stops the XIN clock when high-speed on-chip oscillator mode or low-speed on-chip oscillator mode is selected. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock, set the bits in the following order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (on-chip oscillator clock selected). 2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged. 3. Only when the CM05 bit to 1 (XIN clock stops) and the CM07 bit is set to 1 (XCIN clock), P12_0 and P12_1 can be used as I/O ports. 4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). 5. Change the CM07 bit from 0 to 1 (XCIN clock) after the XCIN clock oscillation has become stable. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register. REJ09B0441-0010 Rev.0.10 Page 129 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 1 (CM1) b6 CM16 0 b5 — 1 b4 CM14 0 b3 CM13 0 b2 CM12 0 b1 CM11 0 b0 CM10 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0007h Bit b7 Symbol CM17 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name CM10 All clock stop control bit (2, 5) CM11 CM12 CM13 CM14 — CM16 CM17 Function 0: Clock oscillates 1: All clocks stop (stop mode) XIN-XOUT on-chip feedback resistor 0: On-chip feedback resistor enabled select bit 1: On-chip feedback resistor disabled XCIN-XCOUT on-chip feedback 0: On-chip feedback resistor enabled resistor select bit 1: On-chip feedback resistor disabled 0: I/O ports P12_0 and P12_1 Port/XIN-XOUT switch bit (5, 6, 7) 1: XIN-XOUT pin Low-speed on-chip oscillator 0: Low-speed on-chip oscillator on 1: Low-speed on-chip oscillator off oscillation stop bit (3, 4) Reserved bit Set to 1. System clock division select bit 1 (1) b7 b6 0 0: No division mode 0 1: Divide-by-2 mode 1 0: Divide-by-4 mode 1 1: Divide-by-16 mode Notes: 1. When the CM06 bit is set to 0, bits CM16 and CM17 are enabled. 2. When the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). It remains unchanged even if 1 is written to it. 4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14 bit to 0 (low-speed on-chip oscillator on). 5. To use P12_0 and P12_1 as input ports, set the CM13 bit to 0 (I/O ports), the CM05 bit in the CM0 register to 1 (XIN clock stops), and the CM07 bit to 1 (XCIN clock). To use as external clock input, set the CM13 bit to 0 (I/O ports), the CM05 bit to 1 (XIN clock oscillates), the CM07 bit to 0 (XIN clock). When the PD12_0 bit in the PD12 register is further set to 0 (input mode), an external clock can be input. XOUT can be used as the input port P12_1 at this time. 6. When the CM10 bit is set to 1 (stop mode), the XOUT pin is held high while the CM13 bit is set to 1 (XIN-XOUT pin). 7. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register. REJ09B0441-0010 Rev.0.10 Page 130 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2.3 System Clock Control Register 3 (CM3) b6 CM36 0 b5 CM35 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 CM30 0 R/W R/W — Address 0009h Bit b7 Symbol CM37 After Reset 0 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name CM30 Wait control bit (1) — — — — CM35 Function 0: Other than wait mode 1: MCU enters wait mode Nothing is assigned. If necessary, set to 0. When read, the content is 0. CPU clock division ratio select bit when exiting wait mode 0: Following settings are enabled: CM06 bit in CM0 register Bits CM16 and CM17 in CM1 register 1: No division (2) b7 b6 R/W b6 b7 CM36 CM37 CPU clock select bit when exiting wait or stop mode 0 0: MCU exits with the CPU clock used immediately before entering wait or stop mode 0 1: Do not set. 1 0: High-speed on-chip oscillator clock selected (3) 1 1: XIN clock selected (4) R/W R/W Notes: 1. When the MCU exits wait mode by a peripheral function interrupt, the CM30 bit is set to 0 (other than wait mode). 2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1 register is set to 00b (no division mode). 3. When bits CM37 to CM36 are set to 10b (high-speed on-chip oscillator clock selected), the following will be set when the MCU exits wait mode or stop mode: • OCD2 bit in OCD register = 1 (on-chip oscillator selected) • FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on) • FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected) 4. When bits CM37 to CM36 are set to 11b (XIN clock selected), the following will be set when the MCU exits wait mode or stop mode. • OM05 bit in OM0 register = 1 (XIN clock oscillates) • OM13 bit in OM1 register = 1 (XIN-XOUT pin) • OCD2 bit in OCD register = 0 (XIN clock selected) Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register. CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). However, the XIN clock, XCIN clock, and on-chip oscillator clock do not stop, so peripheral functions using these clocks continue operating. The MCU exits wait mode by a reset or peripheral function interrupt. If the MCU enters wait mode while the I flag is set to 0 (maskable interrupt disabled), it resumes executing the instruction immediately after the instruction to set the CM30 bit to 1 when exiting wait mode. If the MCU enters wait mode with the WAIT instruction, interrupt handling is performed by the CPU when exiting wait mode. REJ09B0441-0010 Rev.0.10 Page 131 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2.4 Oscillation Stop Detection Register (OCD) b6 — 0 b5 — 0 b4 — 0 b3 OCD3 0 b2 OCD2 1 b1 OCD1 0 b0 OCD0 0 R/W R/W R/W R/W R R/W Address 000Ch Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1) 1: Oscillation stop detection function enabled OCD1 Oscillation stop detection interrupt 0: Disabled (1) enable bit 1: Enabled OCD2 System clock select bit (3) 0: XIN clock selected (6) 1: On-chip oscillator clock selected (2) 0: XIN clock oscillates OCD3 Clock monitor bit (4, 5) 1: XIN clock stops — Reserved bits Set to 0. — — — Notes: 1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or lowspeed on-chip oscillator mode (XIN clock stops). 2. When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). 3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) when the XIN clock oscillation stop is detected while bits OCD1 to OCD0 are set to 11b. When the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged even if 0 (XIN clock selected) is written to it. 4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). 5. The OCD3 bit remains 0 (XIN clock oscillates) when bits OCD1 to OCD0 are set to 00b. 6. Refer to 9.7.1 How to Use Oscillation Stop Detection Function for the switching procedure when the XIN clock re-oscillates after detecting an oscillation stop. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register. 9.2.5 High-Speed On-Chip Oscillator Control Register 7 (FRA7) b5 — b4 — b3 — b2 — b1 — b0 — Address 0015h Bit b7 b6 Symbol — — After Reset When shipping Bit Function b7-b0 32 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA3 register and by transferring the correction value of the FRA6 register to the FRA1 register. R/W R REJ09B0441-0010 Rev.0.10 Page 132 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) b6 — 0 b5 — 0 b4 — 0 b3 FRA03 0 b2 — 0 b1 FRA01 0 b0 FRA00 0 R/W R/W R/W R/W R/W R/W Address 0023h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name FRA00 High-speed on-chip oscillator enable bit FRA01 — FRA03 — — — — Function 0: High-speed on-chip oscillator off 1: High-speed on-chip oscillator on High-speed on-chip oscillator select bit (1) 0: Low-speed on-chip oscillator selected (2) 1: High-speed on-chip oscillator selected Reserved bit Set to 0. fOCO128 clock select bit 0: fOCO-S divided by 128 selected 1: fOCO-F divided by 128 selected Reserved bits Set to 0. Notes: 1. Change the FRA01 bit under the following conditions. • FRA00 = 1 (high-speed on-chip oscillator on) • CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on) • Bits FRA22 to FRA20 in the FRA2 register: All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b Division ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more) Division ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) 2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (highspeed on-chip oscillator off) at the same time. Set the FRA01 bit to 0 before setting the FRA00 bit to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register. 9.2.7 High-Speed On-Chip Oscillator Control Register 1 (FRA1) b5 — b4 — b3 — b2 — b1 — b0 — Address 0024h Bit b7 b6 Symbol — — After Reset When shipping Bit Function b7-b0 The frequency of the high-speed on-chip oscillator can be changed by the following settings. 40 MHz: FRA1=FRA3=Value after a reset 36.864 MHz: Transfer the data of the FRA4 register to the FRA1 register, and transfer the data of the FRA5 register to the FRA3 register. 32 MHz: Transfer the data of the FRA6 register to the FRA1 register, and transfer the data of the FRA7 register to the FRA3 register. R/W R/W Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA1 register. REJ09B0441-0010 Rev.0.10 Page 133 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 FRA22 0 b1 FRA21 0 b0 FRA20 0 R/W R/W R/W R/W Address 0025h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 Symbol Bit Name FRA20 High-speed on-chip oscillator frequency FRA21 switch bit FRA22 Function Division ratio selection These bits select the division ratio for the highspeed on-chip oscillator clock. b2 b1 b0 b3 b4 b5 b6 b7 — — — — — Reserved bits 0 0 0: Divide-by-2 mode 0 0 1: Divide-by-3 mode 0 1 0: Divide-by-4 mode 0 1 1: Divide-by-5 mode 1 0 0: Divide-by-6 mode 1 0 1: Divide-by-7 mode 1 1 0: Divide-by-8 mode 1 1 1: Divide-by-9 mode Set to 0. R/W Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA2 register. REJ09B0441-0010 Rev.0.10 Page 134 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.2.9 High-Speed On-Chip Oscillator Control Register 4 (FRA4) b5 — b4 — b3 — b2 — b1 — b0 — Address 0029h Bit b7 b6 Symbol — — After Reset When shipping Bit Function b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA1 register and by transferring the correction value of the FRA5 register to the FRA3 register. R/W R 9.2.10 High-Speed On-Chip Oscillator Control Register 5 (FRA5) b5 — b4 — b3 — b2 — b1 — b0 — Address 002Ah Bit b7 b6 Symbol — — After Reset When shipping Bit Function b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA3 register and by transferring the correction value of the FRA4 register to the FRA1 register. R/W R 9.2.11 High-Speed On-Chip Oscillator Control Register 6 (FRA6) b5 — b4 — b3 — b2 — b1 — b0 — Address 002Bh Bit b7 b6 Symbol — — After Reset When shipping Bit Function b7-b0 32 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA1 register and by transferring the correction value of the FRA7 register to the FRA3 register. R/W R 9.2.12 High-Speed On-Chip Oscillator Control Register 3 (FRA3) b5 — b4 — b3 — b2 — b1 — b0 — Address 002Fh Bit b7 b6 Symbol — — After Reset When shipping Bit Function b7-b0 The frequency of the high-speed on-chip oscillator can be changed by the following settings. 40 MHz: FRA1=FRA3=Value after a reset 36.864 MHz: Transfer the data of the FRA4 register to the FRA1 register, and transfer the data of the FRA5 register to the FRA3 register. 32 MHz: Transfer the data of the FRA6 register to the FRA1 register, and transfer the data of the FRA7 register to the FRA3 register. R/W R/W Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA3 register. REJ09B0441-0010 Rev.0.10 Page 135 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit The clocks generated by the clock generation circuits are described below. 9.3 XIN Clock The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between pins XIN and XOUT. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XOUT pin. Figure 9.3 shows Examples of XIN Clock Connection Circuit. During and after reset, the XIN clock stops. After setting the CM13 bit in the CM1 register to 1 (XIN-XOUT pin), the XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates). After the XIN clock oscillation stabilizes, the XIN clock is used as the CPU clock source by setting the OCD2 bit in the OCD register to 0 (XIN clock selected). The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) by setting the OCD2 bit is to 1 (on-chip oscillator clock selected). In stop mode, all clocks including the XIN clock stop. Refer to 10. Power Control for details. • When CM05 bit in CM0 register is 0 (XIN clock oscillates) and CM13 bit in CM1 register is 1 (XIN-XOUT pin) • When CM05 bit in CM0 register is 1 (XIN clock stops), CM07 bit is 0 (XIN clock), CM11 bit in CM1 register is 1 (on-chip feedback resistor disabled), and CM13 bit is 0 (input ports P12_0 and P12_1) MCU (on-chip feedback resistor) XIN (1) MCU (on-chip feedback resistor) XIN XOUT Open XOUT Rf Rd (1) Externally generated clock CIN COUT VCC VSS External clock input circuit Ceramic resonator external circuit Note: 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity settings. Use the values recommended by the oscillator manufacturer. If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions. Figure 9.3 Examples of XIN Clock Connection Circuit REJ09B0441-0010 Rev.0.10 Page 136 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.4 On-Chip Oscillator Clock The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed onchip oscillator). This clock is selected by the FRA01 bit in the FRA0 register. 9.4.1 Low-Speed On-Chip Oscillator Clock The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock, and peripheral function clock (fOCO, fOCO-S, and fOCO128). After a reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 1 (no division) is selected as the CPU clock. If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed on-chip oscillator automatically starts operating and supplies the necessary clock for the MCU. The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating ambient temperature. Application products must be designed with sufficient margin to allow for frequency changes. 9.4.2 High-Speed On-Chip Oscillator Clock The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock, and peripheral function clock (fOCO, fOCO-F, fOCO40M, and fOCO128). To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO, and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows: • All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b • Division ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more) • Division ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) After a reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). Frequency correction data is stored in registers FRA4 to FRA7. To adjust the frequency of the high-speed on-chip oscillator clock to 36.864 MHz, first transfer the correction value of the FRA4 register to the FRA1 register and the correction value of the FRA5 register to the FRA3 register before using the values. This enables the setting errors of bit rates such as 9,600 bps and 38,400 bps to be 0% when the serial interface is used in UART mode (refer to Table 24.8 and Table 25.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected)). To adjust the frequency of the high-speed on-chip oscillator clock to 32 MHz, first transfer the correction value of the FRA6 register to the FRA1 register and the correction value of the FRA7 register to the FRA3 register before using the values. REJ09B0441-0010 Rev.0.10 Page 137 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.5 XCIN Clock The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XCIN clock oscillation circuit is configured by connecting a resonator between pins XCIN and XCOUT. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 9.4 shows Examples of XCIN Clock Connection Circuits. Bits CM04 to CM03 in the CM0 register are set to 00b (external clock input disabled, XCIN clock oscillates) by reset and the XCIN clock starts oscillating (with the on-chip feedback resistor enabled). After the XCIN clock oscillation stabilizes following reset, the XCIN clock is used as the CPU clock source by setting the CM07 bit in the CM07 register to 1 (XCIN clock). When the CM03 bit is set to 1 (XCIN clock stops), the XCIN clock stops. When bits CM04 to CM03 are set to 10b (external clock input enabled, XCIN clock oscillates), an externally generated clock can also be input to the XCIN pin. Leave the XCOUT pin open at this time. This MCU has an on-chip feedback resistor, which can be disabled/enabled by the CM12 bit in the CM1 register. When the XCIN clock is not used, set bits CM04 to CM03 to 01b (external clock input disabled, XCIN clock stops) and the CM12 bit to 1 (on-chip feedback resistor disabled). In stop mode, all clocks including the XCIN clock stop. Refer to 10. Power Control for details. • When CM03 bit in CM0 register is 0 (XCIN clock oscillates) and CM04 bit is 0 (external clock input disabled) • When CM03 bit in CM0 register is 1 (XCIN clock stops) and CM04 bit is 1 (external clock input enabled) MCU (on-chip feedback resistor) XCIN Rf ( 1) MCU (on-chip feedback resistor) XCIN XCOUT Open Rd (1) XCOUT Externally generated clock CIN COUT VCC VSS External crystal oscillator circuit External clock input circuit Note: 1. Insert a damping resistor and a feedback resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity settings. Use the value recommended by the oscillator manufacturer. If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions. Figure 9.4 Examples of XCIN Clock Connection Circuits REJ09B0441-0010 Rev.0.10 Page 138 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.6 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. (Refer to Figure 9.1 Clock Generation Circuit.) 9.6.1 System Clock The system clock is the clock source for the CPU and peripheral function clocks. The XIN clock, XCIN clock, or on-chip oscillator clock can be selected. 9.6.2 CPU Clock The CPU clock is an operating clock for the CPU and the watchdog timer. The system clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. The division ratio can be selected by the CM06 bit in the CM0 register and bits CM16 and CM17 in the CM1 register. Use the XCIN clock while the XCIN clock oscillation stabilizes. After a reset, the low-speed on-chip oscillator clock divided by 1 (no division) is used as the CPU clock. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings of CM06 in CM0 register and bits CM16 and CM17 in CM1 register enabled). 9.6.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) The peripheral function clock is an operating clock for the peripheral functions. The fi (i = 1, 2, 4, 8, and 32) clock is generated by the system clock divided by i. It is used for timers RA, RB, RC, RD, RE, RG, the serial interface, the A/D converter, and the LCD waveform control circuit. When the MCU enters wait mode after bits CM02 to CM01 in the CM0 register are set to 01, 10, or 11, the fi clock stops. 9.6.4 fOCO fOCO is an operating clock for the peripheral functions. This clock runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA. In wait mode, the fOCO clock does not stop. 9.6.5 fOCO40M fOCO40M is used as the count source for timers RC, RD, and RG. This clock is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. In wait mode, the fOCO40M clock does not stop. This clock can be used with supply voltage VCC = 3.0 to 5.5 V. 9.6.6 fOCO-F fOCO-F is used as the count source for timers RC and RD, and the A/D converter. This clock is generated by the high-speed on-chip oscillator, divided by i (i = 2, 3, 4, 5, 6, 7, 8, or 9; division ratio selected by the FRA2 register). It is supplied by setting the FRA00 bit to 1. In wait mode, the fOCO-F clock does not stop. REJ09B0441-0010 Rev.0.10 Page 139 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.6.7 fOCO-S fOCO-S is an operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (lowspeed on-chip oscillator on). In wait mode, the fOCO-S clock does not stop. 9.6.8 fOCO128 fOCO128 clock is generated by fOCO-S or fOCO-E divided by 128. fOCO-S divided by 128 is selected by setting the FRA03 bit to 0 and fOCO-F divided by 128 is selected by setting the FRA03 bit to 1. fOCO128 is configured as the capture signal used in the TRCGRA register for timer RC and timer RD0 for timer RD. 9.6.9 fC-LCD fC-LCD is used in the LCD waveform control circuit. Use this clock only while the XCIN clock oscillation stabilizes. 9.6.10 fC, fC2, fC4, and fC32 fC, fC2, fC4, and fC32 are used for timers RA, RD, RE and the serial interface. Use theses clocks while the XCIN clock oscillation stabilizes. 9.6.11 fOCO-WDT fOCO-WDT is an operating clock for the watchdog timer. This clock is generated by the low-speed on-chip oscillator for the watchdog timer and supplied by setting the CSPRO bit in the CSPR register to 1 (count source protection mode enabled). In count source protection mode for the watchdog timer, the fOCO-WDT clock does not stop. REJ09B0441-0010 Rev.0.10 Page 140 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.7 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 9.2 lists the Specifications of Oscillation Stop Detection Function. When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the MCU is placed in the following states if the XIN clock stops. • OCD2 bit in OCD register = 1 (on-chip oscillator clock selected) • OCD3 bit in OCD register = 1 (XIN clock stops) • CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on) • Oscillation stop detection interrupt request is generated Table 9.2 Specifications of Oscillation Stop Detection Function Item Specification Oscillation stop detection clock and frequency bandwidth f(XIN) ≥ 2 MHz Condition for enabling the oscillation stop detection Bits OCD1 to OCD0 are set to 11b. function Operation at oscillation stop detection Oscillation stop detection interrupt generation 9.7.1 How to Use Oscillation Stop Detection Function monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. Table 9.3 lists the Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt. Figure 9.6 shows an Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt. When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source for the CPU clock and the peripheral functions by a program. Figure 9.5 shows the Procedure for Switching Low-Speed On-Chip Oscillator to XIN Clock. To enter wait mode while the oscillation stop detection function is used, set bits CM02 to CM1 to 00 (peripheral function clock does not stop in wait mode). Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an external cause, set bits OCD1 to OCD0 to 00b to stop or start the XIN clock by a program (select stop mode or change the CM05 bit). This function cannot be used when the XIN clock frequency is below 2 MHz. In this case, set bits OCD1 to OCD0 to 00b. To use the low-speed on-chip oscillator clock as the clock source for the CPU clock and the peripheral functions after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip oscillator selected) and then bits OCD1 to OCD0 to 11b. To use the high-speed on-chip oscillator clock as the clock source for the CPU clock and the peripheral functions after detecting the oscillation stop, first set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01 bit to 1 (high-speed on-chip oscillator selected). Then set bits OCD1 to OCD0 to 11b. Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage • • • • • Table 9.3 Generated Interrupt Source Bit Indicating Interrupt Source Oscillation stop detection (a) OCD3 bit in OCD register = 1 (when (a) or (b)) (b) Bits OCD1 to OCD0 in OCD register = 11b and OCD2 bit = 1 Watchdog timer VW2C3 bit in VW2C register = 1 Voltage monitor 1 VW1C2 bit in VW1C register = 1 Voltage monitor 2 VW2C2 bit in VW2C register = 1 REJ09B0441-0010 Rev.0.10 Page 141 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit Switch to XIN clock NO Check several times whether OCD3 bit is set to 0 (XIN clock oscillates) YES Set bits OCD1 to OCD0 to 00b Set OCD2 bit to 0 (XIN clock selected) End OCD3 to OCD0: Bits in OCD register Figure 9.5 Procedure for Switching Low-Speed On-Chip Oscillator to XIN Clock Determination of interrupt sources OCD3 = 1? (XIN clock stops) NO YES OCD1 = 1 (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as the system clock)? NO YES VW2C3 = 1? (watchdog timer underflow) NO YES VW2C2 = 1? (Vdet2 passed) NO YES Set OCD1 bit to 0 (oscillation stop detection interrupt disabled) (1) To oscillation stop detection interrupt routine To watchdog timer interrupt routine To voltage monitor 2 interrupt routine To voltage monitor 1 interrupt routine Note: 1. This disables multiple oscillation stop detection interrupts. OCD1 to OCD3: Bits in OCD register VW2C2, VW2C3: Bits in VW2C register Figure 9.6 Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Jul 30, 2008 REJ09B0441-0010 Rev.0.10 Page 142 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit 9.8 9.8.1 Notes on Clock Generation Circuit Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used when the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b. 9.8.2 Oscillation Circuit Constants Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system. To use the MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled) and connect the feedback resistor to the chip externally. REJ09B0441-0010 Rev.0.10 Page 143 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10. Power Control There are four power control modes. All modes other than wait mode, stop mode, and power-off mode are referred to as standard operating mode. 10.1 Introduction Table 10.1 lists each mode. Figure 10.1 shows the State Transitions in Power Control Mode. Table 10.1 Power Control Mode High-speed clock High-speed on-chip oscillator Low-speed clock Low-speed on-chip oscillator Operation The CPU and peripheral functions operate. The CPU and peripheral functions operate. The CPU stops and peripheral functions operate. The CPU and peripheral functions stop (oscillation stops). Functions other than the low-speed clock and timer RE stop or all functions stop. Standard operating mode Wait mode Stop mode Power-off mode REJ09B0441-0010 Rev.0.10 Page 144 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control State Transitions in Power Control Mode Power-off mode Successive write to POMCR0 register Interrupt (timer RE) WKUP0, WKUP1 input Reset Standard operating mode Low-speed on-chip oscillator mode CM07 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0 CM07 = 1 CM05 = 0 CM13 = 1 OCD2 = 0 CM07 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0 FRA00 = 1 FRA01 = 1 High-speed clock mode CM05 = 0 CM07 = 0 CM13 = 1 OCD2 = 0 CM07 = 1 Low-speed clock mode CM04 = 1 CM07 = 1 CM05 = 0 CM07 = 0 CM13 = 1 OCD2 = 0 CM14 = 0 FRA01 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 CM05 = 0 CM13 = 1 OCD2 = 0 CM07 = 1 CM07 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 High-speed on-chip oscillator mode CM07 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 Interrupt WAIT instruction CM30 = 1 Interrupt CM10 = 1 Wait mode CPU operation stops Stop mode All oscillators stop CM04, CM05, CM07: Bits in CM0 register CM13, CM14: Bits in CM1 register CM30: Bit in CM3 register OCD2: Bit in OCD register FRA00, FRA01: Bits in FRA0 register Figure 10.1 State Transitions in Power Control Mode REJ09B0441-0010 Rev.0.10 Page 145 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2 10.2.1 Registers System Clock Control Register 0 (CM0) b6 CM06 0 b5 CM05 1 b4 CM04 0 b3 CM03 0 b2 CM02 0 b1 CM01 0 b0 — 0 R/W R/W R/W R/W Address 0006h Bit b7 Symbol CM07 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Reserved bit Set to 0. CM01 Peripheral function clock stop bit in b1 b0 0 0: Peripheral function clock does not stop in CM02 wait mode wait mode 0 1: Clocks f1 to f32 stop in wait mode 1 0: Clocks f1 to f32 and fC stop in wait mode 1 1: Clocks f1 to f32, fC, and fC-LCD stop in wait mode CM03 XCIN clock stop bit 0: XCIN clock oscillates 1: XCIN clock stops CM04 XCIN external clock input enable bit 0: External clock input disabled 1: External clock input enabled CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates 1: XIN clock stops (2) CM06 System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled 1: Divide-by-8 mode CM07 XIN and XCIN clock select bit (5) 0: XIN clock 1: XCIN clock R/W R/W R/W R/W R/W Notes: 1. The CM05 bit stops the XIN clock when high-speed on-chip oscillator mode or low-speed on-chip oscillator mode is selected. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock, set the bits in the following order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (on-chip oscillator clock selected). 2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged. 3. Only when the CM05 bit to 1 (XIN clock stops) and the CM07 bit is set to 1 (XCIN clock), P12_0 and P12_1 can be used as I/O ports. 4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). 5. Change the CM07 bit from 0 to 1 (XCIN clock) after the XCIN clock oscillation has become stable. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register. REJ09B0441-0010 Rev.0.10 Page 146 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2.2 System Clock Control Register 1 (CM1) b6 CM16 0 b5 — 1 b4 CM14 0 b3 CM13 0 b2 CM12 0 b1 CM11 0 b0 CM10 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0007h Bit b7 Symbol CM17 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name CM10 All clock stop control bit (2, 5) CM11 CM12 CM13 CM14 — CM16 CM17 Function 0: Clock oscillates 1: All clocks stop (stop mode) XIN-XOUT on-chip feedback resistor 0: On-chip feedback resistor enabled select bit 1: On-chip feedback resistor disabled XCIN-XCOUT on-chip feedback 0: On-chip feedback resistor enabled resistor select bit 1: On-chip feedback resistor disabled 0: I/O ports P12_0 and P12_1 Port/XIN-XOUT switch bit (5, 6, 7) 1: XIN-XOUT pin 0: Low-speed on-chip oscillator on Low-speed on-chip oscillator 1: Low-speed on-chip oscillator off oscillation stop bit (3, 4) Reserved bit Set to 1. System clock division select bit 1 (1) b7 b6 0 0: No division mode 0 1: Divide-by-2 mode 1 0: Divide-by-4 mode 1 1: Divide-by-16 mode Notes: 1. When the CM06 bit is set to 0, bits CM16 and CM17 are enabled. 2. When the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). It remains unchanged even if 1 is written to it. 4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14 bit to 0 (low-speed on-chip oscillator on). 5. To use P12_0 and P12_1 as input ports, set the CM13 bit to 0 (I/O ports), the CM05 bit in the CM0 register to 1 (XIN clock stops), and the CM07 bit to 1 (XCIN clock). To use as external clock input, set the CM13 bit to 0 (I/O ports), the CM05 bit to 1 (XIN clock oscillates), the CM07 bit to 0 (XIN clock). When the PD12_0 bit in the PD12 register is further set to 0 (input mode), an external clock can be input. XOUT can be used as the input port P12_1 at this time. 6. When the CM10 bit is set to 1 (stop mode), the XOUT pin is held high while the CM13 bit is set to 1 (XIN-XOUT pin). 7. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register. REJ09B0441-0010 Rev.0.10 Page 147 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2.3 System Clock Control Register 3 (CM3) b6 CM36 0 b5 CM35 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 CM30 0 R/W R/W — Address 0009h Bit b7 Symbol CM37 After Reset 0 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name CM30 Wait control bit (1) — — — — CM35 Function 0: Other than wait mode 1: MCU enters wait mode Nothing is assigned. If necessary, set to 0. When read, the content is 0. CPU clock division ratio select bit when exiting wait mode 0: Following settings are enabled: CM06 bit in CM0 register Bits CM16 and CM17 in CM1 register 1: No division (2) b7 b6 R/W b6 b7 CM36 CM37 CPU clock select bit when exiting wait or stop mode 0 0: MCU exits with the CPU clock used immediately before entering wait or stop mode 0 1: Do not set. 1 0: High-speed on-chip oscillator clock selected (3) 1 1: XIN clock selected (4) R/W R/W Notes: 1. When the MCU exits wait mode by a peripheral function interrupt, the CM30 bit is set to 0 (other than wait mode). 2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1 register is set to 00b (no division mode). 3. When bits CM37 to CM36 are set to 10b (high-speed on-chip oscillator clock selected), the following will be set when the MCU exits wait mode or stop mode: • OCD2 bit in OCD register = 1 (on-chip oscillator selected) • FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on) • FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected) 4. When bits CM37 to CM36 are set to 11b (XIN clock selected), the following will be set when the MCU exits wait mode or stop mode. • OM05 bit in OM0 register = 1 (XIN clock oscillates) • OM13 bit in OM1 register = 1 (XIN-XOUT pin) • OCD2 bit in OCD register = 0 (XIN clock selected) Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register. CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). However, the XIN clock, XCIN clock, and on-chip oscillator clock do not stop, so peripheral functions using these clocks continue operating. The MCU exits wait mode by a reset or peripheral function interrupt. If the MCU enters wait mode while the I flag is set to 0 (maskable interrupt disabled), it resumes executing the instruction immediately after the instruction to set the CM30 bit to 1 when exiting wait mode. If the MCU enters wait mode with the WAIT instruction, interrupt handling is performed by the CPU when exiting wait mode. REJ09B0441-0010 Rev.0.10 Page 148 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2.4 Oscillation Stop Detection Register (OCD) b6 — 0 b5 — 0 b4 — 0 b3 OCD3 0 b2 OCD2 1 b1 OCD1 0 b0 OCD0 0 R/W R/W R/W R/W R R/W Address 000Ch Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1) 1: Oscillation stop detection function enabled OCD1 Oscillation stop detection interrupt 0: Disabled (1) enable bit 1: Enabled OCD2 System clock select bit (3) 0: XIN clock selected (6) 1: On-chip oscillator clock selected (2) OCD3 Clock monitor bit (4, 5) 0: XIN clock oscillates 1: XIN clock stops — Reserved bits Set to 0. — — — Notes: 1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or lowspeed on-chip oscillator mode (XIN clock stops). 2. When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). 3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) when the XIN clock oscillation stop is detected while bits OCD1 to OCD0 are set to 11b. When the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged even if 0 (XIN clock selected) is written to it. 4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). 5. The OCD3 bit remains 0 (XIN clock oscillates) when bits OCD1 to OCD0 are set to 00b. 6. Refer to 9.7.1 How to Use Oscillation Stop Detection Function for the switching procedure when the XIN clock re-oscillates after detecting an oscillation stop. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register. REJ09B0441-0010 Rev.0.10 Page 149 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2.5 High-Speed On-Chip Oscillator Control Register 0 (FRA0) b6 — 0 b5 — 0 b4 — 0 b3 FRA03 0 b2 — 0 b1 FRA01 0 b0 FRA00 0 R/W R/W R/W R/W R/W R/W Address 0023h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name FRA00 High-speed on-chip oscillator enable bit FRA01 — FRA03 — — — — High-speed on-chip oscillator select bit (1) Reserved bit fOCO128 clock select bit Reserved bits Function 0: High-speed on-chip oscillator off 1: High-speed on-chip oscillator on 0: Low-speed on-chip oscillator selected (2) 1: High-speed on-chip oscillator selected Set to 0. 0: fOCO-S divided by 128 selected 1: fOCO-F divided by 128 selected Set to 0. Notes: 1. Change the FRA01 bit under the following conditions. • FRA00 = 1 (high-speed on-chip oscillator on) • CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on) • Bits FRA22 to FRA20 in the FRA2 register: All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b Division ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more) Division ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) 2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (highspeed on-chip oscillator off) at the same time. Set the FRA01 bit to 0 before setting the FRA00 bit to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register. REJ09B0441-0010 Rev.0.10 Page 150 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2.6 Voltage Detect Register 2 (VCA2) b2 VCA22 0 0 b1 VCA21 0 0 b0 VCA20 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0034h Bit b7 b6 b5 b4 b3 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 After Reset The LVDAS bit in the OFS register is set to 1. 0 0 0 0 0 After Reset The LVDAS bit in the OFS register is set to 0. 0 0 1 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name VCA20 Internal power low consumption enable bit (1) VCA21 Comparator A1 reference voltage input select bit VCA22 LVCMP1 comparison voltage external input select bit VCA23 Comparator A2 reference voltage input select bit VCA24 LVCMP2 comparison voltage external input select bit VCA25 Voltage detection 0 enable bit (3) VCA26 Voltage detection 1/comparator A1 enable bit (4) VCA27 Voltage detection 2/comparator A2 enable bit (5) Function 0: Low consumption disabled 1: Low consumption enabled (2) 0: Internal reference voltage 1: LVREF pin input voltage 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage 0: Internal reference voltage 1: LVREF pin input voltage 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 10.7 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. REJ09B0441-0010 Rev.0.10 Page 151 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.2.7 Power-Off Mode Control Register 0 (POMCR0) b6 POM06 0 b5 POM05 0 b4 POM04 0 b3 POM03 0 b2 POM02 0 b1 POM01 0 b0 POM00 0 Address 0020h Bit b7 Symbol POM07 After Reset X Initial write: Selection of the pin status in power-off mode and the exit methods Bit Symbol Bit Name Function b0 POM00 Power-off mode select bit 0: Power-off 0 (all functions stop) 1: Power-off 1 (timer RE enabled) b1 POM01 Reserved bits Set to 0. b2 POM02 b3 POM03 WKUP1 input enable bit 0: Input disabled b4 b5 b6 b7 POM04 Reserved bits POM05 POM06 POM07 1: Input enabled Set to 0. R/W W W W W W W W W Second to fifth write: Entering power-off mode Bit Function b7 to b0 Write 88h, 15h, 92h, and 25h successively. Read Bit b0 b1 b2 b3 b4 b5 b6 b7 R/W W Symbol Bit Name POM00 WKUP0 source power-off exit flag POM01 WKUP1 source power-off exit flag Function 0: Undetected 1: Detected R/W R R R — — — — POM06 Timer RE source power-off exit flag — 0: Undetected 1: Detected Nothing is assigned. When read, the content is undefined. 0: Undetected 1: Detected Nothing is assigned. When read, the content is undefined. R R Note: 1. Write to the POMCR0 register five times successively to enter power-off mode. REJ09B0441-0010 Rev.0.10 Page 152 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.3 Standard Operating Mode Table 10.2 lists the Clock Selection in Standard Operating Mode. In standard operating mode, the CPU and peripheral function clocks are supplied to operate the CPU and the peripheral functions. Power control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. If unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program until oscillation stabilizes before the MCU exits. Table 10.2 Clock Selection in Standard Operating Mode OCD Register OCD2 High-speed clock mode No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 Low-speed clock mode No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 High-speed on-chip oscillator mode No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 Low-speed on-chip oscillator mode No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 0 0 0 0 0 CM17 0 0 1 CM1 Register CM16 0 1 0 CM14 CM0 Register FRA0 Register Modes CM13 CM07 CM06 CM05 CM04 CM03 FRA01 FRA00 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 − − − − − 1 1 1 1 1 1 1 1 1 − − 1 0 0 1 − 1 0 0 1 − 1 0 0 1 − 1 − 1 0 1 0 − 1 0 1 0 − 1 0 1 0 − 1 − − − − − − − − − − − − − − − 0 0 0 0 0 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 0 0 0 0 0 − − − − − − − − − − − − − − − 0 0 0 0 0 − − − − − − − − − − − − − − − − − − − − 1 1 1 1 1 0 0 0 0 0 − − − − − − − − − − 1 1 1 1 1 − − − − − −: Indicates that either 0 or 1 can be set. REJ09B0441-0010 Rev.0.10 Page 153 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.3.1 High-Speed Clock Mode The XIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. When the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on), fOCO can be used for timer RA. Also, when the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. 10.3.2 Low-Speed Clock Mode The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read mode enabled). Also, when the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. To enter wait mode from low-speed clock mode, lower consumption current in wait mode is enabled by setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled). To reduce the power consumption, refer to 10.7 Reducing Power Consumption. 10.3.3 High-Speed On-Chip Oscillator Mode The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. When the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG. Also, when the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. 10.3.4 Low-Speed On-Chip Oscillator Mode When the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 0, the low-speed on-chip oscillator is used as the on-chip oscillator clock. At this time, the on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. When the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG. Also, When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read mode enabled). To enter wait mode from low-speed clock mode, current consumption in wait mode can be further reduced by setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled). To reduce the power consumption, refer to 10.7 Reducing Power Consumption. REJ09B0441-0010 Rev.0.10 Page 154 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.4 Wait Mode Since the CPU clock stops in wait mode, CPU operation using the CPU clock and watchdog timer operation with count source protection mode disabled are halted. However, the XIN clock, XCIN clock, and on-chip oscillator clock do not stop, so peripheral functions using these clocks continue operating. 10.4.1 Peripheral Function Clock Stop Function The peripheral function clock to stop in wait mode can be selected by setting bits CM01 and CM02 in the CM0 register (peripheral function clock stop bits in wait mode). This controls power consumption according to applications. 10.4.2 Entering Wait Mode The MCU enters wait mode by executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1 (MCU enters wait mode). When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1 bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1 (MCU enters wait mode). If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the CPU clock does not stop. 10.4.3 Pin Status in Wait Mode Each I/O port retains its states immediately before the MCU enters wait mode. REJ09B0441-0010 Rev.0.10 Page 155 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.4.4 Exiting Wait Mode The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by bits CM01 and CM02. Table 10.3 Interrupt Serial interface interrupt Interrupts to Exit Wait Mode and Usage Conditions CM02 to CM01 = 00b Usable when operating with an internal or external clock. CM02 to CM01 = 01b Usable when operating with fC or an external clock. (Do not use.) CM02 to CM01 = 10b Usable when operating with an external clock. (Do not use.) CM02 to CM01 = 11b Usable when operating with an external clock. (Do not use.) Clock synchronous Usable in all modes. serial I/O with chip select interrupt / I2C bus interface interrupt Key input interrupt A/D conversion interrupt Timer RA interrupt Usable (Do not use.) Usable in all modes. Usable (Do not use.) Usable if there is no filter in event counter mode. Usable by selecting fOCO, fC, or fC32 as the count source. (Do not use.) (Do not use.) Usable by selecting fOCO40M as the count source. Usable when operating in real time clock mode. (Do not use.) Usable if there is no filter. Usable Usable (Do not use.) Usable in count source protection mode. Usable Usable Usable by selecting fCLCD as the count source. Usable (Do not use.) Usable if there is no filter in event counter mode. Usable by selecting fOCO as the count source. (Do not use.) (Do not use.) Usable by selecting fOCO40M as the count source. Usable when operating in real time clock mode. (Do not use.) Usable if there is no filter. Usable Usable (Do not use.) Usable in count source protection mode. Usable Usable Usable by selecting fCLCD as the count source. Usable (Do not use.) Usable if there is no filter in event counter mode. Usable by selecting fOCO as the count source. (Do not use.) (Do not use.) Usable by selecting fOCO40M as the count source. Usable when operating in real time clock mode. (Do not use.) Usable if there is no filter. Usable Usable (Do not use.) Usable in count source protection mode. Usable Usable (Do not use.) Timer RB interrupt Timer RC interrupt Timer RD interrupt Usable in all modes. Usable in all modes. Usable in all modes. Timer RE interrupt Timer RG interrupt INT interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt Oscillation stop detection interrupt Usable in all modes. Usable in all modes. Usable Usable Usable Usable Watchdog timer interrupt Usable in count source protection mode. Comparator A1 interrupt Comparator A2 interrupt LCD counter interrupt Usable Usable Usable The following interrupts can be used to exit wait mode: • When bits CM02 to CM01 are set to 00b (peripheral function clock does not stop in wait mode), peripheral function interrupts other than A/D conversion interrupts. • When bits CM02 to CM01 are set to 01b (clocks f1 to f32 stop in wait mode), the interrupts of the peripheral functions operating with external signals, the on-chip oscillator clock, or clocks fC1 to f32. • When bits CM02 to CM01 are set to 10b (clocks f1 to f32 and fC stop in wait mode), the interrupts of the peripheral functions operating with external signals or the on-chip oscillator clock. • When bits CM02 to CM01 are set to 11b (clocks f1 to f32, fC, and fC-LCD stop in wait mode), the same applies when bits CM02 to CM01 are set to 10b. Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions. REJ09B0441-0010 Rev.0.10 Page 156 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control Figure 10.2 shows the Time from Wait Mode to Interrupt Routine Execution after CM30 Bit in CM3 Register is Set to 1 (MCU Enters Wait Mode). To use a peripheral function interrupt to exit wait mode, set up the following before setting the CM30 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled). (2) Operate the peripheral function to be used for exiting wait mode. When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register and the VCA20 bit in the VCA2 register, as shown in Figure 10.2. The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits CM16 and CM17 in the CM1 register automatically change. FMR0 Register VCA2 Register FMSTP Bit VCA20 Bit 0 (internal power low consumption disabled) 1 (internal power low consumption enabled) 0 (internal power low consumption disabled 1 (internal power low consumption enabled) Internal Power Stabilization Time (T0) Time until Flash Memory Activation (T1) Time until CPU Clock Supply (T2) Time for Interrupt Sequence (T3) Remarks 0 µs Period of system clock Period of CPU clock Period of CPU clock × 1 cycle + 60 µs × 2 cycles × 20 cycles (max.) 100 µs (max.) The total of T0 to T3 is the time from wait mode until an interrupt routine is executed. Period of system clock × 1 cycle 100 µs (max.) Same as above Same as above 0 (flash memory operates) 0 µs 1 (flash memory stops) T0 Internal power stabilization time 100 µs (max.) Interrupt request generation T1 Flash memory activation sequence T2 CPU clock restart sequence T3 Wait mode Interrupt sequence Figure 10.2 Time from Wait Mode to Interrupt Routine Execution after CM30 Bit in CM3 Register is Set to 1 (MCU Enters Wait Mode) REJ09B0441-0010 Rev.0.10 Page 157 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control Figure 10.3 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting stop mode. When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register and the VCA20 bit in the VCA2 register, as shown in Figure 10.3. The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits CM16 and CM17 in the CM1 register automatically change. FMR0 Register VCA2 Register FMSTP Bit VCA20 Bit 0 (internal power low consumption disabled) 1 (internal power low consumption enabled) 0 (internal power low consumption disabled 1 (internal power low consumption enabled) Internal Power Stabilization Time (T0) Time until Flash Memory Activation (T1) Time until CPU Clock Supply (T2) Time for Interrupt Sequence (T3) Remarks 0 µs Period of system clock Period of CPU clock Period of CPU clock × 1 cycle + 60 µs × 2 cycles × 20 cycles (max.) 100 µs (max.) The total of T0 to T3 is the time from wait mode until an interrupt routine is executed. Period of system clock × 1 cycle 100 µs (max.) Same as above Same as above 0 (flash memory operates) 0 µs 1 (flash memory stops) T0 Internal power stabilization time 100 µs (max.) Interrupt request generation T1 Flash memory activation sequence T2 CPU clock restart sequence T3 Wait mode Interrupt sequence Figure 10.3 Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed REJ09B0441-0010 Rev.0.10 Page 158 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.5 Stop Mode All oscillator circuits except fOCO-WDT stop in stop mode. Since the CPU clock and the peripheral function clock stop, CPU operation and peripheral function operation using these clocks are halted. If the voltage applied to the VCC pin is VRAM or more, the content of internal RAM is retained. The peripheral functions clocked by external signals continue operating. Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions. Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions Usage Conditions − Interrupt Key input interrupt INT interrupt Timer RA interrupt Serial interface interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt Comparator A1 interrupt Comparator A2 interrupt Usable if there is no filter. Usable if there is no filter when an external pulse is counted in event counter mode. When an external clock is selected. Usable in digital filter disabled mode (the VW1C1 bit in the VW1C register is set to 1). Usable in digital filter disabled mode (the VW2C1 bit in the VW2C register is set to 1). Usable in digital filter disabled mode (the VW1C1 bit in the VW1C register is set to 1). Usable in digital filter disabled mode (the VW2C1 bit in the VW2C register is set to 1). 10.5.1 Entering Stop Mode The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode). To use stop mode, set the following before the MCU enters stop mode: • Bits OCD1 to OCD0 in the OCD register = 00b • CM35 bit in CM3 register = 0 (settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled) 10.5.2 Pin Status in Stop Mode Each I/O port retains its state before the MCU enters stop mode. However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pin), the XOUT (P12_0) pin is held high. REJ09B0441-0010 Rev.0.10 Page 159 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.5.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.4 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting stop mode. When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply starts. The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled). FMR0 Register Internal Power Stabilization Time (T0) FMSTP Bit 0 (flash memory operates) 1 (flash memory stops) Time until Flash Memory Activation (T2) Time until CPU Clock Supply (T3) Time for Interrupt Sequence (T4) Remarks 100 µs (max.) Period of system clock × 1 cycle + 60 µs (max.) Period of system clock × 1 cycle Period of CPU clock × 2 cycles Period of CPU clock × 20 cycles 100 µs (max.) Same as above Same as above The total of T0 to T4 is the time from wait mode until an interrupt routine is executed. T0 T1 Oscillation time of CPU clock source used immediately before stop mode T2 T3 T4 Stop mode Internal power stabilization time Flash memory activation sequence CPU clock restart sequence Interrupt sequence 100 µs (max.) Interrupt request generation Figure 10.4 Time from Stop Mode to Interrupt Routine Execution REJ09B0441-0010 Rev.0.10 Page 160 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.6 Power-Off Mode All functions stop in power-off mode. However, the low-speed clock and timer RE functions can be set to operate or stop by means of register settings. The least power is consumed in this mode. 10.6.1 Pin Handling in Power-Off Mode Figure 10.5 shows Pin Handling in Power-Off Mode. To use this mode, hardware reset input is required. For details of hardware resets, refer to 5.2 Hardware Reset. 10.6.2 Entering Power-Off Mode Table 10.5 lists the register settings in power-off mode. The pin status in power-off mode and the method of exiting are selected by the initial write to the POMCR0 register. When 88h, 15h, 92h, and 25h are then written successively, the MCU enters power-off mode. • Power-off 0 When the POM00 bit is set to 0 (power-off 0) by the initial write, all functions stop once the MCU enters power-off mode. • Power-off 1 When the POM00 bit is set to 1 (power-off 1) by the initial write, all functions except the low-speed clock and timer RE stop once the MCU enters power-off mode. The timer RE interrupt can be used to exit the mode when power-off 1 is selected. An access to another register during the write to the POMCR0 register does not affect entering the mode. 10.6.3 Pin Status in Power-Off Mode Table 10.6 lists the Pin Status in Power-Off Mode. When the MCU enters power-off mode, the contents of RAM and registers are not retained. Save the data needs to be retained to the data flash before entering poweroff mode. (1) When power-off mode is used Always pull up WKUP0. Pull up WKUP1 when selected as the exit source. Input a low-level signal to exit the mode. (2) When power-off mode is not used Connect WKUP0 to VSS. MCU VCC VCC MCU WKUP0 WKUP1 WKUP0 RESET RESET Input a hardware reset as reset input. For details of resets, refer to 5.2 Hardware Reset. A hardware reset or the power-on reset function can be used as reset input. Figure 10.5 Pin Handling in Power-Off Mode REJ09B0441-0010 Rev.0.10 Page 161 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.6.4 Exiting Power-Off Mode To exit power-off mode, input a low signal pulse to the RESET, WKUP0, or WKUP1 pin or use the timer RE interrupt (power-off 1 is selected). The timer RE interrupt enabled in the TREC2 register can be used to exit the mode. After exiting power-off mode, the operation is the same as a normal reset sequence. When power-off mode is exited, the exit source can be identified by reading the flags in the SDCR0 register. The values of these flags are undefined after power-on and set to 0 by writing to the SDCR0 register. If multiple exit sources coincide, multiple flags are set. Figure 10.6 show the Time from Power-Off Mode to Reset Vector Address Read Execution. Table 10.5 Entering Power-Off Mode and Exit Methods Status All functions stop when the SDC00 bit is set to 0 (power-off 0) by the initial write. Exit Method RESET input, WKUP0 input, or WKUP1 input Entering Power-Off Mode Write the pin state and the exit method to the POMCR0 register (1, 2) in power-off mode. Then, write 88h,15h, 92h, and 25h successively. Functions other the low-speed clock and RESET input, timer RE interrupt, timer RE stop when the SDC00 bit is set to WKUP0 input, or WKUP1 input 1 (power-off 1) by the initial write. Notes: 1. To use WKUP1 to exit power-off mode, set the POM03 bit to 1 (input enabled) by the initial write to the POMCR0 register. 2. To use timer RE to exit power-off mode, enable the timer RE interrupt in registers TREIC and TRECR2, then set the POM00 bit in the POMCR0 register to 1 (timer RE enabled). When all interrupts are disabled by the TRECR2 register, the low-speed clock and timer RE functions operate, but timer RE cannot be used to exit power-off mode. Table 10.6 Ports P0 to P7 Pin Status in Power-Off Mode Status The states of registers LSE0 to LSE7 before entering power-off mode are retained. When LCD ports are selected by these registers, low-level output. When ports are selected, the pins are placed in the high-impedance state. High impedance WKUP0 input Oscillation is off (high impedance) at power-off 0, and oscillation is on at power-off 1. High impedance Pin Name Ports 10 to P13 WKUP0 XCIN, XCOUT VL1 to VL4 Internal Power Stabilization Time (T0) Internal Reset Time (T1) Time until Flash Memory Activation (T2) Idling Time (T3) Remarks Max. 2 ms 64 µs (fOCO-S clock × 8 cycles) Max. 1,424 µs CPU clock × 108 to 178 cycles 224 µs CPU clock × 28 cycles The total of T0 to T3 is the time from power-off mode until a reset vector address is read. T0 T1 T2 T3 Power-off mode Internal power stabilization time Internal reset time Flash memory activation sequence Idling time Power-off exit source generation Note: 1. If the with of low-level input to the RESET or WKUP0 pin exceeds the internal power stabilization time and internal reset time (T0 +T1), the excess is added to the time until a reset vector address is read. Figure 10.6 Time from Power-Off Mode to Reset Vector Address Read Execution REJ09B0441-0010 Rev.0.10 Page 162 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.7 Reducing Power Consumption This section describes key points and processing methods for reducing power consumption. They should be referred to when designing a system or creating a program. 10.7.1 Voltage Detection Circuit When voltage monitor 1 and comparator A1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage detection 1 circuit disabled). When voltage monitor 2 and comparator A2 are not used, set the VCA27 bit in the VCA2 register to 0 (voltage detection 2 circuit disabled). When power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0 (voltage detection 0 circuit disabled). 10.7.2 Ports Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance state. Unnecessary ports should be set to input and fixed to a stable electric potential before the MCU enters wait mode or stop mode. 10.7.3 Clocks Power consumption generally depends on the number of the operating clocks and their frequencies. The fewer the number of operating clocks or the lower their frequencies, the more power consumption decreases. Unnecessary clocks should be stopped accordingly. Stopping the low-speed on-chip oscillator oscillation: CM14 bit in CM1 register Stopping the high-speed on-chip oscillator oscillation: FRA00 bit in FRA0 register 10.7.4 Wait Mode, Stop Mode, and Power-Off Mode Power consumption can be reduced in wait mode, stop mode, and power-off mode. 10.7.5 Stopping Peripheral Function Clocks When peripheral function clocks are not necessary in wait mode, set bits CM01 and CM02 bit in the CM0 register to stop the clock. 10.7.6 Timers When timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff). When timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff). When timer RC is not used, set the MSTTRC bit in the MSTCR register to 1 (standby). When timer RD is not used, set the MSTTRD bit in the MSTCR register to 1 (standby). When timer RG is not used, set the MSTTRG bit in the MSTCR register to 1 (standby). REJ09B0441-0010 Rev.0.10 Page 163 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.7.7 A/D Converter When the A/D converter is not used, power consumption can be reduced by setting the ADSTBY bit in the ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow. 10.7.8 Clock Synchronous Serial Interface When the SSU or I2C bus is not used, set the MSTIIC bit in the MSTCR register to 1 (standby). 10.7.9 Reducing Internal Power Consumption When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal power consumption can be reduced by using the VCA20 bit in the VCA2 register. Figure 10.7 shows the Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. To enable reduced internal power consumption by the VCA20 bit, follow this procedure. Exit wait mode by interrupt Procedure for enabling reduced internal power consumption using the VCA20 bit (Note 1) In the interrupt routine Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled) (2) (This is automatically set when exiting wait mode) Step (2) Stop the XIN clock and the high-speed on-chip oscillator clock Step (6) Start the XIN clock or the high-speed on-chip oscillator clock Step (3) VCA20 ← 1 (internal power low consumption enabled) (2, 3) Step (7) (Wait until the XIN clock or the high-speed on-chip oscillator clock oscillation stabilizes) If it is necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine, execute steps (6) and (7) in the routine. Step (4) Enter wait mode (4) Step (8) Enter high-speed clock mode or high-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled) (2) Interrupt handling Step (6) Start the XIN clock or the high-speed on-chip oscillator clock Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode If the high-speed clock or high-speed on-chip oscillator starts during the interrupt routine, execute steps (1) to (3) at the end of the routine. Step (7) (Wait until the XIN clock or the high-speed on-chip oscillator clock oscillation stabilizes) Step (2) Stop the XIN clock and the high-speed on-chip oscillator clock Step (8) Enter high-speed clock mode or high-speed on-chip oscillator mode Step (3) VCA20 ← 1 (internal power low consumption enabled) (2, 3) Interrupt handling completed Notes: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When the MCU enters wait mode, follow 10.4 Wait Mode. VCA20: Bit in VCA2 register Figure 10.7 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit REJ09B0441-0010 Rev.0.10 Page 164 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.7.10 Stopping Flash Memory In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by stopping the flash memory using the FMSTP bit in the FMR0 register. Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memory stops). The FMSTP bit must be written to by a program transferred to RAM. When the MUC enters stop mode or wait mode while CPU rewrite mode is disabled, the power for the flash memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This eliminates the need to set the FMR0 register. Figure 10.8 shows the Handling Procedure Example for Reducing Power Consumption Using FMSTP Bit. FMSTP bit setting program After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) Transfer the FMSTP bit setting program to RAM Write 1 to the FMSTP bit (flash memory stops. low power consumption state) (1) Jump to the FMSTP bit setting program (The subsequent processing is executed by the program in the RAM) Enter low-speed clock mode or low-speed on-chip oscillator mode Stop the high-speed on-chip oscillator Process in low-speed clock mode or low-speed on-chip oscillator mode Switch the clock source for the CPU clock (2) Write 0 to the FMSTP bit (flash memory operates) Write 0 to the FMR01 bit (CPU rewrite mode disabled) Notes: 1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled), set the FMSTP bit to 1 (flash memory stops). 2. Before switching the CPU clock source, make sure the designated clock is stable. 3. Insert a wait time of 60 µs by a program. Do not access the flash memory during this wait time. Wait until the flash memory circuit stabilizes (60 µs) (3) Jump to the specified address in the flash memory FMR01, FMSTP: Bits in FMR0 register Figure 10.8 Handling Procedure Example for Reducing Power Consumption Using FMSTP Bit REJ09B0441-0010 Rev.0.10 Page 165 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.7.11 Low-Current-Consumption Read Mode In low-speed clock mode and low-speed on-chip oscillator mode, the current consumption when reading the flash memory can be reduced by setting the FMR27 bit in the FMR2 register to 1 (enabled). Figure 10.9 shows the Handling Procedure Example of Low-Current-Consumption Read Mode. Handling procedure for enabling low-current-consumption read mode by the FMR27 bit Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode Step (2) Stop the high-speed on-chip oscillator clock Step (3) FMR27 ← 1 (low-current-consumption read mode enabled) (1) Step (4) Enter low-current-consumption read mode (2) Step (5) FMR27 ← 0 (low-current-consumption read mode disabled) Step (6) Start the high-speed on-chip oscillator clock Step (7) (Wait until the high-speed on-chip oscillator clock oscillation stabilizes) Step (8) Enter high-speed on-chip oscillator mode Notes: 1. To set the FMR27 bit to 1, first write 0 and then write 1 immediately. After writing 0, do not generate an interrupt before writing 1. 2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled). FMR27: Bit in FMR2 register Figure 10.9 Handling Procedure Example of Low-Current-Consumption Read Mode REJ09B0441-0010 Rev.0.10 Page 166 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control 10.8 10.8.1 Notes on Power Control Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least four NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. • Program example to enter stop mode BCLR 1, FMR0; CPU rewrite mode disabled BSET 0, PRCR; Protect disabled FSET I; Enable interrupt BSET 0, CM1; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP 10.8.2 Wait Mode To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least four NOP instructions after the WAIT instruction. • Program example to execute the WAIT instruction BCLR 1, FMR0; CPU rewrite mode disabled FSET I; Enable interrupt WAIT; Wait mode NOP NOP NOP NOP 10.8.3 Power-Off Mode To enter power-off mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then access the POMCR0 register. A period of a few microseconds is required between accessing the POMCR0 register and entering power-off mode. As the CPU continues to operate during this period, insert the NOP and the WAIT instructions to stop the program. • Program example to enter power-off mode (when timer RE and the low-speed clock is enabled) BCLR 1, FMR0; CPU rewrite mode disabled MOV. B #08H, POMCR0; Select power-off 0 and WKUP1 input enabled MOV. B #88H, POMCR0; Fixed value MOV. B #15H, POMCR0; Fixed value MOV. B #92H, POMCR0; Fixed value MOV. B #25H, POMCR0; Fixed value NOP; NOP; NOP; NOP; Enter power-off mode WAIT; Wait mode REJ09B0441-0010 Rev.0.10 Page 167 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 11. Protection 11. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows: • Registers protected by PRC0 bit: Registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3 • Registers protected by PRC1 bit: Registers PM0 and PM1 • Registers protected by PRC2 bit: PD0 register • Registers protected by PRC3 bit: Registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C 11.1 11.1.1 Register Protect Register (PRCR) b6 — 0 b5 — 0 b4 — 0 b3 PRC3 0 b2 PRC2 0 b1 PRC1 0 b0 PRC0 0 R/W R/W Address 000Ah Bit b7 Symbol — After Reset 0 Bit b0 Symbol Bit Name PRC0 Protect bit 0 b1 PRC1 Protect bit 1 b2 PRC2 Protect bit 2 b3 PRC3 Protect bit 3 b4 b5 b6 b7 — — — — Reserved bits Reserved bits Function Enables writing to registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3. 0: Write disabled 1: Write enabled Enables writing to registers PM0 and PM1. 0: Write disabled 1: Write enabled Enables writing to the PD0 register. 0: Write disabled 1: Write enabled (1) Enables writing to registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C. 0: Write disabled 1: Write enabled Set to 0. When read, the content is 0. R/W R/W R/W R/W R Note: 1. The PRC2 bit is set to 0 after writing 1 to it and executing a write to any address. Since the other bits are not set to 0, set them to 0 by a program. REJ09B0441-0010 Rev.0.10 Page 168 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12. Interrupts 12.1 12.1.1 Introduction Types of Interrupts Figure 12.1 shows the Types of Interrupts. Software (non-maskable interrupts) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Voltage monitor 1 / compatator A1 Voltage monitor 2 / compatator A2 Single step (2) Address break (2) Address match Interrupts Special (non-maskable interrupts) Hardware Peripheral function (1) (maskable interrupts) (3) (3) Notes: 1. A peripheral function interrupt is generated by a peripheral function in the MCU. 2. Do not use these interrupts. These are provided exclusively for use by development tools. 3. A non-maskable or maskable interrupt can be selected by bits IREQ1SEL and IREQ2SEL in the CMPA register. Figure 12.1 Types of Interrupts • Maskable interrupts: • Non-maskable interrupts: These interrupts are enabled or disabled by the interrupt enable flag (I flag). The interrupt priority can be changed based on the interrupt priority level. These interrupts are not enabled or disabled by the interrupt enable flag (I flag). The interrupt priority cannot be changed based on the interrupt priority level. REJ09B0441-0010 Rev.0.10 Page 169 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt An overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions that set the O flag are as follows: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB. 12.1.2.3 BRK Interrupt A BRK interrupt is generated when the BRK instruction is executed. 12.1.2.4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to 63 can be specified with the INT instruction. Because software interrupt numbers are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used. REJ09B0441-0010 Rev.0.10 Page 170 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 15. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the oscillation stop detection function, refer to 9. Clock Generation Circuit. 12.1.3.3 Voltage Monitor 1/Comparator A1 Interrupt A voltage monitor 1/Comparator A1 interrupt is generated by the voltage detection circuit or the comparator A. A non-maskable or maskable interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 32. Comparator A. 12.1.3.4 Voltage Monitor 2/Comparator A2 Interrupt A voltage monitor 2/Comparator A2 interrupt is generated by the voltage detection circuit or the comparator A. A non-maskable or maskable interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 32. Comparator A. 12.1.3.5 Single-Step Interrupt, Address Break Interrupt Do not use these interrupts. They are provided exclusively for use by development tools. 12.1.3.6 Address Match Interrupt An address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMAD0 to RMAD1 if the AIER0 bit in the AIER0 register or AIER1 bit in the AIER1 register is set to 1 (address match interrupt enabled). For details of the address match interrupt, refer to 12.6 Address Match Interrupt. 12.1.4 Peripheral Function Interrupts A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts are maskable. Refer to Table 12.2 Relocatable Vector Tables for sources of the corresponding peripheral function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral functions. REJ09B0441-0010 Rev.0.10 Page 171 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows an Interrupt Vector. MSB LSB Vector address (L) Low-order address Middle-order address 0000 High-order address 0000 Vector address (H) Figure 12.2 Interrupt Vector 0000 12.1.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to 35.3 Functions to Prevent Flash Memory from being Rewritten. Table 12.1 Fixed Vector Tables Vector Addresses Remarks Reference Address (L) to (H) 0FFDCh to 0FFDFh Interrupt with R8C/Tiny Series UND instruction Software Manual 0FFE0h to 0FFE3h Interrupt with INTO instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. 0FFE8h to 0FFEBh 12.6 Address Match Interrupt 0FFECh to 0FFEFh 0FFF0h to 0FFF3h 15. Watchdog Timer, 9. Clock Generation Circuit, 6. Voltage Detection Circuit, 32. Comparator A Interrupt Source Undefined instruction Overflow BRK instruction Address match Single step (1) Watchdog timer, Oscillation stop detection, Voltage monitor 1/ comparator A1, Voltage monitor 2/ comparator A2 Address break (1) (Reserved) Reset 0FFF4h to 0FFF7h 0FFF8h to 0FFFBh 0FFFCh to 0FFFFh 5. Resets Note: 1. Do not use these interrupts. They are provided exclusively for use by development tools. REJ09B0441-0010 Rev.0.10 Page 172 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Vector Addresses (1) Address (L) to Address (H) +0 to +3 (0000h to 0003h) +4 to +7 (0004h to 0007h) +12 to +15 (000Ch to 000Fh) +16 to +19 (0010h to 0013h) +20 to +23 (0014h to 0017h) +24 to +27 (0018h to 001Bh) +28 to +31 (001Ch to 001Fh) +32 to +35 (0020h to 0023h) +36 to +39 (0024h to 0027h) +40 to +43 (0028h to 002Bh) +44 to +47 (002Ch to 002Fh) +48 to +51 (0030h to 0033h) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) +60 to +63 (003Ch to 003Fh) Software Interrupt Interrupt Control Number Register 0 − 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reference Interrupt Source BRK instruction (3) Flash memory ready (Reserved) INT7 INT6 INT5 INT4 Timer RC Timer RD0 Timer RD1 Timer RE UART2 transmission/NACK2 UART2 reception/ACK2 Key input A/D conversion Synchronous serial communication unit/ I2C bus interface (2) (Reserved) UART0 transmission UART0 reception UART1 transmission UART1 reception INT2 Timer RA (Reserved) Timer RB INT1 INT3 (Reserved) (Reserved) INT0 UART2 bus collision detection (Reserved) R8C/Tiny Series Software Manual FMRDYIC 35. Flash Memory − − INT7IC 12.4 INT Interrupt INT6IC INT5IC INT4IC 12.4 INT Interrupt 12.4 INT Interrupt 12.4 INT Interrupt 20. Timer RC 21. Timer RD 22. Timer RE 25. Serial Interface (UART2) 12.5 Key Input Interrupt 30. A/D Converter 27. Synchronous Serial Communication Unit (SSU), 28. I2C bus Interface − 24. Serial Interface (UARTi (i = 0 or 1)) TRCIC TRD0IC TRD1IC TREIC S2TIC S2RIC KUPIC ADIC SSUIC/IIC IC − S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC − TRBIC INT1IC INT3IC − − INT0IC +68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +76 to +79 (004Ch to 004Fh) +80 to +83 (0050h to 0053h) +84 to +87 (0054h to 0057h) +88 to +91 (0058h to 005Bh) +96 to +99 (0060h to 0063h) +100 to +103 (0064h to 0067h) +104 to +107 (0068h to 006Bh) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 12.4 INT Interrupt 18. Timer RA − 19. Timer RB 12.4 INT Interrupt − − +116 to +119 (0074h to 0077h) +120 to +123 (0078h to 007Bh) 30 31 +128 to +131 (0080h to 0083h) to 32 to 41 Software (3) +164 to +167 (00A4h to 00A7h) (Reserved) 42 Timer RG +172 to +175 (00ACh to 00AFh) 43 (Reserved) 44 to 49 Voltage monitor 1/comparator A1 +200 to +203 (00C8h to 00CBh) 50 Voltage monitor 2/comparator A2 +204 to +207 (00CCh to 00CFh) 51 (Reserved) 52 to 55 (3) +224 to +227 (00E0h to 00E3h) to 56 to 63 Software +252 to +255 (00FCh to 00FFh) Notes: 1. These addresses are relative to those in the INTB register. 2. Selectable by the IICSEL bit in the SSUIICSR register. 3. These interrupts are not disabled by the I flag. 12.4 INT Interrupt U2BCNIC 25. Serial Interface (UART2) − − − R8C/Tiny Series Software Manual − − TRGIC 23. Timer RG − − VCMP1IC 6. Voltage Detection Circuit VCMP2IC 32. Comparator A − − − R8C/Tiny Series Software Manual REJ09B0441-0010 Rev.0.10 Page 173 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.2 12.2.1 Registers Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0053h (S1TIC), 0054h (S1RIC), 0056h (TRAIC), 0058h (TRBIC), 005Eh (U2BCNIC), 0072h (VCMP1IC), 0073h (VCMP2IC), Bit b7 b6 b5 b4 b3 b2 b1 Symbol — — — — IR ILVL2 ILVL1 After Reset X X X X X 0 0 Bit b0 b1 b2 Symbol Bit Name ILVL0 Interrupt priority level select bit ILVL1 ILVL2 Function b2 b1 b0 b0 ILVL0 0 R/W R/W R/W R/W b3 b4 b5 b6 b7 IR — — — — 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Interrupt request bit 0: No interrupt requested 1: Interrupt requested Nothing is assigned. If necessary, set to 0. When read, the content is undefined. R/W (1) — Note: 1. Only 0 can be written to the IR bit. Do not write 1 to this bit. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 12.8.5 Rewriting Interrupt Control Register. REJ09B0441-0010 Rev.0.10 Page 174 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.2.2 Interrupt Control Register (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC, TRGIC) Address 0041h (FMRDYIC), 0047h (TRCIC), 0048h (TRD0IC), 0049h (TRD1IC), 004Fh (SSUIC/IICIC (Note 1)), 006Bh (TRGIC) Bit b7 b6 b5 b4 b3 b2 b1 Symbol — — — — IR ILVL2 ILVL1 After Reset X X X X X 0 0 Bit b0 b1 b2 Symbol Bit Name ILVL0 Interrupt priority level select bit ILVL1 ILVL2 Function b2 b1 b0 b0 ILVL0 0 R/W R/W R/W R/W b3 b4 b5 b6 b7 IR — — — — 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Interrupt request bit 0: No interrupt requested 1: Interrupt requested Nothing is assigned. If necessary, set to 0. When read, the content is undefined. R/W (1) — Note: 1. Selectable by the IICSEL bit in the SSUIICSR register. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 12.8.5 Rewriting Interrupt Control Register. REJ09B0441-0010 Rev.0.10 Page 175 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.2.3 INTi Interrupt Control Register (INTiIC) (i = 0 to 7) Address 0043h (INT7IC), 0044h (INT6IC), 0045h (INT5IC), 0046h (INT4IC), 0055h (INT2IC), 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) Bit b7 b6 b5 b4 b3 b2 b1 Symbol — — — POL IR ILVL2 ILVL1 After Reset X X 0 0 X 0 0 Bit b0 b1 b2 Symbol Bit Name ILVL0 Interrupt priority level select bit ILVL1 ILVL2 Function b2 b1 b0 b0 ILVL0 0 R/W R/W R/W R/W b3 b4 b5 b6 b7 IR POL — — — 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Interrupt request bit 0: No interrupt requested 1: Interrupt requested (3) 0: Falling edge selected Polarity switch bit 1: Rising edge selected (2) Reserved bit Set to 0. Nothing is assigned. If necessary, set to 0. When read, the content is undefined. R/W (1) R/W R/W — Notes: 1. Only 0 can be written to the IR bit. Do not write 1 to this bit. 2. When the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (falling edge selected). 3. The IR bit may be set to 1 (interrupt requested) when the POL bit is rewritten. Refer to 12.8.4 Changing Interrupt Sources. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 12.8.5 Rewriting Interrupt Control Register. REJ09B0441-0010 Rev.0.10 Page 176 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.3 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in the corresponding interrupt control register. 12.3.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.3.2 IR Bit The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. After the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. However, the IR bit operations of the timer RC interrupt, the timer RD interrupt, the synchronous serial communication unit interrupt the I2C bus interface interrupt, and the flash memory interrupt are different. Refer to 12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources). 12.3.3 Bits ILVL2 to ILVL0, IPL Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels Enabled by IPL. The following are the conditions when an interrupt is acknowledged: • I flag = 1 • IR bit = 1 • Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another. Table 12.3 Bits ILVL2 to ILVL0 000b 001b 010b 011b 100b 101b 110b 111b Settings of Interrupt Priority Levels Interrupt Priority Level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Priority Table 12.4 IPL 000b 001b 010b 011b 100b 101b 110b 111b Interrupt Priority Levels Enabled by IPL Enabled Interrupt Priority Level Interrupt level 1 and above Interrupt level 2 and above Interrupt level 3 and above Interrupt level 4 and above Interrupt level 5 and above Interrupt level 6 and above Interrupt level 7 and above All maskable interrupts disabled − Low REJ09B0441-0010 Rev.0.10 Page 177 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.3.4 Interrupt Sequence The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below. Figure 12.3 shows the Time Required for Executing Interrupt Sequence. (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested). (2) (2) The FLG register is saved to a temporary register (1) in the CPU immediately before entering the interrupt sequence. (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (interrupts disabled). The D flag is set to 0 (single-step interrupt disabled). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed. (4) The CPU internal temporary register (1) is saved on the stack. (5) The PC is saved on the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. 1 CPU Clock Address Bus Data Bus RD WR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Address 0000h Interrupt information Undefined Undefined Undefined SP-2 SP-1 SP-4 SP-4 content SP-3 SP-3 content VEC VEC content VEC+1 VEC+1 content VEC+2 VEC+2 content PC SP-2 content SP-1 content Note: 1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions. Figure 12.3 Time Required for Executing Interrupt Sequence Notes: 1. These registers cannot be accessed by the user. 2. Refer to 12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources) for the IR bit operations of the above interrupts. REJ09B0441-0010 Rev.0.10 Page 178 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.3.5 Interrupt Response Time Figure 12.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response time includes the period from when an interrupt request is generated until the currently executing instruction is completed (refer to (a) in Figure 12.4) and the period required for executing the interrupt sequence (20 cycles, refer to (b) in Figure 12.4). Interrupt request generation Interrupt request acknowledgement Time Instruction (a) Interrupt sequence 20 cycles (b) Instruction in interrupt routine Interrupt response time (a) The period from when an interrupt request is generated until the currently executing instruction is completed. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (no wait states if the divisor is a register). (b) 21 cycles for address match and single-step interrupts. Figure 12.4 Interrupt Response Time 12.3.6 IPL Change when Interrupt Request is Acknowledged When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt is Acknowledged. Table 12.5 IPL Value When Software or Special Interrupt is Acknowledged Value Set in IPL 7 No change Interrupt Source without Interrupt Priority Level Watchdog timer, oscillation stop detection, voltage monitor 1/comparator A1, voltage monitor 2/comparator A2, address break Software, address match, single-step REJ09B0441-0010 Rev.0.10 Page 179 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.3.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved on the stack, the 16 low-order bits in the PC are saved. Figure 12.5 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers should be saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used (1) with a single instruction. Note: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB. Address MSB Stack LSB Address MSB Stack LSB m−4 m−3 m−2 m−1 m m−4 m−3 m−2 m−1 PCL PCM FLGL FLGH PCH [SP] New SP value (1) Previous stack contents Previous stack contents [SP] SP value before interrupt request acknowledgement (1) m Previous stack contents Previous stack contents m+1 m+1 PCL PCM PCH FLGL FLGH : 8 low-order bits of PC : 8 middle-order bits of PC : 4 high-order bits of PC : 8 low-order bits of FLG : 4 high-order bits of FLG Stack state before interrupt request acknowledgement Stack state after interrupt request acknowledgement Note: 1. When an INT instruction for software numbers 32 to 63 has been executed, this SP is indicated by the U flag. Otherwise it is ISP. Figure 12.5 Stack State Before and After Acknowledgement of Interrupt Request REJ09B0441-0010 Rev.0.10 Page 180 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 12.6 shows the Register Saving Operation. Address Stack Saving sequence [SP]−5 [SP]−4 [SP]−3 [SP]−2 [SP]−1 PCL PCM FLGL FLGH PCH (3) (4) Saved, 8 bits at a time (1) (2) [SP] Completed saving registers in four operations PCL PCM PCH FLGL FLGH : 8 low-order bits of PC : 8 middle-order bits of PC : 4 high-order bits of PC : 8 low-order bits of FLG : 4 high-order bits of FLG Note: 1. [SP] indicates the SP initial value when an interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. When an INT instruction for software numbers 32 to 63 has been executed, this SP is indicated by the U flag. Otherwise it is ISP. Figure 12.6 Register Saving Operation REJ09B0441-0010 Rev.0.10 Page 181 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.3.8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved on the stack, are automatically restored. The program, that was running before the interrupt request was acknowledged, starts running again. Registers saved by a program in an interrupt routine should be saved using the POPM instruction or a similar instruction before executing the REIT instruction. 12.3.9 Interrupt Priority If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. Set bits ILVL2 to ILVL0 to select any priority level for maskable interrupts (peripheral function). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the higher priority interrupts acknowledged. The priority of the watchdog timer and other special interrupts is set by hardware. Figure 12.7 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. When an instruction is executed, the MCU executes the interrupt routine. Reset Address break Watchdog timer Oscillation stop detection Voltage monitor 1/comparator A1 Voltage monitor 2/comparator A2 Peripheral function Single step Address match High Low Figure 12.7 Hardware Interrupt Priority REJ09B0441-0010 Rev.0.10 Page 182 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.3.10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 12.8 shows the Interrupt Priority Level Selection Circuit. Level 0 (initial value) Priority level of interrupts Voltage monitor 1 / comparator A1 Priority level of interrupts Highest Timer RC UART2 bus collision detection INT5 UART1 reception INT7 Voltage monitor 2 / comparator A2 UART0 reception Timer RG A/D conversion INT2 UART2 reception/ACK2 INT3 Timer RE Timer RB Timer RD0 Timer RA UART1 transmission INT6 UART0 transmission INT0 SSU / I2C bus (1) INT1 Key input INT4 UART2 transmission/ NACK2 Flash memory ready Timer RD1 IPL Lowest Interrupt request level select output signal Interrupt request acknowledgement Peripheral function interrupt priority (if priority levels are same) I flag Address match Watchdog timer Oscillation stop detection Voltage monitor 1 / comparator A1 Voltage monitor 2 / comparator A2 Note: 1. Selectable by the IICSEL bit in the SSUIICSR register. Figure 12.8 Interrupt Priority Level Selection Circuit REJ09B0441-0010 Rev.0.10 Page 183 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.4 12.4.1 INT Interrupt INTi Interrupt (i = 0 to 7) The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register is to 1 (enabled). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. The input pin used as the INTi input can be selected. Also, inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the pulse output forced cutoff input of timer RC and timer RD, and the external trigger input of timer RB. Table 12.6 lists the Pin Configuration of INT Interrupt. Table 12.6 Pin Configuration of INT Interrupt Pin Name INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Assigned Pin P3_0 or P11_0 P3_1 or P11_1 P3_2 or P11_2 P3_3 or P11_3 P3_4 or P11_4 P3_5 or P11_5 P3_6 or P11_6 P3_7 or P11_7 I/O Input Input Input Input Input Input Input Input Function INT0 interrupt input, timer RB external trigger input, timer RC and timer RD pulse output forced cutoff input INT1 interrupt input INT2 interrupt input INT3 interrupt input INT4 interrupt input INT5 interrupt input INT6 interrupt input INT7 interrupt input REJ09B0441-0010 Rev.0.10 Page 184 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.4.2 INT Interrupt Input Pin Select Register (INTSR) Address 018Eh Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol INT7SEL0 INT6SEL0 INT5SEL0 INT4SEL0 INT3SEL0 INT2SEL0 INT1SEL0 INT0SEL0 After Reset 0 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name 0: P3_0 assigned 1: P11_0 assigned 0: P3_1 assigned 1: P11_1 assigned 0: P3_2 assigned 1: P11_2 assigned 0: P3_3 assigned 1: P11_3 assigned 0: P3_4 assigned 1: P11_4 assigned 0: P3_5 assigned 1: P11_5 assigned 0: P3_6 assigned 1: P11_6 assigned 0: P3_7 assigned 1: P11_7 assigned Function R/W R/W R/W R/W R/W R/W R/W R/W R/W INT0SEL0 INT0 pin select bit INT1SEL0 INT1 pin select bit INT2SEL0 INT2 pin select bit INT3SEL0 INT3 pin select bit INT4SEL0 INT4 pin select bit INT5SEL0 INT5 pin select bit INT6SEL0 INT6 pin select bit INT7SEL0 INT7 pin select bit The INTSR register selects which pin is assigned as the INTi (i = 1 to 7) input. To use the INTi, set this register. Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this register during INTi operation. REJ09B0441-0010 Rev.0.10 Page 185 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.4.3 External Input Enable Register 0 (INTEN) b6 INT3EN 0 b5 INT2PL 0 b4 INT2EN 0 b3 INT1PL 0 b2 INT1EN 0 b1 INT0PL 0 Function 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges b0 INT0EN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 01FAh Bit b7 Symbol INT3PL After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name INT0EN INT0 input enable bit INT0PL INT0 input polarity select bit (1, 2) INT1EN INT1 input enable bit INT1PL INT1 input polarity select bit (1, 2) INT2EN INT2 input enable bit INT2PL INT2 input polarity select bit (1, 2) INT3EN INT3 input enable bit INT3PL INT3 input polarity select bit (1, 2) Notes: 1. To set the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 12.8.4 Changing Interrupt Sources. REJ09B0441-0010 Rev.0.10 Page 186 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.4.4 External Input Enable Register 1 (INTEN1) b6 IN7EN 0 b5 INT6PL 0 b4 INT6EN 0 b3 INT5PL 0 b2 INT5EN 0 b1 INT4PL 0 Function 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges b0 INT4EN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 01FBh Bit b7 Symbol INT7PL After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name INT4EN INT4 input enable bit INT4PL INT4 input polarity select bit (1, 2) INT5EN INT5 input enable bit INT5PL INT5 input polarity select bit (1, 2) INT6EN INT6 input enable bit INT6PL INT6 input polarity select bit (1, 2) IN7EN INT7 input enable bit INT7PL INT7 input polarity select bit (1, 2) Notes: 1. To set the INTiPL bit (i = 4 to 7) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 12.8.4 Changing Interrupt Sources. REJ09B0441-0010 Rev.0.10 Page 187 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.4.5 INT Input Filter Select Register 0 (INTF) b6 INT3F0 0 b5 INT2F1 0 b4 INT2F0 0 b3 INT1F1 0 b2 INT1F0 0 b1 INT0F1 0 Function b1 b0 Address 01FCh Bit b7 Symbol INT3F1 After Reset 0 Bit b0 b1 b0 INT0F0 0 R/W R/W R/W Symbol Bit Name INT0F0 INT0 input filter select bit INT0F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b3 b2 b2 b3 INT1F0 INT1 input filter select bit INT1F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b5 b4 R/W R/W b4 b5 INT2F0 INT2 input filter select bit INT2F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b7 b6 R/W R/W b6 b7 INT3F0 INT3 input filter select bit INT3F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W R/W 12.4.6 INT Input Filter Select Register 1 (INTF1) b6 INT7F0 0 b5 INT6F1 0 b4 INT6F0 0 b3 INT5F1 0 b2 INT5F0 0 b1 INT4F1 0 Function b1 b0 Address 01FDh Bit b7 Symbol INT7F1 After Reset 0 Bit b0 b1 b0 INT4F0 0 R/W R/W R/W Symbol Bit Name INT4F0 INT4 input filter select bit INT4F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b3 b2 b2 b3 INT5F0 INT5 input filter select bit INT5F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b5 b4 R/W R/W b4 b5 INT6F0 INT6 input filter select bit INT6F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b7 b6 R/W R/W b6 b7 INT7F0 INT7 input filter select bit INT7F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W R/W REJ09B0441-0010 Rev.0.10 Page 188 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.4.7 INTi Input Filter (i = 0 to 7) The INTi input contains a digital filter. The sampling clock is selected using bits INTiF0 and INTiF1 in the INTF register. The INTi level is sampled every sampling clock cycle and if the sampled input level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested). Figure 12.9 shows the INTi Input Filter Configuration. Figure 12.10 shows an Operating Example of INTi Input Filter. INTiF1 to INTiF0 f1 f8 f32 = 01b = 10b = 11b Sampling clock INTiEN INTiF1 to INTiF0 = other than 00b INTi Digital filter (matches 3 times) INTi interrupt INTiPL = 0 = 00b Both-edge detection INTiPL = 1 circuit i = 0 to 7 INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register Figure 12.9 INTi Input Filter Configuration INTi input Sampling timing IR bit in INTiIC register Set to 0 by a program. Note: 1. This is an operating example when bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter enabled). i = 0 to 7 Figure 12.10 Operating Example of INTi Input Filter REJ09B0441-0010 Rev.0.10 Page 189 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.5 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K17. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN bit (i = 0 to 7) in the KIEN register is be used to select whether or not the pins are used as the KIi input. The KIiPL bit in the KIEN register is also be used to select the input polarity. When inputting a low signal to the KIi pin, which sets the KIiPL bit to 0 (falling edge), the input to the other pins K10 to K17 is not detected as interrupts. When inputting a high signal to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the input to the other pins K10 to K17 is also not detected as interrupts. Figure 12.11 shows a Block Diagram of Key Input Interrupt. Table 12.7 lists the Key Input Interrupt Pin Configuration. Pull-up control register value for the corresponding port Pull-up transistor KUPIC register Direction register value for the corresponding port KI7PL = 0 KI7 KI7PL = 1 Pull-up transistor KI6PL = 0 KI6 KI6PL = 1 Pull-up transistor KI5PL = 0 KI5 KI5PL = 1 Pull-up transistor KI4PL = 0 KI4 KI4PL = 1 Pull-up transistor KI3PL = 0 KI3 KI3PL = 1 Pull-up transistor KI2PL = 0 KI2 KI2PL = 1 Pull-up transistor KI1PL = 0 KI1 KI1PL = 1 Pull-up transistor KI0PL = 0 KI0 KI0PL = 1 KI7EN bit KI6EN bit Interrupt control circuit Key input interrupt request KI5EN bit KI4EN bit KI3EN bit KI2EN bit KI1EN bit KI0EN bit i = 0 to 7 KIiEN, KIiPL: Bits in KIEN or KIEN1 register Figure 12.11 Block Diagram of Key Input Interrupt REJ09B0441-0010 Rev.0.10 Page 190 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts Table 12.7 Key Input Interrupt Pin Configuration Pin Name KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 I/O Input Input Input Input Input Input Input Input Function KI0 interrupt input KI1 interrupt input KI2 interrupt input KI3 interrupt input KI4 interrupt input KI5 interrupt input KI6 interrupt input KI7 interrupt input REJ09B0441-0010 Rev.0.10 Page 191 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.5.1 Key Input Pin Select Register (KISR) b6 KI6SEL0 0 b5 KISEL0 0 b4 KI4SEL0 0 b3 KI3SEL0 0 b2 KI2SEL0 0 b1 KI1SEL0 0 b0 KI0SEL0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 018Dh Bit b7 Symbol KI7SEL0 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name KI0SEL0 KI0 pin select bit KI1SEL0 KI1 pin select bit KI2SEL0 KI2 pin select bit KI3SEL0 KI3 pin select bit KI4SEL0 KI4 pin select bit KI5SEL0 KI5 pin select bit KI6SEL0 KI6 pin select bit KI7SEL0 KI7 pin select bit Function 0: P2_0 assigned 1: P10_0 assigned 0: P2_1 assigned 1: P10_1 assigned 0: P2_2 assigned 1: P10_2 assigned 0: P2_3 assigned 1: P10_3 assigned 0: P2_4 assigned 1: P10_4 assigned 0: P2_5 assigned 1: P10_5 assigned 0: P2_6 assigned 1: P10_6 assigned 0: P2_7 assigned 1: P10_7 assigned The KISR register selects which pin is assigned as the KIi (i = 1 to 7) input. To use the KIi, set this register. Set the KISR register before setting the KIi associated registers. Also, do not change the setting values in this register during KIi operation. REJ09B0441-0010 Rev.0.10 Page 192 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.5.2 Key Input Enable Register 0 (KIEN) b6 KI3EN 0 b5 KI2PL 0 b4 KI2EN 0 b3 KI1PL 0 b2 KI1EN 0 b1 KI0PL 0 Function 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge b0 KI0EN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 01FEh Bit b7 Symbol KI3PL After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name KI0EN KI0 input enable bit KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL KI0 input polarity select bit KI1 input enable bit KI1 input polarity select bit KI2 input enable bit KI2 input polarity select bit KI3 input enable bit KI3 input polarity select bit The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN register is rewritten. Refer to 12.8.4 Changing Interrupt Sources. REJ09B0441-0010 Rev.0.10 Page 193 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.5.3 Key Input Enable Register 1 (KIEN1) b6 KI7EN 0 b5 KI6PL 0 b4 KI6EN 0 b3 KI5PL 0 b2 KI5EN 0 b1 KI4PL 0 Function 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge 0: Disabled 1: Enabled 0: Falling edge 1: Rising edge b0 KI4EN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 01FFh Bit b7 Symbol KI7PL After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name KI4EN KI4 input enable bit KI4PL KI5EN KI5PL KI6EN KI6PL KI7EN KI7PL KI4 input polarity select bit KI5 input enable bit KI5 input polarity select bit KI6 input enable bit KI6 input polarity select bit KI7 input enable bit KI7 input polarity select bit The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN1 register is rewritten. Refer to 12.8.4 Changing Interrupt Sources. REJ09B0441-0010 Rev.0.10 Page 194 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.6 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi (i = 0 or 1) register. This interrupt is used as a break function by the debugger. When the on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1, and fixed vector tables) in the user system. Set the starting address of any instruction in the RMADi (i = 0 or 1) register. The AIERi bit in the AIERi register can be used to select the interrupt enabled or disabled. The address match interrupt is not affected by the I flag and IPL. The PC value (refer to 12.3.7 Saving Registers) which is saved on the stack when an address match interrupt request is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match interrupt, follow one of the following means: • Rewrite the contents of the stack and use the REIT instruction to return. • Use an instruction such as POP to restore the stack to its previous state before the interrupt request was acknowledged. Then use a jump instruction to return. Table 12.8 lists the PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged. Table 12.8 PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged Address Indicated by RMADi Register (i = 0 or 1) • Instruction with 2-byte operation code (2) • Instruction with 1-byte operation code (2) ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest STNZ #IMM8,dest STZX #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (however, dest = A0 or A1) • Instructions other than listed above PC Value Saved (1) Address indicated by RMADi register + 2 Address indicated by RMADi register + 1 Notes: 1. Refer to the 12.3.7 Saving Registers. 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 12.9 Correspondence Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1 REJ09B0441-0010 Rev.0.10 Page 195 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1) b4 — 0 — 0 b3 — 0 — 0 b2 — 0 — 0 b1 — 0 — 0 b0 AIER0 0 AIER1 0 Address 01C3h (AIER0), 01C7h (AIER1) Bit b7 b6 b5 Symbol — — — After Reset 0 0 0 Symbol After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 — 0 — 0 — 0 AIER0 register AIER1 register Symbol Bit Name AIERi Address match interrupt i enable bit — — — — — — — Function 0: Disabled 1: Enabled Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W — 12.6.2 Address Match Interrupt Register i (RMADi) (i = 0 or 1) b2 — X b10 — X b18 — X b1 — X b9 — X b17 — X b0 — X b8 — X b16 — X R/W R/W — Address 01C2h to 01C0h (RMAD0), 01C6h to 01C4h (RMAD1) Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Symbol After Reset Bit Symbol After Reset b15 — X b23 — 0 b14 — X b22 — 0 b13 — X b21 — 0 b12 — X b20 — 0 b11 — X b19 — X Bit Symbol Function Setting Range b19 to b0 — Address setting register for address match interrupt 00000h to FFFFFh b20 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b21 — b22 — b23 — REJ09B0441-0010 Rev.0.10 Page 196 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources) The interrupts of timer RC, timer RD (timer RD0) interrupt, timer RD (timer RD1), timer RG, the synchronous serial communication unit, the I2C bus interface, and the flash memory each have multiple interrupt request sources. An interrupt request is generated by the logical OR of several interrupt request sources and is reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these peripheral functions has its own interrupt request source status register (status register) and interrupt request source enable register (enable register) to control the generation of interrupt requests (change of the IR bit in the interrupt control register). Table 12.10 lists the Registers Associated with Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory and Figure 12.12 shows a Block Diagram of Timer RD Interrupt. Table 12.10 Registers Associated with Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory Status Register of Interrupt Request Source TRCSR TRDSR0 TRDSR1 TRGSR SSSR Peripheral Function Name Timer RC Timer RD Timer RD0 Timer RD1 Timer RG Synchronous serial communication unit I2C bus interface Flash memory Enable Register of Interrupt Request Source TRCIER TRDIER0 TRDIER1 TRGIER SSER ICIER RDYSTIE BSYAEIE CMDERIE Interrupt Control Register TRCIC TRD0IC TRD1IC TRGIC SSUIC IICIC FMRDYIC ICSR RDYSTI BSYAEI Timer RD i IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit Timer RD i interrupt request (IR bit in TRDiIC register) i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register Figure 12.12 Block Diagram of Timer RD Interrupt REJ09B0441-0010 Rev.0.10 Page 197 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts As with other maskable interrupts, the interrupts of timer RC, timer RD (timer RD0), timer RD (timer RD1), timer RG, the synchronous serial communication unit, the I2C bus interface, and the flash memory are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply: • When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested). • When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR bit is set to 0 (no interrupt requested). That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be retained. Also, the IR bit is not set to 0 even if 0 is written to this bit. • Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged. The IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the status register to 0. • When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set to 1, the IR bit remains 1. • When multiple bits in the enable register are set to 1, use the status register to determine which request source causes an interrupt. Refer to chapters of the individual peripheral functions (20. Timer RC, 21. Timer RD, 23. Timer RG, 27. Synchronous Serial Communication Unit (SSU), 28. I2C bus Interface, and 35. Flash Memory) for the status register and enable register. For the interrupt control register, refer to 12.3 Interrupt Control. REJ09B0441-0010 Rev.0.10 Page 198 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.8 12.8.1 Notes on Interrupts Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the IR bit for the acknowledged interrupt is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated. 12.8.2 SP Setting Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is acknowledged before setting a value in the SP, the program may run out of control. 12.8.3 External Interrupt, Key Input Interrupt Either the low-level width or high-level width shown in the Electrical Characteristics is required for the signal input to pins INT0 to INT7 and pins KI0 to KI7, regardless of the CPU clock. For details, refer to Table 36.XX (VCC = 5 V), Table 36.XX (VCC = 3 V), Table 36.XX (VCC = 1.8 V) External Interrupt INTi (i = 0 to 7) Input, Key Input Interrupt KIi (i = 0 to 7). REJ09B0441-0010 Rev.0.10 Page 199 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.8.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources. Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of the interrupt assigned to a software interrupt number. Therefore, if a mode change of a peripheral function involves the source, polarity, or timing of an interrupt, set the IR bit to 0 (no interrupt requested) after making these changes. Refer to the descriptions of the individual peripheral functions for related interrupts. Figure 12.13 shows a Procedure Example for Changing Interrupt Sources. Interrupt source change Disable interrupts (2, 3) Change interrupt sources (including the mode of peripheral functions) Set the IR bit to 0 (no interrupt request) using the MOV instruction (3) Enable interrupts (2, 3) Change completed IR bit: Bit in the interrupt control register bit for the interrupt whose source is to be changed Notes: 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt whose source is to be changed. 3. Refer to 12.8.5 Rewriting Interrupt Control Register for the instructions to use and related notes. Figure 12.13 Procedure Example for Changing Interrupt Sources REJ09B0441-0010 Rev.0.10 Page 200 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 12. Interrupts 12.8.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that register are generated. If an interrupt request may be generated, disable the interrupt before rewriting the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling the interrupt, be careful to choose appropriate instructions. Changing any bit other than the IR bit If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET. Changing the IR bit Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested). Use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to (b) regarding rewriting the contents of interrupt control registers using the sample programs. Examples 1 to 3 shows how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer. Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use the POPC instruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h POPC FLG ; Enable interrupts REJ09B0441-0010 Rev.0.10 Page 201 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 13. ID Code Areas 13. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode. This function prevents the flash memory from being read, rewritten, or erased. 13.1 Introduction The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the respective vector highest-order addresses of the fixed vector table. Figure 13.1 shows the ID Code Areas. ID code areas Address 0FFDFh to 0FFDCh 0FFE3h to 0FFE0h 0FFE7h to 0FFE4h 0FFEBh to 0FFE8h 0FFEFh to 0FFECh 0FFF3h to 0FFF0h 0FFF7h to 0FFF4h 0FFFBh to 0FFF8h 0FFFFh to 0FFFCh ID3 ID4 ID5 ID6 ID7 OFS ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2 Address break vector (Reserved) Reset vector 4 bytes Figure 13.1 ID Code Areas REJ09B0441-0010 Rev.0.10 Page 202 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 13. ID Code Areas 13.2 Functions The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the commands sent from the serial programmer or the on-chip debugging emulator are acknowledged. If the ID codes do not match, the commands are not acknowledged. To use the serial programmer or the on-chip debugging emulator, first write predetermined ID codes to the ID code areas. If 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes are not checked and all commands are accepted. As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The character sequence of the ASCII codes “ALeRASE” is the reserved word used for the forced erase function. The character sequence of the ASCII codes “Protect” is the reserved word used for the standard serial I/O mode disabled function. Table 13.1 shows the ID Code Reserved Word. The reserved word is a set of reserved characters when all the addresses and data in the ID code storage addresses sequentially match Table 13.1. When the forced erase function or standard serial I/O mode disabled function is not used, use another character sequence of the ASCII codes. Table 13.1 ID Code Reserved Word ID Code Storage Address 0FFDFh 0FFE3h 0FFEBh 0FFEFh 0FFF3h 0FFF7h 0FFFBh ID1 ID2 ID3 ID4 ID5 ID6 ID7 lD Code Reserved Word (ASCII) (1) ALeRASE Protect 41h (upper-case “A”) 50h (upper-case “P”) 4Ch (upper-case “L”) 72h (lower-case “r”) 65h (lower-case “e”) 6Fh (lower-case “o”) 52h (upper-case “R”) 74h (lower-case “t”) 41h (upper-case “A”) 65h (lower-case “e”) 53h (upper-case “S”) 63h (lower-case “c”) 45h (upper-case “E”) 74h (lower-case “t”) Note: 1. Reserve word: A set of characters when all the addresses and data in the ID code storage addresses sequentially match Table 13.1. REJ09B0441-0010 Rev.0.10 Page 203 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 13. ID Code Areas 13.3 Forced Erase Function This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the onchip debugging emulator are “ALeRASE” in ASCII code, the content of the user ROM area will be erased at once. However, if the contents of the ID code addresses are set to other than “ALeRASE” (other than Table 13.1 ID Code Reserved Word) when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), forced erasure is not executed and the ID codes are checked with the ID code check function. Table 13.2 lists the Conditions and Operations of Forced Erase Function. When the contents of the ID code addresses are set to “ALeRASE” in ASCII code, if the ID codes sent from the serial programmer or the on-chip debugging emulator are “ALeRASE”, the content of the user ROM area will be erased. If the ID codes sent from the serial programmer are other than “ALeRASE”, the ID codes do not match and no command is acknowledged, thus the user ROM area remains protected. Table 13.2 Conditions and Operations of Forced Erase Function Condition ID code from serial programmer or on-chip debugging emulator ALeRASE ID code in ID code storage address ALeRASE Other than ALeRASE (1) Bits ROMCP1 and ROMCR in OFS register – Other than 01b (ROM code protect disabled) 01b (ROM code protect enabled) – Operation All erasure of user ROM area (forced erase function) Other than ALeRASE ALeRASE Other than ALeRASE (1) – ID code check (ID code check function) ID code check (ID code check function. No ID code match) ID code check (ID code check function) Note: 1. For “Protect”, refer to 13.4 Standard Serial I/O Mode Disabled Function. 13.4 Standard Serial I/O Mode Disabled Function This function is used in standard serial I/O mode. When the I/D codes in the ID code storage addresses are set to the reserved character sequence of the ASCII codes “Protect” (refer to Table 13.1 ID Code Reserved Word), communication with the serial programmer or the on-chip debugging emulator is not performed. This does not allow the flash memory to be read, rewritten, or erased using the serial programmer or the on-chip debugging emulator. Also, if the ID codes are also set to the reserved character sequence of the ASCII codes “Protect” when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), ROM code protection cannot be disabled using the serial programmer or the on-chip debugging emulator. This prevents the flash memory from being read, rewritten, or erased using the serial programmer, the on-chip debugging emulator, or the parallel programmer. REJ09B0441-0010 Rev.0.10 Page 204 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 13. ID Code Areas 13.5 13.5.1 Notes on ID Code Areas Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.) REJ09B0441-0010 Rev.0.10 Page 205 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 14. Option Function Select Area 14. Option Function Select Area 14.1 Introduction The option function select area is used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation. The reset vector highest-order-addresses, 0FFFFh and 0FFDBh, are assigned as the option function select area. Figure 14.1 shows the Option Function Select Area. Option function select area Address 0FFDBh to 0FFD8h OFS2 Reserved area 0FFFFh to 0FFFCh OFS Reset vector 4 bytes Figure 14.1 Option Function Select Area REJ09B0441-0010 Rev.0.10 Page 206 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 14. Option Function Select Area 14.2 Registers Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation. 14.2.1 Option Function Select Register (OFS) b6 LVDAS 1 b5 b4 b3 b2 VDSEL1 VDSEL0 ROMCP1 ROMCR 1 1 1 1 b1 — 1 b0 WDTON 1 (Note 1) R/W R/W R/W R/W R/W Address 0FFFFh Bit b7 Symbol CSPROINI When shipping 1 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name WDTON Watchdog timer start select bit — Reserved bit ROMCR ROM code protect disable bit ROMCP1 ROM code protect bit VDSEL0 Voltage detection 0 level select bit (2) VDSEL1 Function 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset Set to 1. 0: ROM code protect disabled 1: ROMCP1 bit enabled 0: ROM code protect enabled 1: ROM code protect disabled b5 b4 b6 b7 LVDAS Voltage detection 0 circuit start bit (3) CSPROINI Count source protection mode after reset select bit R/W 0 0: 3.80 V selected (Vdet0_3) R/W 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) 0: Voltage monitor 0 reset enabled after reset R/W 1: Voltage monitor 0 reset disabled after reset 0: Count source protection mode enabled after reset R/W 1: Count source protection mode disabled after reset Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. REJ09B0441-0010 Rev.0.10 Page 207 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 14. Option Function Select Area 14.2.2 Option Function Select Register 2 (OFS2) b6 — 1 b5 — 1 b4 — 1 b3 b2 b1 b0 WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 1 1 1 1 (Note 1) Function b1 b0 Address 0FFDBh Bit b7 Symbol — When shipping 1 Bit b0 b1 Symbol Bit Name WDTUFS0 Watchdog timer underflow period set bit WDTUFS1 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh b3 b2 R/W R/W R/W b2 b3 WDTRCS0 Watchdog timer refresh acknowledgement period WDTRCS1 set bit b4 b5 b6 b7 — — — — Reserved bits 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% Set to 1. R/W R/W R/W Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 15.3.1.1 Refresh Acknowledgment Period. REJ09B0441-0010 Rev.0.10 Page 208 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 14. Option Function Select Area 14.3 14.3.1 Notes on Option Function Select Area Setting Example of Option Function Select Area As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.) REJ09B0441-0010 Rev.0.10 Page 209 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. 15.1 Introduction The watchdog timer contains a 14-bit counter and allows selection of count source protection mode enable or disable. Table 15.1 lists the Watchdog Timer Specifications. Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset. Figure 15.1 shows the Watchdog Timer Block Diagram. Table 15.1 Watchdog Timer Specifications Item Count source Count operation Count start condition Count Source Protection Mode Disabled CPU clock Count Source Protection Mode Enabled Low-speed on-chip oscillator clock for the watchdog timer Count stop condition Watchdog timer initialization conditions Operations at underflow Selectable functions Decrement Either of the following can be selected: • After a reset, count starts automatically. • Count starts by writing to the WDTS register. Stop mode, wait mode None • Reset • Write 00h and then FFh to the WDTR register (with acknowledgement period setting). • Underflow Watchdog timer interrupt Watchdog timer reset or watchdog timer reset • Division ratio of the prescaler Selectable by the WDTC7 bit in the WDTC register or the CM07 bit in the CM0 register. • Count source protection mode Whether count source protection mode is enabled or disabled after a reset can be selected by the CSPROINI bit in the OFS register (flash memory). If count source protection mode is disabled after a reset, it can be enabled or disabled by the CSPRO bit in the CSPR register (program). • Start or stop of the watchdog timer after a reset Selectable by the WDTON bit in the OFS register (flash memory). • Initial value of the watchdog timer Selectable by bits WDTUFS0 and WDTUFS1 in the OFS2 register. • Refresh acknowledgement period for the watchdog timer Selectable by bits WDTRCS0 and WDTRCS1 in the OFS2 register. REJ09B0441-0010 Rev.0.10 Page 210 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer Prescaler 1/16 CPU clock 1/128 1/2 CM07 = 0, WDC7 = 0 CSPRO = 0 CM07 = 0, WDC7 = 1 CM07 = 1 CSPRO = 1 PM12 = 0 Watchdog timer interrupt request Watchdog timer (Note 1) PM12 = 1 Watchdog timer reset Low-speed on-chip oscillator for watchdog timer Oscillation starts when CSPRO = 1 Internal reset signal (Low active) Bits WDTRCS0 and WDTRCS1 Write to WDTR register Refresh period control circuit CSPRO: Bit in CSPR register WDTC7: Bit in WDTC register PM12: Bit in PM1 register CM07: Bit in CM0 register WDTUFS0, WDTUFS1, WDTRCS0, WDTRCS1: Bits in OFS2 register Note: 1. A value set by bits WDTUFS0 and WDTUFS1 is set in the watchdog timer (value when shipping: 3FFFh). Figure 15.1 Watchdog Timer Block Diagram REJ09B0441-0010 Rev.0.10 Page 211 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.2 15.2.1 Registers Processor Mode Register 1 (PM1) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 PM12 0 b1 — 0 Function Set to 0. b0 — 0 R/W R/W R/W — Address 0005h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name — Reserved bits — PM12 WDT interrupt/reset switch bit — — — — — 0: Watchdog timer interrupt 1: Watchdog timer reset (1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bit Set to 0. R/W Note: 1. The PM12 bit is set to 1 when 1 is written by a program (and remains unchanged even if 0 is written to it). This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled). Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register. 15.2.2 Watchdog Timer Reset Register (WDTR) b6 — X b5 — X b4 — X b3 — X b2 — X b1 — X b0 — X R/W W Address 000Dh Bit b7 Symbol — After Reset X Bit Function b7 to b0 Writing 00h and then FFh into this register initializes the watchdog timer. The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2 register. (1) Note: 1. Write the WDTR register during the count operation of the watchdog timer. 15.2.3 Watchdog Timer Start Register (WDTS) b6 — X b5 — X b4 — X b3 — X b2 — X b1 — X b0 — X R/W W Address 000Eh Bit b7 Symbol — After Reset X Bit Function b7 to b0 A write instruction to this register starts the watchdog timer. REJ09B0441-0010 Rev.0.10 Page 212 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.2.4 Watchdog Timer Control Register (WDTC) b6 — 0 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W R R R R R R R R/W Address 000Fh Bit b7 Symbol WDTC7 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol — — — — — — — WDTC7 Bit Name Function The following bits of the watchdog timer can be read. When bits WDTUFS1 to WDTUFS0 in the OFS2 register are 00b (03FFh): b5 to b0 01b (0FFFh): b8 to b3 10b (1FFFh): b9 to b4 11b (3FFFh): b10 to b5 Reserved bit Prescaler select bit When read, the content is 0. 0: Divide-by-16 1: Divide-by-128 15.2.5 Count Source Protection Mode Register (CSPR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 — 0 Address 001Ch Bit b7 Symbol CSPRO After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 (Note 1) R/W R/W Symbol Bit Name Function — Reserved bits Set to 0. — — — — — — CSPRO Count source protection mode select bit (2) 0: Count source protection mode disabled 1: Count source protection mode enabled R/W Notes: 1. When 0 is written to the CSPROINI bit in the OFS register, the value after reset is 10000000b. 2. To set the CSPRO bit to 1, write 0 and then 1 to it. This bit cannot be set to 0 by a program. REJ09B0441-0010 Rev.0.10 Page 213 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.2.6 Option Function Select Register (OFS) b6 LVDAS 1 b5 b4 b3 b2 VDSEL1 VDSEL0 ROMCP1 ROMCR 1 1 1 1 b1 — 1 b0 WDTON 1 (Note 1) R/W R/W R/W R/W R/W Address 0FFFFh Bit b7 Symbol CSPROINI When shipping 1 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name WDTON Watchdog timer start select bit — Reserved bit ROMCR ROM code protect disable bit ROMCP1 ROM code protect bit VDSEL0 Voltage detection 0 level select bit (2) VDSEL1 Function 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset Set to 1. 0: ROM code protect disabled 1: ROMCP1 bit enabled 0: ROM code protect enabled 1: ROM code protect disabled b5 b4 b6 b7 LVDAS Voltage detection 0 circuit start bit (3) CSPROINI Count source protection mode after reset select bit R/W 0 0: 3.80 V selected (Vdet0_3) R/W 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) 0: Voltage monitor 0 reset enabled after reset R/W 1: Voltage monitor 0 reset disabled after reset 0: Count source protection mode enabled after reset R/W 1: Count source protection mode disabled after reset Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. REJ09B0441-0010 Rev.0.10 Page 214 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.2.7 Option Function Select Register 2 (OFS2) b6 — 1 b5 — 1 b4 — 1 b3 b2 b1 b0 WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 1 1 1 1 (Note 1) Function b1 b0 Address 0FFDBh Bit b7 Symbol — When shipping 1 Bit b0 b1 Symbol Bit Name WDTUFS0 Watchdog timer underflow period set bit WDTUFS1 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh b3 b2 R/W R/W R/W b2 b3 WDTRCS0 Watchdog timer refresh acknowledgement period WDTRCS1 set bit b4 b5 b6 b7 — — — — Reserved bits 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% Set to 1. R/W R/W R/W Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 15.3.1.1 Refresh Acknowledgment Period. REJ09B0441-0010 Rev.0.10 Page 215 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.3 15.3.1 Functional Description Common Items for Multiple Modes Refresh Acknowledgment Period 15.3.1.1 The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can be selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register. Figure 15.2 shows the Refresh Acknowledgement Period for Watchdog Timer. Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, a refresh operation executed during the refresh acknowledgement period is acknowledged. Any refresh operation executed during the period other than the above is processed as an incorrect write, and a watchdog timer interrupt or watchdog timer reset (selectable by the PM12 bit in the PM1 register) is generated. Do not execute any refresh operation while the count operation of the watchdog timer is stopped. Watchdog timer period Count starts Refresh can be acknowledged Processed as incorrect write (1) Underflow Refresh acknowledge period 100% (WDTRCS1 to WDTRCS0 = 11b) Refresh can be acknowledged 75% (WDTRCS1 to WDTRCS0 = 10b) Processed as incorrect write (1) Refresh can be acknowledged Refresh can be acknowledged 50% (WDTRCS1 to WDTRCS0 = 01b) Processed as incorrect write (1) 25% (WDTRCS1 to WDTRCS0 = 00b) 0% 25% 50% 75% 100% WDTRCS0, WDTRCS1: Bits in OFS2 register Note: 1. A watchdog timer interrupt or watchdog timer reset is generated. Figure 15.2 Refresh Acknowledgement Period for Watchdog Timer REJ09B0441-0010 Rev.0.10 Page 216 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.3.2 Count Source Protection Mode Disabled The count source for the watchdog timer is the CPU clock when count source protection mode is disabled. Table 15.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled). Table 15.2 Watchdog Timer Specifications (Count Source Protection Mode Disabled) Item Count source Count operation Period Specification CPU clock Decrement Division ratio of prescaler (n) × count value of watchdog timer (m) (1) CPU clock n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or 2 when the low-speed clock is selected (CM07 bit in CM0 register = 1) m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register Example: The period is approximately 13.1 ms when: - The CPU clock frequency is set to 20 MHz. - The prescaler is divided by 16. - Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh). • Reset • Write 00h and then FFh to the WDTR register. (3) • Underflow The operation of the watchdog timer after a reset is selected by the WDTON bit (2) in the OFS register (address 0FFFFh). • When the WDTON bit is set to 1 (watchdog timer is stopped after reset). The watchdog timer and prescaler are stopped after a reset and start counting when the WDTS register is written to. • When the WDTON bit is set to 0 (watchdog timer starts automatically after reset). The watchdog timer and prescaler start counting automatically after a reset. Stop mode, wait mode (Count resumes from the retained value after exiting.) • When the PM12 bit in the PM1 register is set to 0. Watchdog timer interrupt • When the PM12 bit in the PM1 register is set to 1. Watchdog timer reset (refer to 5.5 Watchdog Timer Reset) Watchdog timer initialization conditions Count start conditions Count stop condition Operations at underflow Notes: 1. The watchdog timer is initialized when 00h and then FFh is written to the WDTR register. The prescaler is initialized after a reset. This may cause some errors due to the prescaler during the watchdog timer period. 2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 3. Write the WDTR register during the count operation of the watchdog timer. REJ09B0441-0010 Rev.0.10 Page 217 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer 15.3.3 Count Source Protection Mode Enabled The count source for the watchdog timer is the low-speed on-chip oscillator clock for the watchdog timer when count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the watchdog timer. Table 15.3 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled). Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Enabled) Item Count source Count operation Period Watchdog timer initialization conditions Count start conditions Count stop condition Operation at underflow Registers, bits Specification Low-speed on-chip oscillator clock Decrement Count value of watchdog timer (m) Low-speed on-chip oscillator clock for the watchdog timer m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register Example: The period is approximately 8.2 ms when: - The on-chip oscillator clock for the watchdog timer is set to 125 kHz. - Bits WDTUFS1 to WDTUFS0 are set to 00b (03FFh). • Reset • Write 00h and then FFh to the WDTR register. (3) • Underflow The operation of the watchdog timer after a reset is selected by the WDTON bit (1) in the OFS register (address 0FFFFh). • When the WDTON bit is set to 1 (watchdog timer is stopped after reset). The watchdog timer and prescaler are stopped after a reset and start counting when the WDTS register is written to. • When the WDTON bit is set to 0 (watchdog timer starts automatically after reset). The watchdog timer and prescaler start counting automatically after a reset. None (Count does not stop even in wait mode once it starts. The MCU does not enter stop mode.) Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.) • When the CSPPRO bit in the CSPR register is set to 1 (count source protection mode enabled) (2), the following are set automatically: - The low-speed on-chip oscillator for the watchdog timer is on. - The PM12 bit in the PM1 register is set to 1 (watchdog timer reset when the watchdog timer underflows). Notes: 1. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. To set this bit, write 0 to bit 7 of address 0FFFFh with a flash programmer. 3. Write the WDTR register during the count operation of the watchdog timer. REJ09B0441-0010 Rev.0.10 Page 218 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16. DTC The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrupt to perform data transfers. The DTC and CPU use the same bus, and the DTC takes priority over the CPU in using the bus. To control DTC data transfers, control data comprised of a transfer source address, a transfer destination address, and operating modes are allocated in the DTC control data area. Each time the DTC is activated, the DTC reads control data to perform data transfers. 16.1 Overview Table 16.1 lists the DTC Specifications and Figure 16.1 shows DTC Block Diagram. Table 16.1 DTC Specifications Specification 38 sources 24 sets 64 Kbytes (00000h to 0FFFFh) 256 times 255 times 256 bytes 255 bytes Byte Transfers end on completion of the transfer causing the DTCCTj register value to change from 1 to 0. On completion of the transfer causing the DTCCTj register value to change from 1 to 0, the repeat area address is initialized and the DTRLDj register value is reloaded to the DTCCTj register to continue transfers. Fixed or incremented Addresses of the area not selected as the repeat area are fixed or incremented. See Table 16.5 DTC Activation Sources and DTC Vector Addresses. When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed, the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the data transfer. When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the transfer. When bits DTCENi0 to DTCENi7 in the DTCENi registers are 1 (activation enabled), data transfer is started each time the corresponding DTC activation sources are generated. • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled). • When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed. • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled). • When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed while the RPTINT bit is 1 (interrupt generation enabled). Item Activation sources Allocatable control data Address space which can be transferred Maximum number of transfer Normal mode times Repeat mode Maximum size of block to be Normal mode transferred Repeat mode Unit of transfers Transfer mode Normal mode Repeat mode Address control Normal mode Repeat mode Priority of activation sources Interrupt request Normal mode Repeat mode Transfer start Transfer stop Normal mode Repeat mode i = 0 to 6, j = 0 to 23 REJ09B0441-0010 Rev.0.10 Page 219 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC CPU Peripheral interrupt request DTBLS DTCCT DTRLD DTSAR DTCTL Interrupt controller Bus interface Peripheral bus Figure 16.1 DTC Block Diagram 16.2 Registers When the DTC is activated, control data (DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj, j = 0 to 23) allocated in the control data area is read, and then transferred to the control registers (DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR) in the DTC. On completion of the DTC data transfer, the contents of the DTC control registers are written back to the control data area. Each DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR register cannot be directly read or written to. DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj are allocated as control data at addresses from 2C40h to 2CFFh in the DTC control data area, and can be directly accessed. Also, registers DTCTL and DTCENi (i = 0 to 6) can be directly accessed. REJ09B0441-0010 Rev.0.10 Page 220 of 809 Jul 30, 2008 Peripheral functions Peripheral interrupt request DTDAR ROM RAM Internal bus DTCEN0 to DTCEN6 DTC activation request Control circuit DTCCR DTCCR: DTC control register DTBLS: DTC block size register DTCCT: DTC transfer count register DTRLD: DTC transfer count reload register DTSAR: DTC source address register DTDAR: DTC destination address register DTCTL: DTC activation control register DTCEN0 to DTCEN6: DTC activation enable registers 0 to 6 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.2.1 DTC Control Register j (DTCCRj) (j = 0 to 23) b0 MODE X R/W R/W R/W R/W R/W R/W R/W R/W Address See Table 16.4 Control Data Allocation Addresses. Bit b7 b6 b5 b4 b3 b2 b1 Symbol — — RPTINT CHNE DAMOD SAMOD RPTSEL After Reset X X X X X X X Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol MODE Bit Name Transfer mode select bit RPTSEL Repeat area select bit (1) SAMOD Source address control bit (2) DAMOD Destination address control bit (2) CHNE Chain transfer enable bit (3) RPTINT Repeat mode interrupt enable bit (1) — — Reserved bits Function 0: Normal mode 1: Repeat mode 0: Transfer destination is the repeat area. 1: Transfer source is the repeat area. 0: Fixed 1: Incremented 0: Fixed 1: Incremented 0: Chain transfers disabled 1: Chain transfers enabled 0: Interrupt generation disabled 1: Interrupt generation enabled Set to 0. Notes: 1. This bit is valid when the MODE bit is 1 (repeat mode). 2. Settings of bits SAMOD and DAMOD are invalid for the repeat area. 3. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled). 16.2.2 DTC Block Size Register j (DTBLSj) (j = 0 to 23) b2 — X b1 — X b0 — X Setting Range 00h to FFh (1) R/W R/W Address See Table 16.4 Control Data Allocation Addresses. Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit b7 to b0 Function These bits specify the size of the data block to be transferred by one activation. Note: 1. When the DTBLS register is set to 00h, the block size is 256 bytes. REJ09B0441-0010 Rev.0.10 Page 221 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.2.3 DTC Transfer Count Register j (DTCCTj) (j = 0 to 23) b2 — X b1 — X b0 — X Setting Range 00h to FFh (1) R/W R/W Address See Table 16.4 Control Data Allocation Addresses. Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Function b7 to b0 These bits specify the number of times of DTC data transfers. Note: 1. When the DTCCT register is set to 00h, the number of transfer times is 256. Each time the DTC is activated, the DTCCT register is decremented by 1. 16.2.4 DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23) b2 — X b1 — X b0 — X Setting Range 00h to FFh (1) R/W R/W Address See Table 16.4 Control Data Allocation Addresses. Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Function b7 to b0 This register value is reloaded to the DTCCT register in repeat mode. Note: 1. Set the initial value for the DTCCT register. 16.2.5 DTC Source Address Register j (DTSARj) (j = 0 to 23) b2 — X b10 — X b1 — X b9 — X b0 — X b8 — X Setting Range 0000h to FFFFh R/W R/W Address See Table 16.4 Control Data Allocation Addresses. Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Symbol After Reset Bit b15 to b0 b15 — X b14 — X b13 — X b12 — X b11 — X Function These bits specify a transfer source address for data transfer. 16.2.6 DTC Destination Register j (DTDARj) (j = 0 to 23) b2 — X b10 — X b1 — X b9 — X b0 — X b8 — X Setting Range 0000h to FFFFh R/W R/W Address See Table 16.4 Control Data Allocation Addresses. Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Symbol After Reset b15 — X b14 — X b13 — X b12 — X b11 — X Bit Function b15 to b0 These bits specify a transfer destination address for data transfer. REJ09B0441-0010 Rev.0.10 Page 222 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.2.7 DTC Activation Enable Registers i (DTCENi) (i = 0 to 6) Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Ch (DTCEN4), 008Dh (DTCEN5), 008Eh (DTCEN6) Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 DTCENi2 DTCENi1 DTCENi0 After Reset 0 0 0 0 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name DTCENi0 DTC activation enable bit DTCENi1 DTCENi2 DTCENi3 DTCENi4 DTCENi5 DTCENi6 DTCENi7 Function 0: Activation disabled 1: Activation enabled R/W R/W R/W R/W R/W R/W R/W R/W R/W i = 0 to 6 The DTCENi registers enable/disable DTC activation by interrupt sources. Table 16.2 shows Correspondences between Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt Sources. Table 16.2 Correspondences between Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt Sources DTCENi7 Bit INT0 Key input DTCENi6 Bit INT1 A/D conversion DTCENi5 Bit INT2 UART0 reception Comparator A2 Timer RD0 inputcapture/ comparematch A DTCENi4 Bit INT3 UART0 transmission Comparator A1 Timer RD0 inputcapture/ comparematch B DTCENi3 Bit INT4 UART1 reception DTCENi2 Bit INT5 UART1 transmission DTCENi1 Bit INT6 UART2 reception Timer RC inputcapture/ comparematch A Timer RD1 inputcapture/ comparematch A DTCENi0 Bit INT7 UART2 transmission Timer RC inputcapture/ comparematch B Timer RD1 inputcapture/ comparematch B Register DTCEN0 DTCEN1 DTCEN2 SSU/I2C bus SSU/I2C bus receive data transmit full data empty Timer RC inputcapture/ comparematch C Timer RD1 inputcapture/ comparematch C Timer RC inputcapture/ comparematch D Timer RD1 inputcapture/ comparematch D — — DTCEN3 Timer RD0 inputcapture/ comparematch C Timer RD0 inputcapture/ comparematch D DTCEN4 — — — — — — DTCEN5 — — Timer RE — — — — Timer RG inputcapture/ comparematch A DTCEN6 Timer RG inputcapture/ comparematch B Timer RA — Timer RB Flash memory ready status — — — REJ09B0441-0010 Rev.0.10 Page 223 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.2.8 DTC Activation Control Register (DTCTL) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 NMIF 0 b0 — 0 R/W R/W R/W — Address 0080h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol — NMIF — — — — — — Bit Name Function Reserved bit Set to 0. Non-maskable interrupt generation 0: Non-maskable interrupts not generated 1: Non-maskable interrupts generated bit (1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Note: 1. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. The DTCTL register controls DTC activation when a non-maskable interrupt (an interrupt by the watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated. NMIF Bit (Non-Maskable Interrupt Generation Bit) The NMIF bit is set to 1 when a watchdog timer interrupt, an oscillation stop detection interrupt, a voltage monitor 1 interrupt, or a voltage monitor 2 interrupt is generated. When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed. REJ09B0441-0010 Rev.0.10 Page 224 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3 16.3.1 Function Description Overview When the DTC is activated, control data is read from the DTC control data area to perform data transfers and control data after data transfer is written back to the DTC control data area. 24 sets of control data can be stored in the DTC control data area, which allows 24 types of data transfers to be performed. There are two transfer modes: normal mode and repeat mode. When the CHNE bit in the DTCCRj (j = 0 to 23) register is set to 1 (chain transfers enabled), multiple control data is read and data transfers are continuously performed by one activation source (chain transfers). A transfer source address is specified by the 16-bit register DTSARj, and a transfer destination address is specified by the 16-bit register DTDARj. The values in the registers DTSARj and DTDARj are separately fixed or incremented according to the control data on completion of the data transfer. 16.3.2 Activation Sources The DTC is activated by an interrupt source. Figure 16.2 is a Block Diagram Showing Control of DTC Activation Sources. The interrupt sources to activate the DTC are selected with the DTCENi (i = 0 to 6) register. The DTC sets 0 (activation disabled) to the corresponding bit among bits DTCENi0 to DTCENi7 in the DTCENi register during operation when the setting of data transfer (the first transfer in chain transfers) is either of the following: • Transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode • Transfer causing the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode If the data transfer setting is not either of the above and the activation source is an interrupt source for timer RC, timer RD, or the flash memory, the DTC sets 0 to the interrupt source flag corresponding to the activation source during operation. Table 16.3 shows the DTC Activation Sources and Interrupt Source Flags for Setting to 0 during DTC Operation. If multiple activation sources are simultaneously generated, DTC activation will be performed according to the DTC activation source priority. If multiple activation sources are simultaneously generated on completion of DTC operation, the next transfer will be performed according to the priority. DTC activation is not affected by the I flag or interrupt control register, unlike with interrupt request operation. Therefore, even if interrupt requests cannot be acknowledged because interrupts are disabled, DTC activation requests can be acknowledged. The IR bit in the interrupt control register does not change even when an interrupt source to enable DTC activation is generated. Interrupt controller Interrupt request Peripheral interrupt request Select interrupt source or DTC activation source DTC activation request Peripheral function 1 Peripheral function 2 (timer RC, timer RD, flash memory) Peripheral interrupt request DTC Select DTC activation or interrupt generation. DTCENi Set the interrupt source flag in the status register to 0. Set the bit among bits DTCENi0 to DTCENi7 (i = 0 to 6) to 0. Clear control Figure 16.2 Block Diagram Showing Control of DTC Activation Sources REJ09B0441-0010 Rev.0.10 Page 225 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC Table 16.3 DTC Activation Sources and Interrupt Source Flags for Setting to 0 during DTC Operation Interrupt Source Flag for Setting to 0 IMFA bit in TRCSR register IMFB bit in TRCSR register IMFC bit in TRCSR register IMFD bit in TRCSR register IMFA bit in TRDSR0 register IMFB bit in TRDSR0 register IMFC bit in TRDSR0 register IMFD bit in TRDSR0 register IMFA bit in TRDSR1 register IMFB bit in TRDSR1 register IMFC bit in TRDSR1 register IMFD bit in TRDSR1 register RDYSTI bit in FST register DTC activation source generation Timer RC input-capture/compare-match A Timer RC input-capture/compare-match B Timer RC input-capture/compare-match C Timer RC input-capture/compare-match D Timer RD0 input-capture/compare-match A Timer RD0 input-capture/compare-match B Timer RD0 input-capture/compare-match C Timer RD0 input-capture/compare-match D Timer RD1 input-capture/compare-match A Timer RD1 input-capture/compare-match B Timer RD1 input-capture/compare-match C Timer RD1 input-capture/compare-match D Flash memory ready status REJ09B0441-0010 Rev.0.10 Page 226 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.3 Control Data Allocation and DTC Vector Table Control data is allocated in the following order: registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj (j = 0 to 23). Table 16.4 shows the Control Data Allocation Addresses. Table 16.4 Register Symbol DTCD0 DTCD1 DTCD2 DTCD3 DTCD4 DTCD5 DTCD6 DTCD7 DTCD8 DTCD9 DTCD10 DTCD11 DTCD12 DTCD13 DTCD14 DTCD15 DTCD16 DTCD17 DTCD18 DTCD19 DTCD20 DTCD21 DTCD22 DTCD23 j = 0 to 23 Control Data Allocation Addresses Address 2C40h to 2C47h 2C48h to 2C4Fh 2C50h to 2C57h 2C58h to 2C5Fh 2C60h to 2C67h 2C68h to 2C6Fh 2C70h to 2C77h 2C78h to 2C7Fh 2C80h to 2C87h 2C88h to 2C8Fh 2C90h to 2C97h 2C98h to 2C9Fh 2CA0h to 2CA7h 2CA8h to 2CAFh 2CB0h to 2CB7h 2CB8h to 2CBFh 2CC0h to 2CC7h 2CC8h to 2CCFh 2CD0h to 2CD7h 2CD8h to 2CDFh 2CE0h to 2CE7h 2CE8h to 2CEFh 2CF0h to 2CF7h 2CF8h to 2CFFh DTCCRj Register 2C40h 2C48h 2C50h 2C58h 2C60h 2C68h 2C70h 2C78h 2C80h 2C88h 2C90h 2C98h 2CA0h 2CA8h 2CB0h 2CB8h 2CC0h 2CC8h 2CD0h 2CD8h 2CE0h 2CE8h 2CF0h 2CF8h DTBLSj Register 2C41h 2C49h 2C51h 2C59h 2C61h 2C69h 2C71h 2C79h 2C81h 2C89h 2C91h 2C99h 2CA1h 2CA9h 2CB1h 2CB9h 2CC1h 2CC9h 2CD1h 2CD9h 2CE1h 2CE9h 2CF1h 2CF9h DTCCTj Register 2C42h 2C4Ah 2C52h 2C5Ah 2C62h 2C6Ah 2C72h 2C7Ah 2C82h 2C8Ah 2C92h 2C9Ah 2CA2h 2CAAh 2CB2h 2CBAh 2CC2h 2CCAh 2CD2h 2CDAh 2CE2h 2CEAh 2CF2h 2CFAh DTRLDj Register 2C43h 2C4Bh 2C53h 2C5Bh 2C63h 2C6Bh 2C73h 2C7Bh 2C83h 2C8Bh 2C93h 2C9Bh 2CA3h 2CABh 2CB3h 2CBBh 2CC3h 2CCBh 2CD3h 2CDBh 2CE3h 2CEBh 2CF3h 2CFBh DTSARj Register (Lower 8 Bits) 2C44h 2C4Ch 2C54h 2C5Ch 2C64h 2C6Ch 2C74h 2C7Ch 2C84h 2C8Ch 2C94h 2C9Ch 2CA4h 2CACh 2CB4h 2CBCh 2CC4h 2CCCh 2CD4h 2CDCh 2CE4h 2CECh 2CF4h 2CFCh DTSARj Register (Higher 8 Bits) 2C45h 2C4Dh 2C55h 2C5Dh 2C65h 2C6Dh 2C75h 2C7Dh 2C85h 2C8Dh 2C95h 2C9Dh 2CA5h 2CADh 2CB5h 2CBDh 2CC5h 2CCDh 2CD5h 2CDDh 2CE5h 2CEDh 2CF5h 2CFDh DTDARj Register (Lower 8 Bits) 2C46h 2C4Eh 2C56h 2C5Eh 2C66h 2C6Eh 2C76h 2C7Eh 2C86h 2C8Eh 2C96h 2C9Eh 2CA6h 2CAEh 2CB6h 2CBEh 2CC6h 2CCEh 2CD6h 2CDEh 2CE6h 2CEEh 2CF6h 2CFEh DTDARj Register (Higher 8 Bits) 2C47h 2C4Fh 2C57h 2C5Fh 2C67h 2C6Fh 2C77h 2C7Fh 2C87h 2C8Fh 2C97h 2C9Fh 2CA7h 2CAFh 2CB7h 2CBFh 2CC7h 2CCFh 2CD7h 2CDFh 2CE7h 2CEFh 2CF7h 2CFFh Control Data No. Control Data 0 Control Data 1 Control Data 2 Control Data 3 Control Data 4 Control Data 5 Control Data 6 Control Data 7 Control Data 8 Control Data 9 Control Data 10 Control Data 11 Control Data 12 Control Data 13 Control Data 14 Control Data 15 Control Data 16 Control Data 17 Control Data 18 Control Data 19 Control Data 20 Control Data 21 Control Data 22 Control Data 23 REJ09B0441-0010 Rev.0.10 Page 227 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC When the DTC is activated, one control data is selected according to the data read from the vector table which has been assigned to each activation source, and the selected control data is read from the DTC control data area. Table 16.5 shows the DTC Activation Sources and DTC Vector Addresses. A one-byte vector table area is assigned to each activation source and one value from 00000000b to 00010111b (control data numbers in Table 16.4) is stored in each area to select one of the 24 control data sets. Figures 16.3 to 16.6 show the DTC Internal Operation Flowchart. Table 16.5 DTC Activation Sources and DTC Vector Addresses Interrupt Name INT0 INT1 INT2 INT3 INT4 INT5 INT6 Key input A/D UART0 UART1 UART2 SSU/I2C bus Voltage detection circuit Timer RC INT7 Key input A/D conversion UART0 reception UART0 transmission UART1 reception UART1 transmission UART2 reception UART2 transmission Receive data full Transmit data empty Comparator A2 Comparator A1 Input-capture/compare-match A Input-capture/compare-match B Input-capture/compare-match C Input-capture/compare-match D Input-capture/compare-match A Input-capture/compare-match B Input-capture/compare-match C Input-capture/compare-match D Input-capture/compare-match A Input-capture/compare-match B Input-capture/compare-match C Input-capture/compare-match D Timer RE Input-capture/compare-match A Input-capture/compare-match B Timer RA Timer RB Flash memory ready status Source No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 33 42 47 48 49 51 52 DTC Vector Address 2C00h 2C01h 2C02h 2C03h 2C04h 2C05h 2C06h 2C07h 2C08h 2C09h 2C0Ah 2C0Bh 2C0Ch 2C0Dh 2C0Eh 2C0Fh 2C10h 2C11h 2C12h 2C13h 2C16h 2C17h 2C18h 2C19h 2C1Ah 2C1Bh 2C1Ch 2C1Dh 2C1Eh 2C1Fh 2C20h 2C21h 2C2Ah 2C2Fh 2C30h 2C31h 2C33h 2C34h Priority High Interrupt Request Source External input Timer RD0 Timer RD1 Timer RE Timer RG Timer RA Timer RB Flash memory Low REJ09B0441-0010 Rev.0.10 Page 228 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC DTC activation source generation NMIF = 1? Branch 1 0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated when transfer is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode Read DTC vector DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) register RPTINT, CHNE: Bits in DTCCRj register NMIF: Bit in DTCTL register Read control data Write 0 to the bit among DTCENi0 to DTCENi7 Generate an interrupt request for the CPU Branch 1 No Transfer data Yes Read control data Transfer data Read control data Write back control data Transfer data Write back control data Transfer data CHNE=1? No Yes Write back control data CHNE=1? No Yes Write back control data CHNE=1? No Yes CHNE=1? No Yes End Interrupt handling Figure 16.3 DTC Internal Operation Flowchart When DTC Activation Source is not SSU/I2C bus, Timer RC, Timer RD, or Flash Memory Interrupt Source DTC activation source generation NMIF = 1? Branch 1 0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated when transfer is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode Read DTC vector DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) register RPTINT, CHNE: Bits in DTCCRj register NMIF: Bit in DTCTL register Read control data Branch 1 No Write 0 to the interrupt source flag in the status register Yes Write 0 to the bit among DTCENi0 to DTCENi7 Generate an interrupt request for the CPU Read control data Read control data Transfer data Transfer data Transfer data Transfer data Write back control data Write back control data Write back control data Write back control data CHNE=1? No Yes Yes CHNE=1? No CHNE=1? No Yes CHNE=1? No Yes End Interrupt handling Figure 16.4 DTC Internal Operation Flowchart When DTC Activation Source is Timer RC, Timer RD, or Flash Memory Interrupt Source REJ09B0441-0010 Rev.0.10 Page 229 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC DTC activation source generation NMIF = 1? Branch 1 0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated when transfer is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode Read DTC vector DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) register RPTINT, CHNE: Bits in DTCCRj register NMIF: Bit in DTCTL register RDRF: Bit in SSSR/ICSR register Read control data Write 0 to the bit among DTCENi0 to DTCENi7 Generate an interrupt request for the CPU Branch 1 No Transfer data (Reading the receive data register sets the RDRF bit to 0) (1) Yes Read control data Transfer data (Reading the receive data register does not set the RDRF bit to 0) Read control data Write back control data Transfer data (Reading the receive data register sets the RDRF bit to 0) (1) Write back control data Transfer data (Reading the receive data register does not set the RDRF bit to 0) CHNE=1? No Yes Write back control data CHNE=1? No Yes Write back control data CHNE=1? No Yes CHNE=1? No Yes End Interrupt handling Note: 1. When the DTC activation source is SSU/I2C bus receive data full, the DTC does not set the RDRF bit in the SSSR register/the ICSR register to 0. Instead, reading the receive data register during DTC data transfer sets the RDRF bit to 0. Figure 16.5 DTC Internal Operation Flowchart When DTC Activation Source is SSU/I2C bus Receive Data Full DTC activation source generation NMIF = 1? Branch 1 0 is written to the bit among bits DTCENi0 to DTCENi7 when transfer is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode Read DTC vector DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) register RPTINT, CHNE: Bits in DTCCRj register NMIF: Bit in DTCTL register TDRE: Bit in SSSR/ICSR register Read control data Branch 1 No Transfer data (writing the transmit data register sets the TDRE bit to 0) (1) Yes Write 0 to the bit among DTCENi0 to DTCENi7 Read control data Transfer data (writing the transmit data register sets the TDRE bit to 0) (1) Read control data Write back control data Transfer data (writing the transmit data register sets the TDRE bit to 0) (1) Write back control data Transfer data (writing the transmit data register sets the TDRE bit to 0) (1) CHNE=1? No Yes Write back control data CHNE=1? No Yes Write back control data CHNE=1? No Yes CHNE=1? No Yes End Note: 1. When the DTC activation source is SSU/I2C bus transmit data empty, the DTC does not set the TDRE bit in the SSSR register/the ICSR register to 0. Instead, writing data to the transmit data register during DTC data transfer sets the TDRE bit to 0. Figure 16.6 DTC Internal Operation Flowchart When DTC Activation Source is SSU/I2C bus Transmit Data Empty REJ09B0441-0010 Rev.0.10 Page 230 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.4 Normal Mode One to 256 bytes of data are transferred by one activation. The number of transfer times can be 1 to 256. When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed, an interrupt request for the CPU is generated during DTC operation. Table 16.6 shows Register Functions in Normal Mode. Figure 16.7 shows Data Transfers in Normal Mode. Table 16.6 Register Functions in Normal Mode Symbol DTBLSj DTCCTj DTRLDj DTSARj DTDARj Function Size of the data block to be transferred by one activation Number of times of data transfers Not used Data transfer source address Data transfer destination address Register DTC block size register j DTC transfer count register j DTC transfer count reload register j DTC source address register j DTC destination address register j j =0 to 23 Transfer source SRC Transfer Transfer destination DST Size of the data block to be transferred by one activation (N bytes) DTBLSj = N DTSARj = SRC DTDARj = DST j = 0 to 23 Bits b3 to b0 in DTCCR register 00X0b 01X0b 10X0b 11X0b X: 0 or 1 Source address Destination address control control Fixed Incremented Fixed Incremented Fixed Fixed Incremented Incremented Source address after transfer SRC SRC+N SRC SRC+N Destination address after transfer DST DST DST+N DST+N Figure 16.7 Data Transfers in Normal Mode REJ09B0441-0010 Rev.0.10 Page 231 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.5 Repeat Mode One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be specified as the repeat area. The number of transfer times can be 1 to 255. On completion of the specified number of transfer times, the DTCCTj (i =0 to 23) register and the address specified for the repeat area are initialized to continue transfers. When the data transfer causing the DTCCTj register value to change to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), an interrupt request for the CPU is generated during DTC operation. The lower 8 bits of the initial value for the repeat area address must be 00h. The size of data to be transferred must be set to 255 bytes or less before the specified number of transfer times is completed. Table 16.7 shows Register Functions in Repeat Mode. Figure 16.8 shows Data Transfers in Repeat Mode. Table 16.7 Register Functions in Repeat Mode Function Size of the data block to be transferred by one activation Number of times of data transfers This register value is reloaded to the DTCCT register. (Data transfer count is initialized.) Data transfer source address Data transfer destination address Register Symbol DTC block size register j DTBLSj DTC transfer count register j DTCCTj DTC transfer count reload register j DTRLDj DTC source address register j DTC destination address register j j =0 to 23 DTCCTj register ≠ 1 DTSARj DTDARj Transfer source SRC Transfer Transfer destination DST Size of the data block to be transferred by one activation (N bytes) DTBLSj = N DTCCTj ≠ 1 DTSARj = SRC DTDARj = DST j = 0 to 23 Bits b3 to b0 in DTCCR register 0X11b 1X11b X001b X101b X: 0 or 1 DTCCTj register = 1 Source address Destination address control control Repeat area Repeat area Fixed Incremented Fixed Incremented Repeat area Repeat area Source address after transfer SRC+N SRC+N SRC SRC+N Destination address after transfer DST DST+N DST+N DST+N Repeat area SRC0/DST0 … Address of the repeat area is initialized after a transfer. SRC/DST DTBLSj = N DTCCTj = 1 DTSARj = SRC DTDARj = DST j = 0 to 23 Bits b3 to b0 in DTCCR register 0X11b 1X11b X001b X101b Source address Destination address control control Repeat area Repeat area Fixed Incremented Fixed Incremented Repeat area Repeat area Source address after transfer SRC0 SRC0 SRC SRC+N Destination address after transfer DST DST+N DST0 DST0 SRC0: Initial source address value DST0: Initial destination address value X: 0 or 1 Figure 16.8 Data Transfers in Repeat Mode REJ09B0441-0010 Rev.0.10 Page 232 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.6 Chain Transfers When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers can be continuously performed by one activation source. Figure 16.9 shows a Flow of Chain Transfers. When the DTC is activated, one control data is selected according to the data read from the DTC vector address corresponding to the activation source, and the selected control data is read from the DTC control data area. When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately following the current control data is read and transferred after the current transfer is completed. This operation is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is completed. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled). DTC activation source generation Read DTC vector Read control data 1 DTC control data area Control data 1 CHNE = 1 Control data 2 CHNE = 0 Transfer data Write back control data 1 Read control data 2 Data transfer Write back control data 2 CHNE: Bit in DTCCRj register End of DTC transfers Figure 16.9 Flow of Chain Transfers 16.3.7 Interrupt Sources When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal mode, and when the data transfer causing the DTCCTj register value to change to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request corresponding to the activation source is generated for the CPU during DTC operation. However, no interrupt request is generated for the CPU when the activation source is SSU/I2C bus transmit data empty. Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether the interrupt request is generated or not is determined either by the number of transfer times specified for the first type of the transfer or the RPTINT bit. When an interrupt request is generated for the CPU, the bit among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 6) registers corresponding to the activation source are set to 0 (activation disabled). REJ09B0441-0010 Rev.0.10 Page 233 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.8 Operation Timings The DTC requires four clock cycles to read control data allocated in the DTC control data area. The number of clock cycles required to write back control data differs depending on the control data settings. Figure 16.10 shows an Example of DTC Operation Timings and Figure 16.11 shows an Example of DTC Operation Timings in Chain Transfers. Table 16.8 shows the Specifications of Control Data Write-Back Operation. CPU clock Read vector Address Used by CPU Read Write Used by CPU Read control data Transfer data Write back control data Figure 16.10 Example of DTC Operation Timings CPU clock Read vector Address Used by CPU Read Write Read Write Used by CPU Read control data Transfer data Write back control data Read control data Transfer data Write back control data Figure 16.11 Example of DTC Operation Timings in Chain Transfers Table 16.8 Bits b3 to b0 in DTCCR Register 00X0b 01X0b 10X0b 11X0b 0X11b 1X11b X001b X101b j = 0 to 23 X: 0 or 1 Specifications of Control Data Write-Back Operation Operating Mode Address Control Source Fixed Normal mode Incremented Fixed Destination Fixed Fixed Incremented Control Data to be Written Back DTRLDj DTSARj DTDARj Register Register Register Not written Not written Written back Written back back back Not written Written back Written back Written back back Not written Written back Written back Written back back Written back Written back Written back Written back Not written Written back Written back Written back back Written back Written back Written back Written back Not written Written back Written back Written back back Written back Written back Written back Written back DTCCTj Register Number of Clock Cycles 1 2 2 3 2 3 2 3 Incremented Incremented Repeat area Repeat mode Fixed Incremented Fixed Incremented Repeat area REJ09B0441-0010 Rev.0.10 Page 234 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.9 Number of DTC Execution Cycles Table 16.9 shows the Operations Following DTC Activation and Required Number of Cycles for each operation. Table 16.10 shows the Number of Clock Cycles Required for Data Transfers. Table 16.9 Operations Following DTC Activation and Required Number of Cycles Control Data Read/Write (J) 5 to 7 5 to 7 Data Read Data Write Internal Operation 2 2 Vector Read 1 1 (Note 1) (Note 1) (Note 1) (Note 1) Note: 1. For the number of clock cycles required for data read/write, see Table 16.10 Number of Clock Cycles Required for Data Transfers. Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N, (1) When N = 2n (even), two-byte transfers are performed n times. (2) When N = 2n + 1 (odd), 2-byte transfers are performed n times followed by one 1-byte transfer. Table 16.10 Operation Number of Clock Cycles Required for Data Transfers Unit of Transfers 1-byte SK1 2-byte SK2 1-byte SL1 2-byte SL2 On-Chip RAM (During DTC Transfers) Even Odd Address Address 1 1 2 1 1 2 On-Chip ROM (User Area) 1 2 On-Chip ROM (Data Area) 2 4 SFR (Word Access) Even Odd Address Address 2 2 4 2 2 4 SFR (Byte Access) 2 4 2 4 Data read Data write — — — — From Tables 16.9 and 16.10, the total number of required execution cycles can be obtained by the following formula: Number of required execution cycles = 1 + Σ[formula A] + 2 Σ: Sum of the cycles for the number of transfer times performed by one activation source ([the number of transfer times for which CHNE is set to 1] + 1) (1) For N = 2n (even) Formula A = J + n • SK2 + n • SL2 (2) For N = 2n+1 (odd) Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1 J: Number of cycles required to read or write back control data REJ09B0441-0010 Rev.0.10 Page 235 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags 16.3.10.1 Interrupt Sources Except for Flash Memory, Timer RC, Timer RD, and Synchronous Serial Communication Unit (SSU)/I2C bus When the DTC activation source is an interrupt source except for the flash memory, timer RC, timer RD, or the synchronous serial communication unit/I2C bus, the same DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock after the interrupt source is generated. If a DTC activation source is generated during DTC operation and acknowledged, the same DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock on completion of the DTC transfer immediately before the DTC is activated by the source. 16.3.10.2 Flash Memory When the DTC activation source is flash memory ready status, even if a flash memory ready status interrupt request is generated, it is not acknowledged as the DTC activation source after the RDYSTI bit in the FST register is set to 1 (flash memory ready status interrupt request) and before the DTC sets the RDYSTI bit to 0 (no flash memory ready status interrupt request). If a flash memory ready status interrupt request is generated after the DTC sets the RDYSTI bit to 0, the DTC acknowledges it as the activation source. 8 to 12 cycles of the CPU clock are required after the RDYSTI bit is set to 1 and before the DTC sets the interrupt request flag to 0. If a flash memory ready status interrupt request is generated during DTC operation and acknowledged as the DTC activation source, the RDYSTI bit is set to 0 after 8 to 12 cycles of the CPU clock on completion of the DTC transfer immediately before the DTC is activated by the source. 16.3.10.3 Timer RC, Timer RD When the DTC activation source is an interrupt source for timer RC or timer RD, even if an input capture/compare match in individual timers occurs, it is not acknowledged as the DTC activation source after the interrupt source flag is set to 1 and before the DTC sets the flag to 0. If an input capture/compare match occurs after the DTC sets the interrupt source flag to 0, the DTC acknowledges it as the activation source. 8 to 12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock are required after the interrupt source flag is set to 1 and before the DTC sets the flag to 0. If individual DTC activation sources are generated for timer C and timer D during DTC operation and acknowledged, the interrupt source flag is set to 0 after 8 to 12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock on completion of the DTC transfer immediately before the DTC is activated by the source. 16.3.10.4 SSU/I2C bus Receive Data Full When the DTC activation source is SSU/I2C bus receive data full, read the SSRDR register/the ICDRR register using a data transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by reading the SSRDR register/ the ICDRR register. If an interrupt source for receive data full is subsequently generated, the DTC acknowledges it as the activation source. 16.3.10.5 SSU/I2C bus Transmit Data Empty When the DTC activation source is SSU/I2C bus transmit data empty, write to the SSTDR register/the ICDRT register using a data transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT register. If an interrupt source for transmit data empty is subsequently generated, the DTC acknowledges it as the activation source. REJ09B0441-0010 Rev.0.10 Page 236 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC 16.4 16.4.1 Notes on DTC DTC activation source • Do not generate any DTC activation sources before entering wait mode or during wait mode. • Do not generate any DTC activation sources before entering stop mode or during stop mode. 16.4.2 DTCENi (i = 0 to 6) Registers • Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated. • When the interrupt source flag in the status register for the peripheral function is 1, do not modify the corresponding activation source bit among bits DTCENi0 to DTCENi7. • Do not access the DTCENi register using a DTC transfer. 16.4.3 Peripheral Modules • Do not set the status register bit for the peripheral function to 0 using a DTC transfer. • When the DTC activation source is SSU/I2C bus receive data full, read the SSRDR register/the ICDRR register using a DTC transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by reading the SSRDR register/the ICDRR register. However, the RDRF bit is not set to 0 by reading the SSRDR register/the ICDRR register when the DTC data transfer setting is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCRj register value to change from 1 to 0 while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode. • When the DTC activation source is SSU/I2C bus transmit data empty, write to the SSTDR register/the ICDRT register using a DTC transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT register. REJ09B0441-0010 Rev.0.10 Page 237 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 17. Timers 17. Timers The following six types of timers are available: • Timer RA: 8-bit timer with an 8-bit prescaler • Timer RB: 8-bit timer with an 8-bit prescaler • Timer RC: 16-bit timer • Timer RD: Two 16-bit timers • Timer RE: 4-bit counter and 8-bit counter • Timer RG: 16-bit timer All these timers operate independently. REJ09B0441-0010 Rev.0.10 Page 238 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 17. Timers Table 17.1 Item Configuration Functional Comparison of Timers Timer RA0 8-bit timer with 8-bit prescaler (with reload register) Decrement • • • • • • f1 f2 f8 fOCO fC32 fC Timer RB 8-bit timer with 8-bit prescaler (with reload register) Decrement • • • • f1 f2 f8 Timer RA underflow Timer RC 16-bit timer (with input capture and output compare) Increment • f1 • f2 • f4 • f8 • f32 • fOCO40M • fOCO-F • TRCCLK Timer mode (output compare function) Timer mode (output compare function) Timer mode (input capture function; 4 pins) Timer RD 16-bit timer × 2 (with input capture and output compare) Timer RE 4-bit counter 8-bit counter Increment/Decrement Increment • • • • f4 f8 f32 fC4 Timer RG 16-bit timer (with input capture and output compare) Increment/ Decrement • f1 • f2 • f4 • f8 • f32 • fOCO40M • TRGCLKA • TRGCLKB Timer mode (output compare function) Timer mode (output compare function), Please counting mode Timer mode (Input capture function; 2 pins) Count Count sources Function Count of the internal count source Count of the external count source External pulse width/period measurement Timer mode Event counter mode Pulse width measurement mode, pulse period measurement mode Pulse output mode (1), Event counter mode (1) Timer mode — • f1 • f2 • f4 • f8 • f32 • fOCO40M • fOCO-F • TRDCLK Timer mode (output compare function) Timer mode (output compare function) Timer mode (input compare function; 2 × 4 pins) — — — — PWM output Programmable waveform generation mode Timer mode (output compare function; 4 pins) (1), PWM mode (3 pins), PWM2 mode (1 pin) PWM mode (3 pins) One-shot waveform output — Three-phase waveforms output — Programmable one-shot generation mode, Programmable wait one-shot generation mode — Timer mode (output compare function; 2 × 4 pins) (1), PWM mode (2 × 3 pins), PWM3 mode (2 × 2 pins) PWM mode (2 × 3 pins) Output compare mode (1) Timer mode (output compare function; 2 pins), PWM mode (1 pin) — — — Timer Input pin Timer mode — (only fC32 count) TRAIO INT0 — INT0, TRCCLK, TRCTRG, TRCIOA, TRCIOB, TRCIOC, TRCIOD TRCIOA, TRCIOB, TRCIOC, TRCIOD Compare match/input capture A to D interrupt, Overflow interrupt, INT0 interrupt Reset synchronous PWM mode (2 × 3 pins, Sawtooth wave modulation), Complementary PWM mode (2 × 3 pins, triangular wave modulation, dead time) — INT0, TRDCLK, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 Compare match/input capture A0 to D0 interrupt, Compare match/input capture A1 to D1 interrupt, Overflow interrupt, Underflow interrupt (2), INT0 interrupt Provided — — Real-time clock mode — — TRGCLKA, TRGCLKB, TRGIOA, TRGIOB TRGIOA, TRGIOB Compare match/ input capture A to B interrupt, Underflow interrupt (2), Overflow interrupt Output pin TRAO TRAIO Timer RA interrupt TRBO TREO Related interrupt Timer RB interrupt, INT0 interrupt Timer RE interrupt Timer stop Provided Provided Provided Provided Provided Notes: 1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of the pulses are the same. 2. The underflow interrupt can be set to timer RD1 and timer RG. REJ09B0441-0010 Rev.0.10 Page 239 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18. Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler. 18.1 Introduction The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 18.2 to 18.6 the Specifications of Each Mode). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 18.1 shows the Timer RA Block Diagram. Table 18.1 lists the Timer RA Pin Configuration. Timer RA supports the following five operating modes: • Timer mode: The timer counts an internal count source. • Pulse output mode: The timer counts an internal count source and outputs pulses which invert the polarity by underflow of the timer. • Event counter mode: The timer counts external pulses. • Pulse width measurement mode: The timer measures the pulse width of an external pulse. • Pulse period measurement mode: The timer measures the pulse period of an external pulse. Bits TCK2 to TCK0 f1 = 001b f8 = 010b fOCO = 011b f2 = 100b fC32 = 110b fC = 000b TCKCUT bit Bits TMOD2 to TMOD0 = other than 010b Data bus Bits TIOGT1 to TIOGT0 Event input always enabled = 01b Event input enabled for “H” period of INT2 Event input enabled for “H” period of TRCIOD (timer RC compare match signal) = 10b Bits TMOD2 to TMOD0 = 010b = 00b Reload register TCSTF bit Reload register Underflow signal Counter TRAPRE register (prescaler) Counter TRA register (timer) Timer RA interrupt Bits TIPF1 to TIPF0 = 01b f1 = 10b f8 = 11b f32 Digital filter Bits TIPF1 to TIPF0 = other than 000b Bits TMOD2 to TMOD0 = 011b or 100b Count control circuit Polarity switching = 00b Measurement end signal Bits TMOD2 to TMOD0 = 001b TOPCR bit TRAIO pin TOENA bit TRAO pin Q TEDGSEL = 0 TEDGSEL = 1 Q Toggle flip-flop CLR CK Write to TRAMR register Write 1 to TSTOP bit TCSTF, TSTOP: Bits in TRACR register TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: Bits in TRAIOC register TMOD0 to TMOD2, TCK0 to TCK2, TCKCUT: Bits in TRAMR register Figure 18.1 Timer RA Block Diagram Table 18.1 Timer RA Pin Configuration Pin Name TRAIO TRAO Assigned Pin P11_4 P11_5 I/O I/O Output Function Function differs according to the mode. Refer to descriptions of individual modes for details. REJ09B0441-0010 Rev.0.10 Page 240 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.2 18.2.1 Registers Timer RA Control Register (TRACR) b6 — 0 b5 TUNDF 0 b4 TEDGF 0 b3 — 0 b2 TSTOP 0 b1 TCSTF 0 b0 TSTART 0 R/W R/W R R/W — R/W R/W — Address 0100h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name TSTART Timer RA count start bit (1) Function 0: Count stops 1: Count starts 0: Count stops TCSTF Timer RA count status flag (1) 1: During count operation TSTOP Timer RA count forcible stop bit (2) When this bit is set to 1, the count is forcibly stopped. When read, the content is 0. — Nothing is assigned. If necessary, set to 0. When read, the content is 0. TEDGF Active edge judgment flag (3, 4) 0: Active edge not received 1: Active edge received (end of measurement period) 0: No underflow TUNDF Timer RA underflow flag (3, 4) 1: Underflow — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Notes: 1. Refer to 18.8 Notes on Timer RA for notes regarding bits TSTART and TCSTF. 2. When 1 is written to the TSTOP bit, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after a reset. 3. Bits TEDGF and TUNDF can be set to 0 by writing 0 to these bits by a program. However, their value remains unchanged when 1 is written. 4. Set to 0 in timer mode, pulse output mode, and event counter mode. In pulse width measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, write 1 to them. 18.2.2 Timer RA I/O Control Register (TRAIOC) b6 TIOGT0 0 b5 TIPF1 0 b4 TIPF0 0 b3 TIOSEL 0 b2 TOENA 0 b1 b0 TOPCR TEDGSEL 0 0 Address 0101h Bit b7 Symbol TIOGT1 After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 0 Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 TIOGT0 TIOGT1 Bit Name TRAIO polarity switch bit TRAIO output control bit TRAO output enable bit Hardware LIN function select bit TRAIO input filter select bit TRAIO event input control bit Function R/W Function varies according to the operating mode. R/W R/W R/W R/W R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 241 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.2.3 Timer RA Mode Register (TRAMR) b6 TCK2 0 b5 TCK1 0 b4 TCK0 0 b3 — 0 b2 TMOD2 0 b1 TMOD1 0 Function b2 b1 b0 Address 0102h Bit b7 Symbol TCKCUT After Reset 0 Bit b0 b1 b2 b0 TMOD0 0 R/W R/W R/W R/W b3 b4 b5 b6 b7 0 0 0: Timer mode 0 0 1: Pulse output mode 0 1 0: Event counter mode 0 1 1: Pulse width measurement mode 1 0 0: Pulse period measurement mode 1 0 1: Do not set. 1 1 0: Do not set. 1 1 1: Do not set. — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b6 b5 b4 TCK0 Timer RA count source select bit 0 0 0: f1 TCK1 0 0 1: f8 TCK2 0 1 0: fOCO 0 1 1: f2 1 0 0: fC32 1 0 1: Do not set. 1 1 0: fC 1 1 1: Do not set. TCKCUT Timer RA count source cutoff bit 0: Count source provided 1: Count source cut off Symbol Bit Name TMOD0 Timer RA operating mode select bit TMOD1 TMOD2 — R/W R/W R/W R/W When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rewrite the TRAMR register. 18.2.4 Timer RA Prescaler Register (TRAPRE) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 Address 0103h Bit b7 Symbol — After Reset 1 (Note 1) R/W R/W R/W R/W R/W Bit Mode b7 to b0 Timer mode Pulse output mode Event counter mode Pulse width measurement mode Function Counts an internal count source. Counts an external count source. Measures the pulse width of input pulses from external (counts an internal count source). Pulse period measurement mode Measures the pulse period of input pulses from external (counts an internal count source). Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh 00h to FFh R/W Note: 1. When 1 is written to the TSTOP bit in the TRACR register, the TRAPRE register is set to FFh. REJ09B0441-0010 Rev.0.10 Page 242 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.2.5 Timer RA Register (TRA) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 Address 0104h Bit b7 Symbol — After Reset 1 Bit Mode b7 to b0 All modes (Note 1) R/W R/W Function Counts the TRAPRE register underflows. Setting Range 00h to FFh Note: 1. When 1 is written to the TSTOP bit in the TRACR register, the TRAPRE register is set to FFh. 18.2.6 Timer RA Pin Select Register (TRASR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 b0 TRAIOSEL1 TRAIOSEL0 0 0 Function b1 b0 Address 0180h Bit b7 Symbol — After Reset 0 Bit b0 b1 Symbol Bit Name TRAIOSEL0 TRAIO pin select bit TRAIOSEL1 0 0: TRAIO pin not used 0 1: P11_4 assigned R/W R/W R/W b2 b3 b4 b5 b6 b7 — — — — — — 1 0: INT4 assigned 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Note: 1. To use hardware LIN, set 01b to bits TRAIOSEL1 to TRAIOSEL0. To use the I/O pin for timer RA, set the TRASR register. Set this register before setting the timer RA associated registers. Also, do not change the setting value of this register during timer RA operation. REJ09B0441-0010 Rev.0.10 Page 243 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.3 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 18.2). Table 18.2 Timer Mode Specifications Item Count sources Count operations Division ratio Count start condition Count stop conditions Interrupt request generation timing TRAIO pin function TRAO pin function Read from timer Write to timer Specification f1, f2, f8, fOCO, fC32 • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register 1 (count starts) is written to the TSTART bit in the TRACR register. • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. When timer RA underflows [timer RA interrupt]. Programmable I/O port Programmable I/O port The count value can be read out by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). 18.3.1 Timer RA I/O Control Register (TRAIOC) in Timer Mode b6 TIOGT0 0 b5 TIPF1 0 b4 TIPF0 0 b3 TIOSEL 0 b2 TOENA 0 b1 b0 TOPCR TEDGSEL 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0101h Bit b7 Symbol TIOGT1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 TIOGT0 TIOGT1 Bit Name TRAIO polarity switch bit TRAIO output control bit TRAO output enable bit Hardware LIN function select bit TRAIO input filter select bit TRAIO event input control bit Function Set to 0 in timer mode. Set to 0. However, set to 1 when the hardware LIN function is used. Set to 0 in timer mode. REJ09B0441-0010 Rev.0.10 Page 244 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.3.2 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 18.2 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation. Write 01h into the TRAPRE register and 25h into the TRA register by a program. Count source After writing, the reload register is written with the first count source. Reload register of timer RA prescaler Previous value Reload with the second count source Counter of timer RA prescaler 06h 05h 04h 01h 00h New value (01h) Reload at underflow 01h 00h 01h 00h 01h 00h After writing, the reload register is written at the first underflow. Reload register of timer RA Previous value New value (25h) Reload at the second underflow Counter of timer RA 03h 02h 25h 24h IR bit in TRAIC register 0 The IR bit remains unchanged until underflow is generated by a new value. The above applies under the following condition: Both the TSTART and TCSTF bits in the TRACR register are set to 1 (during count operation). Figure 18.2 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation REJ09B0441-0010 Rev.0.10 Page 245 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.4 Pulse Output Mode In pulse output mode, an internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 18.3). Table 18.3 Pulse Output Mode Specifications f1, f2, f8, fOCO, fC32, fC • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. Division ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request When timer RA underflows [timer RA interrupt]. generation timing TRAIO pin function Pulse output or programmable output port TRAO pin function Programmable I/O port or inverted output of TRAIO Read from timer The count value can be read out by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). Selectable functions • TRAIO signal polarity switch function The level when the pulse output starts is selected by the TEDGSEL bit in the TRAIOC register. (1) • TRAO output function Pulses inverted from the TRAIO output polarity can be output from the TRAO pin (selectable by the TOENA bit in the TRAIOC register). • Pulse output stop function Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register. • TRAIO pin select function Use of the TRAIO pin is selected by the TRAIOSEL0 bit in the TRASR register. Note: 1. By writing to the TRAMR register, the output pulse is set to the level when the pulse output starts. Item Count sources Count operations Specification REJ09B0441-0010 Rev.0.10 Page 246 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.4.1 Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode b6 TIOGT0 0 b5 TIPF1 0 b4 TIPF0 0 b3 TIOSEL 0 b2 TOENA 0 b1 b0 TOPCR TEDGSEL 0 0 R/W R/W R/W R/W Address 0101h Bit b7 Symbol TIOGT1 After Reset 0 Bit b0 b1 b2 Symbol Bit Name TEDGSEL TRAIO polarity switch bit TOPCR TOENA TRAIO output control bit TRAO output enable bit b3 b4 b5 b6 b7 TIOSEL TIPF0 TIPF1 TIOGT0 TIOGT1 Hardware LIN function select bit TRAIO input filter select bit TRAIO event input control bit Function 0: TRAIO output starts at high 1: TRAIO output starts at low 0: TRAIO output 1: Port P11_4 0: Port P11_5 1: TRAO output (inverted TRAIO output is output from P11_5) Set to 0. Set to 0 in pulse output mode. R/W R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 247 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.5 Event Counter Mode In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 18.4). Table 18.4 Event Counter Mode Specifications Item Count source Count operations Specification External signal input to the TRAIO pin (active edge selectable by a program) • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. Division ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request When timer RA underflows [timer RA interrupt]. generation timing TRAIO pin function Count source input TRAO pin function Programmable I/O port or pulse output (1) Read from timer Write to timer The count value can be read out by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). • INT2 input polarity switch function The active edge of the count source is selected by the TEDGSEL bit in the TRAIOC register. • Count source input pin select function Use of the TRAIO pin is selected by the TRAIOSEL0 bit in the TRASR register. • Pulse output function Pulses of inverted polarity can be output from the TRAO pin each time the timer underflows (selectable by the TOENA bit in the TRAIOC register). (1) • Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register. • Event input control function The enabled period for the event input to the TRAIO pin is selected by bits TIOGT0 and TIOGT1 in the TRAIOC register. Selectable functions Note: 1. By writing to the TRAMR register, the output pulse is set to the level when the pulse output starts. REJ09B0441-0010 Rev.0.10 Page 248 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.5.1 Timer RA I/O Control Register (TRAIOC) in Event Counter Mode b6 TIOGT0 0 b5 TIPF1 0 b4 TIPF0 0 b3 TIOSEL 0 b2 TOENA 0 b1 b0 TOPCR TEDGSEL 0 0 R/W R/W Address 0101h Bit b7 Symbol TIOGT1 After Reset 0 Bit b0 Symbol Bit Name TEDGSEL TRAIO polarity switch bit b1 b2 b3 b4 b5 TOPCR TOENA TIOSEL TIPF0 TIPF1 b6 b7 TIOGT0 TIOGT1 Function 0: Count at the rising edge of TRAIO input and TRAO output starts at low 1: Count at the falling edge of TRAIO input and TRAO output starts at high TRAIO output control bit Set to 0 in event counter mode. TRAO output enable bit 0: Port P11_05 1: TRAO output Hardware LIN function select bit Set to 0. b5 b4 TRAIO input filter select bit (1) 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b7 b6 TRAIO event input control bit 0 0: Event input always enabled 0 1: Event input enabled for high-level period of INT2 1 0: Event input enabled for low-level period of timer RC compare match signal 1 1: Do not set. R/W R/W R/W R/W R/W R/W R/W Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. REJ09B0441-0010 Rev.0.10 Page 249 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.6 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the TRAIO pin is measured (refer to Table 18.5). Figure 18.3 shows an Operating Example in Pulse Width Measurement Mode. Table 18.5 Pulse Width Measurement Mode Specifications Item Count sources Count operations Specification f1, f2, f8, fOCO, fC32, fC • Decrement • The count is continued only while the measured pulse is high or low level. • When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1 (count starts) is written to the TSTART bit in the TRACR register. • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. • When timer RA underflows [timer RA interrupt]. • Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] Measured pulse input Programmable I/O port The count value can be read out by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). • Measurement level setting A high-level or low-level period is selected by the TEDGSEL bit in the TRAIOC register. • Measured pulse input pin select function Use of the TRAIO pin is selected by bits TRAIOSEL0 in the TRASR register. • Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register. Count start condition Count stop conditions Interrupt request generation timing TRAIO pin function TRAO pin function Read from timer Write to timer Selectable functions REJ09B0441-0010 Rev.0.10 Page 250 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.6.1 Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement Mode b6 TIOGT0 0 b5 TIPF1 0 b4 TIPF0 0 b3 TIOSEL 0 b2 TOENA 0 b1 b0 TOPCR TEDGSEL 0 0 R/W R/W R/W R/W R/W R/W R/W Address 0101h Bit b7 Symbol TIOGT1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name TEDGSEL TRAIO polarity switch bit TOPCR TOENA TIOSEL TIPF0 TIPF1 TRAIO output control bit TRAO output enable bit Hardware LIN function select bit TRAIO input filter select bit (1) Function 0: Low-level width of TRAIO input is measured 1: High-level width of TRAIO input is measured Set to 0 in pulse width measurement mode. Set to 0. However, set to 1 when the hardware LIN function is used. b5 b4 b6 b7 TIOGT0 TIOGT1 TRAIO event input control bit 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling Set to 0 in pulse width measurement mode. R/W R/W Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. REJ09B0441-0010 Rev.0.10 Page 251 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.6.2 Operating Example n = higher: content of TRA register; lower: content of TRAPRE register FFFFh n Measurement starts Underflow Content of counter (hex) Measurement stops Measurement stops 0000h Set to 1 by a program. TSTART bit in TRACR register 1 0 Measurement starts Measurement starts Period Measured pulse (TRAIO pin input) 1 0 Set to 0 when an interrupt request is acknowledged or by a program. IR bit in TRAIC register 1 0 Set to 0 by a program. TEDGF bit in TRACR register 1 0 Set to 0 by a program. TUNDF bit in TRACR register 1 0 The above applies under the following conditions: • High-level width of measured pulse is measured. (TEDGSEL = 1) • TRAPRE = FFh Figure 18.3 Operating Example in Pulse Width Measurement Mode REJ09B0441-0010 Rev.0.10 Page 252 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.7 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the TRAIO pin is measured (refer to Table 18.6). Figure 18.4 shows an Operating Example in Pulse Period Measurement Mode. Table 18.6 Pulse Period Measurement Mode Specifications Item Count sources Count operations Specification f1, f2, f8, fOCO, fC32, fC • Decrement • After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads the contents of the reload register at the second underflow of timer RA prescaler and continues counting. 1 (count starts) is written to the TSTART bit in the TRACR register. • 0 (count stops) is written to TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. • When timer RA underflows or reloads [timer RA interrupt]. • Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] Measured pulse input (1) Programmable I/O port The count value can be read out by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). • Measurement period selection The measurement period of the input pulse is selected by the TEDGSEL in the TRAIOC register. • Measured pulse input pin select function Use of the TRAIO pin is selected by bits TRAIOSEL0 in the TRASR register. • Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register. Count start condition Count stop conditions Interrupt request generation timing TRAIO pin function TRAO pin function Read from timer Write to timer Selectable functions Note: 1. Input a pulse with a period longer than twice the timer RA prescaler period. Also, input a pulse with a longer high-/low-level width than the timer RA prescaler period. If a pulse with a shorter period is input to the TRAIO pin, the input may be ignored. REJ09B0441-0010 Rev.0.10 Page 253 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.7.1 Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement Mode b6 TIOGT0 0 b5 TIPF1 0 b4 TIPF0 0 b3 TIOSEL 0 b2 TOENA 0 b1 b0 TOPCR TEDGSEL 0 0 R/W R/W Address 0101h Bit b7 Symbol TIOGT1 After Reset 0 Bit b0 Symbol Bit Name TEDGSEL TRAIO polarity switch bit b1 b2 b3 b4 b5 TOPCR TOENA TIOSEL TIPF0 TIPF1 TRAIO output control bit TRAO output enable bit Hardware LIN function select bit TRAIO input filter select bit (1) Function 0: Period from one rising edge to next rising edge of measured pulse is measured 1: Period from one falling edge to next falling edge of measured pulse is measured Set to 0 in pulse period measurement mode. Set to 0. b5 b4 b6 b7 TIOGT0 TIOGT1 TRAIO event input control bit 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling Set to 0 in pulse period measurement mode. R/W R/W R/W R/W R/W R/W R/W Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. REJ09B0441-0010 Rev.0.10 Page 254 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.7.2 Operating Example Underflow signal of timer RA prescaler Set to 1 by a program. TSTART bit in TRACR register 1 0 Count starts Measured pulse (TRAIO pin input) 1 0 TRA reload TRA reload Contents of TRA 0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh Underflow Retained Retained Contents of read-out buffer (1) 0Fh 0Eh 0Dh 0Bh 0Ah 09h 0Dh 01h 00h 0Fh 0Eh TRA read (3) (Note 2) (Note 2) TEDGF bit in TRACR register 1 0 Set to 0 by a program. (Note 4) (Note 6) TUNDF bit in TRACR register 1 0 Set to 0 by a program. (Note 5) IR bit in TRAIC register 1 0 Set to 0 when an interrupt request is acknowledged or by a program. The above applies when the period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with the initial value of the TRA register as 0Fh. Notes: 1. The content of the read-out buffer can be read by reading the TRA register in pulse period measurement mode. 2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge received) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge received). The contents of the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously. Figure 18.4 Operating Example in Pulse Period Measurement Mode REJ09B0441-0010 Rev.0.10 Page 255 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA 18.8 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. • Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time in the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READMODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. • When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. • The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. • When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. • The TCSTF bit remains 0 (count stops) for zero or one cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first active edge of the count source after The TCSTF bit is set to 1 (during count operation). The TCSTF bit remains 1 for zero or one cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Note: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA • When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. • When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. REJ09B0441-0010 Rev.0.10 Page 256 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19. Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler. 19.1 Introduction The prescaler and timer each consist of a reload register and counter (refer to Tables 1 9.2 to 19.5 for the Specifications of Each Mode) for accessing the reload register and counter. Timer RB has timer RB primary and timer RB secondary as reload registers. The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 19.1 shows the Timer RB Block Diagram. Table 19.1 lists the Timer RB Pin Configuration. Timer RB supports the four operating modes: • Timer mode: • Programmable waveform generation mode: • Programmable one-shot generation mode: • Programmable wait one-shot generation mode: The timer counts an internal count source (peripheral function clock or timer RA underflows). The timer outputs pulses of a given width successively. The timer outputs a one-shot pulse. The timer outputs a delayed one-shot pulse. Reload register Bits TCK1 to TCK0 f1 = 00b f8 = 01b Timer RA underflow Data bus TRBSC register Reload register TRBPR register Reload register Timer RB interrupt TCKCUT bit Counter TRBPRE register (prescaler) TSTART bit TOSSTF bit INT0 interrupt Counter (timer RB) (timer) Bits TMOD1 to TMOD0 = 10b or 11b f2 = 10b = 11b INT0 pin Digital filter One edge/both edges input polarity switching Polarity selection INOSEG bit TOPL = 1 Q Q INT0PL bit Bits TMOD1 to TMOD0 = 01b, 10b, 11b TOCNT = 0 INOSTG bit INT0EN bit TRBO pin P11_6 bit in P11 register TOCNT = 1 Toggle flip-flop CLR CK TOPL = 0 TCSTF bit Bits TMOD1 to TMOD0 = 01b, 10b, 11b TSTART, TCSTF: Bits in TRBCR register TOSSTF: Bit in TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register TMOD0, TMOD1, TCK0, TCK1, TCKCUT: Bits in TRBMR register Figure 19.1 Timer RB Block Diagram Table 19.1 Timer RB Pin Configuration Pin Name TRBO Assigned Pin P11_6 I/O Output Function Pulse output (programmable waveform generation mode, programmable one-shot generation mode, programmable wait one-shot generation mode) REJ09B0441-0010 Rev.0.10 Page 257 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.2 19.2.1 Registers Timer RB Control Register (TRBCR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 TSTOP 0 b1 TCSTF 0 b0 TSTART 0 R/W R/W R R/W — Address 0108h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name TSTART Timer RB count start bit (1) TCSTF TSTOP — — — — — Function 0: Count stops 1: Count starts 0: Count stops Timer RB count status flag (1) 1: During count operation (3) (1, 2) When this bit is set to 1, the count is forcibly Timer RB count forcible stop bit stopped. When read, the content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Notes: 1. Refer to 19.7 Notes on Timer RB for precautions regarding bits TSTART, TCSTF and TSTOP. 2. When 1 is written to the TSTOP bit, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 3. Indicates that count operation is in progress in timer mode or programmable waveform mode. In programmable one-shot generation mode or programmable wait one-shot generation mode, it indicates that a one-shot pulse trigger has been acknowledged. 19.2.2 Timer RB One-Shot Control Register (TRBOCR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 TOSSTF 0 b1 TOSSP 0 b0 TOSST 0 R/W R/W R/W Address 0109h Bit b7 Symbol — After Reset 0 Bit b0 b1 Symbol TOSST b2 b3 b4 b5 b6 b7 Function When this bit is set to 1, one-shot trigger generated. When read, the content is 0. TOSSP Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot pulses (including programmable wait one-shot pulses) stops. When read, the content is 0. 0: One-shot stopped TOSSTF Timer RB one-shot status flag (1) 1: One-shot operating (including wait period) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — — Bit Name Timer RB one-shot start bit R — Note: 1. When 1 is written to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0. The TRBOCR register is enabled when bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot generation mode) or 11b (programmable wait one-shot generation mode). REJ09B0441-0010 Rev.0.10 Page 258 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.2.3 Timer RB I/O Control Register (TRBIOC) b6 — 0 b5 — 0 b4 — 0 b3 b2 INOSEG INOSTG 0 0 b1 TOCNT 0 b0 TOPL 0 R/W R/W R/W R/W R/W — Address 010Ah Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TOPL TOCNT INOSTG INOSEG — — — — Bit Name Function Timer RB output level select bit Function varies according to the operating mode. Timer RB output switch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. 19.2.4 Timer RB Mode Register (TRBMR) b6 — 0 b5 TCK1 0 b4 TCK0 0 b3 TWRC 0 b2 — 0 b1 TMOD1 0 b0 TMOD0 0 R/W R/W R/W Address 010Bh Bit b7 Symbol TCKCUT After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function TMOD0 Timer RB operating mode select bit (1) b1 b0 0 0: Timer mode TMOD1 0 1: Programmable waveform generation mode 1 0: Programmable one-shot generation mode 1 1: Programmable wait one-shot generation mode — Nothing is assigned. If necessary, set to 0. When read, the content is 0. TWRC Timer RB write control bit (2) 0: Write to reload register and counter 1: Write to reload register only b5 b4 TCK0 Timer RB count source select bit (1) 0 0: f1 TCK1 0 1: f8 1 0: Timer RA underflow 1 1: f2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. TCKCUT Timer RB count source cutoff bit (1) 0: Count source provided 1: Count source cut off — R/W R/W R/W — R/W Notes: 1. Change bits TMOD0 and TMOD1, TCK0 and TCK1, and TCKCUT when both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). 2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable waveform generation mode, programmable one-shot generation mode, or programmable wait one-shot generation mode, the TWRC bit must be set to 1 (write to reload register only). REJ09B0441-0010 Rev.0.10 Page 259 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.2.5 Timer RB Prescaler Register (TRBPRE) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh R/W R/W R/W R/W R/W Address 010Ch Bit b7 Symbol — After Reset 1 Bit Mode b7 to b0 Timer mode Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Function Counts an internal count source or timer RA underflows. When 1 is written to the TSTOP bit in the TRBCR register, the TRBPRE register is set to FFh. 19.2.6 Timer RB Secondary Register (TRBSC) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W — W (2) — W (2) Address 010Dh Bit b7 Symbol — After Reset 1 Bit Mode b7 to b0 Timer mode Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Function Setting Range Disabled 00h to FFh Counts timer RB prescaler underflows (1) 00h to FFh Disabled Counts timer RB prescaler underflows (one-shot width is counted) 00h to FFh 00h to FFh Notes: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. The count value can be read by reading the TRBPR register even when the secondary period is being counted. When 1 is written to the TSTOP bit in the TRBCR register, the TRBSC register is set to FFh. To write to the TRBSC register, perform the following steps. (1) Write the value into the TRBSC register. (2) Write the value into the TRBPR register. (If the value does not change, write the same value second time.) REJ09B0441-0010 Rev.0.10 Page 260 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.2.7 Timer RB Primary Register (TRBPR) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W R/W R/W R/W R/W Address 010Eh Bit b7 Symbol — After Reset 1 Bit Mode b7 to b0 Timer mode Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Function Setting Range Counts timer RB prescaler underflows. 00h to FFh Counts timer RB prescaler underflows. (1) 00h to FFh Counts timer RB prescaler underflows (one-shot width is counted) Counts timer RB prescaler underflows (wait period width is counted) 00h to FFh 00h to FFh Note: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. When 1 is written to the TSTOP bit in the TRBCR register, the TRBPR register is set to FFh. 19.2.8 Timer RB/RC Pin Select Register (TRBRCSR) b5 — Address 0181h Bit b7 b6 TRCTRGSEL1 TRCTRGSEL0 Symbol After Reset 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b4 TRCCLKSEL0 b3 — b2 — b1 — b0 — 0 0 0 0 0 0 R/W — Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — TRCCLKSEL0 TRCCLK pin select bit 0: TRCCLK pin not used 1: TRCCLK pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 b6 TRCTRGSEL0 TRCTRG pin select bit 0 0: TRCTRG pin not used TRCTRGSEL1 0 1: P3_7 assigned 1 0: P4_3 assigned 1 1: P4_4 assigned R/W — R/W R/W The register function for timer RB is not implemented. To use the I/O pins for timer RC, set the TRBRCSR register. Set this register before setting the timer RC associated registers. Also, do not change the setting value of the TRCCLKSEL0 bit during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 261 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.3 Timer Mode In timer mode, a internally generated count source or timer RA underflows are counted (refer to Table 19.2). Registers TRBOCR and TRBSC are not used in this mode. Table 19.2 Timer Mode Specifications Item Count sources Count operations Specification f1, f2, f8, timer RA underflow • Decrement • When the timer underflows, it reloads the reload register content before the count continues (when timer RB underflows, the content of timer RB primary reload register is reloaded). 1/(n+1)(m+1) n: Value set in TRBPRE register, m: Value set in TRBPR register 1 (count starts) is written to the TSTART bit in the TRBCR register. • 0 (count stops) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. When timer RB underflows [timer RB interrupt]. Programmable I/O port Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE and TRBPR are written during count operation: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 19.3.2 Timer Write Control during Count Operation.) Division ratio Count start condition Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin function Read from timer Write to timer 19.3.1 Timer RB I/O Control Register (TRBIOC) in Timer Mode b6 — 0 b5 — 0 b4 — 0 b3 b2 INOSEG INOSTG 0 0 b1 TOCNT 0 b0 TOPL 0 R/W R/W R/W R/W R/W — Address 010Ah Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TOPL TOCNT INOSTG INOSEG — — — — Bit Name Function Timer RB output level select bit Set to 0 in timer mode. Timer RB output switch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. REJ09B0441-0010 Rev.0.10 Page 262 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.3.2 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter value is not updated immediately after the WRITE instruction is executed. If the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted when the prescaler value changes. Figure 19.2 shows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation. REJ09B0441-0010 Rev.0.10 Page 263 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB When the TWRC bit is set to 0 (write to reload register and counter) Write 01h into the TRBPRE register and 25h into the TRBPR register by a program. Count source After writing, the reload register is written with the first count source. Reloads register of timer RB prescaler Previous value Reload with the second count source Reload at underflow New value (01h) Counter of timer RB prescaler 06h 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h After writing, the reload register is written at the first underflow. Reloads register of timer RB Previous value New value (25h) Reload at the second underflow Counter of timer RB 03h 02h 25h 24h IR bit in TRBIC register 0 The IR bit remains unchanged until underflow is generated by a new value. When the TWRC bit is set to 1 (write to reload register only) Write 01h into the TRBPRE register and 25h into the TRBPR register by a program. Count source After writing, the reload register is written with the first count source. Reloads register of timer RB prescaler Previous value New value (01h) Reload at underflow Counter of timer RB prescaler 06h 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h 01h 00h 01h After writing, the reload register is written at the first underflow. Reloads register of timer RB Previous value New value (25h) Reload at underflow Counter of timer RB 03h 02h 01h 00h 25h IR bit in TRBIC register 0 Only the prescaler values are updated, extending the duration until timer RB underflows. The above applies under the following condition: Both the TSTART and TCSTF bits in the TRBCR register are set to 1 (during count operation). Figure 19.2 Operating Example of Timer RB when Counter Value is Rewritten during Count Operation REJ09B0441-0010 Rev.0.10 Page 264 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.4 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 19.3). Counting starts by counting the setting value of the TRBPR register. The TRBOCR register is unused in this mode. Figure 19.3 shows an Operating Example in Timer RB in Programmable Waveform Generation Mode. Table 19.3 Programmable Waveform Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement • When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Primary period: (n+1)(m+1)/fi Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Frequency of count source n: Value set in TRBPRE register m: Value set in TRBPR register p: Value set in TRBSC register 1 (count starts) is written to the TSTART bit in the TRBCR register. • 0 (count stops) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. In half a cycle of the count source, after timer RB underflows during the secondary period (at the same time as the TRBO output change) [timer RB interrupt] Programmable output port or pulse output Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE (1). • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only. (2) • Output level select function The output level during primary and secondary periods is selected by the TOPL bit in the TRBIOC register. Item Count sources Count operations Width and period of output waveform Count start condition Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin function Read from timer Write to timer Selectable function Notes: 1. Even when the secondary period is being counted, the TRBPR register may be read. 2. The set values are reflected in the waveform output beginning with the following primary period after writing to the TRBPR register. REJ09B0441-0010 Rev.0.10 Page 265 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.4.1 Timer RB I/O Control Register (TRBIOC) in Programmable Waveform Generation Mode b6 — 0 b5 — 0 b4 — 0 b3 b2 INOSEG INOSTG 0 0 b1 TOCNT 0 b0 TOPL 0 R/W R/W Address 010Ah Bit b7 Symbol — After Reset 0 Bit b0 Symbol TOPL b1 b2 b3 b4 b5 b6 b7 Function 0: High-level output for the primary period, low-level output for the secondary period Low-level output when the timer is stopped 1: Low-level output for the primary period, high-level output for the secondary period High-level output when the timer is stopped TOCNT Timer RB output switch bit 0: Timer RB waveform is output 1: P11_6 port latch value is output INOSTG One-shot trigger control bit Set to 0 in programmable waveform generation mode. INOSEG One-shot trigger polarity select bit — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — Bit Name Timer RB output level select bit R/W R/W R/W — REJ09B0441-0010 Rev.0.10 Page 266 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.4.2 Operating Example Set to 1 by a program. TSTART bit in TRBCR register 1 0 Count source Underflow signal of Timer RB prescaler Timer RB secondary reload Timer RB primary reload Counter of timer RB 01h 00h 02h 01h 00h 01h 00h 02h Set to 0 when an interrupt request is acknowledged or by a program. IR bit in TRBIC register 1 0 Set to 0 by a program. TOPL bit in TRBIO register 1 0 Waveform output starts Waveform output inverted Waveform output starts 1 TRBO pin output 0 Primary period Secondary period Primary period The initial output is the same level as during the secondary period. The above applies under the following conditions: TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TOCNT in TRBIOC register = 0 (timer RB waveform output from the TRBO pin) Figure 19.3 Operating Example in Timer RB in Programmable Waveform Generation Mode REJ09B0441-0010 Rev.0.10 Page 267 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.5 Programmable One-shot Generation Mode In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 19.4). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode. Figure 19.4 shows an Operating Example in Programmable One-Shot Generation Mode. Table 19.4 Programmable One-Shot Generation Mode Specifications f1, f2, f8, timer RA underflow • The setting value of the TRBPR register is decremented. • When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops). • When the count stops, the timer reloads the content of the reload register before it stops. One-shot pulse (n+1)(m+1)/fi output time fi: Frequency of count source n: Value set in TRBPRE register, m: Value set in TRBPR register Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated. • 1 (one-shot starts) is written to the TOSST bit in the TRBOCR register. • Trigger input to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during the primary period • 1 (one-shot stops) is written to the TOSSP bit in the TRBOCR register. • 0 (count stops) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. Interrupt request In half a cycle of the count source, after the timer underflows (at the same time as generation timing the waveform output from the TRBO pin ends) [timer RB interrupt] TRBP pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input • When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE and TRBPR are written during count operation, values are written to the reload register only (1). • Output level select function The output level of the one-shot pulse waveform is selected by the TOPL bit in the TRBIOC register. • One-shot trigger select function Refer to 19.5.3 One-Shot Trigger Selection. Item Count sources Count operations Specification Read from timer Write to timer Selectable functions Note: 1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register. REJ09B0441-0010 Rev.0.10 Page 268 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode b6 — 0 b5 — 0 b4 — 0 b3 b2 INOSEG INOSTG 0 0 b1 TOCNT 0 b0 TOPL 0 R/W R/W Address 010Ah Bit b7 Symbol — After Reset 0 Bit b0 Symbol TOPL Bit Name Timer RB output level select bit b1 b2 b3 b4 b5 b6 b7 TOCNT Timer RB output switch bit INOSTG One-shot trigger control bit (1) Function 0: High-level output of a one-shot pulse, low-level output when the timer is stopped 1: Low-level output of a one-shot pulse, high-level output when the timer is stopped Set to 0 in programmable one-shot generation mode. R/W R/W R/W — 0: INT0 pin one-shot trigger disabled 1: INT0 pin one-shot trigger enabled INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger 1: Rising edge trigger — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — Note: 1. Refer to 19.5.3 One-Shot Trigger Selection. REJ09B0441-0010 Rev.0.10 Page 269 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.5.2 Operating Example Set to 1 by a program. TSTART bit in TRBCR register 1 0 Set to 1 by a program. Set to 0 when count ends. Set to 1 by INT0 pin input trigger TOSSTF bit in TRBOCR register 1 0 INT0 pin input Count source Underflow signal of timer RB prescaler Count starts Timer RB primary reload Count starts Timer RB primary reload Counter of timer RB 01h 00h 01h 00h 01h Set to 0 when an interrupt request is acknowledged or by a program. IR bit in TRBIC register 1 0 Set to 0 by a program. TOPL bit in TRBIOC register 1 0 Waveform output starts Waveform output ends Waveform output starts Waveform output ends 1 TRBIO pin output 0 The above applies under the following conditions: TRBPRE = 01h, TRBPR = 01h TOPL in TRBIOC register = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at the rising edge) Figure 19.4 Operating Example in Programmable One-Shot Generation Mode REJ09B0441-0010 Rev.0.10 Page 270 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.5.3 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes: • 1 is written to the TOSST bit in the TRBOCR register by a program. • Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings: • Set the PD4_5 bit in the PD4 register to 0 (input port). • Select the INT0 digital filter with bits INT0F0 and INT0F1 in the INTF register. • Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select falling or rising edge with the INOSEG bit in TRBIOC register. • Set the INT0EN bit in the INTEN register to 0 (enabled). • After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin. • Processing to handle the interrupts is required. Refer to 12. Interrupts, for details. • If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts). • If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes. REJ09B0441-0010 Rev.0.10 Page 271 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.6 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 19.5). When a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value of the TRBSC register after waiting for a given length of time equal to the setting value of the TRBPR register. Figure 19.5 shows an Operating Example in Programmable Wait One-Shot Generation Mode. Table 19.5 Programmable Wait One-Shot Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • The setting value of the timer RB primary is decremented. • When a count of the timer RB primary underflows, the timer reloads the contents of timer RB secondary before the count continues. • When a count of the timer RB secondary underflows, the timer reloads the contents of timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops). • When the count stops, the timer reloads the content of the reload register before it stops. (n+1)(m+1)/fi fi: Frequency of count source n: Value set in TRBPRE register, m: Value set in TRBPR register (n+1)(p+1)/fi fi: Frequency of count source n: Value set in TRBPRE register, p: Value set in TRBSC register • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated. • 1 (one-shot starts) is written to the TOSST bit in the TRBOCR register. • Trigger input to the INT0 pin • When reloading completes after timer RB underflows during the secondary period. • 1 (one-shot stops) is written to the TOSSP bit in the TRBOCR register. • 0 (count stops) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. In half a cycle of the count source after timer RB underflows during secondary period (at the same time as the waveform output from the TRBO pin ends) [timer RB interrupt]. Pulse output • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input • When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE, TRBSC, and TRBPR are written during count operation, values are written to the reload registers only. (1) • Output level select function The output level of the one-shot pulse waveform is selected by the TOPL bit in the TRBIOC register. • One-shot trigger select function Refer to 19.5.3 One-Shot Trigger Selection. Item Count sources Count operations Wait time One-shot pulse output time Count start conditions Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin functions Read from timer Write to timer Selectable functions Note: 1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR. REJ09B0441-0010 Rev.0.10 Page 272 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode b6 — 0 b5 — 0 b4 — 0 b3 b2 INOSEG INOSTG 0 0 b1 TOCNT 0 b0 TOPL 0 R/W R/W Address 010Ah Bit b7 Symbol — After Reset 0 Bit b0 Symbol TOPL Bit Name Timer RB output level select bit b1 b2 b3 b4 b5 b6 b7 TOCNT Timer RB output switch bit INOSTG One-shot trigger control bit (1) Function 0: High-level output of a one-shot pulse, low-level output when the timer stops or during wait 1: Low-level output of a one-shot pulse, low-level output when the timer stops or during wait Set to 0 in programmable wait one-shot generation mode. R/W R/W R/W — 0: INT0 pin one-shot trigger disabled 1: INT0 pin one-shot trigger enabled INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger 1: Rising edge trigger — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — Note: 1. Refer to 19.5.3 One-Shot Trigger Selection. REJ09B0441-0010 Rev.0.10 Page 273 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.6.2 Operating Example Set to 1 by a program. TSTART bit in TRBCR register 1 0 Set to 1 by setting 1 to the TOSST bit in the TRBOCR register, or INT0 pin input trigger. Set to 0 when count ends. TOSSTF bit in TRBOCR register 1 0 INT0 pin input Count source Underflow signal of Timer RB prescaler Count starts Timer RB secondary reload Timer RB primary reload Counter of timer RB 01h 00h 04h 03h 02h 01h 00h 01h Set to 0 when an interrupt request is acknowledged or by an program. IR bit in TRBIC register 1 0 Set to 0 by a program. TOPL bit in TRBIOC register 1 0 Wait starts Waveform output starts Waveform output ends 1 TRBIO pin output 0 Wait (primary period) One-shot pulse (secondary period) The above applies under the following conditions: TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at the rising edge) Figure 19.5 Operating Example in Programmable Wait One-Shot Generation Mode REJ09B0441-0010 Rev.0.10 Page 274 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.7 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time in the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR register to 1 (oneshot stops), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. • The TCSTF bit remains 0 (count stops) for one or two cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts counting at the first active edge of the count source after the TCSTF bit is set to 1 (during count operation). The TCSTF bit remains 1 for one or two cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Note: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR • When the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. • When 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. When 1 is written to the TOSSP bit during the period between when 1 is written to the TOSST bit and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, when 1 is written to the TOSST bit during the period between when 1 is written to the TOSSP bit and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1. 19.7.1 Timer Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. 19.7.2 Programmable Waveform Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. REJ09B0441-0010 Rev.0.10 Page 275 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB 19.7.3 Programmable One-Shot Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously during count operation, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously during count operation, allow three or more cycles of the prescaler underflow for each write interval. 19.7.4 Programmable Wait One-shot Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. REJ09B0441-0010 Rev.0.10 Page 276 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20. Timer RC Timer RC is a 16-bit timer with four I/O pins. 20.1 Introduction Timer RC uses either f1 or fOCO40M as its operating clock. Table 20.1 lists the Timer RC Operating Clocks. Table 20.1 Timer RC Operating Clocks Condition The count source is f1, f2, f4, f8, f32, or TRCCLK input. (Bits TCK2 to TCK0 in the TRCCR1 register are set to 000b to 101b.) The count source is fOCO40M. (Bits TCK2 to TCK0 in the TRCCR1 register are set to 110b.) Timer RC Operating Clock f1 fOCO40M Table 20.2 lists the Timer RC Pin Configuration. Figure 20.1 shows the Timer RC Block Diagram. Timer RC supports the following three modes: • Timer mode - Input capture function The counter value is captured to a register, using an external signal as the trigger. - Output compare function A match between the values of a counter and a register is detected. (Pin output can be changed at detection.) The following two modes use the output compare function: • PWM mode Pulses of a given width are output continuously. • PWM2 mode A one-shot waveform or PWM waveform is output following the trigger after the wait time has elapsed. For the input capture function, the output compare function, and in PWM mode, settings may be selected independently for each pin. In PWM2 mode, waveforms are output based on a combination of the counter or the register. REJ09B0441-0010 Rev.0.10 Page 277 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC f1, f2, f4, f8, f32, fOCO40M TRCMR register TRCCR1 register TRCIER register TRCSR register TRCIOR0 register TRCIOR1 register TRC register Data bus INT0 Count source select circuit TRCCLK TRCIOA/TRCTRG TRCIOB Timer RC control circuit TRCIOC TRCIOD TRCGRA register TRCGRB register TRCGRC register TRCGRD register TRCCR2 register TRCDF register TRCOER register TRCADCR register Timer RC interrupt request Figure 20.1 Timer RC Block Diagram Table 20.2 Timer RC Pin Configuration Pin Name TRCIOA TRCIOB TRCIOC TRCIOD TRCCLK TRCTRG P4_4 Assigned Pin I/O I/O Function Function differs according to the mode. Refer to descriptions of individual modes for details. P4_5, P4_6, or P4_7 P4_6 P4_7 P4_3 P3_7, P4_3, or P4_4 Input Input External clock input PWM2 mode external trigger input REJ09B0441-0010 Rev.0.10 Page 278 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2 Registers Table 20.3 lists the Registers Associated with Timer RC. Table 20.3 Registers Associated with Timer RC Mode Timer Address Symbol Input Output PWM Capture Compare Function Function 0008h MSTCR Valid Valid Valid 0120h TRCMR Valid Valid Valid 0121h TRCCR1 Valid Valid Valid PWM2 Valid Valid Valid Related Information 0122h 0123h 0124h TRCIER Valid TRCSR Valid TRCIOR0 Valid Valid Valid Valid Valid Valid − Valid Valid − 0125h TRCIOR1 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0181h 0182h 0183h −: Invalid TRC Valid Valid Valid Valid Valid Valid Valid 20.2.1 Module Standby Control Register (MSTCR) 20.2.2 Timer RC Mode Register (TRCMR) Timer RC control register 1 20.2.3 Timer RC Control Register 1 (TRCCR1) 20.5.1 Timer RC Control Register 1 (TRCCR1) in Timer Mode (Output Compare Function) 20.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode 20.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode 20.2.4 Timer RC Interrupt Enable Register (TRCIER) 20.2.5 Timer RC Status Register (TRCSR) Timer RC I/O control register 0, timer RC I/O control register 1 20.2.6 Timer RC I/O Control Register 0 (TRCIOR0) 20.2.7 Timer RC I/O Control Register 1 (TRCIOR1) 20.4.1 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Input Capture Function) 20.4.2 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Input Capture Function) 20.5.2 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Output Compare Function) 20.5.3 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Output Compare Function) 20.2.8 Timer RC Counter (TRC) 20.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) TRCGRA Valid TRCGRB TRCGRC TRCGRD TRCCR2 − TRCDF Valid TRCOER − TRCADCR − TRBRCSR Valid TRCPSR0 Valid TRCPSR1 Valid − − − − Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid 20.2.10 Timer RC Control Register 2 (TRCCR2) 20.2.11 Timer RC Digital Filter Function Select Register (TRCDF) 20.2.12 Timer RC Output Master Enable Register (TRCOER) 20.2.13 Timer RC Trigger Control Register (TRCADCR) 20.2.14 Timer RB/RC Pin Select Register (TRBRCSR) 20.2.15 Timer RC Pin Select Register 0 (TRCPSR0) 20.2.16 Timer RC Pin Select Register 1 (TRCPSR1) REJ09B0441-0010 Rev.0.10 Page 279 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. REJ09B0441-0010 Rev.0.10 Page 280 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.2 Timer RC Mode Register (TRCMR) b6 — 1 b5 BFD 0 b4 BFC 0 b3 PWM2 1 b2 PWMD 0 b1 PWMC 0 b0 PWMB 0 R/W R/W R/W R/W R/W R/W R/W — R/W Address 0120h Bit b7 Symbol TSTART After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PWMB Function 0: Timer mode 1: PWM mode 0: Timer mode PWMC PWM mode of TRCIOC select bit (1) 1: PWM mode PWMD PWM mode of TRCIOD select bit (1) 0: Timer mode 1: PWM mode PWM2 PWM2 mode select bit 0: PWM 2 mode 1: Timer mode or PWM mode BFC TRCGRC register function select bit (2) 0: General register 1: Buffer register of TRCGRA register BFD TRCGRD register function select bit 0: General register 1: Buffer register of TRCGRB register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. TSTART TRC count start bit 0: Count stops 1: Count starts Bit Name PWM mode of TRCIOB select bit (1) Notes: 1. These bits are enabled when the PWM2 bit is set to 1 (timer mode or PWM mode). 2. Set the BFC bit to 0 (general register) in PWM2 mode. For notes on the TRCMR register in PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. REJ09B0441-0010 Rev.0.10 Page 281 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.3 Timer RC Control Register 1 (TRCCR1) b6 TCK2 0 b5 TCK1 0 b4 TCK0 0 b3 TOD 0 b2 TOC 0 b1 TOB 0 b0 TOA 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 0121h Bit b7 Symbol CCLR After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 Symbol TOA TOB TOC TOD TCK0 TCK1 TCK2 Bit Name TRCIOA output level select bit (1) TRCIOB output level select bit (1) TRCIOC output level select bit (1) TRCIOD output level select bit (1) Count source select bit (1) Function Function varies according to the operating mode (function). b6 b5 b4 b7 CCLR TRC counter clear select bit 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: fOCO-F (2) 0: Clear disabled (free-running operation) 1: TRC counter cleared by input capture or by compare match with the TRCGRA register R/W Note: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency. 20.2.4 Timer RC Interrupt Enable Register (TRCIER) b6 — 1 b5 — 1 b4 — 1 b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W — Address 0122h Bit b7 Symbol OVIE After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IMIEA IMIEB IMIEC IMIED — — — OVIE Bit Name Function Input-capture/compare-match interrupt 0: Interrupt (IMIA) by IMFA bit disabled enable bit A 1: Interrupt (IMIA) by IMFA bit enabled Input-capture/compare-match interrupt 0: Interrupt (IMIB) by IMFB bit disabled enable bit B 1: Interrupt (IMIB) by IMFB bit enabled Input-capture/compare-match interrupt 0: Interrupt (IMIC) by IMFC bit disabled enable bit C 1: Interrupt (IMIC) by IMFC bit enabled Input-capture/compare-match interrupt 0: Interrupt (IMID) by IMFD bit disabled enable bit D 1: Interrupt (IMID) by IMFD bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. Overflow interrupt enable bit 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W REJ09B0441-0010 Rev.0.10 Page 282 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.5 Timer RC Status Register (TRCSR) b6 — 1 b5 — 1 b4 — 1 b3 IMFD 0 b2 IMFC 0 b1 IMFB 0 b0 IMFA 0 R/W R/W R/W R/W R/W — Address 0123h Bit b7 Symbol OVF After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IMFA IMFB IMFC IMFD — — — OVF Function [Condition for setting to 0] Write 0 after reading. (1) [Condition for setting to 1] Refer to Table 20.4 Conditions for Setting Bit of Each Flag to 1. Nothing is assigned. If necessary, set to 0. When read, the content is 1. Bit Name Input-capture/compare-match flag A Input-capture/compare-match flag B Input-capture/compare-match flag C Input-capture/compare-match flag D Overflow flag [Condition for setting to 0] Write 0 after reading. (1) [Condition for setting to 1] Refer to Table 20.4 Conditions for Setting Bit of Each Flag to 1. R/W Note: 1. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it.) • The bit’s value remains unchanged if 1 is written to it. Table 20.4 Bit Symbol IMFA IMFB IMFC IMFD OVF Conditions for Setting Bit of Each Flag to 1 Timer Mode PWM Mode PWM2 Mode Input capture Function Output Compare Function When the values of registers TRC and TRCGRA match. TRCIOA pin input edge (1) TRCIOB pin input edge (1) TRCIOC pin input edge (1) When the values of registers TRC and TRCGRB match. When the values of registers TRC and TRCGRC match. (2) TRCIOD pin input edge (1) When the values of registers TRC and TRCGRD match. (2) When the TRC register overflows. Notes: 1. Edge selected by bits IOj0 and IOj1 (j = A, B, C, or D) in registers TRCIOR0 and TRCIOR1. 2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB). REJ09B0441-0010 Rev.0.10 Page 283 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.6 Timer RC I/O Control Register 0 (TRCIOR0) b6 IOB2 0 b5 IOB1 0 b4 IOB0 0 b3 — 1 b2 IOA2 0 b1 IOA1 0 b0 IOA0 0 R/W R/W R/W R/W R/W R/W R/W R/W — Address 0124h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IOA0 TRCGRA control bit IOA1 IOA2 TRCGRA mode select bit (1) — IOB0 IOB1 IOB2 — Function Function varies according to the operating mode (function). 0: Output compare function 1: Input capture function Reserved bit Set to 1. TRCGRB control bit Function varies according to the operating mode (function). (2) 0: Output compare function TRCGRB mode select bit 1: Input capture function Nothing is assigned. If necessary, set to 0. When read, the content is 1. Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The TRCIOR0 register is enabled in timer mode. It is disabled in PWM mode and PWM2 mode. 20.2.7 Timer RC I/O Control Register 1 (TRCIOR1) b6 IOD2 0 b5 IOD1 0 b4 IOD0 0 b3 IOC3 1 b2 IOC2 0 b1 IOC1 0 b0 IOC0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0125h Bit b7 Symbol IOD3 After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IOC0 TRCGRC control bit IOC1 IOC2 TRCGRC mode select bit (1) IOC3 IOD0 IOD1 IOD2 IOD3 TRCGRC register function select bit TRCGRD control bit TRCGRD mode select bit (2) TRCGRD register function select bit Function Function varies according to the operating mode (function). 0: Output compare function 1: Input capture function 0: TRCIOA output register 1: General register or buffer register Function varies according to the operating mode (function). 0: Output compare function 1: Input capture function 0: TRCIOB output register 1: General register or buffer register Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The TRCIOR1 register is enabled in timer mode. It is disabled in PWM mode and PWM2 mode. REJ09B0441-0010 Rev.0.10 Page 284 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.8 Timer RC Counter (TRC) b5 — 0 b13 — 0 b4 — 0 b12 — 0 b3 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Address 0127h to 0126h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 Bit Function b15 to b0 Counts a count source. Count operation is increment. When an overflow occurs, the OVF bit in the TRCSR register is set to 1. Access the TRC register in 16-bit units. Do not access it in 8-bit units. 20.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) Address 0129h to 0128h (TRCGRA), 012Bh to 012Ah (TRCGRB), 012Dh to 012Ch (TRCGRC), 012Fh to 012Eh (TRCGRD) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Function varies according to the operating mode. Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units. REJ09B0441-0010 Rev.0.10 Page 285 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.10 Timer RC Control Register 2 (TRCCR2) Address 0130h Bit b7 Symbol TCEG1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 TCEG0 0 b5 CSEL 0 b4 — 1 b3 — 1 b2 POLD 0 b1 POLC 0 b0 POLB 0 R/W R/W R/W R/W — R/W b6 b7 Symbol Bit Name Function 0: TRCIOB output level selected as low active POLB PWM mode output level 1: TRCIOB output level selected as high active control bit B (1) POLC PWM mode output level 0: TRCIOC output level selected as low active 1: TRCIOC output level selected as high active control bit C (1) POLD PWM mode output level 0: TRCIOD output level selected as low active 1: TRCIOD output level selected as high active control bit D (1) — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — 0: Count continues at compare match with CSEL TRC count operation select bit (2) the TRCGRA register 1: Count stops at compare match with the TRCGRA register b7 b6 TCEG0 TRCTRG input edge select bit (3) 0 0: Trigger input from the TRCTRG pin disabled TCEG1 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W R/W Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode, these bits are disabled. 20.2.11 Timer RC Digital Filter Function Select Register (TRCDF) Address 0131h Bit b7 Symbol DFCK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 DFCK0 0 b5 — 0 b4 DFTRG 0 b3 DFD 0 b2 DFC 0 b1 DFB 0 b0 DFA 0 R/W R/W R/W R/W R/W R/W — R/W R/W Symbol Bit Name Function DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFB TRCIOB pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFC TRCIOC pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFD TRCIOD pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFTRG TRCTRG pin digital filter function select bit (2) 0: Function is not used 1: Function is used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 b6 DFCK0 Digital filter function clock select bit (1, 2) 0 0: f32 DFCK1 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK0 to TCK2 in the TRCCR1 register) Notes: 1. These bits are enabled for the input capture function. 2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). REJ09B0441-0010 Rev.0.10 Page 286 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.12 Timer RC Output Master Enable Register (TRCOER) Address 0132h Bit b7 Symbol PTO After Reset 0 Bit b0 b6 — 1 b5 — 1 b4 — 1 b3 ED 1 b2 EC 1 b1 EB 1 b0 EA 1 R/W R/W Symbol Bit Name EA TRCIOA output disable bit (1) b1 EB b2 EC b3 ED b4 b5 b6 b7 — — — PTO Function 0: Output enabled 1: Output disabled (TRCIOA pin functions as a programmable I/O port) (1) 0: Output enabled TRCIOB output disable bit 1: Output disabled (TRCIOB pin functions as a programmable I/O port) 0: Output enabled TRCIOC output disable bit (1) 1: Output disabled (TRCIOC pin functions as a programmable I/O port) (1) 0: Output enabled TRCIOD output disable bit 1: Output disabled (TRCIOD pin functions as a programmable I/O port) Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W — INT0 of pulse output forced cutoff signal input enabled bit 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (Bits EA, EB, EC, and ED are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin) R/W Note: 1. These bits are disabled for pins set as input-capture input. 20.2.13 Timer RC Trigger Control Register (TRCADCR) Address 0133h Bit b7 Symbol — After Reset 0 Bit b0 b6 — 0 b5 — 0 b4 — 0 b3 b2 b1 b0 ADTRGDE ADTRGCE ADTRGBE ADTRGAE 0 0 0 0 R/W R/W b1 b2 b3 b4 b5 b6 b7 Function 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRA ADTRGBE A/D trigger B enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRB ADTRGCE A/D trigger C enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRC ADTRGDE A/D trigger D enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRD — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — Symbol Bit Name ADTRGAE A/D trigger A enable bit R/W R/W R/W — REJ09B0441-0010 Rev.0.10 Page 287 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.14 Timer RB/RC Pin Select Register (TRBRCSR) Address 0181h Bit b7 b6 Symbol TRCTRGSEL1 TRCTRGSEL0 After Reset 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b5 — b4 TRCCLKSEL0 b3 — b2 — b1 — b0 — 0 0 0 0 0 0 R/W — Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — TRCCLKSEL0 TRCCLK pin select bit 0: TRCCLK pin not used 1: TRCCLK pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 b6 TRCTRGSEL0 TRCTRG pin select bit 0 0: TRCTRG pin not used TRCTRGSEL1 0 1: P3_7 assigned 1 0: P4_3 assigned 1 1: P4_4 assigned R/W — R/W R/W The register function for timer RB is not implemented. To use the I/O pins for timer RC, set the TRBRCSR register. Set this register before setting the timer RC associated registers. Also, do not change the setting value of the TRCCLKSEL0 bit during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 288 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.15 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 — 0 b5 b4 TRCIOBSEL1 TRCIOBSEL0 0 0 b3 — 0 b2 — 0 b1 — 0 b0 TRCIOASEL0 0 R/W R/W — Symbol Bit Name TRCIOASEL0 TRCIOA pin select bit — — — TRCIOBSEL0 TRCIOB pin select bit TRCIOBSEL1 Function 0: TRCIOA pin not used 1: TRCIOA pin used Nothing is assigned. If necessary, set to 0. When read, the content is 0. b5 b4 b6 b7 — — 0 0: TRCIOB pin not used 0 1: P4_5 assigned 1 0: P4_6 assigned 1 1: P4_7 assigned Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W — The TRCPSR0 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 289 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.2.16 Timer RC Pin Select Register 1 (TRCPSR1) Address 0183h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 — 0 b5 — 0 b4 TRCIODSEL0 0 b3 — 0 b2 — 0 b1 — 0 b0 TRCIOCSEL0 0 R/W R/W — Symbol Bit Name TRCIOCSEL0 TRCIOC pin select bit (1) — — — TRCIODSEL0 TRCIOD pin select bit (2) — — — Function 0: TRCIOC pin not used 1: P4_6 assigned Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0: TRCIOD pin not used 1: P4_7 assigned Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W — Notes: 1. When bits TRCIOBSEL1 to TRCIOBSEL0 in the TRCPSR0 register are set to 10b (P4_6 assigned as TRCIOB pin), P4_6 functions as the TRCIOB pin regardless of the content of the TRCIOCSEL0 bit. 2. When bits TRCIOBSEL1 to TRCIOBSEL0 in the TRCPSR0 register are set to 11b (P4_7 assigned as TRCIOB pin), P4_7 functions as the TRCIOB pin regardless of the content of the TRCIODSEL0 bit. The TRCPSR1 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. REJ09B0441-0010 Rev.0.10 Page 290 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.3 20.3.1 Common Items for Multiple Modes Count Source The method of selecting the count source is common to all modes. Table 20.5 lists the Count Source Selection, and Figure 20.2 shows the Count Source Block Diagram. Table 20.5 Count Source Selection Selection Method The count source is selected by bits TCK0 to TCK2 in TRCCR1 register - The FRA00 bit in the FRA0 register set to 1 (high-speed on-chip oscillator on). - Bits TCK2 to TCK0 in the TRCCR1 register are set to 110b (fOCO40M). External signal input - Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising to TRCCLK pin edge of external clock) - The corresponding direction bit in the direction register is set is set to 0 (input mode) Count Source f1, f2, f4, f8, f32 fOCO40M f1 f2 f4 f8 f32 TRCCLK fOCO40M TCK2 to TCK0 = 000b = 001b = 010b = 011b = 100b = 101b = 110b Count source TRC register TCK0 to TCK2: Bits in TRCCR1 register Figure 20.2 Count Source Block Diagram The pulse width of the external clock input to the TRCCLK pin should be set to three cycles or more of the timer RC operation clock. (See Table 20.1 Timer RC Operating Clocks.) To select fOCO40M as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M). REJ09B0441-0010 Rev.0.10 Page 291 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.3.2 Buffer Operation Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer register of the TRCGRA or TRCGRB register. • Buffer register of TRCGRA register: TRCGRC register • Buffer register of TRCGRB register: TRCGRD register Buffer operation differs depending on the mode. Table 20.6 lists the Buffer Operation in Each Mode, Figure 20.3 shows the Buffer Operation of Input Capture Function, and Figure 20.4 shows the Buffer Operation of Output Compare Function. Table 20.6 Buffer Operation in Each Mode Transfer Destination Register The content of the TRCGRA (TRCGRB) register is transferred to the buffer register. Output compare function Compare match between the TRC The content of the buffer register is register and the TRCGRA (TRCGRB) transferred to the TRCGRA PWM mode register (TRCGRB) register. PWM2 mode • Compare match between the TRC The content of the buffer register register and the TRCGRA register (TRCGRD) is transferred to the • TRCTRG pin trigger input TRCGRB register. Function, Mode Input capture function Transfer Timing Input capture signal input TRCIOA input (input capture signal) TRCGRC register TRCGRA register TRC TRCIOA input TRC register n-1 n Transfer n+1 TRCGRA register m Transfer n TRCGRC register (buffer) m The above applies under the following conditions: • The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register of the TRCGRA register). • Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge). Figure 20.3 Buffer Operation of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 292 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC Compare match signal TRCGRC register TRCGRA register Comparator TRC TRC register m-1 m m+1 TRCGRA register m Transfer n TRCGRC register (buffer) n TRCIOA output The above applies under the following conditions: • The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register of the TRCGRA register). • Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (low-level output at compare match). Figure 20.4 Buffer Operation of Output Compare Function Make the following settings in timer mode. • To use the TRCGRC register as the buffer register of the TRCGRA register: Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. • To use the TRCGRD register as the buffer register of the TRCGRB register: Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. When the TRCGRC or TRCGRD register is also used as the buffer register for the output compare function, in PWM mode, or PWM2 mode, the IMFC or IMFD bit in the TRCSR register is set to 1 by a compare match with the TRC register. When the TRCGRC register or TRCGRD register is also used as the buffer register for the input capture function, the IMFC or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC or TRCIOD pin. REJ09B0441-0010 Rev.0.10 Page 293 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.3.3 Digital Filter The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is determined when three matches occur. The digital filter function and sampling clock can be selected using the TRCDF register. Figure 20.5 shows a Block Diagram of Digital Filter. TCK2 to TCK0 f1 f2 f4 f8 f32 TRCCLK fOCO40M fOCO-F = 001b = 010b = 011b Count source = 100b = 101b = 110b = 111b = 000b f32 f8 f1 DFCK1 to DFCK0 = 00b = 01b = 10b = 11b IOA2 to IOA0 IOB2 to IOB0 IOC2 to IOC0 IOD2 to IOD0 (or TCEG1 to TCEG0) Sampling clock DFj (or DFTRG) C TRCIOj input signal (or TRCTRG input signal) D Latch Timer RC operating clock f1 or fOCO40M C D Latch Q Q D C Q Latch D C Q Latch D C Q Latch Match detect circuit 1 Edge detect circuit 0 Clock cycle selected by TCK2 to TCK0 (or DFCK1 to DFCK0) Sampling clock TRCIOj input signal (or TRCTRG input signal) Input signal after passing through digital filter Three matches occur and a signal change is confirmed. Maximum signal transmission delay is five sampling clocks. If fewer than three matches occur, the matches are recognized as noise and no transmission is performed. j = A, B, C, or D TCK0 to TCK2: Bits in TRCCR1 register DFTRG, DFCK0, DFCK1, DFj: Bits in TRCDF register IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register TCEG0, TCEG1: Bits in TRCCR2 register Figure 20.5 Block Diagram of Digital Filter REJ09B0441-0010 Rev.0.10 Page 294 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.3.4 Forced Cutoff of Pulse Output When using the timer mode’s output compare function, PWM mode, or PWM2 mode, pulse output from the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a programmable I/O port by means of input to the INT0 pin. A pin used for output by the timer mode’s output compare function, PWM mode, or PWM2 mode can be set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output enabled). If a low-level signal is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1 (timer RC output disabled, TRCIOj output pin functions as a programmable I/O port). When one or two cycles of the timer RC operation clock after a low-level signal input to the INT0 pin (refer to Table 20.1 Timer RC Operating Clocks) has elapsed, the TRCIOj output pin functions as a programmable I/O port. Make the following settings to use this function. • Set the pin state following forced cutoff of pulse output (high impedance (input), low-level output, or highlevel output). (Refer to 7. I/O Ports.) • Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register. • Set the direction registers for the I/O ports selected as INT0 to input mode: When INT0 is assigned to P3_0 by the INT0SEL0 bit in the INTSR register, set the PD3_0 bit in the PD3 register to 0 (input mode). When INT0 is assigned to P11_0 by the INT0SEL0 bit in the INTSR register, set the PD11_0 bit in the PD11 register to 0 (input mode). • Select the INT0 digital filter with bits INT0F0 and INT0F1 in the INTF register. • Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled). The IR bit in the INT0IC register is set to 1 (interrupt requested) in accordance with the setting of the POL bit and a change in the INT0 pin input (refer to 12.8 Notes on Interrupts). For details on interrupts, refer to 12. Interrupts. REJ09B0441-0010 Rev.0.10 Page 295 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC EA bit write value EA bit DQ S Timer RC output data INT0 input PTO bit TRCIOA EB bit write value EB bit DQ S Timer RC output data TRCIOB EC bit write value EC bit DQ S Timer RC output data TRCIOC ED bit write value ED bit DQ S Timer RC output data TRCIOD EA, EB, EC, ED, PTO: Bits in TRCOER register Figure 20.6 Forced Cutoff of Pulse Output REJ09B0441-0010 Rev.0.10 Page 296 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.4 Timer Mode (Input Capture Function) This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A, B, C, or D) pin acts as a trigger for transferring the content of the TRC register (counter) to the TRCGRj register (input capture). The input capture function, or any other mode or function, can be selected for each individual pin. Table 20.7 lists the Input Capture Function Specifications, Figure 20.7 shows a Block Diagram of Input Capture Function, Table 20.8 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 20.8 shows an Operating Example of Input Capture Function. Table 20.7 Input Capture Function Specifications Item Count sources Count operation Count period Count start condition Count stop condition Interrupt request generation timing TRCIOA, TRCIOB, TRCIOC, and TRCIOD pins function INT0 pin function Read from timer Write to timer Selectable functions Specification f1, f2, f4, f8, f32, fOCO40M External signal (rising edge) input to the TRCCLK pin Increment 1/fk × 65,536 fk: Frequency of count source 1 (count starts) is written to the TSTART bit in the TRCMR register. 0 (count stops) is written to the TSTART bit in the TRCMR register. The TRC register retains a value before the count stops. • Input capture (active edge of the TRCIOj input) • TRC register overflows Programmable I/O port or input capture input (selectable for each individual pin) Programmable I/O port or INT0 interrupt input The count value can be read by reading TRC register. The TRC register can be written to. • Input-capture input pin selection One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD • Input-capture input active edge selection Rising edge, falling edge, or both rising and falling edges • Buffer operation (Refer to 20.3.2 Buffer Operation.) • Digital filter (Refer to 20.3.3 Digital Filter.) • Timing for setting the TRC register to 0000h Overflow or input capture j = A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 297 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC Polarity switching Input capture signal (Note 1) TRCGRA register TRC register TRCGRC register Polarity switching TRCIOC Input capture signal TRCIOB Polarity switching Input capture signal (Note 2) TRCGRB register fOCO Divided by 128 fOCO128 IOA3 = 0 Input capture signal TRCGRB register TRCIOD Polarity switching TRCIOA (Note 3) IOA3 = 1 Input capture signal Notes: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register for the TRCGRA register) 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register is used as the buffer register for the TRCGRB register) 3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal. Figure 20.7 Block Diagram of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 298 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.4.1 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Input Capture Function) b6 IOB2 0 b5 IOB1 0 b4 IOB0 0 b3 IOA3 1 b2 IOA2 0 b1 IOA1 0 Function b1 b0 Address 0124h Bit b7 Symbol — After Reset 1 Bit b0 b1 b0 IOA0 0 R/W R/W R/W Symbol Bit Name IOA0 TRCGRA control bit IOA1 b2 b3 b4 b5 IOA2 IOA3 IOB0 IOB1 b6 b7 IOB2 — 0 0: Input capture to the TRCGRA register at the rising edge 0 1: Input capture to the TRCGRA register at the falling edge 1 0: Input capture to the TRCGRA register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. R/W TRCGRA mode select bit (1) 0: fOCO128 signal R/W TRCGRA input-capture input 1: TRCIOA pin input switch bit (3) b5 b4 TRCGRB control bit R/W 0 0: Input capture to the TRCGRB register at the R/W rising edge 0 1: Input capture to the TRCGRB register at the falling edge 1 0: Input capture to the TRCGRB register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. R/W TRCGRB mode select bit (2) Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. 3. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function). REJ09B0441-0010 Rev.0.10 Page 299 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.4.2 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Input Capture Function) b6 IOD2 0 b5 IOD1 0 b4 IOD0 0 b3 IOC3 1 b2 IOC2 0 b1 IOC1 0 Function b1 b0 Address 0125h Bit b7 Symbol IOD3 After Reset 1 Bit b0 b1 b0 IOC0 0 R/W R/W R/W Symbol Bit Name IOC0 TRCGRC control bit IOC1 b2 b3 b4 b5 IOC2 IOC3 IOD0 IOD1 TRCGRC mode select bit (1) TRCGRC register function select bit TRCGRD control bit 0 0: Input capture to the TRCGRC register at the rising edge 0 1: Input capture to the TRCGRC register at the falling edge 1 0: Input capture to the TRCGRC register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. Set to 1. b5 b4 R/W R/W R/W R/W b6 b7 IOD2 IOD3 TRCGRD mode select bit (2) TRCGRD register function select bit 0 0: Input capture to the TRCGRD register at the rising edge 0 1: Input capture to the TRCGRD register at the falling edge 1 0: Input capture to the TRCGRD register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. Set to 1. R/W R/W Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Table 20.8 Functions of TRCGRj Register when Using Input Capture Function Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRC TRCGRD − Setting BFC = 0 BFD = 0 BFC = 1 BFD = 1 Input Capture Input Pin General register. Can be used to read the TRC register value TRCIOA at input capture. TRCIOB General register. Can be used to read the TRC register value TRCIOC at input capture. TRCIOD Buffer registers. Can be used to retain the transferred value TRCIOA from the general register. (Refer to 20.3.2 Buffer Operation.) TRCIOB Register Function j = A, B, C, or D BFC, BFD: Bits in TRCMR register REJ09B0441-0010 Rev.0.10 Page 300 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.4.3 Operating Example TRCCLK input count source TRC register count value FFFFh 0009h 0006h 0000h TSTART bit in TRCMR register 1 0 65,536 TRCIOA input TRCGRA register Transfer TRCGRC register 0006h 0009h Transfer 0006h IMFA bit in TRCSR register OVF bit in TRCSR register 1 0 1 0 Set to 0 by a program. The above applies under the following conditions: • The CCLR bit in the TRCCR1 register is set to 1 (TRC counter cleared by input capture). • Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (TRCCLK input selected as the count source). • Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input). • The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register of the TRCGRA register). Figure 20.8 Operating Example of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 301 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.5 Timer Mode (Output Compare Function) This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D) match (compare match). When a match occurs, a signal is output from the TRCIOj pin at a given level. The output compare function, or other mode or function, can be selected for each individual pin. Table 20.9 lists the Output Compare Function Specifications, Figure 20.9 shows a Block Diagram of Output Compare Function, Table 20.10 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 20.10 shows an Operating Example of Output Compare Function. Table 20.9 Count sources Count operation Count periods Output Compare Function Specifications Item Specification f1, f2, f4, f8, f32, fOCO40M, fOCO-F External signal input to the TRCCLK pin (rising edge) Increment • The CCLR bit in the TRCCR1 register is set to 0 (free-running operation): 1/fk × 65,536 fk: Frequency of count source • The CCLR bit in the TRCCR1 register is set to 1 (TRC register is set to 0000h by TRCGRA compare match): 1/fk × (n + 1) n: Value set in TRCGRA register Compare match 1 (count starts) is written to the TSTART bit in the TRCMR register. • When the CSEL bit in the TRCCR2 register is set to 0 (count continues after compare match with the TRCGRA register). 0 (count stops) is written to the TSTART bit in the TRCMR register. The output compare output pin retains the output level before the count stops, the TRC register retains a value before the count stops. • When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register). The count stops at a compare match with the TRCGRA register. The outputcompare output pin retains the level after the output is changed by the compare match. • Compare match (the contents of the TRC register and the TRCGRj register match.) • TRC register overflow Programmable I/O port or output compare output (selectable for each individual pin) Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRC register. The TRC register can be written to. • Output-compare output pin selection One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD • Output level selection at the compare match Low-level output, High-level output, or toggle output • Initial output level selection Selectable output level for the period from the count start to the compare match • Timing for setting the TRC register to 0000h Overflow or compare match with the TRCGRA register • Buffer operation (Refer to 20.3.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 20.3.4 Forced Cutoff of Pulse Output.) • Timer RC can be used as an internal timer by disabling the timer RC output • Changing output pins for registers TRCGRC and TRCGRD TRCGRC can be used for output control of the TRCIOA pin and TRCGRD can be used for output control of the TRCIOB pin. • A/D trigger generation Waveform output timing Count start condition Count stop condition Interrupt request generation timing TRCIOA, TRCIOB, TRCIOC, and TRCIOD pins function INT0 pin function Read from timer Write to timer Selectable functions j = A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 302 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC TRC Output control Compare match signal Comparator TRCGRA TRCIOA TRCIOC Output control Compare match signal Comparator TRCGRC TRCIOB Output control Compare match signal Comparator TRCGRB TRCIOD Output control Compare match signal Comparator TRCGRD Figure 20.9 Block Diagram of Output Compare Function REJ09B0441-0010 Rev.0.10 Page 303 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.5.1 Timer RC Control Register 1 (TRCCR1) in Timer Mode (Output Compare Function) b6 TCK2 0 b5 TCK1 0 b4 TCK0 0 b3 TOD 0 b2 TOC 0 b1 TOB 0 b0 TOA 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 0121h Bit b7 Symbol CCLR After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 Symbol TOA TOB TOC TOD TCK0 TCK1 TCK2 b7 CCLR Bit Name Function (1, 2) 0: Initial output at low TRCIOA output level select bit TRCIOB output level select bit (1, 2) 1: Initial output at high TRCIOC output level select bit (1, 2) TRCIOD output level select bit (1, 2) b6 b5 b4 Count source select bit (1) 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: Do not set. TRC counter clear select bit 0: Clear disabled (free-running operation) 1: Clear by compare match with the TRCGRA register R/W Notes: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. Table 20.10 Functions of TRCGRj Register when Using Output Compare Function Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRC TRCGRD − Setting Register Function General register. Write a compare value to one of these registers. General register. Write a compare value to one of these registers. Buffer register. Write the next compare value to one of these registers. (Refer to 20.3.2 Buffer Operation.) BFC = 0 BFD = 0 BFC = 1 BFD = 1 Output Compare Output Pin TRCIOA TRCIOB TRCIOC TRCIOD TRCIOA TRCIOB j = A, B, C, or D BFC, BFD: Bits in TRCMR register REJ09B0441-0010 Rev.0.10 Page 304 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.5.2 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Output Compare Function) b6 IOB2 0 b5 IOB1 0 b4 IOB0 0 b3 IOA3 1 b2 IOA2 0 b1 IOA1 0 Function b1 b0 Address 0124h Bit b7 Symbol — After Reset 1 Bit b0 b1 b0 IOA0 0 R/W R/W R/W Symbol Bit Name IOA0 TRCGRA control bit IOA1 b2 b3 b4 b5 IOA2 IOA3 IOB0 IOB1 TRCGRA mode select bit (1) TRCGRA input capture input switch bit TRCGRB control bit 0 0: Pin output by compare match is disabled (TRCIOA pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRCGRA register 1 0: High-level output at compare match with the TRCGRA register 1 1: Toggle output at compare match with the TRCGRA register Set to 0 (output compare) for the output compare function. Set to 1. b5 b4 R/W R/W R/W R/W b6 b7 IOB2 — 0 0: Pin output by compare match is disabled (TRCIOB pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRCGRB register 1 0: High-level output at compare match with the TRCGRB register 1 1: Toggle output at compare match with the TRCGRB register Set to 0 (output compare) for the output compare TRCGRB mode select bit (2) function. Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W — Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. REJ09B0441-0010 Rev.0.10 Page 305 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.5.3 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Output Compare Function) b6 IOD2 0 b5 IOD1 0 b4 IOD0 0 b3 IOC3 1 b2 IOC2 0 b1 IOC1 0 Function b1 b0 Address 0125h Bit b7 Symbol IOD3 After Reset 1 Bit b0 b1 b0 IOC0 0 R/W R/W R/W Symbol Bit Name IOC0 TRCGRC control bit IOC1 b2 b3 b4 b5 IOC2 IOC3 IOD0 IOD1 TRCGRC mode select bit (1) TRCGRC register function select bit TRCGRD control bit 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRCGRC register 1 0: High-level output at compare match with the TRCGRC register 1 1: Toggle output at compare match with the TRCGRC register Set to 0 (output compare) for the output compare function. 0: TRCIOA output register 1: General register or buffer register b5 b4 R/W R/W R/W R/W b6 b7 IOD2 IOD3 TRCGRD mode select bit (2) TRCGRD register function select bit 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRCGRD register 1 0: High-level output at compare match with the TRCGRD register 1 1: Toggle output at compare match with the TRCGRD register Set to 0 (output compare) for the output compare function. 0: TRCIOB output register 1: General register or buffer register R/W R/W Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in theTRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. REJ09B0441-0010 Rev.0.10 Page 306 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.5.4 Operating Example Count source TRC register value m n p Count restarts Count stops TSTART bit in TRCMR register 1 0 m+1 m+1 Output level held TRCIOA output Output inverted at compare match Initial output “L” IMFA bit in TRCSR register 1 0 Set to 0 by a program. n+1 TRCIOB output Output level held “H” output at compare match Initial output “L” 1 0 Set to 0 by a program. P+1 “L” output at compare match Output level held IMFB bit in TRCSR register TRCIOC output Initial output “H” IMFC bit in TRCSR register 1 0 Set to 0 by a program. m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register The above applies under the following conditions: • Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers). • Bits EA, EB, and EC in the TRCOER register are set to 0 (TRCIOA, TRCIOB, and TRCIOC pin output enabled). • The CCLR bit in the TRCCR1 register is set to 1 (TRC register is set to 0000h by compare match with TRCGRA register ). • Bits TOA and TOB in the TRCCR1 register are are set to 0 (initial output at low until compare match) and the TOC bit is set to 1 (initial output at high until compare match). • Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted by TRCGRA compare match). • Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (TRCIOB high-level output at TRCGRB compare match). • Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (TRCIOC low-level output at TRCGRC compare match). • The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match). Figure 20.10 Operating Example of Output Compare Function REJ09B0441-0010 Rev.0.10 Page 307 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.5.5 Changing Output Pins in Registers TRCGRC and TRCGRD The TRCGRC register can be used for output control of the TRCIOA pin, and the TRCGRD register can be used for output control of the TRCIOB pin. Each pin output can be controlled as follows: • TRCIOA output is controlled by the values of registers TRCGRA and TRCGRC. • TRCIOB output is controlled by the values of registers TRCGRB and TRCGRD. TRC Output control Compare match signal Comparator TRCGRA TRCIOA TRCIOC Output control Compare match signal Comparator TRCGRC TRCIOB Output control Compare match signal Comparator TRCGRB TRCIOD Output control Compare match signal Comparator TRCGRD Figure 20.11 Changing Output Pins in Registers TRCGRC and TRCGRD Change output pins in registers TRCGRC and TRCGRD as follows: • Set the IOC3 bit in the TRCIOR1 register to 0 (TRCIOA output register) and set the IOD3 bit to 0 (TRCIOB output register). • Set bits BFC and BFD in the TRCMR register to 0 (general register). • Set different values in registers TRCGRC and TRCGRA. Also, set different values in registers TRCGRD and TRCGRB. REJ09B0441-0010 Rev.0.10 Page 308 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC Figure 20.12 shows an Operating Example When TRCGRC Register is Used for Output Control of TRCIOA Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin. Count source TRC register value FFFFh m n p q 0000h m+1 n+1 p+1 q+1 Initial output “L” TRCIOA output Output inverted by compare match IMFA bit in TRCSR register 1 0 Set to 0 by a program. IMFC bit in TRCSR register 1 0 Set to 0 by a program. p-q m-n Initial output “L” TRCIOB output Output inverted by compare match IMFB bit in TRCSR register 1 0 Set to 0 by a program. IMFD bit in TRCSR register 1 0 Set to 0 by a program. m: Value set in TRCGRA register n: Value set in TRCGRC register p: Value set in TRCGRB register q: Value set in TRCGRD register The above applies under the following conditions: Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers). Bits EA and EB in the TRCOER register are set to 0 (TRCIOA and TRCIOB pin output enabled). The CCLR bit in the TRCCR1 register are set to 1 (TRC register is set to 0000h by compare match with the TRCGRA register). Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output at low until compare match). Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted by TRCGRA register compare match). Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted by TRCGRB register compare match). Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted by TRCGRC register compare match). The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register). Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted by TRCGRD register compare match). The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register). The CSEL bit in the TRCCR2 register are set to 0 (TRC count continues after compare match). Figure 20.12 Operating Example When TRCGRC Register is Used for Output Control of TRCIOA Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin REJ09B0441-0010 Rev.0.10 Page 309 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.6 PWM Mode This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output. PWM mode or timer mode can be selected for each individual pin. (However, the TRCGRA register cannot be used for timer mode since the register is used when using any pin for PWM mode.) Table 20.11 lists the PWM Mode Specifications, Figure 20.13 shows a Block Diagram of PWM Mode, Table 20.12 lists the Functions of TRCGRh Register in PWM Mode, and Figures 20.14 and 20.15 show Operating Examples in PWM Mode. Table 20.11 PWM Mode Specifications Item Count source Count operation PWM waveform Specification f1, f2, f4, f8, f32, fOCO40M, fOCO-F External signal (rising edge) input to the TRCCLK pin Increment PWM period: 1/fk × (m + 1) Active level width: 1/fk × (m - n) Inactive width: 1/fk × (n + 1) fk: Frequency of count source m: Value set in TRCGRA register n: Value set in TRCGRj register m+1 n+1 m-n (Active level is low) Count start condition Count stop condition Interrupt request generation timing TRCIOA pin function TRCIOB, TRCIOC, and TRCIOD pins function INT0 pin function Read from timer Write to timer Selectable functions 1 (count starts) is written to the TSTART bit in the TRCMR register. • When the CSEL bit in the TRCCR2 register is set to 0 (count continues after compare match with the TRCGRA register). 0 (count stops) is written to the TSTART bit in the TRCMR register. The PWM output pin retains the output level before the count stops, The TRC register retains a value before the count stops. • When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register). The count stops at a compare match with the TRCGRA register. The PWM output pin retains the level after the output is changed by the compare match. • Compare match (the contents of the TRC register and the TRCGRj register match) • TRC register overflow Programmable I/O port Programmable I/O port or PWM output (selectable for each individual pin) Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRC register. The TRC register can be written to. • One to three pins selectable as PWM pins One or more of pins TRCIOB, TRCIOC, and TRCIOD • Active level selectable for each individual pin • Initial level selectable for each individual pin • Buffer operation (Refer to 20.3.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 20.3.4 Forced Cutoff of Pulse Output.) • A/D trigger generation j = B, C, or D h = A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 310 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC TRC Compare match signal TRCIOB Compare match signal Comparator TRCGRA (Note 1) TRCIOC Output control Comparator Compare match signal TRCGRB TRCIOD Compare match signal Comparator TRCGRC (Note 2) Comparator TRCGRD Notes: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register of the TRCGRA register). 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register is used as the buffer register of the TRCGRB register). Figure 20.13 Block Diagram of PWM Mode REJ09B0441-0010 Rev.0.10 Page 311 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode b6 TCK2 0 b5 TCK1 0 b4 TCK0 0 b3 TOD 0 b2 TOC 0 b1 TOB 0 b0 TOA 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 0121h Bit b7 Symbol CCLR After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 Symbol TOA TOB TOC TOD TCK0 TCK1 TCK2 Bit Name TRCIOA output level select bit (1) TRCIOB output level select bit (1, 2) TRCIOC output level select bit (1, 2) TRCIOD output level select bit (1, 2) Count source select bit (1) Function Disabled in PWM mode. 0: Initial output selected as non-active level 1: Initial output selected as active level b6 b5 b4 b7 CCLR TRC counter clear select bit 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: Do not set. 0: Clear disabled (free-running operation) R/W 1: Clear by compare match with the TRCGRA register Notes: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. REJ09B0441-0010 Rev.0.10 Page 312 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.6.2 Timer RC Control Register 2 (TRCCR2) in PWM Mode b6 TCEG0 0 b5 CSEL 0 b4 — 1 b3 — 1 b2 POLD 0 b1 POLC 0 b0 POLB 0 R/W R/W R/W R/W — R/W Address 0130h Bit b7 Symbol TCEG1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function POLB PWM mode output level 0: TRCIOB output level selected as low active 1: TRCIOB output level selected as high active control bit B (1) POLC PWM mode output level 0: TRCIOC output level selected as low active 1: TRCIOC output level selected as high active control bit C (1) POLD PWM mode output level 0: TRCIOD output level selected as low active 1: TRCIOD output level selected as high active control bit D (1) — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — CSEL TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Trigger input from the TRCTRG pin disabled TCEG1 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W R/W Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode these bits are disabled. Table 20.12 Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRC TRCGRD Functions of TRCGRh Register in PWM Mode Setting − − BFC = 0 BFD = 0 BFC = 1 BFD = 1 Register Function General register. Set the PWM period. General register. Set the PWM output change point. General register. Set the PWM output change point. PWM Output Pin − TRCIOB TRCIOC TRCIOD Buffer register. Set the next PWM period. (Refer to 20.3.2 Buffer − Operation.) Buffer register. Set the next PWM output change point. (Refer to TRCIOB 20.3.2 Buffer Operation.) j = A, B, C, or D BFC, BFD: Bits in TRCMR register Note: 1. The output level does not change even if a compare match occurs when the TRCGRA register value (PWM period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value. REJ09B0441-0010 Rev.0.10 Page 313 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.6.3 Operating Example Count source TRC register value m n p q m+1 n+1 Active level “H” TRCIOB output Initial output “L” until compare match Inactive level “L” p+1 m-p m-n TRCIOC output Initial output “H” until compare match Inactive level “H” q+1 m-q TRCIOD output Active level “L” Initial output “L” utnil compare match IMFA bit in TRCSR register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 Set to 0 by a program. Set to 0 by a program. IMFD bit in TRCSR register 1 0 m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register q: Value set in TRCGRD register The above applies under the following conditions: • Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers). • Bits EB, EC, and ED in the TRCOER register are set to 0 (TRCIOB, TRCIOC, and TRCIOD pin output enabled). • Bits TOB and TOC in the TRCCR1 register are set to 0 (inactive level) and the TOD bit is set to 1 (active level). • The POLB bit in the TRCCR2 register is set to 1 (high active), bits POLC and POLD are set to 0 (low active). Figure 20.14 Operating Example in PWM Mode REJ09B0441-0010 Rev.0.10 Page 314 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC TRC register value p m q n 0000h TSTART bit in TRCMR register 1 0 Duty 0% TRCIOB output does not switch to “L” because no compare match with the TRCGRB register has occurred. TRCIOB output TRCGRB register n p (p>m) Rewrite by a program. q IMFA bit in TRCSR register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRCSR register 1 0 TRC register value m p n 0000h TSTART bit in TRCMR register 1 0 If compare matches occur simultaneously with registers TRCGRA and TRCGRB, the compare match with the TRCGRB register has priority. TRCIOB output switches to “L” (i.e. no change). Duty 100% TRCIOB output switches to “L” at compare match with the TRCGRB register (i.e. no change). TRCIOB output TRCGRB register n m Rewrite by a program. p IMFA bit in TRCSR register 1 0 Set to 0 by a program. IMFB bit in TRCSR register 1 0 Set to 0 by a program. m: Value set in TRCGRA register The above applies under the following conditions: • The EB bit in the TRCOER register is set to 0 (TRCIOB pin output enabled). • The POLB bit in the TRCCR2 register is set to 0 (low active). Figure 20.15 Operating Example in PWM Mode (Duty 0% and Duty 100%) REJ09B0441-0010 Rev.0.10 Page 315 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.7 PWM2 Mode This mode outputs a single PWM waveform. After a given wait time has elapsed following the trigger, the pin output switches to active level. Then, after a given duration, the output switches back to inactive level. Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use PWM2 mode to output a programmable wait one-shot waveform. Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with it. Figure 20.16 shows a Block Diagram of PWM2 Mode, Table 20.13 lists the PWM2 Mode Specifications, Table 20.14 lists the Functions of TRCGRj Register in PWM2 Mode, and Figures 20.17 to 20.19 show Operating Examples in PWM2 Mode. Trigger signal Compare match signal TRCTRG Input control Count clear signal (Note 1) TRC Comparator TRCGRA Comparator TRCGRB TRCGRD register TRCIOB Output control Comparator TRCGRC Note: 1. The BFD bit in the TRCMR register is set to 1 (TRCGRD register is used as the buffer register of the TRCGRB register). Figure 20.16 Block Diagram of PWM2 Mode REJ09B0441-0010 Rev.0.10 Page 316 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC Table 20.13 Item Count source PWM2 Mode Specifications Specification f1, f2, f4, f8, f32, fOCO40M, fOCO-F External signal input to TRCCLK pin (rising edge) TRC register increment PWM period: 1/fk × (m + 1) (no TRCTRG input) Active level width: 1/fk × (n - p) Wait time from count start or trigger: 1/fk × (p + 1) fk: Frequency of count source m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register TRCTRG input m+1 n+1 p+1 TRCIOB output n-p n-p (TRCTRG: Rising edge, active level is high) n+1 p+1 Count operation PWM waveform Count start conditions Count stop conditions Interrupt request generation timing TRCIOA/TRCTRG pins function TRCIOB pin function TRCIOC/TRCIOD pins function INT0 pin function Read from timer Write to timer Selectable functions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues). 1 (count starts) is written to the TSTART bit in the TRCMR register. • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts). A trigger is input to the TRCTRG pin. • 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in the TRCCR2 register is set to 0 or 1. The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in the TRCCR1 register. The TRC register retains the value before the count stops. • The count stops at a compare match with TRCGRA while the CSEL bit in the TRCCR2 register is set to 1 The TRCIOB pin outputs the initial level. The TRC register retains the value before the count stops when the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set to 0000h when the CCLR bit in the TRCCR1 register is set to 1. • Compare match (the contents of the TRC register and the TRCGRj register match.) • TRC register overflow Programmable I/O port or TRCTRG input PWM output Programmable I/O port Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRC register. The TRC register can be written to. • External trigger and active edge selection The edge or edges of the signal input to the TRCTRG pin can be used as the PWM output trigger: rising edge, falling edge, or both rising and falling edges • Buffer operation (Refer to 20.3.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 20.3.4 Forced Cutoff of Pulse Output.) • Digital filter (Refer to 20.3.3 Digital Filter.) • A/D trigger generation j = A, B, or C REJ09B0441-0010 Rev.0.10 Page 317 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode b6 TCK2 0 b5 TCK1 0 b4 TCK0 0 b3 TOD 0 b2 TOC 0 b1 TOB 0 b0 TOA 0 R/W R/W R/W Address 0121h Bit b7 Symbol CCLR After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function TOA TRCIOA output level select bit (1) Disabled in PWM2 mode. TOB TRCIOB output level select bit (1, 2) 0: Active level is high (Initial output at low High-level output at compare match with the TRCGRC register Low-level output at compare match with the TRCGRB register) 1: Active level is low (Initial output at high Low-level output at compare match with the TRCGRC register High-level output at compare match with the TRCGRB register) (1) TOC Disabled in PWM2 mode. TRCIOC output level select bit TOD TRCIOD output level select bit (1) b6 b5 b4 TCK0 Count source select bit (1) 0 0 0: f1 TCK1 0 0 1: f2 TCK2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: Do not set. CCLR TRC counter clear select bit 0: Clear disabled (free-running operation) 1: Clear by compare match with the TRCGRA register R/W R/W R/W R/W R/W R/W Notes: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. Table 20.14 Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRD Functions of TRCGRj Register in PWM2 Mode Setting − − BFC = 0 BFD = 0 BFD = 1 Register Function PWM2 Output Pin General register. Set the PWM period. TRCIOB pin General register. Set the PWM output change point. General register. Set the PWM output change point (wait time after trigger). (Not used in PWM2 mode.) − Buffer register. Set the next PWM output change point. (Refer to TRCIOB pin 20.3.2 Buffer Operation.) j = A, B, C, or D BFC, BFD: Bits in TRCMR register Note: 1. Do not set registers TRCGRB and TRCGRC to the same value. REJ09B0441-0010 Rev.0.10 Page 318 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode b6 TCEG0 0 b5 CSEL 0 b4 — 1 b3 — 1 b2 POLD 0 b1 POLC 0 b0 POLB 0 R/W R/W R/W R/W — R/W Address 0130h Bit b7 Symbol TCEG1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function 0: TRCIOB output level selected as low active POLB PWM mode output level 1: TRCIOB output level selected as high active control bit B (1) POLC PWM mode output level 0: TRCIOC output level selected as low active 1: TRCIOC output level selected as high active control bit C (1) POLD PWM mode output level 0: TRCIOD output level selected as low active 1: TRCIOD output level selected as high active control bit D (1) — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — 0: Count continues at compare match with CSEL TRC count operation select bit (2) the TRCGRA register 1: Count stops at compare match with the TRCGRA register b7 b6 TCEG0 TRCTRG input edge select bit (3) 0 0: Trigger input from the TRCTRG pin disabled TCEG1 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W R/W Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode, these bits are disabled. 20.7.3 Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode b6 DFCK0 0 b5 — 0 b4 DFTRG 0 b3 DFD 0 b2 DFC 0 b1 DFB 0 b0 DFA 0 R/W R/W R/W R/W R/W R/W — R/W R/W Address 0131h Bit b7 Symbol DFCK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFB TRCIOB pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFC TRCIOC pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFD TRCIOD pin digital filter function select bit (1) 0: Function is not used 1: Function is used DFTRG TRCTRG pin digital filter function select bit (2) 0: Function is not used 1: Function is used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 b6 DFCK0 Digital filter function clock select bit (1, 2) 0 0: f32 DFCK1 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK0 to TCK2 in the TRCCR1 register) Notes: 1. These bits are enabled for the input capture function. 2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). REJ09B0441-0010 Rev.0.10 Page 319 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.7.4 Operating Example Count source TRC register value FFFFh m TRC register is cleared by TRCGRA register compare match n Previous value is retained whenTSTART bit is set to 0. Set to 0000h by a program. p 0000h TSTART bit in TRCMR register 1 0 Set to 1 by a program. Count stops because CSEL bit is set to 1. TSTART bit is set to 0. CSEL bit in TRCCR2 register 1 0 m+1 n+1 p+1 “H” output at TRCGRC register compare match “L” initial output Return to initial output when TSTART bit is set to 0. No change “H” output at TRCGRC register compare match p+1 “L” output at TRCGRB register compare match No change TRCIOB output IMFA bit in TRCSR register 1 0 IMFB bit in TRCSR register 1 0 Set to 0 by a program. IMFC bit in TRCSR register 1 0 Set to 0 by a program. Set to 0 by a program. TRCGRB register Transfer TRCGRD register n n Transfer Next data Transfer from buffer register to general register m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register The above applies under the following conditions: • The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register, low-level output at compare match with the TRCGRB register). • Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). Figure 20.17 Operating Example in PWM2 Mode (TRCTRG Trigger Input Disabled) REJ09B0441-0010 Rev.0.10 Page 320 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC Count source TRC register value FFFFh m TRC register (counter) is cleared by TRCTRG pin trigger input. TRC register is cleared by TRCGRA register compare match. n Previous value is retained when TSTART bit is set to 0. Set to 0000h by a program. p 0000h Count starts at TRCTRG pin trigger input. Change by a program. TSTART bit is set to 0. Count stops because CSEL bit is set to 1. TRCTRG input Count starts when TSTART bit is set to 1. 1 0 TSTART bit in TRCMR register CSEL bit in TRCCR2 register 1 0 Set to 1 by a program. m+1 n+1 p+1 “H” output at TRCGRC register compare match “L” output at TRCGRB register compare match p+1 n+1 p+1 TRCIOB output “L” initial output Active level so TRCTRG input is disabled. IMFA bit in TRCSR register 1 0 Inactive level so TRCTRG input is enabled. Return to initial value when TSTART bit is set to 0. IMFB bit in TRCSR register 1 0 Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. IMFC bit in TRCSR register 1 0 TRCGRB register n Transfer n n Transfer n Transfer n Transfer Next data TRCGRD register Transfer from buffer register to general register Transfer from buffer register to general register m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register The above applies under the following conditions: • The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register, low-level output at compare match with the TRCGRB register). • Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input). Figure 20.18 Operating Example in PWM2 Mode (TRCTRG Trigger Input Enabled) REJ09B0441-0010 Rev.0.10 Page 321 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC • TRCGRB register setting value greater than TRCGRA register setting value TRC register value n m • TRCGRC register setting value greater than TRCGRA register setting value TRC register value p m n p 0000h TSTART bit in TRCMR register 1 0 p+1 m+1 No compare match with TRCGRB register, so “H” output continues. TRCIOB output TRCIOB output “L” initial output TSTART bit in TRCMR register 0000h 1 0 n+1 m+1 No compare match with TRCGRC register, so “L” output continues. “L” output at TRCGRB register compare match (i.e. no change) “H” output at TRCGRC register compare match 1 0 “L” initial output IMFA bit in TRCSR register IMFA bit in TRCSR register 1 0 IMFB bit in TRCSR register 1 0 Set to 0 by a program. IMFB bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register The above applies under the following conditions: • The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register, low-level output at compare match with the TRCGRB register). • Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). Figure 20.19 Operating Example in PWM2 Mode (Duty 0% and Duty 100%) REJ09B0441-0010 Rev.0.10 Page 322 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.8 Timer RC Interrupt Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector. Table 20.15 lists the Registers Associated with Timer RC Interrupt and Figure 20.20 shows a Block Diagram of Timer RC Interrupt. Table 20.15 Registers Associated with Timer RC Interrupt Timer RC Status Register TRCSR Timer RC Interrupt Enable Register TRCIER Timer RC Interrupt Control Register TRCIC IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit OVF bit OVIE bit Timer RC interrupt request (IR bit in TRCIC register) IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register Figure 20.20 Block Diagram of Timer RC Interrupt Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources. • The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to 1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled). • The IR bit is set to 0 (no interrupt requested) when the bit in the TRCSR register or the corresponding bit in the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not acknowledged. • If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not change. • If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the interrupt request. • The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to 0 within the interrupt routine. Refer to 20.2.5 Timer RC Status Register (TRCSR), for the procedure for setting these bits to 0. Refer to 20.2.4 Timer RC Interrupt Enable Register (TRCIER), for details of the TRCIER register. Refer to 12.3 Interrupt Control, for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables, for information on interrupt vectors. REJ09B0441-0010 Rev.0.10 Page 323 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC 20.9 20.9.1 Notes on Timer RC TRC Register • The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (TRC register cleared by compare match with TRCGRA register). When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h. • Reading from the TRC register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV.W TRC,DATA ;Read 20.9.2 TRCSR Register Reading from the TRCSR register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV.B TRCSR,DATA ;Read 20.9.3 TRCCR1 Register To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency higher than the CPU clock frequency. 20.9.4 Count Source Switching • Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. • After switching the count source from fOCO40M to another clock, allow two or more cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for two or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off). 20.9.5 Input Capture Function • The pulse width of the input capture signal should be set to three cycles or more of the timer RC operation clock (refer to Table 20.1 Timer RC Operating Clocks). • The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used). 20.9.6 TRCMR Register in PWM2 Mode When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA. REJ09B0441-0010 Rev.0.10 Page 324 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21. Timer RD Timer RD has two 16-bit timers (timer RD0 and timer RD1). 21.1 Introduction Timer RDi (i = 0 or 1) has four I/O pins. Timer RD uses either f1 or fOCO40M as its operating clock. Table 21.1 lists the Timer RD Operating Clocks. Table 21.1 Timer RD Operating Clocks Timer RD Operating Clock f1 fOCO40M Condition The count source is f1, f2, f4, f8, f32, fC2, or TRDCLK input. (Bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 000b to 101b.) The count source is fOCO40M. (Bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b.) Figure 21.1 shows the Timer RD Block Diagram, and Table 21.2 lists the Timer RD Pin Configuration. Timer RD supports the following five modes: • Timer mode - Input capture function The counter value is transferred to a register with an external signal as the trigger. - Output compare function A match between the values of a counter and a register is detected. (Pin output can be changed at detection.) The following four modes use the output compare function: • PWM mode Pulse of any width are continuously. • Reset synchronous PWM mode Three-phase waveforms (6) without sawtooth wave modulation and dead time are output. • Complementary PWM mode Three-phase waveforms (6) with triangular wave modulation and dead time are output. • PWM3 mode PWM waveforms (2) with a fixed period are output. For the input capture function, the output compare function, and in PWM mode, timer RD0 and timer RD1 have the equivalent functions, and functions or modes can be selected individually for each pin. Also, a combination of these functions and modes can be used in timer RDi. In reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, a waveform is output with a combination of counters and registers in timer RD0 and timer RD1. REJ09B0441-0010 Rev.0.10 Page 325 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD f1, f2, f4, f8, f32, fC2 fOCO40M Timer RDi TRDi register TRDGRAi register TRDGRBi register TRDGRCi register TRDGRDi register TRDDFi register TRDCRi register TRDIORAi register TRDIORCi register TRDSRi register Data bus INT0 Count source select circuit TRDIOA0/TRDCLK (1) TRDIOB0 (1) Timer RD control circuit TRDIOC0 (1) TRDIOD0 (1) TRDIOA1 (2) TRDIOB1 (2) TRDIOC1 (2) TRDIOD1 (2) TRDIERi register TRDPOCRi register TRDECR register TRDADCR register TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register TRDOER2 register TRDOCR register Timer RD0 interrupt request Timer RD1 interrupt request A/D trigger i = 0 or 1 Notes 1: The TRDPSR0 register is used to select which pin is assigned. 2: The TRDPSR1 register is used to select which pin is assigned. Figure 21.1 Timer RD Block Diagram Table 21.2 Timer RD Pin Configuration Pin Name TRDIOA0/TRDCLK TRDIOB0 TRDIOC0 TRDIOD0 TRDIOA1 TRDIOB1 TRDIOC1 TRDIOD1 Assigned Pin P6_0 or P10_0 P6_1 or P10_1 P6_2 or P10_2 P6_3 or P10_3 P6_4 or P10_4 P6_5 or P10_5 P6_6 or P10_6 P6_7 or P10_7 I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Function varies according to the mode. Refer to descriptions of individual modes for details. REJ09B0441-0010 Rev.0.10 Page 326 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.2 21.2.1 Common Items for Multiple Modes Count Sources The count source selection method is the same in all modes. However, the external clock cannot be selected in PWM3 mode. Table 21.3 Count Source Selection Count Source f1, f2, f4, f8, f32 fOCO40M (1) fC2 External signal input to TRDCLK pin Selection The count source is selected by bits TCK0 to TCK2 in the TRDCRi register. The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on). Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M). Bits TCK2 to TCK0 in the TRDCRi register is set to 101b (TRDCLKi input or fC2) The ITCLKi bit in the TRDECR register is set to 1 (fC2) The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (count source: external clock). The active edge is selected by bits CKEG0 and CKEG1 in the TRDCRi register. The PD2_0 bit in the PD2 register is set to 0 (input mode). i = 0 or 1 Note: 1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V. f1 f2 f4 f8 f32 fOCO40M TCK2 to TCK0 = 000b = 001b = 010b = 011b = 100b = 110b Count source TRDi register ITCLKi = 1 fC2 STCLK = 1 TRDCLK/ TRDIOA0 STCLK = 0 ITCLKi = 0 CKEG1 to CKEG0 Active edge selection = 101b TRDIOA0 I/O or programmable I/O port ITCLK0, ITCLK1: Bits in TRDECR register TCK0 to TCK2, CKEG0, CKEG1: Bits in TRDCRi register STCLK: Bit in TRDFCR register Figure 21.2 Count Source Block Diagram The pulse width of the external clock input to the TRDCLK pin should be set to three or more cycles of the timer RD operating clock. (See Table 21.1 Timer RD Operating Clocks.) To select fOCO40M or fOCO-F as the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M). REJ09B0441-0010 Rev.0.10 Page 327 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.2.2 Buffer Operation The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi in the TRDMR register. • Buffer register of TRDGRAi: TRDGRCi register • Buffer register of TRDGRBi: TRDGRDi register Buffer operation depends on the mode. Table 21.4 lists the Buffer Operation in Each Mode. Table 21.4 Buffer Operation in Each Mode Function and Mode Input capture function Transfer Register The content of the TRDGRAi (TRDGRBi) register is transferred to the buffer register. Output compare function Compare match between the TRDi The content of the buffer register is register and the TRDGRAi transferred to the TRDGRAi PWM mode (TRDGRBi) register (TRDGRBi) register. Reset synchronous PWM Compare match between the TRD0 The content of the buffer register is mode register and the TRDGRA0 register transferred to the TRDGRAi (TRDGRBi) register. Complementary PWM • Compare match between the TRD0 The content of the buffer register is register and the TRDGRA0 register transferred to registers TRDGRB0, mode • TRD1 register underflow TRDGRA1, and TRDGRB1. PWM3 mode Compare match between the TRD0 The content of the buffer register is register and the TRDGRA0 register transferred to registers TRDGRA0, TRDGRB0, TRDGRA1, and TRDGRB1. i = 0 or 1 TRDIOAi input (input capture signal) TRDGRCi register (buffer) TRDGRAi register TRDi Transfer Timing Input capture signal input TRDIOAi input TRDi register n-1 n Transfer n+1 TRDGRAi register m Transfer n TRDGRCi register (buffer) m i = 0 or 1 The above applies under the following conditions: • The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). • Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge). Figure 21.3 Buffer Operation of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 328 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Compare match signal TRDGRCi register (buffer) TRDGRAi register Comparator TRDi TRDi register m-1 m m+1 TRDGRAi register m Transfer n TRDGRCi register (buffer) n TRDIOAi output i = 0 or 1 The above applies under the following conditions: • The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). • Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (low-level output at compare match). Figure 21.4 Buffer Operation of Output Compare Function Perform the following in timer mode (input capture and output compare functions). To use the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register: • Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register). • Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. To use the TRDGRDi register as the buffer register of the TRDGRBi register: • Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register). • Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. For the input capture function, bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when registers TRDGRCi and TRDGRDi are also used as buffer registers. For the output compare function, in reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi register are set to 1 by a compare match with the TRDi register when registers TRDGRCi and TRDGRDi are also as buffer registers. REJ09B0441-0010 Rev.0.10 Page 329 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.2.3 Synchronous Operation The TRD1 register is synchronized with the TRD0 register. • Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register. • Synchronous clear When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set to 0000h. Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0 register is set to 0000h. TRDIOA0 input 0000h is set by input capture. TRD0 register value n writing n n is set. TRD1 register value n n is set. 0000h is set synchronizing with the TRD0 register. The above applies under the following conditions: • The SYNC bit in the TRDMR register is set to 1 (synchronous operation). • Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (TRD0 register is set to 0000h by input capture). Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (TRD1 register is set to 0000h synchronizing with the TRD0 register). • Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b. • Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input) The PWM 3 bit in the TRDFCR register is set to 1. Figure 21.5 Synchronous Operation REJ09B0441-0010 Rev.0.10 Page 330 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.2.4 Pulse Output Forced Cutoff In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable I/O port by the INT0 pin input, and pulse output can be cut off. The pins used for output in the above function or modes can function as the output pin of timer RD when the applicable bit in the TRDOER1 register is set to 0 (timer RD output enabled). When the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled), all bits in the TRDOER1 register are set to 1 (timer RD output disabled, TRDIOji output pin functions as a programmable I/O port) after a low-level signal is applied to the INT0 pin. The TRDIOji output pin is set to a programmable I/O port after a low-level signal is applied to the INT0 pin and waiting for one or two cycles of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks). Set the following to use this function: • Set the pin status (high impedance, low-level, or high-level output) to pulse output forced cutoff by registers P2 and PD2. • Set the INT0EN bit in the INTEN register to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge). • Set the PD4_5 bit in the PD4 register to 0 (input mode). • Set the INT0 digital filter by bits INT0F0 and INT0F1 in the INTF register. • Set the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled). According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in the INT0IC register is set to 1 (interrupt requested). Refer to 12. Interrupts for details of interrupts. REJ09B0441-0010 Rev.0.10 Page 331 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD EA0 bit write value EA0 bit DQ S Timer RD output data Port P6_0/P10_0 direction bit INT0 input PTO bit TRDIOA0 Port P6_0/P10_0 output data Port P6_0/P10_0 input data EB0 bit write value EB0 bit DQ S Timer RD output data Port P6_1/P10_1 direction bit Port P6_1/P10_1 output data Port P6_1/P10_1 input data EC0 bit write value EC0 bit DQ S Timer RD output data Port P6_2/P10_2 direction bit Port P6_2/P10_2 output data Port P6_2/P10_2 input data ED0 bit write value ED0 bit DQ S Timer RD output data Port P6_3/P10_3 direction bit Port P6_3/P10_3 output data Port P6_3/P10_3 input data EA1 bit write value EA1 bit DQ S Timer RD output data Port P6_4/P10_4 direction bit Port P6_4/P10_4 output data Port P6_4/P10_4 input data EB1 bit write value EB1 bit DQ S Timer RD output data Port P6_5/P10_5 direction bit Port P6_5/P10_5 output data Port P6_5/P10_5 input data EC1 bit write value EC1 bit DQ S Timer RD output data Port P6_6/P10_6 direction bit Port P6_6/P10_6 output data Port P6_6/P10_6 input data ED1 bit write value ED1 bit DQ S Timer RD output data Port P6_7/P10_7 direction bit Port P6_7/P10_7 output data Port P6_7/P10_7 input data PTO: Bit in TRDOER2 register EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register TRDIOB0 TRDIOC0 TRDIOD0 TRDIOA1 TRDIOB1 TRDIOC1 TRDIOD1 Figure 21.6 Pulse Output Forced Cutoff REJ09B0441-0010 Rev.0.10 Page 332 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3 Input Capture Function The input capture function measures the external signal width and period. The content of the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C, or D) pin external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the input capture function, or any other mode or function, can be selected for each individual pin. The TRDGRA0 register can also select the fOCO128 signal as input-capture trigger input. Figure 21.7 shows a Block Diagram of Input Capture Function, Table 21.5 lists the Input Capture Function Specifications. Figure 21.8 shows an Operating Example of Input Capture Function. Polarity switching Input capture signal (Note 1) TRDGRAi register TRDi register TRDGRCi register Polarity switching TRDIOCi Input capture signal TRDIOBi Polarity switching Input capture signal (Note 2) TRDGRBi register fOCO Divided by 128 fOCO128 IOA3 = 0 Input capture signal TRDGRDi register TRDIODi Polarity switching TRDIOAi (Note 3) IOA3 = 1 3: The trigger input of the TRDGRA0 register can select the TRDIOA0 pin input or fOCO128 signal. Input capture signal i = 0 or 1 Notes 1: When the BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). 2: When the BFDi bit in the TRDMR register is set to 1 (TRDGRDi register is used as the buffer register of the TRDGRBi register). Figure 21.7 Block Diagram of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 333 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.5 Input Capture Function Specifications Item Count sources Count operations Count period Count start condition Count stop condition Interrupt request generation timing TRDIOA0 pin function TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pins function INT0 pin function Read from timer Write to timer Specification f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Increment When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running operation). 1/fk × 65,536 fk: Frequency of count source 1 (count starts) is written to the TSTARTi bit in the TRDSTR register. 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. • Input capture (active edge of the TRDIOji input or fOCO128 signal edge) • TRDi register overflows Programmable I/O port, input-capture input, or TRDCLK (external clock) input Programmable I/O port, or input-capture input (selectable for each individual pin) Programmable I/O port or INT0 interrupt input The count value can be read by reading the TRDi register. • When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and timer RD1 operate independently). Data can be written to the TRDi register. • When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. • Input-capture input pin selection Either one pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi. • Input-capture input active edge selection The rising edge, falling edge, or both the rising and falling edges • Timing for setting the TRDi register to 0000h Overflow or input capture • Buffer operation (Refer to 21.2.2 Buffer Operation.) • Synchronous operation (Refer to 21.2.3 Synchronous Operation.) • Digital filter The TRDIOji input is sampled and the level is determined when the sampled input level match as three times. • Input-capture trigger selection fOCO128 can be selected for input-capture trigger input of the TRDGRA0 register. Selectable functions i = 0 or 1, j = either A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 334 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. 21.3.2 Timer RD Control Expansion Register (TRDECR) b6 — 0 b5 — 0 b4 — 0 b3 ITCLK0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0135h Bit b7 Symbol ITCLK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W — R/W REJ09B0441-0010 Rev.0.10 Page 335 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.3 Timer RD Start Register (TRDSTR) for Input Capture Function b6 — 1 b5 — 1 b4 — 1 b3 CSEL1 1 b2 b1 b0 CSEL0 TSTART1 TSTART0 1 0 0 R/W R/W R/W R/W R/W — Address 0137h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TSTART0 TSTART1 CSEL0 CSEL1 — — — — Bit Name Function TRD0 count start flag 0: Count stops 1: Count starts TRD1 count start flag TRD0 count operation select bit Set to 1 for the input capture function. TRD1 count operation select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. 21.3.4 Timer RD Mode Register (TRDMR) for Input Capture Function b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 — 1 b2 — 1 b1 — 1 b0 SYNC 0 R/W R/W Address 0138h Bit b7 Symbol BFD1 After Reset 0 Bit b0 Symbol SYNC Bit Name Timer RD synchronous bit b1 b2 b3 b4 b5 b6 b7 — — — BFC0 BFD0 BFC1 BFD1 Function 0: Registers TRD0 and TRD1 operate independently 1: Registers TRD0 and TRD1 operate synchronously Nothing is assigned. If necessary, set to 0. When read, the content is 1. — TRDGRC0 register function select bit TRDGRD0 register function select bit TRDGRC1 register function select bit TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRA0 register 0: General register 1: Buffer register of TRDGRB0 register 0: General register 1: Buffer register of TRDGRA1 register 0: General register 1: Buffer register of TRDGRB1 register R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 336 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.5 Timer RD PWM Mode Register (TRDPMR) for Input Capture Function b6 b5 PWMD1 PWMC1 0 0 b4 PWMB1 0 b3 — 1 b2 b1 PWMD0 PWMC0 0 0 b0 PWMB0 0 R/W R/W R/W R/W — R/W R/W R/W — Address 0139h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PWMB0 PWMC0 PWMD0 — PWMB1 PWMC1 PWMD1 — Bit Name Function PWM mode of TRDIOB0 select bit Set to 0 (timer mode) for the input capture function. PWM mode of TRDIOC0 select bit PWM mode of TRDIOD0 select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOB1 select bit Set to 0 (timer mode) for the input capture function. PWM mode of TRDIOC1 select bit PWM mode of TRDIOD1 select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.3.6 Timer RD Function Control Register (TRDFCR) for Input Capture Function b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 b1 CMD1 0 b0 CMD0 0 R/W R/W R/W R/W Address 013Ah Bit b7 Symbol PWM3 After Reset 1 Bit b0 b1 b2 Symbol CMD0 CMD1 OLS0 Bit Name Combination mode select bit (1) Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit (2) Function Set to 00b (timer mode, PWM mode, or PWM3 mode) for the input capture function. Disabled for the input capture function. b3 OLS1 R/W b4 b5 b6 b7 ADTRG ADEG STCLK PWM3 R/W R/W 0: External clock input disabled 1: External clock input enabled Set to 1 (other than PWM3 mode) for the input capture function. R/W R/W Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. REJ09B0441-0010 Rev.0.10 Page 337 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.7 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) for Input Capture Function b3 DFD 0 b2 DFC 0 b1 DFB 0 b0 DFA 0 R/W R/W R/W R/W R/W — R/W R/W Address 013Eh (TRDDF0), 013Fh (TRDDF1) Bit b7 b6 b5 b4 Symbol DFCK1 DFCK0 — — After Reset 0 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function DFA TRDIOA pin digital filter function 0: Function is not used select bit 1: Function is used DFB TRDIOB pin digital filter function select bit DFC TRDIOC pin digital filter function select bit DFD TRDIOD pin digital filter function select bit — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — DFCK0 Clock select bits for digital filter function b7 b6 0 0: f32 DFCK1 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK0 to TCK2 in the TRCCRi register) REJ09B0441-0010 Rev.0.10 Page 338 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.8 Timer RD Control Register i (TRDCRi) (i = 0 or 1) for Input Capture Function b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 Address 0140h (TRDCR0), 0150h (TRDCR1) Bit b7 b6 b5 b4 Symbol CCLR2 CCLR1 CCLR0 CKEG1 After Reset 0 0 0 0 Bit b0 b1 b2 Symbol Bit Name TCK0 Count source select bit TCK1 TCK2 b0 TCK0 0 R/W R/W R/W R/W 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. b4 b3 b3 b4 CKEG0 External clock edge select bit (3) CKEG1 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. b7 b6 b5 R/W R/W b5 b6 b7 CCLR0 TRDi counter clear select bit CCLR1 CCLR2 0 0 0: Clear disabled (free-running operation) 0 0 1: Clear by input capture to the TRDGRAi register 0 1 0: Clear by input capture to the TRDGRBi register 0 1 1: Synchronous clear (clear simultaneously with other timer RDi counter) (4) 1 0 0: Do not set. 1 0 1: Clear by input capture to the TRDGRCi register 1 1 0: Clear by input capture to the TRDGRDi register 1 1 1: Do not set. R/W R/W R/W Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 4. Enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate synchronously). REJ09B0441-0010 Rev.0.10 Page 339 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.9 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) for Input Capture Function b3 IOA3 1 b2 IOA2 0 b1 IOA1 0 Function b1 b0 Address 0141h (TRDIORA0), 0151h (TRDIORA1) Bit b7 b6 b5 b4 Symbol — IOB2 IOB1 IOB0 After Reset 1 0 0 0 Bit b0 b1 Symbol IOA0 IOA1 Bit Name TRDGRA control bit b0 IOA0 0 R/W R/W R/W b2 b3 b4 b5 IOA2 IOA3 IOB0 IOB1 TRDGRA mode select bit (1) Input capture input switch bit (3, 4) TRDGRB control bit 0 0: Input capture to the TRDGRAi register at the rising edge 0 1: Input capture to the TRDGRAi register at the falling edge 1 0: Input capture to the TRDGRAi register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. 0: fOCO128 signal 1: TRDIOA0 pin input b5 b4 R/W R/W R/W R/W b6 b7 IOB2 — 0 0: Input capture to the TRDGRBi register at the rising edge 0 1: Input capture to the TRDGRBi register at the falling edge 1 0: Input capture to the TRDGRBi register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. TRDGRB mode select bit (2) Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W — Notes: 1. To select 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as the buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. 3. The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1. 4. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function). REJ09B0441-0010 Rev.0.10 Page 340 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.10 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) for Input Capture Function Address 0142h (TRDIORC0), 0152h (TRDIORC1) Bit b7 b6 b5 b4 Symbol IOD3 IOD2 IOD1 IOD0 After Reset 1 0 0 0 Bit b0 b1 Symbol Bit Name IOC0 TRDGRC control bit IOC1 b3 IOC3 1 b2 IOC2 0 b1 IOC1 0 Function b1 b0 b0 IOC0 0 R/W R/W R/W b2 b3 b4 b5 IOC2 IOC3 IOD0 IOD1 TRDGRC mode select bit (1) TRDGRC register function select bit TRDGRD control bit 0 0: Input capture to the TRDGRCi register at the rising edge 0 1: Input capture to the TRDGRCi register at the falling edge 1 0: Input capture to the TRDGRCi register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. Set to 1 (general register or buffer register) for the input capture function. b5 b4 R/W R/W R/W R/W b6 b7 IOD2 IOD3 TRDGRD mode select bit (2) TRDGRD register function select bit 0 0: Input capture to the TRDGRDi register at the rising edge 0 1: Input capture to the TRDGRDi register at the falling edge 1 0: Input capture to the TRDGRDi register at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. Set to 1 (general register or buffer register) for the input capture function. R/W R/W Notes: 1. To select 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as the buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. REJ09B0441-0010 Rev.0.10 Page 341 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) for Input Capture Function Address 0143h (TRDSR0), 0153h (TRDSR1) Bit b7 b6 b5 b4 Symbol — — UDF OVF After Reset 1 1 1 0 After Reset 1 1 0 0 Bit b0 Symbol Bit Name IMFA Input-capture/compare-match flag A b3 IMFD 0 0 b2 IMFC 0 0 b1 IMFB 0 0 b0 IMFA 0 0 TRDSR0 register TRDSR1 register R/W R/W Function [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1]. TRDSR0 register: fOCO128 signal edge when the IOA3 bit in the TRDIORA0 register is set to 0 (fOCO128 signal). Input edge of TRDIOA0 pin when the IOA3 bit in the TRDIORA0 register is set to 1 (TRDIOA0 input) (3). b1 IMFB b2 IMFC b3 IMFD b4 OVF b5 b6 b7 UDF — — TRDSR1 register: Input edge of TRDIOA1 pin (3). Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] Input edge of TRDIOBi pin (3). Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] Input edge of TRDIOCi pin (4). Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] Input edge of TRDIODi pin (4). Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. Disabled for the input capture function. Underflow flag (1) Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W R/W R/W — Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. 3. Edge selected by bits IOj0 and IOj1 (j = A or B) in the TRDIORAi register. 4. Edge selected by bits IOk0 and IOk1 (k = C or D) in the TRDIORCi register. Including when the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as a buffer register) REJ09B0441-0010 Rev.0.10 Page 342 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) for Input Capture Function Address 0144h (TRDIER0), 0154h (TRDIER1) Bit b7 b6 b5 b4 Symbol — — — OVIE After Reset 1 1 1 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IMIEA Input-capture/compare-match interrupt enable bit A IMIEB Input-capture/compare-match interrupt enable bit B IMIEC Input-capture/compare-match interrupt enable bit C IMIED Input-capture/compare-match interrupt enable bit D OVIE Overflow/underflow interrupt enable bit — — — b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W R/W — Function 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.3.13 Timer RD Counter i (TRDi) (i = 0 or 1) for Input Capture Function Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1) Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset 0 0 0 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b13 — 0 b12 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 Counts an count source. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units. REJ09B0441-0010 Rev.0.10 Page 343 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) for Input Capture Function Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Refer to Table 21.6 TRDGRji Register Functions for Input Capture Function Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled for the input capture function: TRDOER1, TRDOER2, TRDOCR, TRDPOCR0, and TRDPOCR1. Table 21.6 TRDGRji Register Functions for Input Capture Function Register TRDGRAi TRDGRBi TRDGRCi TRDGRDi TRDGRCi TRDGRDi Setting − BFCi = 0 BFDi = 0 BFCi = 1 BFDi = 1 Register Function General register The value of the TRDi register can be read at input capture. General register The value of the TRDi register can be read at input capture. Buffer register The value of the TRDi register can be read at input capture. (Refer to 21.2.2 Buffer Operation) Input-Capture Input Pin TRDIOAi TRDIOBi TRDIOCi TRDIODi TRDIOAi TRDIOBi i = 0 or 1, j = either A, B, C, or D BFCi, BFDi: Bits in TRDMR register The pulse width of the input capture signal input to the TRDIOji pin should be set to three or more cycles of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks) when the digital filter is not used (the DFj bit in the TRDDFi register is set to 0). REJ09B0441-0010 Rev.0.10 Page 344 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.15 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 345 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.16 Timer RD Pin Select Register 1 (TRDPSR1) Address 0185h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 346 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.17 Operating Example TRDCLK input count source TRDi register count value FFFFh 0009h 0006h 0000h TSTARTi bit in TRDSTR register 1 0 65,536 TRDIOAi input TRDGRAi register Transfer TRDGRCi register 0006h 0009h Transfer 0006h IMFA bit in TRDSRi register OVF bit in TRDSRi register 1 0 1 0 Set to 0 by a program. i = 0 or 1 The above applies under the following conditions: Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (TRDi register set to 0000h by TRDGRAi register input capture). Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input selected as the count source). Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge selected as the count source). Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input). The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). Figure 21.8 Operating Example of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 347 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.3.18 Digital Filter The TRDIOji input is sampled and the level is determined when the sampled input level matches three times. The digital filter function and sampling clock can be selected using the TRDDFi register. Figure 21.9 shows a Block Diagram of Digital Filter. TCK2 to TCK0 fOCO40M ITCLKi=1 fC2 TRDCLK ITCLKi=0 f32 f8 f4 f2 f1 =101b =100b Count source =011b =010b =001b =000b =110b f32 f8 f1 DFCK1 to DFCK0 =00b =01b =10b =11b IOA0 to IOA2 IOB0 to IOB2 IOC0 to IOC3 IOD0 to IOD3 Sampling clock DFj C TRDIOji input signal D Latch Timer RD operating clock f1 or fOCO40M C D Latch Q Q D C Q Latch D C Q Latch D C Q Latch 1 Match detection circuit Edge detection circuit 0 Clock period selected by bits TCK0 to TCK2 or bits DFCK0 and DFCK1 Sampling clock TRDIOji input signal Three matches occur and a signal change is confirmed. Input signal through digital filtering Maximum signal transmission delay is five sampling clocks. If fewer than three matches occur, the matches are recognized as noise and no transmission is performed. i = 0 or 1, j = either A, B, C, or D ITCLK0, ITCLK1: Bits in TRDECR register TCK0 to TCK2: Bits in TRDCRi register DFCK0, DFCK1 and DFj: Bits in TRDDF register IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register Figure 21.9 Block Diagram of Digital Filter REJ09B0441-0010 Rev.0.10 Page 348 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4 Output Compare Function This function detects matches (compare match) between the content of the TRDGRji (j = either A, B, C, or D) register and the content of the TRDi (i = 0 or 1) register. When the content matches, a user-set level is output from the TRDIOji pin. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the output compare function, or any other mode or function, can be selected for each individual pin. Figure 21.10 shows a Block Diagram of Output Compare Function, Table 21.7 lists the Output Compare Function Specifications. Figure 21.11 shows an Operating Example of Output Compare Function. Timer RD0 TRD0 Compare match signal Output control TRDIOA0 IOC3 = 0 in TRDIORC0 register Comparator TRDGRA0 Compare match signal TRDIOC0 Output control IOC3 = 1 Comparator Compare match signal TRDGRC0 TRDIOB0 Output control IOD3 = 0 in TRDIORD0 register Comparator TRDGRB0 Compare match signal TRDIOD0 Output control IOD3 = 1 Comparator TRDGRD0 Timer RD1 TRD1 Compare match signal Output control TRDIOA1 IOC3 = 0 in TRDIORC1 register Comparator TRDGRA1 Compare match signal TRDIOC1 Output control IOC3 = 1 Comparator Compare match signal TRDGRC1 TRDIOB1 Output control IOD3 = 0 in TRDIORD1 register Comparator TRDGRB1 Compare match signal TRDIOD1 Output control IOD3 = 1 Comparator TRDGRD1 Figure 21.10 Block Diagram of Output Compare Function REJ09B0441-0010 Rev.0.10 Page 349 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.7 Output Compare Function Specifications Specification f1, f2, f4, f8, f32, fC2, fOCO40M, External signal input to the TRDCLK pin (active edge selectable by a program) Increment • When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running operation) 1/fk × 65,536 fk: Frequency of count source • Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (TRDi register is set to 0000h at compare match with the TRDGRji register). Frequency of count source x (n+1) n: Value set in TRDGRji register Compare match 1 (count starts) is written to the TSTARTi bit in the TRDSTR register. • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The output compare output pin holds output level before the count stops. • When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRAi register. The output compare output pin holds the level after the output changes by the compare match. • Compare match (the contents of the TRDi register and the TRDGRji register match.) • TRDi register overflow Programmable I/O port, output-compare output, or TRDCLK (external clock) input Programmable I/O port or output-compare output (selectable for each individual pin) Item Count sources Count operations Count period Waveform output timing Count start condition Count stop conditions Interrupt request generation timing TRDIOA0 pin function TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pins function INT0 pin function Read from timer Write to timer Selectable functions Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRDi register. • When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and timer RD1 operate independently). Data can be written to the TRDi register. • When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. • Output-compare output pin selection Either one or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi. • Output level selection at the compare match Low-level output, high-level output, or output level inversion • Initial output level selected Selectable level for the period from the count start to the compare match • Timing for setting the TRDi register to 0000h Overflow or compare match with the TRDGRAi register • Buffer operation (Refer to 21.2.2 Buffer Operation.) • Synchronous operation (Refer to 21.2.3 Synchronous Operation.) • Changing output pins for registers TRDGRCi and TRDGRDi The TRDGRCi register can be used as output control of the TRDIOAi pin and the TRDGRDi register can be used as output control of the TRDIOBi pin. • Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.) • Timer RD can be used as the internal timer without output. • A/D trigger generation i = 0 or 1, j = either A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 350 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. REJ09B0441-0010 Rev.0.10 Page 351 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.2 Timer RD Control Expansion Register (TRDECR) b6 — 0 b5 — 0 b4 — 0 b3 ITCLK0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0135h Bit b7 Symbol ITCLK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W — R/W 21.4.3 Timer RD Trigger Control Register (TRDADCR) Address 0136h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E After Reset 0 0 0 0 0 0 0 0 Bit b0 Symbol Bit Name ADTRGA0E A/D trigger A0 enable bit Function 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W R/W b1 ADTRGB0E A/D trigger B0 enable bit R/W b2 ADTRGC0E A/D trigger C0 enable bit R/W b3 ADTRGD0E A/D trigger D0 enable bit R/W b4 ADTRGA1E A/D trigger A1 enable bit R/W b5 ADTRGB1E A/D trigger B1 enable bit R/W b6 ADTRGC1E A/D trigger C1 enable bit R/W b7 ADTRGD1E A/D trigger D1 enable bit R/W REJ09B0441-0010 Rev.0.10 Page 352 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.4 Timer RD Start Register (TRDSTR) for Output Compare Function b6 — 1 b5 — 1 b4 — 1 b3 CSEL1 1 b2 b1 b0 CSEL0 TSTART1 TSTART0 1 0 0 R/W R/W R/W R/W Address 0137h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 Symbol Bit Name TSTART0 TRD0 count start flag (3) b3 b4 b5 b6 b7 Function 0: Count stops (1) 1: Count starts TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — R/W — Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. REJ09B0441-0010 Rev.0.10 Page 353 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.5 Timer RD Mode Register (TRDMR) for Output Compare Function b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 — 1 b2 — 1 b1 — 1 b0 SYNC 0 R/W R/W — Address 0138h Bit b7 Symbol BFD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol SYNC — — — BFC0 BFD0 BFC1 BFD1 Bit Name Timer RD synchronous bit Function 0: Registers TRD0 and TRD1 operate independently 1: Registers TRD0 and TRD1 operate synchronously Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit (1) TRDGRD0 register function select bit (1) TRDGRC1 register function select bit (1) TRDGRD1 register function select bit (1) 0: General register 1: Buffer register of TRDGRA0 register 0: General register 1: Buffer register of TRDGRB0 register 0: General register 1: Buffer register of TRDGRA1 register 0: General register 1: Buffer register of TRDGRB1 register R/W R/W R/W R/W Note: 1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1) register, set the BFji bit in the TRDMR register to 0. 21.4.6 Timer RD PWM Mode Register (TRDPMR) for Output Compare Function b6 b5 PWMD1 PWMC1 0 0 b4 PWMB1 0 b3 — 1 b2 b1 PWMD0 PWMC0 0 0 b0 PWMB0 0 R/W R/W R/W R/W — R/W R/W R/W — Address 0139h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PWMB0 PWMC0 PWMD0 — PWMB1 PWMC1 PWMD1 — Bit Name Function PWM mode of TRDIOB0 select bit Set to 0 (timer mode) for the output compare function. PWM mode of TRDIOC0 select bit PWM mode of TRDIOD0 select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOB1 select bit Set to 0 (timer mode) for the output compare function. PWM mode of TRDIOC1 select bit PWM mode of TRDIOD1 select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. REJ09B0441-0010 Rev.0.10 Page 354 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.7 Timer RD Function Control Register (TRDFCR) for Output Compare Function b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 b1 CMD1 0 b0 CMD0 0 R/W R/W R/W R/W Address 013Ah Bit b7 Symbol PWM3 After Reset 1 Bit b0 b1 b2 Symbol CMD0 CMD1 OLS0 Bit Name Combination mode select bit (1) Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit (2) Function Set to 00b (timer mode, PWM mode, or PWM3 mode) for the output compare function. Disabled for the output compare function. b3 OLS1 R/W b4 b5 b6 b7 ADTRG ADEG STCLK PWM3 R/W R/W 0: External clock input disabled 1: External clock input enabled Set to 1 (other than PWM3 mode) for the output compare function. R/W R/W Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. REJ09B0441-0010 Rev.0.10 Page 355 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.8 Timer RD Output Master Enable Register 1 (TRDOER1) for Output Compare Function b6 EC1 1 b5 EB1 1 b4 EA1 1 b3 ED0 1 b2 EC0 1 b1 EB0 1 b0 EA0 1 R/W R/W Address 013Bh Bit b7 Symbol ED1 After Reset 1 Bit b0 Symbol Bit Name EA0 TRDIOA0 output disable bit b1 EB0 TRDIOB0 output disable bit b2 EC0 TRDIOC0 output disable bit b3 ED0 TRDIOD0 output disable bit b4 EA1 TRDIOA1 output disable bit b5 EB1 TRDIOB1 output disable bit b6 EC1 TRDIOC1 output disable bit b7 ED1 TRDIOD1 output disable bit Function 0: Output enabled 1: Output disabled (TRDIOA0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOA1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W R/W R/W R/W R/W R/W R/W 21.4.9 Timer RD Output Master Enable Register 2 (TRDOER2) for Output Compare Function b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W — — — — — — — R/W Address 013Ch Bit b7 Symbol PTO After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — — — — 0: Pulse output forced cutoff input disabled PTO INT0 of pulse output forced cutoff 1: Pulse output forced cutoff input enabled (1) signal input enabled bit (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. REJ09B0441-0010 Rev.0.10 Page 356 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.10 Timer RD Output Control Register (TRDOCR) for Output Compare Function Address 013Dh Bit b7 Symbol TOD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TOA0 TOB0 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1 b6 TOC1 0 b5 TOB1 0 b4 TOA1 0 b3 TOD0 0 b2 TOC0 0 b1 TOB0 0 b0 TOA0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name TRDIOA0 output level select bit TRDIOB0 output level select bit TRDIOC0 initial output level select bit TRDIOD0 initial output level select bit TRDIOA1 initial output level select bit TRDIOB1 initial output level select bit TRDIOC1 initial output level select bit TRDIOD1 initial output level select bit Function 0: Initial output at low 1: Initial output at high 0: Low 1: High Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRDOCR register is set. REJ09B0441-0010 Rev.0.10 Page 357 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) for Output Compare Function Address 0140h (TRDCR0), 0150h (TRDCR1) Bit b7 b6 b5 b4 Symbol CCLR2 CCLR1 CCLR0 CKEG1 After Reset 0 0 0 0 Bit b0 b1 b2 Symbol Bit Name TCK0 Count source select bit TCK1 TCK2 b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 b0 TCK0 0 R/W R/W R/W R/W 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. b4 b3 b3 b4 CKEG0 External clock edge select bit (3) CKEG1 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. b7 b6 b5 R/W R/W b5 b6 b7 CCLR0 TRDi counter clear select bit CCLR1 CCLR2 0 0 0: Clear disabled (free-running operation) 0 0 1: Clear by compare match with the TRDGRAi register 0 1 0: Clear by compare match with the TRDGRBi register 0 1 1: Synchronous clear (clear simultaneously with other timer RDi counter) (4) 1 0 0: Do not set. 1 0 1: Clear by compare match with the TRDGRCi register 1 1 0: Clear by compare match with the TRDGRDi register 1 1 1: Do not set. R/W R/W R/W Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. This setting is enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 4. This setting is enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate synchronously). REJ09B0441-0010 Rev.0.10 Page 358 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.12 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) for Output Compare Function Address 0141h (TRDIORA0), 0151h (TRDIORA1) Bit b7 b6 b5 b4 Symbol — IOB2 IOB1 IOB0 After Reset 1 0 0 0 Bit b0 b1 Symbol IOA0 IOA1 Bit Name TRDGRA control bit b3 IOA3 1 b2 IOA2 0 b1 IOA1 0 Function b1 b0 b0 IOA0 0 R/W R/W R/W b2 b3 b4 b5 IOA2 IOA3 IOB0 IOB1 b6 b7 IOB2 — 0 0: Pin output by compare match is disabled (TRDIOAi pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRDGRAi register 1 0: High-level output at compare match with the TRDGRAi register 1 1: Toggle output at compare match with the TRDGRAi register (1) Set to 0 (output compare) for the output compare R/W TRDGRA mode select bit function. Input capture input switch bit Set to 1. R/W b5 b4 R/W TRDGRB control bit 0 0: Pin output by compare match is disabled R/W (TRDIOBi pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRDGRBi register 1 0: High-level output at compare match with the TRDGRBi register 1 1: Toggle output at compare match with the TRDGRBi register Set to 0 (output compare) for the output compare R/W TRDGRB mode select bit (2) function. Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Notes: 1. To select 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as the buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. REJ09B0441-0010 Rev.0.10 Page 359 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) for Output Compare Function Address 0142h (TRDIORC0), 0152h (TRDIORC1) Bit b7 b6 b5 b4 Symbol IOD3 IOD2 IOD1 IOD0 After Reset 1 0 0 0 Bit b0 b1 Symbol Bit Name IOC0 TRDGRC control bit IOC1 b3 IOC3 1 b2 IOC2 0 b1 IOC1 0 Function b1 b0 b0 IOC0 0 R/W R/W R/W b2 b3 IOC2 IOC3 b4 b5 IOD0 IOD1 b6 b7 IOD2 IOD3 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRDGRCi register 1 0: High-level output at compare match with the TRDGRCi register 1 1: Toggle output at compare match with the TRDGRCi register Set to 0 (output compare) for the output compare R/W TRDGRC mode select bit (1) function. TRDGRC register function select bit 0: TRDIOA output register R/W (Refer to 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) 1: General register or buffer register b5 b4 R/W TRDGRD control bit 0 0: Pin output by compare match is disabled R/W 0 1: Low-level output at compare match with the TRDGRDi register 1 0: High-level output at compare match with the TRDGRDi register 1 1: Toggle output at compare match with the TRDGRDi register Set to 0 (output compare) for the output compare R/W TRDGRD mode select bit (2) function. TRDGRD register function select bit 0: TRDIOB output register R/W (Refer to 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) 1: General register or buffer register Notes: 1. To select 1 (TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. REJ09B0441-0010 Rev.0.10 Page 360 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.14 Timer RD Status Register i (TRDSRi) (i = 0 or 1) for Output Compare Function Address 0143h (TRDSR0), 0153h (TRDSR1) Bit b7 b6 b5 b4 Symbol — — UDF OVF After Reset 1 1 1 0 After Reset 1 1 0 0 Bit b0 Symbol IMFA Bit Name Input-capture/compare-match flag A b3 IMFD 0 0 b2 IMFC 0 0 b1 IMFB 0 0 b0 IMFA 0 0 TRDSR0 register TRDSR1 register R/W R/W b1 IMFB b2 IMFC b3 IMFD b4 OVF b5 b6 b7 UDF — — Function [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (3). Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (3). Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. This bit is disabled for the output compare Underflow flag (1) function. Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W R/W R/W — Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) •The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). REJ09B0441-0010 Rev.0.10 Page 361 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.15 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) for Output Compare Function Address 0144h (TRDIER0), 0154h (TRDIER1) Bit b7 b6 b5 b4 Symbol — — — OVIE After Reset 1 1 1 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IMIEA Input-capture/compare-match interrupt enable bit A IMIEB Input-capture/compare-match interrupt enable bit B IMIEC Input-capture/compare-match interrupt enable bit C IMIED Input-capture/compare-match interrupt enable bit D OVIE Overflow/underflow interrupt enable bit — — — b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W R/W — Function 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.4.16 Timer RD Counter i (TRDi) (i = 0 or 1) for Output Compare Function Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1) Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset 0 0 0 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b13 — 0 b12 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units. REJ09B0441-0010 Rev.0.10 Page 362 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.17 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) for Output Compare Function Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Refer to Table 21.8 TRDGRji Register Function for Output Compare Function Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled for the output compare function: TRDDF0, TRDDF1, TRDPOCR0, and TRDPOCR1. Table 21.8 TRDGRji Register Function for Output Compare Function Register TRDGRAi TRDGRBi TRDGRCi TRDGRDi TRDGRCi TRDGRDi TRDGRCi TRDGRDi Setting BFji IOj3 − − 0 1 0 1 1 0 Output-Compare Output Pin General register. Write the compare value. TRDIOAi TRDIOBi General register. Write the compare value. TRDIOCi TRDIODi TRDIOAi Buffer register. Write the next compare value. TRDIOBi (Refer to 21.2.2 Buffer Operation.) TRDIOAi output control (Refer to 21.4.21 Changing TRDIOAi Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDIOBi TRDGRDi.) Register Function i = 0 or 1, j = either A, B, C, or D BFji: Bit in TRDMR register IOj3: Bit in TRDIORCi register REJ09B0441-0010 Rev.0.10 Page 363 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.18 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 364 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.19 Timer RD Pin Select Register 1 (TRDPSR1) Address 0185h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 365 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.20 Operating Example Count source TRDi register value m n p Count restarts Count stops TSTARTi bit in TRDSTR register 1 0 m+1 m+1 Output level held TRDIOAi output Output inverted by compare match Initial output “L” IMFA bit in TRDSRi register 1 0 Set to 0 by a program. n+1 TRDIOBi output n+1 Initial output “L” IMFB bit in TRDSRi register 1 0 Set to 0 by a program. P+1 “L” output at compare match TRDIOCi output Initial output “H” Output level held “H” output at compare match Output level held IMFC bit in TRDSRi register 1 0 Set to 0 by a program. i = 0 or 1 M: Value set in TRDGRAi register n: Value set in TRDGRBi register p: Value set in TRDGRCi register The above applies under the following conditions: The CSELi bit in the TRDSTR register is set to 1 (TRDi register count continues after compare match). Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (TRDIOAi, TRDIOBi and TRDIOCi pin output enabled). Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (TRDi register is set to 000h by compare match with the TRDGRAi register). Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output at low until compare match), the TOCi bit is set to 1 (initial output at high until compare match). Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted by TRDGRAi register compare match). Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi high-level output at TRDGRBi register compare match). Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi low-level output at TRDGRCi register compare match). The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output). Figure 21.11 Operating Example of Output Compare Function REJ09B0441-0010 Rev.0.10 Page 366 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi The TRDGRCi register can be used for output control of the TRDIOAi pin, and the TRDGRDi register can be used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows: • TRDIOAi output is controlled by the values of registers TRDGRAi and TRDGRCi. • TRDIOBi output is controlled by the values of registers TRDGRBi and TRDGRDi. Timer RD0 TRD0 Compare match signal Output control TRDIOA0 IOC3 = 0 in TRDIORC0 register Comparator TRDGRA0 Compare match signal TRDIOC0 Output control IOC3 = 1 Comparator Compare match signal TRDGRC0 TRDIOB0 Output control IOD3 = 0 in TRDIORD0 register Comparator TRDGRB0 Compare match signal TRDIOD0 Output control IOD3 = 1 Comparator TRDGRD0 Timer RD1 TRD1 Compare match signal Output control TRDIOA1 IOC3 = 0 in TRDIORC1 register Comparator TRDGRA1 Compare match signal TRDIOC1 Output control IOC3 = 1 Comparator Compare match signal TRDGRC1 TRDIOB1 Output control IOD3 = 0 in TRDIORD1 register Comparator TRDGRB1 Compare match signal TRDIOD1 Output control IOD3 = 1 Comparator TRDGRD1 Figure 21.12 Changing Output Pins in Registers TRDGRCi and TRDGRDi Change output pins in registers TRDGRCi and TRDGRDi as follows: • Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register. • Set the BFji bit in the TRDMR register to 0 (general register). • Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers TRDGRDi and TRDGRBi. REJ09B0441-0010 Rev.0.10 Page 367 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Figure 21.13 shows an Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin. Count source TRDi register value FFFFh m n p q 0000h m+1 n+1 p+1 q+1 Initial output “L” TRDIOAi output Output inverted by compare match IMFA bit in TRDSRi register 1 0 Set to 0 by a program. IMFC bit in TRDSRi register 1 0 Set to 0 by a program. p-q m-n Initial output “L” TRDIOBi output Output inverted by compare match IMFB bit in TRDSRi register 1 0 Set to 0 by a program. IMFD bit in TRDSRi register 1 0 Set to 0 by a program. i = 0 or 1 m: Value set in TRDGRAi register n: Value set in TRDGRCi register p: Value set in TRDGRBi register q: Value set in TRDGRDi register The above applies under the following conditions: The CSELi bit in the TRDSTR register is set to 1 (TRDi register count continues after compare match). Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EAi and EBi in the TRDOER1 register are set to 0 (TRDIOAi and TRDIOBi pin output enabled). Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (TRDi register is set to 0000h by compare match with the TRDGRAi register). Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output at low until compare match). Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted by TRDGRAi register compare match). Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted by TRDGRBi register compare match). Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted by TRDGRCi register compare match). Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted by TRDGRDi register compare match). Figure 21.13 Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin REJ09B0441-0010 Rev.0.10 Page 368 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.4.22 A/D Trigger Generation A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used. REJ09B0441-0010 Rev.0.10 Page 369 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5 PWM Mode In PWM mode, a PWM waveform is output. Up to three PWM waveforms with the same period can be output by timer RDi (i = 0 or 1). Also, up to six PWM waveforms with the same period can be output by synchronizing timer RD0 and timer RD1. Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and TRDGRji register, PWM mode, or any other mode or function, can be selected for each individual pin. (However, since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used for other modes.) Figure 21.14 shows a Block Diagram of PWM Mode, and Table 21.9 lists the PWM Mode Specifications. Figures 21.15 and 21.16 show Operation Examples in PWM Mode. TRDi Compare match signal TRDIOBi Compare match signal Comparator TRDGRAi (Note 1) TRDIOCi Output control Comparator Compare match signal TRDGRBi TRDIODi Compare match signal Comparator TRDGRCi (Note 2) Comparator TRDGRDi i = 0 or 1 Notes: 1. When the BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). 2. When the BFDi bit in the TRDMR register is set to 1 (TRDGRDi register is used as the buffer register of the TRDGRBi register). Figure 21.14 Block Diagram of PWM Mode REJ09B0441-0010 Rev.0.10 Page 370 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.9 PWM Mode Specifications Item Count sources Count operations PWM waveform Specification f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Increment PWM period: 1/fk x (m+1) Active level width: 1/fk x (m-n) Inactive level width: 1/fk x (n+1) fk: Frequency of count source m: Value set in TRDGRAi register n: Value set in TRDGRji register m +1 n+1 m -n (Active level is low) 1 (count starts) is written to the TSTARTi bit in the TRDSTR register. • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops. • When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRAi register. The PWM output pin holds the level after the output changes by the compare match. Interrupt request generation • Compare match (the contents of the TRDi register and the TRDGRhi register match.) timing • TRDi register overflow TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input TRDIOA1 pin function Programmable I/O port TRDIOB0, TRDIOC0, TRDIOD0, Programmable I/O port or pulse output TRDIOB1, TRDIOC1, TRDIOD1 (selectable for each individual pin) pins function INT0 pin function Read from timer Write to timer Selectable functions Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRDi register. The value can be written to the TRDi register. • One to three PWM output pins selectable per timer RDi Either one pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi pin. • Active level selectable for each individual pin. • Initial output level selectable for each individual pin. • Synchronous operation (Refer to 21.2.3 Synchronous Operation.) • Buffer operation (Refer to 21.2.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.) • A/D trigger generation Count start condition Count stop conditions i = 0 or 1 j = either B, C, or D h = either A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 371 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. REJ09B0441-0010 Rev.0.10 Page 372 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.2 Timer RD Control Expansion Register (TRDECR) b6 — 0 b5 — 0 b4 — 0 b3 ITCLK0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0135h Bit b7 Symbol ITCLK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W — R/W 21.5.3 Timer RD Trigger Control Register (TRDADCR) Address 0136h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E After Reset 0 0 0 0 0 0 0 0 Bit b0 Symbol Bit Name ADTRGA0E A/D trigger A0 enable bit Function 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W R/W b1 ADTRGB0E A/D trigger B0 enable bit R/W b2 ADTRGC0E A/D trigger C0 enable bit R/W b3 ADTRGD0E A/D trigger D0 enable bit R/W b4 ADTRGA1E A/D trigger A1 enable bit R/W b5 ADTRGB1E A/D trigger B1 enable bit R/W b6 ADTRGC1E A/D trigger C1 enable bit R/W b7 ADTRGD1E A/D trigger D1 enable bit R/W REJ09B0441-0010 Rev.0.10 Page 373 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.4 Timer RD Start Register (TRDSTR) in PWM Mode b6 — 1 b5 — 1 b4 — 1 b3 CSEL1 1 b2 b1 b0 CSEL0 TSTART1 TSTART0 1 0 0 R/W R/W R/W R/W Address 0137h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 Symbol Bit Name TSTART0 TRD0 count start flag (3) b3 b4 b5 b6 b7 Function 0: Count stops (1) 1: Count starts TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — R/W — Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. 21.5.5 Timer RD Mode Register (TRDMR) in PWM Mode b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 — 1 b2 — 1 b1 — 1 b0 SYNC 0 R/W R/W — Address 0138h Bit b7 Symbol BFD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol SYNC — — — BFC0 BFD0 BFC1 BFD1 Bit Name Timer RD synchronous bit Function 0: Registers TRD0 and TRD1 operate independently 1: Registers TRD0 and TRD1 operate synchronously Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit TRDGRD0 register function select bit TRDGRC1 register function select bit TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRA0 register 0: General register 1: Buffer register of TRDGRB0 register 0: General register 1: Buffer register of TRDGRA1 register 0: General register 1: Buffer register of TRDGRB1 register R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 374 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.6 Timer RD PWM Mode Register (TRDPMR) in PWM Mode b6 b5 PWMD1 PWMC1 0 0 b4 PWMB1 0 b3 — 1 b2 b1 PWMD0 PWMC0 0 0 b0 PWMB0 0 R/W R/W R/W R/W — R/W R/W R/W — Address 0139h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol PWMB0 PWMC0 PWMD0 — PWMB1 PWMC1 PWMD1 — Bit Name Function PWM mode of TRDIOB0 select bit 0: Timer mode 1: PWM mode PWM mode of TRDIOC0 select bit PWM mode of TRDIOD0 select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOB1 select bit 0: Timer mode 1: PWM mode PWM mode of TRDIOC1 select bit PWM mode of TRDIOD1 select bit Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.5.7 Timer RD Function Control Register (TRDFCR) in PWM Mode b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 b1 CMD1 0 b0 CMD0 0 R/W R/W R/W R/W Address 013Ah Bit b7 Symbol PWM3 After Reset 1 Bit b0 b1 b2 Symbol CMD0 CMD1 OLS0 Bit Name Combination mode select bit (1) Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit (2) Function Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM mode. Disabled in PWM mode. b3 OLS1 R/W b4 b5 b6 b7 ADTRG ADEG STCLK PWM3 R/W R/W 0: External clock input disabled 1: External clock input enabled Set to 1 (other than PWM3 mode) in PWM mode. R/W R/W Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. REJ09B0441-0010 Rev.0.10 Page 375 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.8 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM Mode b6 EC1 1 b5 EB1 1 b4 EA1 1 b3 ED0 1 b2 EC0 1 b1 EB0 1 b0 EA0 1 R/W R/W R/W Address 013Bh Bit b7 Symbol ED1 After Reset 1 Bit b0 b1 Symbol Bit Name EA0 TRDIOA0 output disable bit EB0 TRDIOB0 output disable bit b2 EC0 TRDIOC0 output disable bit b3 ED0 TRDIOD0 output disable bit b4 b5 EA1 EB1 TRDIOA1 output disable bit TRDIOB1 output disable bit b6 EC1 TRDIOC1 output disable bit b7 ED1 TRDIOD1 output disable bit Function Set to 1 (TRDIOA0 pin is used as a programmable I/O port) in PWM mode. 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) Set to 1 (TRDIOA1 pin is used as a programmable I/O port) in PWM mode. 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W R/W R/W R/W R/W R/W 21.5.9 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM Mode b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W — — — — — — — R/W Address 013Ch Bit b7 Symbol PTO After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — — — — 0: Pulse output forced cutoff input disabled PTO INT0 of pulse output forced cutoff 1: Pulse output forced cutoff input enabled signal input enabled bit (1) (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. REJ09B0441-0010 Rev.0.10 Page 376 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.10 Timer RD Output Control Register (TRDOCR) in PWM Mode Address 013Dh Bit b7 Symbol TOD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TOA0 TOB0 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1 b6 TOC1 0 b5 TOB1 0 b4 TOA1 0 b3 TOD0 0 b2 TOC0 0 b1 TOB0 0 b0 TOA0 0 Bit Name TRDIOA0 output level select bit TRDIOB0 output level select bit (1) TRDIOC0 initial output level select bit (1) TRDIOD0 initial output level select bit (1) TRDIOA1 initial output level select bit TRDIOB1 initial output level select bit (1) TRDIOC1 initial output level select bit (1) TRDIOD1 initial output level select bit (1) R/W R/W R/W R/W R/W Set this bit to 0 (output enabled) in PWM mode. R/W 0: Inactive level R/W 1: Active level R/W R/W Function Set to 0 (output enabled) in PWM mode. 0: Initial output is inactive level 1: Initial output is active level Note: 1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRDOCR register is set. Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 21.5.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in PWM Mode Address 0140h (TRDCR0), 0150h (TRDCR1) Bit b7 b6 b5 b4 Symbol CCLR2 CCLR1 CCLR0 CKEG1 After Reset 0 0 0 0 Bit b0 b1 b2 Symbol Bit Name TCK0 Count source select bit TCK1 TCK2 b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 b0 TCK0 0 R/W R/W R/W R/W 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. b4 b3 b3 b4 CKEG0 External clock edge select bit (3) CKEG1 b5 b6 b7 CCLR0 TRDi counter clear select bit CCLR1 CCLR2 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. Set to 001b (TRDi register cleared by compare match with TRDGRAi register) in PWM mode. R/W R/W R/W R/W R/W Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). REJ09B0441-0010 Rev.0.10 Page 377 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.12 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM Mode Address 0143h (TRDSR0), 0153h (TRDSR1) Bit b7 b6 b5 b4 Symbol — — UDF OVF After Reset 1 1 1 0 After Reset 1 1 0 0 Bit b0 Symbol IMFA Bit Name Input-capture/compare-match flag A b3 IMFD 0 0 b2 IMFC 0 0 b1 IMFB 0 0 b0 IMFA 0 0 TRDSR0 register TRDSR1 register R/W R/W b1 IMFB b2 IMFC b3 IMFD b4 OVF b5 b6 b7 UDF — — Function [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value. (3) Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value. (3) Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. (1) This bit is disabled in PWM Mode. Underflow flag Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W R/W R/W — Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). REJ09B0441-0010 Rev.0.10 Page 378 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.13 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM Mode Address 0144h (TRDIER0), 0154h (TRDIER1) Bit b7 b6 b5 b4 Symbol — — — OVIE After Reset 1 1 1 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IMIEA Input-capture/compare-match interrupt enable bit A IMIEB Input-capture/compare-match interrupt enable bit B IMIEC Input-capture/compare-match interrupt enable bit C IMIED Input-capture/compare-match interrupt enable bit D OVIE Overflow/underflow interrupt enable bit — — — b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W R/W — Function 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by IMFD bit enabled 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or 1) in PWM Mode Address 0145h (TRDPOCR0), 0155h (TRDPOCR1) Bit b7 b6 b5 b4 Symbol — — — — After Reset 1 1 1 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name POLB PWM mode output level control bit B POLC POLD — — — — — b3 — 1 b2 POLD 0 b1 POLC 0 b0 POLB 0 R/W R/W R/W R/W — Function 0: TRDIOBi output level is selected as low active 1: TRDIOBi output level is selected as high active PWM mode output level control bit C 0: TRDIOCi output level is selected as low active 1: TRDIOCi output level is selected as high active PWM mode output level control bit D 0: TRDIODi output level is selected as low active 1: TRDIODi output level is selected as high active Nothing is assigned. If necessary, set to 0. When read, the content is 1. REJ09B0441-0010 Rev.0.10 Page 379 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.15 Timer RD Counter i (TRDi) (i = 0 or 1) in PWM Mode Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1) Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset 0 0 0 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b13 — 0 b12 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units. REJ09B0441-0010 Rev.0.10 Page 380 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.16 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM Mode Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Refer to Table 21.10 TRDGRji Register Functions in PWM Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled in PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDIORA1, and TRDIORC1. Table 21.10 TRDGRji Register Functions in PWM Mode Register TRDGRAi TRDGRBi TRDGRCi TRDGRDi TRDGRCi TRDGRDi Setting − − BFCi = 0 BFDi = 0 BFCi = 1 BFDi = 1 Register Function PWM Output Pin General register. Set the PWM period − General register. Set the changing point of PWM output TRDIOBi General register. Set the changing point of PWM output TRDIOCi TRDIODi Buffer register. Set the next PWM period − (Refer to 21.2.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM TRDIOBi output (Refer to 21.2.2 Buffer Operation.) i = 0 or 1 BFCi, BFDi: Bits in TRDMR register REJ09B0441-0010 Rev.0.10 Page 381 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.17 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 382 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.18 Timer RD Pin Select Register 1 (TRDPSR1) Address 0185h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 383 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.19 Operating Example Count source TRDi register value m n p q m+1 n+1 Active level “H” TRDIOBi output Initial output “L” until compare match Inactive level “L” p+1 m-p m-n TRDIOCi output Initial output “H” utnil compare match Inactive level “H” q+1 m-q TRDIODi output Active level “L” Initial output “L” until compare match IMFA bit in TRDSRi register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRDSRi register 1 0 IMFC bit in TRDSRi register 1 0 Set to 0 by a program. Set to 0 by a program. IMFD bit in TRDSRi register 1 0 i = 0 or 1 m: Value set in TRDGRAi register n: Value set in TRDGRBi register p: Value set in TRDGRCi register q: Value set in TRDGRDi register The above applies under the following conditions: Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (TRDIOBi, TRDIOCi and TRDIODi pin output enabled). Bits TOBi and TOCi in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1 (active level). The POLB bit in the TRDPOCRi register is set to 1 (active level is high), bits POLC and POLD are set to 0 (active level is low). Figure 21.15 Operating Example in PWM Mode REJ09B0441-0010 Rev.0.10 Page 384 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD TRDi register value p m q n 0000h TSTARTi bit in TRDSTR register 1 0 Since no compare match with TRDGRBi register is generated, “L” is not applied to TRDIOBi output. Duty 0% TRDIOBi output TRDGRBi register n p (p>m) Rewrite by a program. q IMFA bit in TRDSRi register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRDSRi register 1 0 TRDi register value m p n 0000h TSTARTi bit in TRDSTR register 1 0 When compare matches with registers TRDGRAi and TRDGRBi are generated simultaneously, compare match with TRDGRBi register has priority. “L” is applied to TRDIOBi output (no change). Duty 100% “L” is applied to TRDIOBi output at compare match with TRDGRBi register (no change). TRDIOBi output TRDGRBi register n m Rewrite by a program. p IMFA bit in TRDSRi register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRDSRi register 1 0 i = 0 or 1 m: Value set in TRDGRAi register The above applies under the following conditions: The EBi bit in the TRDOER1 register is set to 0 (TRDIOBi pin output enabled). The POLB bit in the TRDPOCRi register is set to 0 (active level is low). Figure 21.16 Operating Example in PWM Mode (Duty 0%, Duty 100%) REJ09B0441-0010 Rev.0.10 Page 385 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.5.20 A/D Trigger Generation A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used. REJ09B0441-0010 Rev.0.10 Page 386 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6 Reset Synchronous PWM Mode In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period (three-phase, sawtooth wave modulation, and no dead time). Figure 21.17 shows a Block Diagram of Reset Synchronous PWM Mode, and Table 21.11 lists the Reset Synchronous PWM Mode Specifications. Figure 21.18 shows an Operating Example in Reset Synchronous PWM Mode. Refer to Figure 21.16 Operating Example in PWM Mode (Duty 0%, Duty 100%) for an operating example in PWM Mode with duty 0% and duty 100%. Buffer (1) TRDGRC0 register TRDGRA0 register Waveform control Period Normal-phase TRDIOC0 TRDGRD0 register TRDGRC1 register TRDGRD1 register TRDGRB0 register TRDGRA1 register TRDGRB1 register TRDIOB0 PWM1 Counter-phase TRDIOD0 Normal-phase TRDIOA1 PWM2 Counter-phase TRDIOC1 Normal-phase TRDIOB1 PWM3 Counter-phase TRDIOD1 Note: 1.When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register). Figure 21.17 Block Diagram of Reset Synchronous PWM Mode REJ09B0441-0010 Rev.0.10 Page 387 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.11 Reset Synchronous PWM Mode Specifications Item Count sources Count operations PWM waveform Specification f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) The TRD0 register is incremented (TRD1 register is not used). PWM period : 1/fk × (m+1) Active level width of normal-phase : 1/fk × (m-n) Active level width of counter-phase: 1/fk × (n+1) fk: Frequency of count source m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register (PWM1 output), Value set in TRDGRA1 register (PWM2 output), Value set in TRDGRB1 register (PWM3 output) m+1 Normal-phase m-n Counter-phase n+1 (Active level is low) Count start condition Count stop conditions Interrupt request generation timing TRDIOA0 pin function TRDIOB0 pin function TRDIOD0 pin function TRDIOA1 pin function TRDIOC1 pin function TRDIOB1 pin function TRDIOD1 pin function TRDIOC0 pin function INT0 pin function Read from timer Write to timer Selectable functions 1 (count starts) is written to the TSTART0 bit in the TRDSTR register. • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. The PWM output pin holds the output level before the count stops • When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRA0 register. The PWM output pin holds the level after the output changes by the compare match. • Compare match (the content of the TRD0 register matches the contents of registers TRDGRj0, TRDGRA1, and TRDGRB1). • TRD0 register overflow Programmable I/O port or TRDCLK (external clock) input PWM1 output normal-phase output PWM1 output counter-phase output PWM2 output normal-phase output PWM2 output counter-phase output PWM3 output normal-phase output PWM3 output counter-phase output Output inverted every PWM period Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRD0 register. The value can be written to the TRD0 register. • The normal-phase and counter-phase active level and initial output level can be selected individually. • Buffer operation (Refer to 21.2.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.) • A/D trigger generation j = either A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 388 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. REJ09B0441-0010 Rev.0.10 Page 389 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.2 Timer RD Control Expansion Register (TRDECR) b6 — 0 b5 — 0 b4 — 0 b3 ITCLK0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0135h Bit b7 Symbol ITCLK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W — R/W 21.6.3 Timer RD Trigger Control Register (TRDADCR) Address 0136h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E After Reset 0 0 0 0 0 0 0 0 Bit b0 Symbol Bit Name ADTRGA0E A/D trigger A0 enable bit Function 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W R/W b1 ADTRGB0E A/D trigger B0 enable bit R/W b2 ADTRGC0E A/D trigger C0 enable bit R/W b3 ADTRGD0E A/D trigger D0 enable bit R/W b4 ADTRGA1E A/D trigger A1 enable bit R/W b5 ADTRGB1E A/D trigger B1 enable bit R/W b6 ADTRGC1E A/D trigger C1 enable bit R/W b7 ADTRGD1E A/D trigger D1 enable bit R/W REJ09B0441-0010 Rev.0.10 Page 390 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.4 Timer RD Start Register (TRDSTR) in Reset Synchronous PWM Mode b6 — 1 b5 — 1 b4 — 1 b3 CSEL1 1 b2 b1 b0 CSEL0 TSTART1 TSTART0 1 0 0 R/W R/W R/W R/W Address 0137h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 Symbol Bit Name TSTART0 TRD0 count start flag (3) b3 b4 b5 b6 b7 Function 0: Count stops (1) 1: Count starts TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — R/W — Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. 21.6.5 Timer RD Mode Register (TRDMR) in Reset Synchronous PWM Mode b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 — 1 b2 — 1 b1 — 1 b0 SYNC 0 R/W R/W — Address 0138h Bit b7 Symbol BFD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol SYNC — — — BFC0 BFD0 BFC1 BFD1 Bit Name Timer RD synchronous bit Function Set to 0 (registers TRD and TRD1 operate independently) in reset synchronous PWM mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit 0: General register 1: Buffer register of TRDGRA0 register TRDGRD0 register function select bit 0: General register 1: Buffer register of TRDGRB0 register TRDGRC1 register function select bit 0: General register 1: Buffer register of TRDGRA1 register TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRB1 register R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 391 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.6 Timer RD Function Control Register (TRDFCR) in Reset Synchronous PWM Mode b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 b1 CMD1 0 b0 CMD0 0 R/W R/W R/W R/W Address 013Ah Bit b7 Symbol PWM3 After Reset 1 Bit b0 b1 b2 Symbol CMD0 CMD1 OLS0 Bit Name Combination mode select bit (1, 2) Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit (3) Function Set to 01b (reset synchronous PWM mode) in reset synchronous PWM mode. 0: Initial output at high, active level is low 1: Initial output at low, active level is high b3 OLS1 R/W b4 b5 b6 b7 ADTRG ADEG STCLK PWM3 Disabled in reset synchronous PWM mode. R/W R/W 0: External clock input disabled 1: External clock input enabled Disabled in reset synchronous PWM mode. R/W R/W Notes: 1. When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or complementary PWM mode in spite of the setting of the TRDPMR register. 2. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits are set to 0 (count stops). 3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. REJ09B0441-0010 Rev.0.10 Page 392 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Reset Synchronous PWM Mode b6 EC1 1 b5 EB1 1 b4 EA1 1 b3 ED0 1 b2 EC0 1 b1 EB0 1 b0 EA0 1 R/W R/W R/W Address 013Bh Bit b7 Symbol ED1 After Reset 1 Bit b0 b1 Symbol Bit Name EA0 TRDIOA0 output disable bit EB0 TRDIOB0 output disable bit b2 EC0 TRDIOC0 output disable bit b3 ED0 TRDIOD0 output disable bit b4 EA1 TRDIOA1 output disable bit b5 EB1 TRDIOB1 output disable bit b6 EC1 TRDIOC1 output disable bit b7 ED1 TRDIOD1 output disable bit Function Set to 1 (TRDIOA0 pin is used as a programmable I/O port) in reset synchronous PWM mode. 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOA1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W R/W R/W R/W R/W R/W 21.6.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Reset Synchronous PWM Mode b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W — — — — — — — R/W Address 013Ch Bit b7 Symbol PTO After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 0 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — — — — 0: Pulse output forced cutoff input disabled PTO INT0 of pulse output forced cutoff 1: Pulse output forced cutoff input enabled (1) signal input enabled bit (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. REJ09B0441-0010 Rev.0.10 Page 393 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.9 Timer RD Control Register 0 (TRDCR0) in Reset Synchronous PWM Mode b6 CCLR1 0 b5 CCLR0 0 b4 CKEG1 0 b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 Address 0140h Bit b7 Symbol CCLR2 After Reset 0 Bit b0 b1 b2 b0 TCK0 0 R/W R/W R/W R/W Symbol Bit Name TCK0 Count source select bit TCK1 TCK2 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. b4 b3 b3 b4 CKEG0 External clock edge select bit (3) CKEG1 b5 b6 b7 CCLR0 TRD0 counter clear select bit CCLR1 CCLR2 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. Set to 001b (TRD0 register cleared at compare match with TRDGRA0 register) in reset synchronous PWM mode. R/W R/W R/W R/W R/W Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). The TRDCR1 register is not used in reset synchronous PWM mode. REJ09B0441-0010 Rev.0.10 Page 394 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Reset Synchronous PWM Mode Address 0143h (TRDSR0), 0153h (TRDSR1) Bit b7 b6 b5 b4 Symbol — — UDF OVF After Reset 1 1 1 0 After Reset 1 1 0 0 Bit b0 Symbol IMFA Bit Name Input-capture/compare-match flag A b3 IMFD 0 0 b2 IMFC 0 0 b1 IMFB 0 0 b0 IMFA 0 0 TRDSR0 register TRDSR1 register R/W R/W b1 IMFB b2 IMFC b3 IMFD b4 OVF b5 b6 b7 UDF — — Function [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (3). Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (3). Overflow flag [Condition for setting this bit to 0] Write 0 after reading (2) [Condition for setting this bit to 1] When the TRDi register overflows. This bit is disabled in reset synchronous PWM Underflow flag (1) mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W R/W R/W — Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). REJ09B0441-0010 Rev.0.10 Page 395 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Reset Synchronous PWM Mode Address 0144h (TRDIER0), 0154h (TRDIER1) Bit b7 b6 b5 b4 Symbol — — — OVIE After Reset 1 1 1 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IMIEA Input-capture/compare-match interrupt enable bit A IMIEB Input-capture/compare-match interrupt enable bit B IMIEC Input-capture/compare-match interrupt enable bit C IMIED Input-capture/compare-match interrupt enable bit D OVIE Overflow/underflow interrupt enable bit — — — b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W R/W — Function 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.6.12 Timer RD Counter 0 (TRD0) in Reset Synchronous PWM Mode Address 0147h to 0146h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b5 — 0 b13 — 0 b4 — 0 b12 — 0 b3 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. The TRD1 register is not used in reset synchronous PWM mode. REJ09B0441-0010 Rev.0.10 Page 396 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.13 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) in Reset Synchronous PWM Mode Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Refer to Table 21.12 TRDGRji Register Functions in Reset Synchronous PWM Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled in reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. Table 21.12 TRDGRji Register Functions in Reset Synchronous PWM Mode Register TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 TRDGRC0 TRDGRD0 Setting − − Register Function General register. Set the PWM period. General register. Set the changing point of PWM1 output. (These registers are not used in reset synchronous PWM mode.) General register. Set the changing point of PWM2 output. General register. Set the changing point of PWM3 output. (These points are not used in reset synchronous PWM mode.) Buffer register. Set the next PWM period. (Refer to 21.2.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM1 output. (Refer to 21.2.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM2 output. (Refer to 21.2.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM3 output. (Refer to 21.2.2 Buffer Operation.) BFC0 = 0 BFD0 = 0 − − PWM Output Pin (Output inverted every PWM period and TRDIOC0 pin) TRDIOB0 TRDIOD0 − TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 − (Output inverted every PWM period and TRDIOC0 pin) TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 BFC1 = 0 BFD1 = 0 BFC0 = 1 BFD0 = 1 TRDGRC1 BFC1 = 1 TRDGRD1 BFD1 = 1 BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register REJ09B0441-0010 Rev.0.10 Page 397 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.14 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 398 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.15 Timer RD Pin Select Register 1 (TRDPSR1) Address 0185h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 399 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.16 Operating Example Count source TRD0 register value m n p q 0000h TSTARTi bit in TRDSTR register 1 0 m+1 m-n TRDIOB0 output n+1 TRDIOD0 output m-p TRDIOA1 output p+1 TRDIOC1 output m-q TRDIOB1 output Initial output “H” q+1 TRDIOD1 output Active level “L” Active level “L” TRDIOC0 output Initial output “H” IMFA bit in TRDSR0 register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRDSR0 register 1 0 IMFA bit in TRDSR1 register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRDSR1 register 1 0 Transfer from the buffer register to the general register during buffer operation Transfer from the buffer register to the general register during buffer operation i = 0 or 1 m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register p: Value set in TRDGRA1 register q: Value set in TRDGRB1 register The above applies under the following condition: Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output at high, active level is low). Figure 21.18 Operating Example in Reset Synchronous PWM Mode REJ09B0441-0010 Rev.0.10 Page 400 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.6.17 A/D Trigger Generation A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used. REJ09B0441-0010 Rev.0.10 Page 401 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7 Complementary PWM Mode In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period (three-phase, triangular wave modulation, and with dead time). Figure 21.19 shows a Block Diagram of Complementary PWM Mode, and Table 21.13 lists the Complementary PWM Mode Specifications. Figure 21.20 shows the Output Model in Complementary PWM Mode, and Figure 21.21 shows an Operating Example in Complementary PWM Mode. Buffer TRDGRA0 register Waveform control Period TRDIOC0 Normal-phase TRDGRD0 register TRDGRC1 register TRDGRD1 register TRDGRB0 register TRDGRA1 register TRDGRB1 register PWM1 Counter-phase Normal-phase PWM2 Counter-phase Normal-phase PWM3 Counter-phase TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 Figure 21.19 Block Diagram of Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 402 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.13 Complementary PWM Mode Specifications Specification f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count source) as bits TCK2 to TCK0 in the TRDCR0 register. Increment or decrement Registers TRD0 and TRD1 are decremented by the compare match with registers TRD0 and TRDGRA0 during increment operation. The TRD1 register value is changed from 0000h to FFFFh during decrement operation, and registers TRD0 and TRD1 are incremented. PWM period: 1/fk × (m+2-p) × 2 (1) Dead time: p Active level width of normal-phase: 1/fk × (m-n-p+1) × 2 Active level width of counter-phase: 1/fk × (n+1-p) × 2 fk: Frequency of count source m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register (PWM1 output) Value set in TRDGRA1 register (PWM2 output) Value set in TRDGRB1 register (PWM3 output) p: Value set in TRD0 register m+2-p n+1 Normal-phase Item Count sources Count operations PWM operations Counter-phase n+1-p p m-p-n+1 (Active level is low) Count start condition Count stop conditions Interrupt request generation timing TRDIOA0 pin function TRDIOB0 pin function TRDIOD0 pin function TRDIOA1 pin function TRDIOC1 pin function TRDIOB1 pin function TRDIOD1 pin function TRDIOC0 pin function INT0 pin function Read from timer Write to timer Selectable functions 1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register. 0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. (The PWM output pin holds the output level before the count stops.) • Compare match (The contents of the TRDi register and the TRDGRji register match.) • TRD1 register underflow Programmable I/O port or TRDCLK (external clock) input PWM1 output normal-phase output PWM1 output counter-phase output PWM2 output normal-phase output PWM2 output counter-phase output PWM3 output normal-phase output PWM3 output counter-phase output Output inverted every 1/2 period of PWM Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input The count value can be read by reading the TRDi register. The value can be written to the TRDi register. • Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.) • The normal-phase and counter-phase active level and initial output level can selected individually. • Selectable transfer timing from the buffer register • A/D trigger generation i = 0 or 1, j = either A, B, C, or D Note: 1. After a count starts, the PWM period is fixed. REJ09B0441-0010 Rev.0.10 Page 403 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. 21.7.2 Timer RD Control Expansion Register (TRDECR) b6 — 0 b5 — 0 b4 — 0 b3 ITCLK0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0135h Bit b7 Symbol ITCLK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W — R/W REJ09B0441-0010 Rev.0.10 Page 404 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.3 Timer RD Trigger Control Register (TRDADCR) Address 0136h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E After Reset 0 0 0 0 0 0 0 0 Bit b0 Symbol Bit Name ADTRGA0E A/D trigger A0 enable bit Function 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W R/W b1 ADTRGB0E A/D trigger B0 enable bit R/W b2 ADTRGC0E A/D trigger C0 enable bit R/W b3 ADTRGD0E A/D trigger D0 enable bit R/W b4 ADTRGA1E A/D trigger A1 enable bit R/W b5 ADTRGB1E A/D trigger B1 enable bit R/W b6 ADTRGC1E A/D trigger C1 enable bit R/W b7 ADTRGD1E A/D trigger D1 enable bit R/W REJ09B0441-0010 Rev.0.10 Page 405 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.4 Timer RD Start Register (TRDSTR) in Complementary PWM Mode b6 — 1 b5 — 1 b4 — 1 b3 CSEL1 1 b2 b1 b0 CSEL0 TSTART1 TSTART0 1 0 0 R/W R/W R/W R/W Address 0137h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 Symbol Bit Name TSTART0 TRD0 count start flag (3) b3 b4 b5 b6 b7 Function 0: Count stops (1) 1: Count starts TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — R/W — Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. 21.7.5 Timer RD Mode Register (TRDMR) in Complementary PWM Mode b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 — 1 b2 — 1 b1 — 1 b0 SYNC 0 R/W R/W — Address 0138h Bit b7 Symbol BFD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol SYNC — — — BFC0 BFD0 BFC1 BFD1 Bit Name Timer RD synchronous bit Function Set to 0 (registers TRD0 and TRD1 operate independently) in complementary PWM mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit TRDGRD0 register function select bit TRDGRC1 register function select bit TRDGRD1 register function select bit Set to 0 (general register) in complementary PWM mode. 0: General register 1: Buffer register of TRDGRB0 register 0: General register 1: Buffer register of TRDGRA1 register 0: General register 1: Buffer register of TRDGRB1 register R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 406 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.6 Timer RD Function Control Register (TRDFCR) in Complementary PWM Mode b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 b1 CMD1 0 Function b1 b0 Address 013Ah Bit b7 Symbol PWM3 After Reset 1 Bit b0 b1 Symbol CMD0 CMD1 b0 CMD0 0 R/W R/W R/W Bit Name Combination mode select bit (1, 2) b2 OLS0 b3 OLS1 b4 b5 ADTRG ADEG Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) 1 0: Complementary PWM mode (transfer from the buffer register to the general register at TRD1 register underflow) 1 1: Complementary PWM mode (transfer from the buffer register to the general register at compare match with registers TRD0 and TRDGRA0.) Other than above: Do not set. 0: Initial output at high, active level is low 1: Initial output at low, active level is high 0: Initial output at high, active level is low 1: Initial output at low, active level is high 0: A/D trigger disabled 1: A/D trigger enabled (3) 0: A/D trigger is generated at compare match between registers TRD0 and TRDGRA0 1: A/D trigger is generated at underflow in the TRD1 register 0: External clock input disabled 1: External clock input enabled Disabled in complementary PWM mode. R/W R/W R/W R/W b6 b7 STCLK PWM3 External clock input select bit PWM3 mode select bit (4) R/W R/W Notes: 1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of the TRDPMR register. 2. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 3. Set the ADCAP bit in the ADCON0 register to 1 (start by timer RD). 4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. REJ09B0441-0010 Rev.0.10 Page 407 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Complementary PWM Mode b6 EC1 1 b5 EB1 1 b4 EA1 1 b3 ED0 1 b2 EC0 1 b1 EB0 1 b0 EA0 1 R/W R/W R/W Address 013Bh Bit b7 Symbol ED1 After Reset 1 Bit b0 b1 Symbol Bit Name EA0 TRDIOA0 output disable bit EB0 TRDIOB0 output disable bit b2 EC0 TRDIOC0 output disable bit b3 ED0 TRDIOD0 output disable bit b4 EA1 TRDIOA1 output disable bit b5 EB1 TRDIOB1 output disable bit b6 EC1 TRDIOC1 output disable bit b7 ED1 TRDIOD1 output disable bit Function Set to 1 (TRDIOA0 pin is used as a programmable I/O port) in complementary PWM mode. 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOA1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W R/W R/W R/W R/W R/W 21.7.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Complementary PWM Mode b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W — — — — — — — R/W Address 013Ch Bit b7 Symbol PTO After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 0 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — — — — 0: Pulse output forced cutoff input disabled PTO INT0 of pulse output forced cutoff 1: Pulse output forced cutoff input enabled (1) signal input enabled bit (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. REJ09B0441-0010 Rev.0.10 Page 408 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.9 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Complementary PWM Mode b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 Address 0140h (TRDCR0), 0150h (TRDCR1) Bit b7 b6 b5 b4 Symbol CCLR2 CCLR1 CCLR0 CKEG1 After Reset 0 0 0 0 Bit b0 b1 b2 Symbol Bit Name TCK0 Count source select bit (3) TCK1 TCK2 b0 TCK0 0 R/W R/W R/W R/W 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. b4 b3 b3 b4 CKEG0 External clock edge select bit (3, 4) CKEG1 b5 b6 b7 CCLR0 TRDi counter clear select bit CCLR1 CCLR2 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. Set to 000b (clear disabled (free-running operation)) in complementary PWM mode. R/W R/W R/W R/W R/W Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values. 4. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). REJ09B0441-0010 Rev.0.10 Page 409 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Complementary PWM Mode Address 0143h (TRDSR0), 0153h (TRDSR1) Bit b7 b6 b5 b4 Symbol — — UDF OVF After Reset 1 1 1 0 After Reset 1 1 0 0 Bit b0 Symbol IMFA Bit Name Input-capture/compare-match flag A b3 IMFD 0 0 b2 IMFC 0 0 b1 IMFB 0 0 b0 IMFA 0 0 TRDSR0 register TRDSR1 register R/W R/W b1 IMFB b2 IMFC b3 IMFD b4 OVF b5 UDF b6 b7 — — Function [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (3). Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (3). Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. [Condition for setting this bit to 0] Underflow flag (1) Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRD1 register underflows. Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W R/W R/W — Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). REJ09B0441-0010 Rev.0.10 Page 410 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Complementary PWM Mode Address 0144h (TRDIER0), 0154h (TRDIER1) Bit b7 b6 b5 b4 Symbol — — — OVIE After Reset 1 1 1 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W R/W — Symbol Bit Name Function IMIEA Input-capture/compare-match interrupt 0: Interrupt (IMIA) by IMFA bit disabled enable bit A 1: Interrupt (IMIA) by IMFA bit enabled IMIEB Input-capture/compare-match interrupt 0: Interrupt (IMIB) by IMFB bit disabled enable bit B 1: Interrupt (IMIB) by IMFB bit enabled IMIEC Input-capture/compare-match interrupt 0: Interrupt (IMIC) by IMFC bit disabled enable bit C 1: Interrupt (IMIC) by IMFC bit enabled IMIED Input-capture/compare-match interrupt 0: Interrupt (IMID) by IMFD bit disabled enable bit D 1: Interrupt (IMID) by the IMFD bit enabled OVIE Overflow/underflow interrupt 0: Interrupt (OVI) by OVF bit disabled enable bit 1: Interrupt (OVI) by OVF bit enabled — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — 21.7.12 Timer RD Counter 0 (TRD0) in Complementary PWM Mode Address 0147h to 0146h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b5 — 0 b13 — 0 b4 — 0 b12 — 0 b3 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 Set the dead time. A count source is counted. Count operation is increment or decrement. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. REJ09B0441-0010 Rev.0.10 Page 411 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.13 Timer RD Counter 1 (TRD1) in Complementary PWM Mode Address 0157h to 0156h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b5 — 0 b13 — 0 b4 — 0 b12 — 0 b3 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 Set 0000h. A count source is counted. Count operation is increment or decrement. When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1. Access the TRD1 register in 16-bit units. Do not access it in 8-bit units. 21.7.14 Timer RD General Registers Ai, Bi, C1, and Di (TRDGRAi, TRDGRBi, TRDGRC1, TRDGRDi) (i = 0 or 1) in Complementary PWM Mode Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Refer to Table 21.14 TRDGRji Register Functions in Complementary PWM Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The TRDGRC0 register is not used in complementary PWM mode. The following registers are disabled in complementary PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. REJ09B0441-0010 Rev.0.10 Page 412 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.14 Register TRDGRA0 − TRDGRji Register Functions in Complementary PWM Mode Setting Register Function General register. Set the PWM period at initialization. Setting range: TRD0 register setting value or above, FFFFh - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). General register. Set the changing point of PWM1 output at initialization. Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). General register. Set the changing point of PWM2 output at initialization. Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). General register. Set the changing point of PWM3 output at initialization. Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). PWM Output Pin (Output inverted every half period of TRDIOC0 pin) TRDGRB0 − TRDIOB0 TRDIOD0 TRDGRA1 − TRDIOA1 TRDIOC1 TRDGRB1 − TRDIOB1 TRDIOD1 TRDGRC0 TRDGRD0 − BFD0 = 1 TRDGRC1 BFC1 = 1 TRDGRD1 BFD1 = 1 This register is not used in complementary PWM mode. Buffer register. Set the changing point of next PWM1 output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB0 register for initialization. Buffer register. Set the changing point of next PWM2 output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRA1 register for initialization. Buffer register. Set the changing point of next PWM3 output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB1 register for initialization. − TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). REJ09B0441-0010 Rev.0.10 Page 413 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.15 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 414 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.16 Timer RD Pin Select Register 1 (TRDPSR1) Address 0185h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 415 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.17 Operating Example TRDi register value TRD0 register value TRDGRA0 register value TRD1 register value TRDGRB0 register value TRDGRA1 register value TRDGRB1 register value 0000h TRDIOB0 output TRDIOD0 output TRDIOA1 output TRDIOC1 output TRDIOB1 output TRDIOD1 output TRDIOC0 output i = 0 or 1 Figure 21.20 Output Model in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 416 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Count source TRDi register value m+1 m TRD0 register value n TRD1 register value p 0000h FFFFh is set. Bits TSTART0 and TSTART1 in TRDSTR register 1 0 TRDIOB0 output Initial output “H” Active level “L” TRDIOD0 output TRDIOC0 output Initial output “H” m+2-p n+1 n+1-p p m-p-n+1 p n+1-p (m-p-n+1) × 2 Width of normalphase active level UDF bit in TRDSR1 register 1 0 1 0 Dead time (n+1-p) × 2 Width of counter-phase active level IMFA bit in TRDSR0 register Set to 0 by a program. TRDGRB0 register n Transfer (when bits CMD1 to CMD0 are set to 11b) n Transfer (when bits CMD1 to CMD0 are set to 10b) Next data Change by a program. TRDGRD0 register n IMFB bit in TRDSR0 register 1 0 Set to 0 by a program. Set to 0 by a program. CMD0, CMD1: Bits in TRDFCR register i = 0 or 1 m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register p: Value set in TRD0 register The above applies under the following condition: Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level at high, active level is low for normal-phase and counter-phase) Figure 21.21 Operating Example in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 417 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.7.18 Transfer Timing from Buffer Register • Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or TRDGRB1 register. When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the TRD1 register underflows. When bits CMD1 to CMD0 are set to 11b, the content is transferred at compare match between registers TRD0 and TRDGRA0. 21.7.19 A/D Trigger Generation A compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion start trigger of the A/D converter. The trigger is selected by bits ADEG and ADTRG in the TRDFCR register. In addition, set bits ADCAP1 to ADCAP0 in the ADMOD register to 01b (start by timer RD). REJ09B0441-0010 Rev.0.10 Page 418 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8 PWM3 Mode In this mode, 2 PWM waveforms are output with the same period. Figure 21.22 shows a Block Diagram of PWM3 Mode, and Table 21.15 lists the PWM3 Mode Specifications. Figure 21.23 shows an Operating Example in PWM3 Mode. Buffer Compare match signal TRD0 Comparator TRDGRA0 TRDGRC0 TRDIOA0 Output control Compare match signal Comparator Compare match signal Comparator TRDGRB0 TRDGRD0 TRDGRA1 TRDGRC1 TRDIOB0 Output control Compare match signal Comparator TRDGRB1 TRDGRD1 Figure 21.22 Block Diagram of PWM3 Mode REJ09B0441-0010 Rev.0.10 Page 419 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.15 PWM3 Mode Specifications Item Count sources Count operations PWM waveform Specification f1, f2, f4, f8, f32, fC2, fOCO40M The TRD0 register is incremented (TRD1 register is not used). PWM period: 1/fk × (m+1) Active level width of TRDIOA0 output: 1/fk × (m-n) Active level width of TRDIOB0 output: 1/fk × (p-q) fk: Frequency of count source m: Value set in TRDGRA0 register n: Value set in TRDGRA1 register p: Value set in TRDGRB0 register q: Value set in TRDGRB1 register m+1 n+1 p+1 q+1 TRDIOA0 output m-n TRDIOB0 output p-q (Active level is high) Count start condition Count stop conditions Interrupt request generation timing TRDIOA0, TRDIOB0 pins function TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pins function INT0 pin function Read from timer Write to timer Selectable functions 1 (count starts) is written to the TSTART0 bit in the TRDSTR register. • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops • When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at compare match with the TRDGRA0 register. The PWM output pin holds the level after the output changes by the compare match. • Compare match (The contents of the TRDi register and the TRDGRji register match.) • TRD0 register overflow PWM output Programmable I/O port Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRD0 register. The value can be written to the TRD0 register. • Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.) • Buffer operation (Refer to 21.2.2 Buffer Operation.) • Active level selectable for each individual pin • A/D trigger generation i = 0 or 1, j = either A, B, C, or D REJ09B0441-0010 Rev.0.10 Page 420 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.1 Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. 21.8.2 Timer RD Control Expansion Register (TRDECR) b6 — 0 b5 — 0 b4 — 0 b3 ITCLK0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0135h Bit b7 Symbol ITCLK1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W — R/W REJ09B0441-0010 Rev.0.10 Page 421 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.3 Timer RD Trigger Control Register (TRDADCR) Address 0136h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E After Reset 0 0 0 0 0 0 0 0 Bit b0 Symbol Bit Name ADTRGA0E A/D trigger A0 enable bit Function 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W R/W b1 ADTRGB0E A/D trigger B0 enable bit R/W b2 ADTRGC0E A/D trigger C0 enable bit R/W b3 ADTRGD0E A/D trigger D0 enable bit R/W b4 ADTRGA1E A/D trigger A1 enable bit R/W b5 ADTRGB1E A/D trigger B1 enable bit R/W b6 ADTRGC1E A/D trigger C1 enable bit R/W b7 ADTRGD1E A/D trigger D1 enable bit R/W REJ09B0441-0010 Rev.0.10 Page 422 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.4 Timer RD Start Register (TRDSTR) in PWM3 Mode b6 — 1 b5 — 1 b4 — 1 b3 CSEL1 1 b2 b1 b0 CSEL0 TSTART1 TSTART0 1 0 0 R/W R/W R/W R/W Address 0137h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 Symbol Bit Name TSTART0 TRD0 count start flag (3) b3 b4 b5 b6 b7 Function 0: Count stops (1) 1: Count starts TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register CSEL1 TRD1 count operation select bit 0: Count stops at compare match with [not used in PWM3 mode] the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — R/W — Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. 21.8.5 Timer RD Mode Register (TRDMR) in PWM3 Mode b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 — 1 b2 — 1 b1 — 1 b0 SYNC 0 R/W R/W — Address 0138h Bit b7 Symbol BFD1 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol SYNC — — — BFC0 BFD0 BFC1 BFD1 Bit Name Timer RD synchronous bit Function Set to 0 (TRD0 and TRD1 operate independently) in PWM3 mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit TRDGRD0 register function select bit TRDGRC1 register function select bit TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRA0 register 0: General register 1: Buffer register of TRDGRB0 register 0: General register 1: Buffer register of TRDGRA1 register 0: General register 1: Buffer register of TRDGRB1 register R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 423 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.6 Timer RD Function Control Register (TRDFCR) in PWM3 Mode b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 b1 CMD1 0 b0 CMD0 0 R/W R/W R/W R/W Address 013Ah Bit b7 Symbol PWM3 After Reset 1 Bit b0 b1 b2 Symbol CMD0 CMD1 OLS0 Bit Name Combination mode select bit (1) Normal-phase output level select bit (enabled in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (enabled in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (enabled in complementary PWM mode) A/D trigger edge select bit (enabled in complementary PWM mode) External clock input select bit PWM3 mode select bit (2) Function Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM3 mode. Disabled in PWM3 mode. b3 OLS1 R/W b4 b5 b6 b7 ADTRG ADEG STCLK PWM3 R/W R/W Set to 0 (external clock input disabled) in PWM3 mode. Set to 0 (PWM3 mode) in PWM3 mode. R/W R/W Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. REJ09B0441-0010 Rev.0.10 Page 424 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.7 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM3 Mode b6 EC1 1 b5 EB1 1 b4 EA1 1 b3 ED0 1 b2 EC0 1 b1 EB0 1 b0 EA0 1 R/W R/W Address 013Bh Bit b7 Symbol ED1 After Reset 1 Bit b0 Symbol Bit Name EA0 TRDIOA0 output disable bit b1 EB0 TRDIOB0 output disable bit b2 b3 b4 b5 b6 b7 EC0 ED0 EA1 EB1 EC1 ED1 TRDIOC0 output disable bit TRDIOD0 output disable bit TRDIOA1 output disable bit TRDIOB1 output disable bit TRDIOC1 output disable bit TRDIOD1 output disable bit Function 0: Output enabled 1: Output disabled (TRDIOA0 pin is used as a programmable I/O port) 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) Set to 1 (programmable I/O port) in PWM3 mode. R/W R/W R/W R/W R/W R/W R/W 21.8.8 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM3 Mode b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W — — — — — — — R/W Address 013Ch Bit b7 Symbol PTO After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — — — — 0: Pulse output forced cutoff input disabled PTO INT0 of pulse output forced cutoff 1: Pulse output forced cutoff input enabled (1) signal input enabled bit (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. REJ09B0441-0010 Rev.0.10 Page 425 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.9 Timer RD Output Control Register (TRDOCR) in PWM3 Mode b6 TOC1 0 b5 TOB1 0 b4 TOA1 0 b3 TOD0 0 b2 TOC0 0 b1 TOB0 0 b0 TOA0 0 R/W R/W Address 013Dh Bit b7 Symbol TOD1 After Reset 0 Bit b0 Symbol Bit Name TOA0 TRDIOA0 output level select bit (1) b1 TOB0 b2 b3 b4 b5 b6 b7 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1 Function 0: Active level is high, initial output at low, high-level output at compare match with the TRDGRA1 register, low-level output at compare match with the TRDGRA0 register 1: Active level is low, initial output at high, low-level output at compare match with the TRDGRA1 register, high-level output at compare match with the TRDGRA0 register 0: Active level is high, TRDIOB0 output level select bit (1) initial output at low, high-level output at compare match with the TRDGRB1register, low-level output at compare match with the TRDGRB0 register 1: Active level is low, initial output at high, low-level output at compare match with the TRDGRB1 register, high-level output at compare match with the TRDGRB0 register TRDIOC0 initial output level select bit Disabled in PWM3 mode. TRDIOD0 initial output level select bit TRDIOA1 initial output level select bit TRDIOB1 initial output level select bit TRDIOC1 initial output level select bit TRDIOD1 initial output level select bit R/W R/W R/W R/W R/W R/W R/W Note: 1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRDOCR register is set. Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). REJ09B0441-0010 Rev.0.10 Page 426 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.10 Timer RD Control Register 0 (TRDCR0) in PWM3 Mode Address 0140h Bit b7 Symbol CCLR2 After Reset 0 Bit b0 b1 b2 b6 CCLR1 0 b5 CCLR0 0 b4 CKEG1 0 b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 b0 TCK0 0 R/W R/W R/W R/W Symbol Bit Name TCK0 Count source select bit TCK1 TCK2 b3 b4 b5 b6 b7 CKEG0 External clock edge select bit CKEG1 CCLR0 TRD0 counter clear select bit CCLR1 CCLR2 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: Do not set. 1 1 0: fOCO40M 1 1 1: Do not set. Disabled in PWM3 mode. Set to 001b (TRD0 register cleared at compare match with TRDGRA0 register) in PWM3 mode. R/W R/W R/W R/W R/W The TRDCR1 register is not used in PWM3 mode for the TRDCR0 register. REJ09B0441-0010 Rev.0.10 Page 427 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM3 Mode Address 0143h (TRDSR0), 0153h (TRDSR1) Bit b7 b6 b5 b4 Symbol — — UDF OVF After Reset 1 1 1 0 After Reset 1 1 0 0 Bit b0 Symbol IMFA Bit Name Input-capture/compare-match flag A b3 IMFD 0 0 b2 IMFC 0 0 b1 IMFB 0 0 b0 IMFA 0 0 TRDSR0 register TRDSR1 register R/W R/W b1 IMFB b2 IMFC b3 IMFD b4 OVF b5 b6 b7 UDF — — Function [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (2). Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (2). Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register overflows. (1) This bit is disabled in PWM3 Mode. Underflow flag Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W R/W R/W R/W — Notes: 1. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. 2. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). REJ09B0441-0010 Rev.0.10 Page 428 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode Address 0144h (TRDIER0), 0154h (TRDIER1) Bit b7 b6 b5 b4 Symbol — — — OVIE After Reset 1 1 1 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name IMIEA Input-capture/compare-match interrupt enable bit A IMIEB Input-capture/compare-match interrupt enable bit B IMIEC Input-capture/compare-match interrupt enable bit C IMIED Input-capture/compare-match interrupt enable bit D OVIE Overflow/underflow interrupt enable bit — — — b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W R/W — Function 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. 21.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode Address 0147h to 0146h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 b5 — 0 b13 — 0 b4 — 0 b12 — 0 b3 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Setting Range 0000h to FFFFh R/W R/W Bit Function b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. The TRD1 register is not used in PWM3 mode. REJ09B0441-0010 Rev.0.10 Page 429 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM3 Mode Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R/W Bit Function b15 to b0 Refer to Table 21.16 TRDGRji Register Functions in PWM3 Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled for the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. REJ09B0441-0010 Rev.0.10 Page 430 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Table 21.16 TRDGRji Register Functions in PWM3 Mode Register Setting TRDGRA0 − TRDGRA1 TRDGRB0 TRDGRB1 TRDGRC0 TRDGRC1 TRDGRD0 TRDGRD1 TRDGRC0 TRDGRC1 TRDGRD0 TRDGRD1 Register Function General register. Set the PWM period. Setting range: TRDGRA1 register setting value or above General register. Set the changing point (the active level timing) of PWM output. Setting range: TRDGRA0 register setting value or below General register. Set the changing point (the timing that returns to initial output level) of PWM output. Setting range: TRDGRB1 register setting value or above, TRDGRA0 register setting value or below General register. Set the changing point (active level timing) of PWM output. Setting range: TRDGRB0 register setting value or below BFC0 = 0 (These registers are not used in PWM3 mode.) BFC1 = 0 BFD0 = 0 BFD1 = 0 BFC0 = 1 Buffer register. Set the next PWM period. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRC1 register setting value or above BFC1 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRC0 register setting value or below BFD0 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRD1 register setting value or above, TRDGRC0 register setting value or below BFD1 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRD0 register setting value or below PWM Output Pin TRDIOA0 TRDIOB0 − TRDIOA0 TRDIOB0 BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1 may be set to 1 (buffer register). REJ09B0441-0010 Rev.0.10 Page 431 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.15 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 Symbol Bit Name TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit TRDIOA0SEL1 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB0SEL0 TRDIOB0 pin select bit TRDIOB0SEL1 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC0SEL0 TRDIOC0 pin select bit TRDIOC0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD0SEL0 TRDIOD0 pin select bit TRDIOD0SEL1 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W R/W The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 432 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.16 Timer RD Pin Select Register 1 (TRDPSR1) Address 0185h Bit After Reset Bit b0 b1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 Function b1 b0 b1 0 b0 0 R/W R/W R/W Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 Symbol Bit Name TRDIOA1SEL0 TRDIOA1 pin select bit TRDIOA1SEL1 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. b3 b2 b2 b3 TRDIOB1SEL0 TRDIOB1 pin select bit TRDIOB1SEL1 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. b5 b4 R/W R/W b4 b5 TRDIOC1SEL0 TRDIOC1 pin select bit TRDIOC1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. b7 b6 R/W R/W b6 b7 TRDIOD1SEL0 TRDIOD1 pin select bit TRDIOD1SEL1 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W R/W The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. REJ09B0441-0010 Rev.0.10 Page 433 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.17 Operating Example Count source TRD0 register value FFFFh m n p q 0000h TSTART0 bit in TRDSTR register 1 0 Count stops CSEL0 bit in TRDSTR register 1 0 Set to 0 by a program. m+1 n+1 p+1 q+1 Output “H” at compare match with the TRDGRA1 register Output “L” at compare match with the TRDGRA0 register p-q m-n TRDIOA0 output Initial output “L” TRDIOB0 output IMFA bit in TRDSR0 register 1 0 Set to 0 by a program. Set to 0 by a program. IMFB bit in TRDSR0 register 1 0 Set to 0 by a program. Set to 0 by a program. TRDGRA0 register m Transfer m Transfer Next data TRDGRC0 register m Transfer from the buffer register to the general register Transfer from the buffer register to the general register j = either A or B m: Value set in TRDGRA0 register n: Value set in TRDGRA1 register p: Value set in TRDGRB0 register q: Value set in TRDGRB1 register The above applies under the following conditions: • Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output at low, high-level at compare match with the TRDGRj1 register, low-level output at compare match with the TRDGRj0 register). • The BFC0 bit in the TRDMR register is set to 1 (TRDGRC0 register is used as the buffer register of the TRDGRA0 register). Figure 21.23 Operating Example in PWM3 Mode REJ09B0441-0010 Rev.0.10 Page 434 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.8.18 A/D Trigger Generation A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used. REJ09B0441-0010 Rev.0.10 Page 435 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.9 Timer RD Interrupt Timer RD generates the timer RDi (i = 0 or 1) interrupt request based on six sources for each timer RD0 and timer RD1. The timer RD interrupt uses the single TRDiIC register (bits IR, and ILVL0 to ILVL2), and a single vector for each timer RD0 and timer RD1. Table 21.17 lists the Registers Associated with Timer RD Interrupt, and Figure 21.24 shows a Block Diagram of Timer RD Interrupt. Table 21.17 Registers Associated with Timer RD Interrupt Timer RD0 Timer RD1 Timer RD Status Register TRDSR0 TRDSR1 Timer RD Interrupt Enable Register TRDIER0 TRDIER1 Timer RD Interrupt Control Register TRD0IC TRD1IC Timer RDi IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit Timer RDi interrupt request (IR bit in TRDiIC register) i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register Figure 21.24 Block Diagram of Timer RD Interrupt As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply: • When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (interrupt enabled), the IR bit in the TRDiIC register is set to 1 (interrupt requested). • When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (no interrupt requested). Therefore, even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. • When the conditions of other request sources are met, the IR bit remains 1. • When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is determined by the TRDSRi register. • Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions of the registers used in different modes (21.3.11, 21.4.14, 21.5.12, 21.6.10, 21.7.10, and 21.8.11). REJ09B0441-0010 Rev.0.10 Page 436 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Refer to Registers TRDSR0 to TRDSR1 in each mode (21.3.11, 21.4.14, 21.5.12, 21.6.10, 21.7.10, and 21.8.11) for the TRDSRi register. Refer to Registers TRDIER0 to TRDIER1 in each mode (21.3.12, 21.4.15, 21.5.13, 21.6.11, 21.7.11, and 21.8.12) for the TRDIERi register. Refer to 12.3 Interrupt Control for information on the TRDiIC register and 12.1.5.2 Relocatable Vector Tables for the interrupt vectors. REJ09B0441-0010 Rev.0.10 Page 437 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.10 Notes on Timer RD 21.10.1 TRDSTR Register • Set the TRDSTR register using the MOV instruction. • When the CSELi (i = 0 or 1) is set to 0 (count stops at compare match between registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit. When the CSELi bit is set to 0, write 0 to the TSTARTi bit to change other bits without changing the TSTARTi bit. To stop counting by a program, write 0 to the TSTARTi bit after setting the CSELi bit to 1. If 1 is written to the CSELi bit and 0 is written to the TSTARTi bit is set to 0 at the same time (with one instruction), the count cannot be stopped. • Table 21.18 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops while the TRDIOji (j = A, B, C, or D) pin is used for the timer RD output. Table 21.18 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops TRDIOji Pin Output when Count Stops Holds the output level immediately before the count stops. Holds the output level after the output changes by the compare match. Stopping Count When the CSELi bit is set to 1, write 0 to the TSTARTi bit and the count stops. When the CSELi bit is set to 0, the count stops at compare match between registers TRDi and TRDGRAi. 21.10.2 TRDi Register (i = 0 or 1) • When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These notes apply when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register. - 001b (Clear by the TRDi register at compare match with the TRDGRAi register.) - 010b (Clear by the TRDi register at compare match with the TRDGRBi register.) - 011b (Synchronous clear) - 101b (Clear by the TRDi register at compare match with the TRDGRCi register.) - 110b (Clear by the TRDi register at compare match with the TRDGRDi register.) • When writing the value to the TRDi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.W #XXXXh, TRD0 ;Write JMP.B L1 ;JMP.B L1: MOV.W TRD0,DATA ;Read REJ09B0441-0010 Rev.0.10 Page 438 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.10.3 TRDSRi Register (i = 0 or 1) When writing the value to the TRDSRi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.B #XXh, TRDSR0 ;Write JMP.B L1 ;JMP.B L1: MOV.B TRDSR0,DATA ;Read 21.10.4 Count Source Switching • Switch the count source after the count stops. Switching procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. • When changing the count source from fOCO40M to another source and stopping fOCO40M, wait two or more cycles of f1 after setting the clock switch, and then stop fOCO40M. Switching procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. (3) Wait for two or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off). 21.10.5 Input Capture Function • The pulse width of the input capture signal should be set to three or more cycles of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks). • The value of the TRDi register is transferred to the TRDGRji register two or three cycles of the timer RD operating clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or D) (when the digital filter is not used). 21.10.6 Reset Synchronous PWM Mode • When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1. • Set to reset synchronous PWM mode by the following procedure: Switching procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode). (4) Set the other registers associated with timer RD again. REJ09B0441-0010 Rev.0.10 Page 439 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD 21.10.7 Complementary PWM Mode • When complementary PWM mode is used for motor control, make sure OLS0 = OLS1. • Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure. Switching procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other timer RD again. Switching procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode). • Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation. When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed. • If the value set in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decrement operation. When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0 and TRDGRA0), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers such as the TRDGRA0 register. TRD0 register count value m+1 TRDGRA0 register setting value m Set to 0 by a program. IMFA bit in TRDSR0 register 1 0 Transfer from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register No transfer from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 11b (transfer from the buffer register to the general register at compare match between registers TRD0 and TRDGRA0). No change Figure 21.25 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 440 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD • The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment operation. The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in the TRD1 register), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains unchanged. TRD0 register count value 1 0 FFFFh Set to 0 by a program. UDF bit in TRDSR0 register OVF bit in TRDSR0 register 1 0 1 0 Transfer from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register No transfer from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 10b (transfer from the buffer register to the general register when the TRD1 register underflows). No change Figure 21.26 Operation when TRD1 Register Underflows in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 441 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD • Using bits CMD1 to CMD0, select the timing of data transfer from the buffer register to the general register. However, transfer takes place with the following timing in spite of the values of bits CMD1 to CMD0 in the following cases: Buffer register value ≥ TRDGRA0 register value: Transfer takes place at underflow of the TRD1 register. After this, when the buffer register is set to 0001h or above and a value smaller than the value of the TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0. n3 m+1 TRD0 register count value n2 n1 0000h TRD1 register count value TRDGRD0 register n2 Transfer n3 Transfer n2 n3 n2 Transfer n2 n1 Transfer n1 TRDGRB0 register n1 Transfer with timing set by bits CMD1 to CMD0 Transfer at TRD1 register underflow because of n3 > m Transfer at TRD1 register underflow because of first setting to n2 < m Transfer with timing set by bits CMD1 to CMD0 TRDIOB0 output TRDIOD0 output m: Value set in TRDGRA0 register The above applies under the following conditions: • Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match between registers TRD0 and TRDGRA0 in complementary PWM mode). • Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase). Figure 21.27 Operation when Buffer Register Value ≥ TRDGRA0 Register Value in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 442 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD When the value of the buffer register is set to 0000h: Transfer takes place at compare match between registers TRD0 and TRDGRA0. After this, when the buffer register is set to 0001h or above and a value than smaller the value of the TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD0 and CMD1. m+1 n2 n1 0000h TRD1 register count value TRD0 register count value TRDGRD0 register n1 Transfer 0000h Transfer n1 0000h n1 Transfer n1 Transfer TRDGRB0 register n2 Transfer with timing set by bits CMD1 to CMD0 Transfer at compare match between registers TRD0 and TRDGRA0 because content of TRDGRD0 register is set to 0000h. Transfer at compare match between registers TRD0 and TRDGRA0 because of first setting to 0001h ≤ n1 < m Transfer with timing set by bits CMD1 to CMD0 TRDIOB0 output TRDIOD0 output m: Value set in TRDGRA0 register The above applies under the following conditions: • Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at TRD1 register underflow in PWM mode). • Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase). Figure 21.28 Operation when Buffer Register Value Is Set to 0000h in Complementary PWM Mode 21.10.8 Count Source fOCO40M • The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V. For supply voltage other than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (fOCO40M selected as the count source). REJ09B0441-0010 Rev.0.10 Page 443 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22. Timer RE Timer RE has a 4-bit counter and 8-bit counter. 22.1 Introduction Timer RE supports the following two modes: • Real-time clock mode A 1-second signal from fC4 is generated and seconds, minutes, hours, and days of the week are counted. • Output compare mode A count source is counted and compare matches are detected. The count source for timer RE is the operating clock that regulates the timing of timer operations. Table 22.1 lists the Timer RE Pin Configuration. Table 22.1 Timer RE Pin Configuration Pin Name TREO P11_7 Assigned Pin I/O Output Function Function differs according to the mode. Refer to descriptions of individual modes for details. REJ09B0441-0010 Rev.0.10 Page 444 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2 Real-Time Clock Mode In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 22.1 shows a Block Diagram of Real-Time Clock Mode, Table 22.2 lists the Real-Time Clock Mode Specifications, and Table 22.3 lists Interrupt Sources. Figure 22.2 shows the Definition of Time Representation and Figure 22.3 shows an Operating Example in Real-Time Clock Mode. RCS6 to RCS4 f2 fC f4 (1/16) fC4 (8.192 kHz) 1/2 4-bit counter (1/256) 8-bit counter (1s) Overflow f8 = 000b = 001b = 010b = 100b = 011b TOENA TREO pin Data bus Overflow Overflow Overflow TRESEC register TREMIN register TREHR register TREWK register 000 PM bit WKIE H12_H24 bit DYIE HRIE Timing control Timer RE interrupt MNIE INT bit SEIE BSY bit TOENA, H12_H24, PM, INT: Bits in TRECR1 register SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register BSY: Bit in registers TRESEC, TREMIN, TREHR and TREWK RCS4 to RCS6: Bits in TRECSR register Figure 22.1 Block Diagram of Real-Time Clock Mode REJ09B0441-0010 Rev.0.10 Page 445 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE Table 22.2 Real-Time Clock Mode Specifications Item Count source Count operation Count start condition Count stop condition Interrupt request generation timing TREO pin function Read from timer Write to timer Selectable function Specification fC4 Increment 1 (count starts) is written to TSTART bit in TRECR1 register. 0 (count stops) is written to TSTART bit in TRECR1 register. Select either one of the following: • Update of second data • Update of minute data • Update of hour data • Update of day of week data • When day of week data is set to 000b (Sunday). Programmable I/O port or output of f2, fC, f4, f8, or 1 Hz When reading TRESEC, TREMIN, TREHR, or TREWK register, the count value can be read. The values read from registers TRESEC, TREMIN, and TREHR are represented by the BCD code. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), the value can be written to registers TRESEC, TREMIN, TREHR, and TREWK. The values written to registers TRESEC, TREMIN, and TREHR are represented by the BCD codes. • 12-hour mode/24-hour mode switch function REJ09B0441-0010 Rev.0.10 Page 446 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2.1 Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode b6 SC12 X b5 SC11 X b4 SC10 X b3 SC03 X b2 SC02 X b1 SC01 X b0 SC00 X R/W R/W R/W R/W R/W R/W R/W R/W R Address 0118h Bit b7 Symbol BSY After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name SC00 1st digit of second count bit SC01 SC02 SC03 SC10 2nd digit of second count bit SC11 SC12 BSY Timer RE busy flag Function Setting Range Count 0 to 9 every second. When the digit 0 to 9 moves up, 1 is added to the 2nd digit of (BCD code) second. When counting 0 to 5, 60 seconds are counted. 0 to 5 (BCD code) This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are being updated. 22.2.2 Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode b6 MN12 X b5 MN11 X b4 MN10 X b3 MN03 X b2 MN02 X b1 MN01 X b0 MN00 X R/W R/W R/W R/W R/W R/W R/W R/W R Address 0119h Bit b7 Symbol BSY After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name MN00 1st digit of minute count bit MN01 MN02 MN03 MN10 2nd digit of minute count bit MN11 MN12 BSY Timer RE busy flag Function Setting Range Count 0 to 9 every minute. When the digit 0 to 9 moves up, 1 is added to the 2nd digit of (BCD code) minute. When counting 0 to 5, 60 minutes are counted. 0 to 5 (BCD code) This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are being updated. REJ09B0441-0010 Rev.0.10 Page 447 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2.3 Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode b6 — X b5 HR11 X b4 HR10 X b3 HR03 X b2 HR02 X b1 HR01 X b0 HR00 X Setting Range 0 to 9 (BCD code) R/W R/W R/W R/W R/W R/W R/W Address 011Ah Bit b7 Symbol BSY After Reset X Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name HR00 1st digit of hour count bit HR01 HR02 HR03 HR10 2nd digit of hour count bit HR11 Function Count 0 to 9 every hour. When the digit moves up, 1 is added to the 2nd digit of hour. b6 b7 — BSY Count 0 to 1 when the H12_H24 bit is set to 0 0 to 2 (12-hour mode). (BCD code) Count 0 to 2 when the H12_H24 bit is set to 1 (24-hour mode). Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. — R 22.2.4 Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode b6 — X b5 — X b4 — X b3 — X b2 WK2 X b1 WK1 X Function b2 b1 b0 Address 011Bh Bit b7 Symbol BSY After Reset X Bit b0 b1 b2 b0 WK0 X R/W R/W R/W R/W Symbol Bit Name WK0 Day of week count bit WK1 WK2 b3 b4 b5 b6 b7 — — — — BSY 0 0 0: Sunday 0 0 1: Monday 0 1 0: Tuesday 0 1 1: Wednesday 1 0 0: Thursday 1 0 1: Friday 1 1 0: Saturday 1 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. R REJ09B0441-0010 Rev.0.10 Page 448 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2.5 Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode b5 PM X b4 TRERST X b3 INT X b2 TOENA 0 b1 TCSTF X b0 — X R/W — R R/W R/W R/W Address 011Ch Bit b7 b6 Symbol TSTART H12_H24 After Reset X X Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. TCSTF Timer RE count status flag 0: Count stopped 1: Counting TOENA TREO pin output enable bit 0: Clock output disabled 1: Clock output enabled INT Interrupt request timing bit Set to 1 in real-time clock mode. TRERST Timer RE reset bit When setting this bit to 0 after setting it to 1, the following will occur: • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. • Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. • The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. PM A.m./p.m. bit When the H12_H24 bit is set to 0 (12-hour mode) (1) 0: a.m. 1: p.m. When the H12_H24 bit is set to 1 (24-hour mode), its value is undefined. H12_H24 Operating mode select bit 0: 12-hour mode 1: 24-hour mode TSTART Timer RE count start bit 0: Count stops 1: Count starts R/W R/W R/W Note: 1. This bit is automatically modified while timer RE counts. Noon H12_H24 bit = 1 (24-hour mode) H12_H24 bit = 0 (12-hour mode) Content of TREHR Register 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 0 13 1 14 2 15 3 16 4 17 5 Content of PM bit Content of TREWK register 0 (a.m.) 000 (Sunday) Date changes 1 (p.m.) Content of TREHR Register H12_H24 bit = 1 (24-hour mode) H12_H24 bit = 0 (12-hour mode) 18 6 19 7 20 8 21 9 22 10 23 11 0 0 1 1 2 2 3 3 ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ Content of PM bit Content of TREWK register 1 (p.m.) 000 (Sunday) 0 (a.m.) 001 (Monday) PM, H12_H24: Bits in TRECR1 register The above applies when counting starts from a.m. 0 on Sunday. Figure 22.2 Definition of Time Representation REJ09B0441-0010 Rev.0.10 Page 449 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2.6 Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode b6 WKIE X b5 DYIE X b4 HRIE X b3 MNIE X b2 SEIE X b1 SEIE05 X b0 SEIE025 X R/W R/W Address 011Dh Bit b7 Symbol COMIE After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function SEIE025 Periodic interrupt triggered every 0: Periodic interrupt triggered every 0.25 seconds is disabled 0.25 seconds enable bit (1) 1: Periodic interrupt triggered every 0.25 seconds is enabled SEIE05 Periodic interrupt triggered every 0: Periodic interrupt triggered every 0.5 seconds is disabled 0.5 seconds enable bit (1) 1: Periodic interrupt triggered every 0.5 seconds is enabled SEIE Periodic interrupt triggered every 0: Periodic interrupt triggered every second is disabled 1: Periodic interrupt triggered every second is enabled second enable bit (1) MNIE Periodic interrupt triggered every 0: Periodic interrupt triggered every minute is disabled 1: Periodic interrupt triggered every minute is enabled minute enable bit (1) HRIE Periodic interrupt triggered every 0: Periodic interrupt triggered every hour is disabled 1: Periodic interrupt triggered every hour is enabled hour enable bit (1) DYIE Periodic interrupt triggered every 0: Periodic interrupt triggered every day is disabled 1: Periodic interrupt triggered every day is enabled day enable bit (1) WKIE Periodic interrupt triggered every 0: Periodic interrupt triggered every week is disabled 1: Periodic interrupt triggered every week is enabled week enable bit (1) COMIE Compare match interrupt Set to 0 in real-time clock mode. enable bit R/W R/W R/W R/W R/W R/W R/W Note: 1. Do not set multiple enable bits to 1 (interrupt enabled). Table 22.3 Interrupt Sources Source Periodic interrupt triggered every week Periodic interrupt triggered every day Periodic interrupt triggered every hour Periodic interrupt triggered every minute Periodic interrupt triggered every second Periodic interrupt triggered every 0.5 seconds Periodic interrupt triggered every 0.25 seconds Interrupt Source The value of the TREWK register is set to 000b (Sunday) (1-week period). The TREWK register is updated (1-day period). The TREHR register is updated (1-hour period). The TREMIN register is updated (1-minute period). The TRESEC register is updated (1-second period). The 8-bit counter is updated (0.5-second period). The 8-bit counter is updated (0.25-second period). Interrupt Enable Bit WKIE DYIE HRIE MNIE SEIE SEIE05 SEIE025 REJ09B0441-0010 Rev.0.10 Page 450 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2.7 Timer RE Count Source Select Register (TRECSR) in Real-Time Clock Mode b6 RCS6 0 b5 RCS5 0 b4 RCS4 0 b3 RCS3 1 b2 RCS2 0 b1 RCS1 0 b0 RCS0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 011Eh Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 Symbol RCS0 RCS1 RCS2 RCS3 RCS4 RCS5 RCS6 Bit Name Count source select bit 4-bit counter select bit Real-time clock mode select bit Clock output select bit (1) Function Set to 00b in real-time clock mode. Set to 0 in real-time clock mode. Set to 1 in real-time clock mode. b6 b5 b4 b7 — 0 0 0: f2 0 0 1: fC 0 1 0: f4 0 1 1: 1 Hz 1 0 0: f8 Other than above: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Note: 1. Write to bits RCS4 to RCS6 when the TOENA bit in the TRECR1 register is set to 0 (clock output disabled). REJ09B0441-0010 Rev.0.10 Page 451 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.2.8 Operating Example 1s Approx. 62.5 ms BSY bit Approx. 62.5 ms Bits SC12 to SC00 in TRESEC register 58 59 00 Bits MN12 to MN00 in TREMIN register 03 04 Bits HR11 to HR00 in TREHR register (Not change) PM bit in TRECR1 register 1 (No change) 0 Bits WK2 to WK0 in TREWK register (No change) Set to 0 when an interrupt is acknowledged or by a program. IR bit in TREIC register (when SEIE bit in TRECR2 register is set to 1 (periodic interrupt triggered every second is enabled)) IR bit in TREIC register (when MNIE bit in TRECR2 register is set to 1 (periodic interrupt triggered every minute is enabled)) 1 0 1 0 BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK Figure 22.3 Operating Example in Real-Time Clock Mode REJ09B0441-0010 Rev.0.10 Page 452 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.3 Output Compare Mode In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and a compare value match is detected with the 8-bit counter. Figure 22.4 shows a Block Diagram of Output Compare Mode, Table 22.4 lists the Output Compare Mode Specifications, and Figure 22.5 shows an Operating Example in Output Compare Mode. RCS6 to RCS4 f4 f8 RCS1 to RCS0 = 00b = 01b f32 fC4 = 10b = 11b RCS2 = 0 f2 fC =000b =001b =010b =100b TREO pin 1/2 4-bit counter RCS2 = 1 TOENA 8-bit counter TQ R =110b Reset TRERST Comparison circuit Match signal COMIE Timer RE interrupt TRERST, TOENA: Bits in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2, RCS4 to RCS6: Bits in TRECSR register TRESEC TREMIN Data bus Figure 22.4 Block Diagram of Output Compare Mode Table 22.4 Output Compare Mode Specifications Specification f4, f8, f32, fC4 • Increment • When the 8-bit counter value matches the TREMIN register content, the value is set back to 00h and the count continues. The count value is retained while the count stops. • When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1) • When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: Frequency of count source n: Value set in TREMIN register 1 (count starts) is written to the TSTART bit in the TRECR1 register. 0 (count stops) is write to the TSTART bit in the TRECR1 register. When the contents of the 8-bit counter and the TREMIN register match. Select either one of the following: • Programmable I/O port • Output of f2, fC, f4, or f8 • Compare output When reading the TRESEC register, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Writing to the TRESEC register is disabled. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. • Selectable use of 4-bit counter • Compare output function Every time the 8-bit counter value matches the TREMIN register content, the TREO output polarity is inverted. The TREO pin outputs a low-level signal after reset is deasserted and timer RE is reset by the TRERST bit in the TRECR1 register. The output level is retained by setting the TSTART bit to 0 (count stops). Item Count sources Count operations Count periods Count start condition Count stop condition Interrupt request generation timing TREO pin function Read from timer Write to timer Selectable functions REJ09B0441-0010 Rev.0.10 Page 453 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.3.1 Timer RE Counter Data Register (TRESEC) in Output Compare Mode b6 — X b5 — X b4 — X b3 — X b2 — X b1 — X b0 — X R/W R Address 0118h Bit b7 Symbol — After Reset X Bit Function b7 to b0 8-bit counter data can be read. Even if timer RE stops counting, the count value is retained. The TRESEC register is set to 00h at the compare match. 22.3.2 Timer RE Compare Data Register (TREMIN) in Output Compare Mode b6 — X b5 — X b4 — X b3 — X Function b2 — X b1 — X b0 — X R/W R Address 0119h Bit b7 Symbol — After Reset X Bit b7 to b0 8-bit compare data is stored. REJ09B0441-0010 Rev.0.10 Page 454 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.3.3 Timer RE Control Register 1 (TRECR1) in Output Compare Mode b5 PM X b4 TRERST X b3 INT X b2 TOENA 0 b1 TCSTF X b0 — X R/W — R R/W R/W R/W Address 011Ch Bit b7 b6 Symbol TSTART H12_H24 After Reset X X Bit b0 b1 b2 b3 b4 Symbol — TCSTF b5 b6 b7 Bit Name Function Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE count status flag 0: Count stopped 1: Counting TOENA TREO pin output enable bit 0: Clock output disabled 1: Clock output enabled INT Interrupt request timing bit Set to 0 in output compare mode. TRERST Timer RE reset bit When setting this bit to 0 after setting it to 1, the following will occur. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. • Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. • The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. PM A.m./p.m. bit Set to 0 in output compare mode. H12_H24 Operating mode select bit Set to 0 in output compare mode. TSTART Timer RE count start bit 0: Count stops 1: Count starts R/W R/W R/W 22.3.4 Timer RE Control Register 2 (TRECR2) in Output Compare Mode b6 WKIE X b5 DYIE X b4 HRIE X b3 MNIE X b2 SEIE X b1 SEIE05 X b0 SEIE025 X R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 011Dh Bit b7 Symbol COMIE After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function SEIE025 Periodic interrupt triggered every Set to 0 in output compare mode. 0.25 seconds enable bit (1) SEIE05 Periodic interrupt triggered every 0.5 seconds enable bit (1) SEIE Periodic interrupt triggered every second enable bit (1) MNIE Periodic interrupt triggered every minute enable bit (1) HRIE Periodic interrupt triggered every hour enable bit (1) DYIE Periodic interrupt triggered every day enable bit (1) WKIE Periodic interrupt triggered every week enable bit (1) COMIE Compare match interrupt 0: Compare match interrupt disabled enable bit 1: Compare match interrupt enabled Note: 1. Do not set multiple enable bits to 1 (interrupt enabled). REJ09B0441-0010 Rev.0.10 Page 455 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.3.5 Timer RE Count Source Select Register (TRECSR) in Output Compare Mode b6 RCS6 0 b5 RCS5 0 b4 RCS4 0 b3 RCS3 1 b2 RCS2 0 b1 RCS1 0 Function b1 b0 Address 011Eh Bit b7 Symbol — After Reset 0 Bit b0 b1 Symbol RCS0 RCS1 b0 RCS0 0 R/W R/W R/W Bit Name Count source select bit (1) b2 b3 b4 b5 b6 RCS2 RCS3 RCS4 RCS5 RCS6 4-bit counter select bit Real-time clock mode select bit Clock output select bit (2) 0 0: f4 0 1: f8 1 0: f32 1 1: fC4 0: Not used 1: Used Set to 0 in output compare mode. b6 b5 b4 R/W R/W R/W R/W R/W b7 — 0 0 0: f2 0 0 1: fC 0 1 0: f4 1 0 0: f8 1 1 0: Compare output Other than above: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Notes: 1. Write to bits RCS0 to RCS1 when the TCSTF bit in the TRECR1 register is set to 0 (count stopped). 2. Write to bits RCS4 to RCS6 when the TOENA bit in the TRECR1 register is set to 0 (clock output disabled). REJ09B0441-0010 Rev.0.10 Page 456 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.3.6 Operating Example Count starts 8-bit counter content (hexadecimal number) TREMIN register setting value Match Match Match 00h Set to 1 by a program. Time TSTART bit in TRECR1 register 1 0 2 cycles of maximum count source TCSTF bit in TRECR1 register 1 0 Set to 0 when an interrupt request is acknowledged or by a program. IR bit in TREIC register 1 0 TREO output “H” “L” The output polarity is inverted at the compare match. The above applies under the following conditions: TOENA bit in TRECR1 register = 1 (clock output enabled) COMIE bit in TRECR2 register = 1 (compare match interrupt enabled) Bits RCS6 to RCS5 in TRECSR register = 11b (compare output) Figure 22.5 Operating Example in Output Compare Mode REJ09B0441-0010 Rev.0.10 Page 457 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.4 22.4.1 Notes on Timer RE Reset A reset input does not reset the timer RE data registers that store data of seconds, minutes, hours, and days of the week. This requires the initial setting of all registers after power on. 22.4.2 Starting and Stopping Count Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. When the TSTART bit is set to 1 (count starts), timer RE starts counting and the TCSTF bit is set to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit. Similarly, when the TSTART bit is set to 0 (count stops), timer RE stops counting and the TCSTF bit is set to 0 (count stops). It takes the time for up to two cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. Note: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR 22.4.3 Register Setting Write to the following registers or bits while timer RE is stopped. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 • Bits H12_H24, PM, and INT in the TRECR1 register • Bits RCS0 to RCS3 in the TRECSR register Timer RE is stopped while bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 22.6 shows a Setting Example in Real-Time Clock Mode. REJ09B0441-0010 Rev.0.10 Page 458 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE TSTART in TRECR1 = 0 Stop timer RE operation TCSTF in TRECR1 = 0? TOENA in TRECR1 = 0 TREIC ← 00h (timer RE interrupt disabled) Disable the timer RE clock output (when necessary) TRERST in TRECR1 = 1 Reset the timer RE registers and the control circuit TRERST in TRECR1 = 0 Set registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in the TRECR1 register Select the clock output Select the clock source Seconds, minutes, hours, days of week, operating mode Set the a.m./p.m., interrupt timing Set TRECR2 Set TREIC (IR bit ← 0, select the interrupt priority level) Select the interrupt source TOENA in TRECR1 = 1 TSTART in TRECR1 = 1 Enable the timer RE clock output (when necessary) Start timer RE operation TCSTF in TRECR1 = 1? Figure 22.6 Setting Example in Real-Time Clock Mode REJ09B0441-0010 Rev.0.10 Page 459 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE 22.4.4 Time Reading Procedure in Real-Time Clock Mode In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (data is not being updated). When reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below. • Using an interrupt Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine. • Monitoring with a program 1 Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated). • Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0. • Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible. REJ09B0441-0010 Rev.0.10 Page 460 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23. Timer RG Timer RG is a 16-bit timer with two I/O pins. 23.1 Introduction Timer RG uses either f1 or fOCO40M as its operating clock. Table 23.1 lists the Timer RG Operating Clocks. Table 23.1 Timer RG Operating Clocks Condition The count source is f1, f2, f4, f8, f32, TRGCLKA input, or TRGCLKB input. (Bits TCK2 toTCK0 in the TRGCR register are set to 000b to 101b, and 111b.) The count source is fOCO40M. (Bits TCK2 toTCK0 in the TRGCR register are set to 110b.) f1 Timer RG Operating Clock fOCO40M Figure 23.1 shows the Timer RG Block Diagram, and Table 23.2 lists the Timer RG Pin Configuration. Timer RG supports the following three modes: • Timer mode - Input capture function: Count at the rising edge, falling edge, or both rising and falling edges - Output compare function: Low-level output, high-level output, or toggle output • PWM mode: PWM output available with any duty • Phase counting mode: Automatic measurement available for the counts of the two-phase encoder REJ09B0441-0010 Rev.0.10 Page 461 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG f1, f2, f4, f8, f32, fOCO40M TRG register Comparator TRGGRA register TRGGRB register TRGGRC register Data bus Count source selection circuit TRGCLKA TRGCLKB TRGIOA TRGIOB TRGGRD register TRGMR register TRGCNTC register TRGCR register TRGIOR register TRGIER register TRGSR register Timer RG Control Circuit Timer RG interrupt request Figure 23.1 Timer RG Block Diagram Table 23.2 Timer RG Pin Configuration Pin Name TRGCLKA Assigned Pin P13_5 I/O Input Function • In phase counting mode A-phase input • In other than phase counting mode External clock A input • In phase counting mode B-phase input • In other than phase counting mode External clock B input • In timer mode (output compare function) TRGGRA output-compare output • In timer mode (input capture function) TRGGRA input-capture input • In PWM mode PWM output • In timer mode (output compare function) TRGGRB output-compare output • In timer mode (input capture function) TRGGRB input-capture input TRGCLKB P13_7 Input TRGIOA P13_4 I/O TRGIOB P13_6 I/O REJ09B0441-0010 Rev.0.10 Page 462 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2 23.2.1 Registers Timer RG Mode Register (TRGMR) b6 — 1 b5 DFCK1 0 b4 DFCK0 0 b3 DFB 0 b2 DFA 0 b1 MDF 0 b0 PWM 0 R/W R/W R/W R/W R/W R/W R/W Address 0170h Bit b7 Symbol TSTART After Reset 0 Bit b0 b1 b2 b3 b4 b5 Symbol PWM MDF DFA DFB DFCK0 DFCK1 Bit Name PWM mode select bit Phase counting mode select bit Digital filer function select bit for TRGIOA pin Digital filer function select bit for TRGIOB pin Digital filter function clock select bit Function 0: Timer Mode 1: PWM mode 0: Increment 1: Phase counting mode 0: Digital filter function not used 1: Digital filter function used 0: Digital filter function not used 1: Digital filter function used b5 b4 b6 b7 0 0: f32 0 1: f8 1 0: f1 1 1: Clock selected by bits TCK0 to TCK2 in TRGCR register — Nothing is assigned. If necessary, set to 0. When read, the content is 1. TSTART TRG count start bit 0: Count stops 1: Count starts — R/W MDF Bit (Phase Counting Mode Select Bit) When the MDF bit is set to 0, the counter counts the count source set by bits TCK0 to TCK2 in the TRGCR register. When the MDF bit is set to 1, the counter counts the phase of input signals from the TRGCLKj pin (j = A or B) as listed in Table 23.12 Increment and Decrement Conditions for TRG Register. REJ09B0441-0010 Rev.0.10 Page 463 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.2 Timer RG Count Control Register (TRGCNTC) b0 CNTEN0 0 R/W R/W Address 0171h Bit b7 b6 b5 b4 b3 b2 b1 Symbol CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 After Reset 0 0 0 0 0 0 0 Bit b0 Symbol CNTEN0 Bit Name Counter enable bit 0 b1 CNTEN1 Counter enable bit 1 b2 CNTEN2 Counter enable bit 2 b3 CNTEN3 Counter enable bit 3 b4 CNTEN4 Counter enable bit 4 b5 CNTEN5 Counter enable bit 5 b6 CNTEN6 Counter enable bit 6 b7 CNTEN7 Counter enable bit 7 Function 0: Disabled 1: Decrement When TRGCLKA input is high and at the rising edge of TRGCLKB input 0: Disabled 1: Decrement When TRGCLKB input is low and at the rising edge of TRGCLKA input 0: Disabled 1: Decrement When TRGCLKA input is low and at the falling edge of TRGCLKB input 0: Disabled 1: Decrement When TRGCLKB input is high and at the falling edge of TRGCLKA input 0: Disabled 1: Increment When TRGCLKB input is low and at the falling edge of TRGCLKA input 0: Disabled 1: Increment When TRGCLKA input is high and at the falling edge of TRGCLKB input 0: Disabled 1: Increment When TRGCLKB input is high and at the rising edge of TRGCLKA input 0: Disabled 1: Increment When TRGCLKA input is low and at the rising edge of TRGCLKB input R/W R/W R/W R/W R/W R/W R/W The TRGCNTC register is used in phase counting mode. This register sets its count conditions. REJ09B0441-0010 Rev.0.10 Page 464 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.3 Timer RG Control Register (TRGCR) b6 CCLR1 0 b5 CCLR0 0 b4 CKEG1 0 b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 Function b2 b1 b0 Address 0172h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b0 TCK0 0 R/W R/W R/W R/W Symbol Bit Name TCK0 Count source select bit (1) TCK1 TCK2 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRGCLKA input 1 1 0: fOCO40M 1 1 1: TRGCLKB input b4 b3 b3 b4 CKEG0 External clock active edge CKEG1 select bit (1) 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both the rising/falling edges 1 1: Do not set. b6 b5 R/W R/W b5 b6 CCLR0 TRG register clear source CCLR1 select bit b7 — 0 0: Clear disabled 0 1: TRG register cleared by input capture or compare match with TRGGRA register 1 0: TRG register cleared by input capture or compare match with TRGGRB register 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 1. R/W R/W — Note: 1. In phase counting mode, the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 are disabled and the operation of phase counting mode has priority. REJ09B0441-0010 Rev.0.10 Page 465 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.4 Timer RG Interrupt Enable Register (TRGIER) b6 — 1 b5 — 1 b4 — 1 b3 OVIE 0 b2 UDIE 0 b1 IMIEB 0 b0 IMIEA 0 R/W R/W R/W R/W R/W — Address 0173h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IMIEA IMIEB UDIE OVIE — — — — Bit Name Input-capture/compare-match interrupt enable bit A Input-capture/compare-match interrupt enable bit B Underflow interrupt enable bit Function 0: Interrupt by IMFA bit disabled 1: Interrupt by IMFA bit enabled 0: Interrupt by IMFB bit disabled 1: Interrupt by IMFB bit enabled 0: Interrupt by UDF bit disabled 1: Interrupt by UDF bit enabled Overflow interrupt enable bit 0: Interrupt by OVF bit disabled 1: Interrupt by OVF bit enabled Nothing is assigned. If necessary, set to 0. When read, the content is 1. REJ09B0441-0010 Rev.0.10 Page 466 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.5 Timer RG Status Register (TRGSR) b6 — 1 b5 — 1 b4 DIRF 0 b3 OVF 0 b2 UDF 0 b1 IMFB 0 b0 IMFA 0 R/W R/W R/W R/W R/W R — Address 0174h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IMFA IMFB UDF OVF DIRF — — — Bit Name Input-capture/compare-match flag A Input-capture/compare-match flag B Underflow flag Overflow flag Count direction flag Function [Condition for setting to 0] Write 0 after reading. (1) [Condition for setting to 1] Refer to Table 23.3 Conditions for Setting Bit of Each Flag to 1. 0: TRG register is decremented 1: TRG register is incremented Nothing is assigned. If necessary, set to 0. When read, the content is 1. Note: 1. The results of writing to these bits are as follows: • The bit is set to 0 when it is first read as 1 and then 0 is written to it. • The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.) • The bit’s value remains unchanged if 1 is written to it. Table 23.3 Bit Symbol IMFA IMFB UDF OVF Conditions for Setting Bit of Each Flag to 1 Timer Mode PWM Mode Input Capture Function Output Compare Function When the values of registers TRG and TRGGRA match. TRGIOA pin input edge (1) When the values of registers TRG and TRGGRB match. TRGIOB pin input edge (1) When the TRG register underflows. When the TRG register overflows. Note: 1. Edge selected by bits IOj0 and IOj1 (j = A or B) in the TRGIOR register. REJ09B0441-0010 Rev.0.10 Page 467 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.6 Timer RG I/O Control Register (TRGIOR) b6 IOB2 0 b5 IOB1 0 b4 IOB0 0 b3 BUFA 0 b2 IOA2 0 b1 IOA1 0 b0 IOA0 0 Address 0175h Bit b7 Symbol BUFB After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IOA0 IOA1 IOA2 BUFA IOB0 IOB1 IOB2 BUFB Bit Name TRGGRA control bit TRGGRA mode select bit TRGGRC register function select bit TRGGRB control bit TRGGRB mode select bit TRGGRD register function select bit Function R/W Function varies depending on the operating mode (function). R/W R/W R/W 0: Output compare function (1) 1: Input capture function (2) 0: Not used as the buffer register of the TRGGRA register R/W 1: Used as the buffer register of the TRGGRA register Function varies depending on the operating mode (function). R/W R/W R/W 0: Output compare function (3) 1: Input capture function (4) 0: Not used as the buffer register of the TRGGRB register R/W 1: Used as the buffer register of the TRGGRB register Notes: 1. When the IOA2 bit is set to 0 (output compare function), the TRGGRA register functions as a compare match register. After a reset, the TRGIOA pin outputs a low-level signal until the first compare match occurs. 2. When the IOA2 bit is set to 1 (input capture function), the TRGGRA register functions as an input capture register. 3. When the IOB2 bit is set to 0 (output compare function), the TRGGRB register functions as a compare match register. After a reset, the TRGIOB pin outputs a low-level signal the until the first compare match occurs. 4. When the IOB2 bit is set to 1 (input capture function), the TRGGRB register functions as an input capture register. REJ09B0441-0010 Rev.0.10 Page 468 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.7 Timer RG Counter (TRG) b5 — 0 b13 — 0 b4 — 0 b12 — 0 b3 — 0 b11 — 0 b2 — 0 b10 — 0 b1 — 0 b9 — 0 b0 — 0 b8 — 0 Address 0177h to 0176h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol After Reset b15 — 0 b14 — 0 Bit Function b15 to b0 In phase counting mode, count operation is increment/decrement. In other modes, count operation is increment. Setting Range 0000h to FFFFh R/W R/W The TRG register is connected to the CPU via the internal 16-bit bus and should be always accessed in 16-bit units. This register operates incrementing and can also operate free-running, period counting, or external event counting. It can be cleared to 0000h by a compare match with the corresponding TRGGRA or TRGGRB register, or an input capture to the TRGGRA or TRGGRB register (count clear function). When the TRGCR register overflows (FFFFh → 0000h), the OVF bit in the TRGSR register is set to 1. When the TRGCR register underflows (0000h → FFFFh), the UDF bit in the TRGSR register is set to 1. REJ09B0441-0010 Rev.0.10 Page 469 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.8 Timer RG General Register A, B, C, D (TRGGRA, TRGGRB, TRGGRC, TRGGRD) Address 0179h to 0178h (TRGGRA), 017Bh to 017Ah (TRGGRB), 017Dh to 017Ch (TRGGRC), 017Fh to 017Eh (TRGGRD) Bit b7 b6 b5 b4 b3 b2 Symbol — — — — — — After Reset 1 1 1 1 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 b13 — 1 b12 — 1 b11 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 Bit Function b15 to b0 Function varies depending on the operating mode. R/W R/W TRGGRA and TRGGRB are 16-bit readable/writable registers with both the output compare and input capture register functions. Switching between these functions is accomplished by means of a setting in the TRGIOR register. When registers TRGGRA and TRGGRB are used as output compare registers, the values of registers TRGGRA and TRGGRB and the value of the TRG register are always compared. When their values match (compare match), bits IMFA and IMFB in the TRGSR register are set to 1. Compare match output can be selected by setting the TRGIOR register. When registers TRGGRA and TRGGRB are used as input capture registers, the value of the TRG register is stored when an externally input capture signals is detected. Bits IMFA and IMFB in the TRGSR register are set to 1 at this time. The detection edge of input capture signals is selected by setting the TRGIOR register. In PWM mode, the settings of the TRGIOR register are ignored. The TRGGRC register can also be used as the buffer register of the TRGGRA register, and the TRGGRD register can be used as the buffer register of the TRGGRB register, respectively. These functions can be selected by setting bits BUFA and BUFB in the TRGIOR register. For example, when the TRGGRA register is set as an output compare register and the TRGGRC register is set as the buffer register of the TRGGRA register, the value of the TRGGRC register is transferred to the TRGGRA register each time compare match A occurs. When the TRGGRA register is set as an input capture register and the TRGGRC register is set as the buffer register of the TRGGRA register, the value of the TRG register is transferred to the TRGGRA register and the value of the TRGGRA register value is transferred to the TRGGRC register each time an input capture occurs. Registers TRGGRA and TRGGRB are connected to the CPU via the internal 16-bit bus and should be accessed in 16-bit units. These registers are set as output compare registers (pin output disabled) after a reset. REJ09B0441-0010 Rev.0.10 Page 470 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.2.9 Timer RG Pin Select Register (TRGPSR) b4 TRGIOASEL0 Address 0187h Bit b7 b6 b5 Symbol TRGCLKBSEL0 TRGCLKASEL0 TRGIOBSEL0 After Reset 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol — — — — TRGIOASEL0 TRGIOBSEL0 b3 — b2 — b1 — b0 — 0 0 0 0 0 R/W — Bit Name Function Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRGIOA pin select bit TRGIOB pin select bit TRGCLKASEL0 TRGCLKA pin select bit TRGCLKBSEL0 TRGCLKB pin select bit 0: TRGIOA pin not used 1: TRGIOA pin used 0: TRGIOB pin not used 1: TRGIOB pin used 0: TRGCLKA pin not used 1: TRGCLKA pin used 0: TRGCLKB pin not used 1: TRGCLKB pin used R/W R/W R/W R/W The TRGPSR register selects which pin is assigned as the timer RG input/output. To use the I/O pins for timer RG, set this register. Set the TRGPSR register before setting the timer RG associated registers. Also, do not change the setting value of this register during timer RG operation. REJ09B0441-0010 Rev.0.10 Page 471 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.3 23.3.1 Common Items for Multiple Modes Count Sources Table 23.4 lists the Count Source Selection, and Figure 23.2 shows the Count Source Block Diagram. When phase counting mode is selected, the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 in the TRGCR register are disabled. Table 23.4 f1 f2, f4, f8, f32 fOCO40M External signal input to TRGCLKA or TRGCLKB pin Count Source Selection Count Source Selection Method The count source is selected by bits TCK0 to TCK2 in the TRGCR register. - The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on). - Bits TCK2 to TCK0 in the TRGCR register are set to 110b (fOCO40M). - Bits TCK2 to TCK0 in the TRGCR register are set to 101b (TRGCLKA input) or 111b (TRGCLKB input). - The active edge is selected by bits CKEG0 and CKEG1 in the TRGCR register. - The corresponding bit in the direction register is set to 0 (input mode). f1 f2 f4 f8 f32 TRGCLKA fOCO40M TRGCLKB TCK2 to TCK0 = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b Count source TRG register TCK0 to TCK2: Bits in TRGCR register Figure 23.2 Count Source Block Diagram The pulse width of an external clock input to the TRGCLKj pin (j =A or B) should be set to three cycles or more of the timer RG operating clock. (See Table 23.1 Timer RG Operating Clocks.) REJ09B0441-0010 Rev.0.10 Page 472 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.3.2 Buffer Operation The BUFA or BUFB bit in the TRGIOR register can be used to select the TRGGRC or TRGGRD register as the buffer register of the TRGGRA or TRGGRB register. • Buffer register of TRGGRA register: TRGGRC register • Buffer register of TRGGRB register: TRGGRD register Buffer operation differs depending on the mode. Table 23.5 lists the Buffer Operation in Each Mode, Figure 23.3 shows the Buffer Operation of Input Capture Function, and Figure 23.4 shows the Buffer Operation of Output Compare Function. Table 23.5 Buffer Operation in Each Mode Transfer Destination Register The content of the TRGGRA (TRGGRB) register is transferred to the buffer register. Output compare function Compare match between the TRG The content of the buffer register is register and the TRGGRA (TRGGRB) transferred to the TRGGRA PWM mode register (TRGGRB) register. Function, Mode Input capture function Transfer Timing Input capture signal input TRGIOA input (input capture signal) TRGGRC register TRGGRA register TRG TRGIOA input TRG register n-1 n Transfer n+1 TRGGRA register m Transfer n TRGGRC register (buffer) m The above applies under the following conditions: • The BUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as the buffer register of the TRGGRA register). • Bits IOA2 to IOA0 in the TRGIOR register are set to 100b (input capture at the rising edge). Figure 23.3 Buffer Operation of Input Capture Function REJ09B0441-0010 Rev.0.10 Page 473 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG Compare match signal TRGGRC register TRGGRA register Comparator TRG TRG register m-1 m m+1 TRGGRA register m Transfer n TRGGRC register (buffer) n TRGIOA output The above applies under the following conditions: • The BUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as the buffer register of the TRGGRA register). • Bits IOA2 to IOA0 in the TRGIOR register are set to 001b (low-level output at compare match). Figure 23.4 Buffer Operation of Output Compare Function REJ09B0441-0010 Rev.0.10 Page 474 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.3.3 Digital Filter The input to TRGIOj (j = A or B) is sampled and the level is determined when three matches occur. The digital filter function and sampling clock are selected by using the TRGMR register. Figure 23.5 shows a Block Diagram of Digital Filter. TCK2 to TCK0 f1 f2 f4 f8 f32 TRGCLKA fOCO40M TRGCLKB = 001b = 010b = 011b Count source = 100b = 101b = 110b = 111b = 000b f32 f8 f1 DFCK1 to DFCK0 = 00b = 01b = 10b = 11b IOA2 to IOA0 IOB2 to IOB0 Sampling clock DFj C TRGIOj input signal D Latch Timer RG operating clock f1 or fOCO40M C D Latch Q Q D C Q Latch D C Q Latch D C Q Latch 1 Match detection circuit Edge detection circuit 0 Clock cycle selected by TCK2 to TCK0 (or DFCK1 to DFCK0) Sampling clock TRGIOj input signal Three matches occur and a signal change is confirmed. Input signal after passing through digital filter Maximum signal transmission delay is five sampling clocks. If fewer than three matches occur, the matches are recognized as noise and no transmission is performed. j = A or B TCK0 to TCK2: Bits in TRGCR register DFCK0, DFCK1, DFj: Bits in TRGMR register IOA0 to IOA2, IOB0 to IOB2: Bits in TRGIOR register Figure 23.5 Block Diagram of Digital Filter REJ09B0441-0010 Rev.0.10 Page 475 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.4 Timer Mode (Input Capture Function) The value of the TRG register can be transferred to the TRGGRA or TRGGRB register when the input edge of the input capture/output compare pin (TRGIOA or TRGIOB) is detected. The detection edge can be selected from the rising edge, falling edge, or both edges. The input capture function can be used for measuring pulse widths and periods. Table 23.6 lists the Input Capture Function Specifications. Table 23.6 Input Capture Function Specifications Item Count sources Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRGCLKj pin (active edge selectable by a program) Increment When bits CCLR1 to CCLR0 in the TRGCR register are set to 00b (free-running operation) 1/fk × 65,536 fk: Frequency of count source 1 (count starts) is written to the TSTART bit in the TRGMR register. 0 (count stops) is written to the TSTART bit in the TRGMR register. • Input capture (active edge of the TRGIOj input) • TRG register overflow Programmable I/O port or input-capture input (selectable for each individual pin) Programmable I/O port or external clock input The count value can be read by reading the TRG register. The TRG register can be written to. • Input-capture input pin selection Either one or both of pins TRGIOA and TRGIOB • Active edge selection for input-capture input Rising edge, falling edge, or both rising and falling edges • Timing for setting the TRG register to 0000h Overflow or input capture • Buffer operation (Refer to 23.3.2 Buffer Operation.) • Digital filter (Refer to 23.3.3 Digital Filter.) Count operation Count period Count start condition Count stop condition Interrupt request generation timing TRGIOA/TRGIOB pins function TRGCLKA/TRGCLKB pins function Read from timer Write to timer Selectable functions j = A or B REJ09B0441-0010 Rev.0.10 Page 476 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.4.1 Timer RG I/O Control Register (TRGIOR) in Timer Mode (Input Capture Function) b6 IOB2 0 b5 IOB1 0 b4 IOB0 0 b3 BUFA 0 b2 IOA2 0 b1 IOA1 0 b0 IOA0 0 R/W R/W R/W Address 0175h Bit b7 Symbol BUFB After Reset 0 Bit b0 b1 Symbol IOA0 IOA1 Bit Name TRGGRA control bit Function b1 b0 b2 b3 b4 b5 IOA2 BUFA IOB0 IOB1 TRGGRA mode select bit (1) TRGGRC register function select bit TRGGRB control bit 0 0: Input capture to TRGGRA at the rising edge 0 1: Input capture to TRGGRA at the falling edge 1 0: Input capture to TRGGRA at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. 0: Not used as the buffer register of the TRGGRA register 1: Used as the buffer register of the TRGGRA register b5 b4 R/W R/W R/W R/W b6 b7 IOB2 BUFB TRGGRB mode select bit (2) TRGGRD register function select bit 0 0: Input capture to TRGGRB at the rising edge 0 1: Input capture to TRGGRB at the falling edge 1 0: Input capture to TRGGRB at both edges 1 1: Do not set. Set to 1 (input capture) for the input capture function. 0: Not used as the buffer register of the TRGGRB register 1: Used as the buffer register of the TRGGRB register R/W R/W Notes: 1. When the IOA2 bit is set to 1 (input capture function), the TRGGRA register functions as an input capture register. 2. When the IOB2 bit is set to 1 (input capture function), the TRGGRB register functions as an input capture register. REJ09B0441-0010 Rev.0.10 Page 477 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.4.2 Procedure Example for Setting Input Capture Operation Figure 23.6 shows a Procedure Example for Setting Input Capture Operation. Input selection (1) Use the TRGIOR register to set TRGGRj (j = A or B) as an input capture register and select the input edge of input capture signals from the following three: the rising edge, falling edge, or both edges. (1) (2) Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. Select input-capture input Count operation starts (2) Input capture operation Figure 23.6 Procedure Example for Setting Input Capture Operation 23.4.3 Input Capture Signal Timing The rising edge, falling edge, or both edges can be selected for input-capture input by setting the TRGIOR register. Figure 23.7 shows the Input-Capture Input Signal Timing. The pulse width of input-capture input signals should be 1.5 f1 or more for a single edge and 2.5 f1 or more for both edges. f1 TRGIOj input Input capture signal (internal signal) TRG register N TRGGRj register N j =A or B Figure 23.7 Input-Capture Input Signal Timing REJ09B0441-0010 Rev.0.10 Page 478 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.4.4 Operating Example Figure 23.8 shows an Operating Example of Input Capture. This example applies when both the rising and falling edges are selected as the input-capture input edge for the TRGIOA pin, the falling edge is selected as the input-capture input edge for the TRGIOB pin, and the TRG register is set to be cleared by the input capture to the TRGGRB register. (1) Use the TRGIOR register to set registers TRGGRA and TRGGRB as input capture registers and select the input edge of input capture signals from the following three: the rising edge, falling edge, or both edges. (2) Set the TSTART bit in TRGMR to 1 and start the count operation of the TRG register. TRG register value TRGIOB 0180h 0160h 0005h 0000h TRGIOB input Time TRGIOA input TRGGRA register 0005h 0160h TRGGRB register 0180h Figure 23.8 Operating Example of Input Capture REJ09B0441-0010 Rev.0.10 Page 479 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.5 Timer Mode (Output Compare Function) This mode (output compare function) detects when the contents of the TRG register and the TRGGRA or TRGGRB register match (compare match). When a match occurs, a signal is output from the TRGIOA or TRGIOB pin at a given level. Table 23.7 lists the Output Compare Function Specifications. Table 23.7 Output Compare Function Specifications Item Count sources Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRGCLKj pin (active edge selectable by a program) Increment • When bits CCLR1 to CCLR0 in the TRGCR register are set to 00b (free-running operation) 1/fk × 65,536 fk: Frequency of count source • When bits CCLR1 to CCLR01 in the TRGCR register are set to 01b or 10b (TRG is set to 0000h by a compare match with TRGGRj) 1/fk × (n+1) n: Value set in TRGGRj register Compare match 1 (count starts) is written to the TSTART bit in the TRGMR register. 0 (count stops) is written to the TSTART bit in the TRGMR register. • Compare match (the contents of the TRG register and the TRGGRj register match) • TRG register overflow Programmable I/O port or output-compare output (selectable for each individual pin) Programmable I/O port or external clock input The count value can be read by reading the TRG register. The TRG register can be written to. • Output-compare output pin selection Either one or both of pins TRGIOA and TRGIOB • Output level selection at compare match Low-level output, high-level output, or inverted output level • Timing for setting the TRG register to 0000h Overflow or compare match with the TRGGRj register • Buffer operation (Refer to 23.3.2 Buffer Operation.) Count operation Count periods Waveform output timing Count start condition Count stop condition Interrupt request generation timing TRGIOA/TRGIOB pins function TRGCLKA/TRGCLKB pins function Read from timer Write to timer Selectable functions j = A or B REJ09B0441-0010 Rev.0.10 Page 480 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.5.1 Timer RG I/O Control Register (TRGIOR) in Timer Mode (Output Compare Function) b6 IOB2 0 b5 IOB1 0 b4 IOB0 0 b3 BUFA 0 b2 IOA2 0 b1 IOA1 0 b0 IOA0 0 R/W R/W R/W Address 0175h Bit b7 Symbol BUFB After Reset 0 Bit b0 b1 Symbol IOA0 IOA1 Bit Name TRGGRA control bit Function b1 b0 b2 b3 b4 b5 IOA2 BUFA IOB0 IOB1 b6 b7 IOB2 BUFB TRGGRA mode select bit (1) TRGGRC register function 0: Not used as the buffer register of the TRGGRA register select bit 1: Used as the buffer register of the TRGGRA register b5 b4 TRGGRB control bit 0 0: Pin output by compare match is disabled (TRGIOB pin functions as a programmable I/O port) 0 1: Low-level output at compare match with TRGGRB 1 0: High-level output at compare match with TRGGRB 1 1: Toggle output at compare match with TRGGRB TRGGRB mode Set to 0 (output compare) for the output compare function. select bit (2) TRGGRD register function 0: Not used as the buffer register of the TRGGRB register select bit 1: Used as the buffer register of the TRGGRB register 0 0: Pin output by compare match is disabled (TRGIOA pin functions as a programmable I/O port) 0 1: Low-level output at compare match with TRGGRA 1 0: High-level output at compare match with TRGGRA 1 1: Toggle output at compare match with TRGGRA Set to 0 (output compare) for the output compare function. R/W R/W R/W R/W R/W R/W Notes: 1. When the IOA2 bit is set to 0 (output compare function), the TRGGRA register functions as a compare match register. After a reset, the TRGIOA pin outputs as follows until the first compare match occurs. IOA1 to IOA0 = 01b: High-level output 10b: Low-level output 11b: Low-level output 2. When the IOB2 bit is set to 0 (output compare function), the TRGGRB register functions as a compare match register. After a reset, the TRGIOB pin outputs as follows until the first compare match occurs. IOB1 to IOB0 = 01b: High-level output 10b: Low-level output 11b: Low-level output REJ09B0441-0010 Rev.0.10 Page 481 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.5.2 Procedure Example for Setting Waveform Output by Compare Match Figure 23.9 shows an Operating Example of Waveform Output by Compare Match. Output selection Select waveform output mode (1) (1) Use the TRGIOR register to select the compare match output from the following three: low-level output, high-level output, or toggle output. When waveform output mode is selected, the ports function as the compare match output pins (TRGIOA and TRGIOB). The output levels of these pins depend on the settings of bits IOA0 and IOA1 and bits IOB0 and IOB1 in the TRGIOR register until the first compare match occurs. (2) Set the timing for generating a compare match in registers TRGGRA and TRGGRB. (3) Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. Set the output timing (2) Count operation starts (3) Waveform output Figure 23.9 Operating Example of Waveform Output by Compare Match 23.5.3 Output-Compare Output Timing A compare match signal is generated at the last state when the TRG register and the TRGGRA or TRGGRB register match (according to the timing for updating the count value that the TRG register matches). When a compare match signal is generated, the output value set by the TRGIOR register is output to the output-compare output pin (TRGIOA or TRGIOB). After the TRG register and the TRGGRA or TRGGRB register match, no compare match signal is generated until the TRG input clock is generated. Figure 23.10 shows the Output-Compare Output Timing. f1 TRG input clock TRG register N N+1 N+2 TRGGRA register N TRGGRB register Compare match A signal (internal signal) Compare match B signal (internal signal) TRGIOA output N+1 TRGIOB output Figure 23.10 Output-Compare Output Timing REJ09B0441-0010 Rev.0.10 Page 482 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.5.4 Operating Example Figure 23.11 shows an Operating Example of Low-Level Output and High-Level Output. This example applies when the TRG register is set for free-running operation, low-level output at compare match A is selected, and high-level output at compare match B is selected. When the selected level and the pin level match, the pin level does not change. TRG register value FFFFh TRGGRB register TRGGRA register 0000h Time TRGIOB output No change No change High-level output TRGIOA output No change No change Low-level output Figure 23.11 Operating Example of Low-Level Output and High-Level Output Figure 23.12 shows an Operating Example of Toggle Output. This example applies when the TRG register is set for period counting operation (counter clear by compare match B), and toggle output at both compare match A and B is selected. Use the TRGIOR register to select the compare match output from the following three: low-level output, highlevel output, or toggle output. When waveform output mode is selected, the ports function as the compare match output pins (TRGIOA and TRGIOB). Set the timing for generating a compare match in registers TRGGRA and TRGGRB. Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. TRG register value Counter cleared by compare match with TRGGRB register TRGGRB register TRGGRA register 0000h Time TRGIOB output Toggle output TRGIOA output Toggle output Figure 23.12 Operating Example of Toggle Output REJ09B0441-0010 Rev.0.10 Page 483 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.6 PWM Mode In PWM mode, registers TRGGRA and TRGGRB are used as a pair and a PWM waveform is output from the TRGIOA output pin. The output setting in the TRGIOR register is invalid for the pins set to PWM mode. Set the high-level output timing for PWM waveforms in the TRGGRA register and the low-level output timing for PWM waveforms in the TRGGRB register. By selecting a compare match with either the TRGGRA or TRGGRB register as the counter clear source for the TRG register, a PWM waveform with a duty of 0% to 100% can be output from the TRGIOA pin. Table 23.8 lists the PWM Mode Specifications, and Table 23.9 lists the Combination of PWM Output Pins and Registers. When the setting values of registers TRGGRA and TRGGRB are the same, the output value does not change even if a compare match occurs. Table 23.8 PWM Mode Specifications Item Count sources Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRGCLKj pin (active edge selectable by a program) Increment • The high-level output timing for PWM waveforms is set in the TRGGRA register. • The low-level output timing for PWM waveforms is set in the TRGGRB register. 1 (count starts) is written to the TSTART bit in the TRGMR register. 0 (count stops) is written to the TSTART bit in the TRGMR register. • Compare match (the contents of the TRG register and the TRGRj register match) • TRG register overflow PWM output Programmable I/O port Programmable I/O port or external clock input The count value can be read by reading the TRG register. The TRG register can be written to. • Timing for setting the TRG register to 0000h Overflow or compare match with the TRGGRj register • Buffer operation (Refer to 23.3.2 Buffer Operation.) Count operation PWM waveform Count start condition Count stop condition Interrupt request generation timing TRGIOA pin function TRGIOB pin function TRGCLKA/TRGCLKB pins function Read from timer Write to timer Selectable functions j = A or B Table 23.9 Output Pin TRGIOA TRGIOB Combination of PWM Output Pins and Registers High-Level Output Low-Level Output TRGGRA TRGGRB I/O port function REJ09B0441-0010 Rev.0.10 Page 484 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.6.1 Procedure Example for Setting PWM Mode Figure 23.13 shows a Procedure Example for Setting PWM Mode. PWM mode (1) Use bits TCK0 to TCK2 in the TRGCR register to select the count source. When an external clock is selected, use bits CKEG0 and CKEG1 in the TRGCR register to select the edge of the external clock. (2) Use bits CCLR0 and CCLR1 in the TRGCR register to select the counter clear source. (3) Set the high-level output timing for PWM output waveforms in the TRGGRA register. Set TRGGRA (3) (4) Set the low-level output timing for PWM output waveforms in the TRGGRB register. (5) Use the PWM bit in the TRGMR register to select PWM mode. When PWM mode is selected, TRGGRA and TRGGRB are set as the output compare registers for setting the high-level output or low-level output timing for PWM output waveforms, regardless of the content of the TRGIOR register. While the TRGIOASEL0 bit in the TRGSR register is set to 1, the TRGIOA pin automatically functions as a PWM output pin. However, regardless of the setting of the TRGIOR register, the TRGIOB pin functions as an I/O port. (6) Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. Select the counter clock (1) Select the counter clear source (2) Set TRGGRB (4) Set PWM mode (5) Count operation starts (6) PWM mode Figure 23.13 Procedure Example for Setting PWM Mode 23.6.2 Operating Example Figure 23.14 shows an Operating Example in PWM Mode (1). When PWM mode is selected while the TRGIOASEL0 bit in the TRGSR register is set to 1, the TRGIOA pin automatically functions as an output pin, high-level output at compare match with the TRGGRA register is selected, and low-level output at compare match with the TRGGRB register is selected. However, regardless of the setting of the TRGIOR register, the TRGIOB pin functions as an I/O port. This example applies when a compare match with the TRGGRA or TRGGRB register is set as the counter clear source for the TRG register. The initial status of the TRGIOA pin depends only on the counter clear sources. This correspondence is shown in Table 23.10. Table 23.10 Correspondence between Initial Status of TRGIOA Pin and Counter Clear Sources Initial Status of TRGIOA Pin High Low Counter Clear Source Compare match with TRGGRA register Compare match with TRGGRB register REJ09B0441-0010 Rev.0.10 Page 485 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG TRG register value Counter cleared by compare match A TRGGRA register TRGGRB register 0000h Time TRGIOA output (a) Counter clear by the compare match with the TRGGRA register TRG register value Counter cleared by compare match B TRGGRB register TRGGRA register 0000h Time TRGIOA output (b) Counter clear by the compare match with the TRGGRB register Figure 23.14 Operating Example in PWM Mode (1) Figure 23.15 shows an example for outputting a PWM waveform with a duty of 0% and 100%. The PWM waveform duty is set to 0% when a compare match with the TRGGRB register is set as the counter clear source under the following conditions: • TRGGRA setting value > TRGGRB setting value The PWM waveform duty is set to 100% when a compare match with TRGGRA register is set as the counter clear source under the following conditions: • TRGGRB setting value > TRGGRA setting value REJ09B0441-0010 Rev.0.10 Page 486 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG TRG register value Counter cleared by compare match B TRGGRB register TRGGRA register 0000h Time TRGIOA output TRGGRA register setting value written TRGGRA register setting value written (a) Duty 0% TRG register value Counter cleared by compare match A TRGGRA register TRGGRB register 0000h Time TRGIOA output TRGGRB register setting value written TRGGRB register setting value written (b) Duty 100% Figure 23.15 Operating Example in PWM Mode (2) REJ09B0441-0010 Rev.0.10 Page 487 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.7 Phase Counting Mode In phase counting mode, the phase difference between the external input signals from two pins TRGCLKA and TRGCLKB is detected and the TRG register is incremented or decremented. When phase counting mode is selected while the bits TRGCLKASEL0 and TRGCLKBSEL0 are set to 1, regardless of the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 in the TRGCR register, pins TRGCLKA and TRGCLKB automatically function as external clock input pins and the TRG register is incrermented or decremented by setting bits CNTEN0 to CNTEN7 in the TRGCNTC register. However, bits CCLR0 and CCLR1 in the TRGCR register and registers TRGIOR, TRGIER, TRGSR, TRGGRA, and TRGGRB are enabled, so the input capture/output compare function, PWM output function, and interrupt sources can be used. The TRG register operates counting at both the rising and falling edges of the TRGCLKA or TRGCLKB pin by setting bits CNTEN0 to CNTEN7. Table 23.11 lists the Phase Counting Mode Specifications, and Table 23.12 lists the Increment and Decrement Conditions for TRG Register. Table 23.11 Phase Counting Mode Specifications Item Count source Count operations Count start condition Count stop condition Interrupt request generation timing TRGIOA pin function TRGIOB pin function TRGCLKA/TRGCLKB pins function Read from timer Write to timer Selectable functions Specification External signal input to the TRGCLKj pin Increment/decrement 1 (count starts) is written to the TSTART bit in the TRGMR register. 0 (count stops) is written to the TSTART bit in the TRGMR register. • Input capture (active edge of the TRGIOj input) • Compare match (the contents of the TRG register and the TRGGRj register match) • TRG register underflow • TRG register overflow Programmable I/O port, input-capture input, output-compare output, or PWM output Programmable I/O port, input-capture input, or output-compare output External clock input The count value can be read by reading the TRG register. The TRG register can be written to. • Selection of counter increment and decrement conditions Selectable by bits CNTEN7 to CNTEN0 bits in the TRGCNTC register. • The input capture/output compare function and PWM function can be used. j = A or B Table 23.12 TRGCLKB pin TRGCLKA pin Bits CNTEN7 to CNTEN0 in TRGCNTC register Value Count direction Increment and Decrement Conditions for TRG Register High Low High Low High Low Low High CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 0 − 1 +1 0 − 1 +1 0 − 1 +1 0 − 1 +1 0 − 1 −1 0 − 1 −1 0 − 1 −1 0 − 1 −1 REJ09B0441-0010 Rev.0.10 Page 488 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.7.1 Timer RG Control Register (TRGCR) in Phase Counting Mode b6 CCLR1 0 b5 CCLR0 0 b4 CKEG1 0 b3 CKEG0 0 b2 TCK2 0 b1 TCK1 0 b0 TCK0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address 0172h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 Symbol TCK0 TCK1 TCK2 CKEG0 CKEG1 CCLR0 CCLR1 Bit Name Count source select bit Function Disabled in phase counting mode. External clock active edge select bit TRG register clear select bit Disabled in phase counting mode. b6 b5 b7 — 0 0: Clear disabled 0 1: TRG register cleared by input capture or compare match with TRGGRA 1 0: TRG register cleared by input capture or compare match with TRGGRB 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 1. — 23.7.2 Procedure Example for Setting Phase Counting Mode Figure 23.16 shows a Procedure Example for Setting Phase Counting Mode. Phase counting mode (1) Set the MDF bit in the TRGMR register to 1 to select phase counting mode. Select phase counting mode (1) (2) Set the TSTART bit in the TRGMR register to 1 to start count operation. Count operation starts (2) Phase counting mode Figure 23.16 Procedure Example for Setting Phase Counting Mode REJ09B0441-0010 Rev.0.10 Page 489 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.7.3 Operating Example Figures 23.17 to 23.20 show operating examples in phase counting mode. Table 23.12 lists the Increment and Decrement Conditions for TRG Register. In phase counting mode, the TRG register is incremented or decremented at both the rising ( ) and falling ( ) edges of the TRGCLKA or TRGCLKB pin by setting bits CNTEN0 to CNTEN7 in the TRGCNTC register. • When the TRGCNTC register value is FFh TRGCLKB input TRGCLKA input TRG register value Increment Decrement Time Figure 23.17 Operating Example in Phase Counting Mode 1 • When the TRGCNTC register value is 24h TRGCLKB input TRGCLKA input TRG register value Increment Decrement Time Figure 23.18 Operating Example in Phase Counting Mode 2 REJ09B0441-0010 Rev.0.10 Page 490 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG • When the TRGCNTC register value is 28h TRGCLKB input TRGCLKA input TRG register value Increment Decrement Time Figure 23.19 Operating Example in Phase Counting Mode 3 • When the TRGCNTC register value is 5Ah TRGCLKB input TRGCLKA input TRG register value Increment Decrement Time Figure 23.20 Operating Example in Phase Counting Mode 4 REJ09B0441-0010 Rev.0.10 Page 491 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.8 Timer RG Interrupt Timer RG generates a timer RG interrupt request from four sources. The timer RG interrupt uses the single TRGIC register (bits IR and ILVL0 to ILVL2) and a single vector. Table 23.13 lists the Registers Associated with Timer RG Interrupt, and Figure 23.21 is a Block Diagram of Timer RG Interrupt. Table 23.13 Registers Associated with Timer RG Interrupt Timer RG Status Register TRGSR Timer RG Interrupt Enable Register TRGIER Timer RG Interrupt Control Register TRGIC IMFA bit IMIEA bit IMFB bit IMIEB bit UDF bit UDIE bit OVF bit OVIE bit Timer RG interrupt request (IR bit in TRGIC register) IMFA, IMFB, UDF, OVF: Bits in TRGSR register IMIEA, IMIEB, UDIE, OVIE: Bits in TRGIER register Figure 23.21 Block Diagram of Timer RG Interrupt Like other maskable interrupts, the timer RG interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because a single interrupt source (timer RG interrupt) is generated from multiple interrupt request sources. • The IR bit in the TRGIC register is set to 1 (interrupt requested) when a bit in the TRGSR register is set to 1 and the corresponding bit in the TRGIER register is also set to 1 (interrupt enabled). • The IR bit is set to 0 (no interrupt requested) when either the bit in the TRGSR register or the corresponding bit in the TRGIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained even if the IR bit is once set to 1 but the interrupt is not acknowledged. • If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not change. • If multiple bits in the TRGIER register are set to 1, use the TRGSR register to determine the source of the interrupt request. • The bits in the TRGSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to 0 within the interrupt routine. Refer to 23.2.5 Timer RG Status Register (TRGSR), for the procedure for setting these bits to 0. Refer to 23.2.4 Timer RG Interrupt Enable Register (TRGIER), for details of the TRGIER register. Refer to 12.3 Interrupt Control, for details of the TRGIC register and 12.1.5.2 Relocatable Vector Tables, for information on interrupt vectors. REJ09B0441-0010 Rev.0.10 Page 492 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG 23.9 23.9.1 Notes on Timer RG Phase Difference, Overlap, and Pulse Width in Phase Counting Mode The phase difference and overlap between the external input signals from pins TRGCLKA and TRGCLKB should be 1.5 f1 or more, respectively. The pulse width should be 2.5 f1 or more. Figure 23.22 shows the Phase Difference, Overlap, and Pulse Width in Phase Counting Mode. Phase difference Phase difference Pulse width Pulse width TRGCLKA input TRGCLKB input Phase difference and overlap: 1.5 f1 or more Pulse width: 2.5 f1 or more Overlap Overlap Figure 23.22 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode REJ09B0441-0010 Rev.0.10 Page 493 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24. Serial Interface (UARTi (i = 0 or 1)) The serial interface consists of three channels, UART0 to UART2. This chapter describes UARTi (i = 0 or 1). 24.1 Introduction UART0 and UART 1 have a dedicated timer to generate a transfer clock and operate independently. Clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode) are supported. Figure 24.1 shows a Block Diagram of UARTi (i = 0 or 1). Figure 24.2 shows a Block Diagram of UARTi (i = 0 or 1) Transmit/Receive Unit. Table 24.1 lists the Pin Configuration of UARTi (i = 0 or 1). UARTi RXDi CLK1 to CLK0 f1 f8 f32 fC = 00b = 01b = 10b = 11b External CKDIR = 1 TXDi 1/16 CKDIR = 0 Internal UiBRG register UART reception Reception control circuit Receive clock Clock synchronous type 1/(n0+1) 1/16 UART transmission Transmission control circuit Transmit clock Transmit/ receive unit 1/2 Clock synchronous type Clock synchronous type (internal clock selected) CKDIR = 0 Clock synchronous type (external clock selected) CKDIR = 1 Clock synchronous type (internal clock selected) CLKi CLK polarity switch circuit i = 0 or 1 CKDIR: Bit in UiMR register CLK0, CLK1: Bits in UiC0 register Figure 24.1 Block Diagram of UARTi (i = 0 or 1) REJ09B0441-0010 Rev.0.10 Page 494 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 1SP PRYE = 0 Clock PAR disabled synchronous type Clock synchronous type UART (7 bits) UART (8 bits) UART (7 bits) UARTi receive register RXDi SP 2SP SP PAR PAR enabled UART PRYE = 1 UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 UART (8 bits) UART (9 bits) Clock synchronous type D6 D5 D4 D3 D2 D1 D0 UiTB register 2SP PRYE = 1 PAR enabled UART (9 bits) UART SP SP 1SP PAR Clock PAR disabled synchronous PRYE = 0 type 0 UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits) UARTi transmit register i = 0 or 1 SP: Stop bit PAR: Parity bit TXDi Figure 24.2 Block Diagram of UARTi (i = 0 or 1) Transmit/Receive Unit Table 24.1 Pin Configuration of UARTi (i = 0 or 1) Pin Name TXD0 RXD0 CLK0 TXD1 RXD1 CLK1 Assigned Pin P13_1 P13_2 P13_3 P4_0 P4_1 P4_2 I/O Output Input I/O Input Output I/O Function Serial data output Serial data input Transfer clock I/O Serial data output Serial data input Transfer clock I/O REJ09B0441-0010 Rev.0.10 Page 495 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.2 24.2.1 Registers UARTi Transmit/Receive Mode Register (UiMR) (i = 0 or 1) b4 STPS 0 b3 CKDIR 0 b2 SMD2 0 b1 SMD1 0 Function b2 b1 b0 Address 00A0h (U0MR), 0160h (U1MR) Bit b7 b6 b5 Symbol — PRYE PRY After Reset 0 0 0 Bit b0 b1 b2 Symbol SMD0 SMD1 SMD2 Bit Name Serial I/O mode select bit b0 SMD0 0 R/W R/W R/W R/W b3 b4 b5 CKDIR STPS PRY Internal/external clock select bit Stop bit length select bit Odd/even parity select bit b6 b7 PRYE — Parity enable bit Reserved bit 0 0 0: Serial interface disabled 0 0 1: Clock synchronous serial I/O mode 1 0 0: UART mode, transfer data 7 bits long 1 0 1: UART mode, transfer data 8 bits long 1 1 0: UART mode, transfer data 9 bits long Other than above: Do not set. 0: Internal clock 1: External clock 0: One stop bit 1: Two stop bits Enabled when PRYE = 1 0: Odd parity 1: Even parity 0: Parity disabled 1: Parity enabled Set to 0. R/W R/W R/W R/W R/W 24.2.2 UARTi Bit Rate Register (UiBRG) (i = 0 or 1) b3 — X b2 — X b1 — X b0 — X Setting Range 00h to FFh R/W W Address 00A1h (U0BRG), 0161h (U1BRG) Bit b7 b6 b5 b4 Symbol — — — — After Reset X X X X Bit Function b7 to b0 If the setting value is n, UiBRG divides the count source by n+1. Write to the UiBRG register while transmission and reception stop. Use the MOV instruction to write to this register. Set bits CLK0 and CLK1 in the UiC0 register before writing to the UiBRG register. REJ09B0441-0010 Rev.0.10 Page 496 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.2.3 UARTi Transmit Buffer Register (UiTB) (i = 0 or 1) b2 — X b10 — X b1 — X b9 — X b0 — X b8 — X R/W W Address 00A3h to 00A2h (U0TB), 0163h to 0162h (U1TB) Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Symbol After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b15 — X b14 — X b13 — X b12 — X b11 — X Symbol Function — Transmit data — — — — — — — — — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — — — — — — — When the transfer data is 9 bits long, write data to the high-order byte first, then low-order byte of the UiTB register. Use the MOV instruction to write to this register. REJ09B0441-0010 Rev.0.10 Page 497 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.2.4 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1) b4 — 0 b3 TXEPT 1 b2 — 0 b1 CLK1 0 Function b1 b0 Address 00A4h (U0C0), 0164h (U1C0) Bit b7 b6 b5 Symbol UFORM CKPOL NCH After Reset 0 0 0 Bit b0 b1 Symbol CLK0 CLK1 b0 CLK0 0 R/W R/W R/W b2 b3 b4 b5 b6 b7 0 0: f1 selected 0 1: f8 selected 1 0: f32 selected 1 1: fC selected — Reserved bit Set to 0. TXEPT Transmit register empty flag 0: Data in the transmit register (transmission in progress) 1: No data in the transmit register (transmission completed) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NCH Data output select bit 0: TXDi pin set as CMOS output 1: TXDi pin set as N-channel open-drain output CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive data input at the rising edge of the transfer clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the transfer clock UFORM Transfer format select bit 0: LSB first 1: MSB first Bit Name BRG count source select bit (1) R/W R — R/W R/W R/W Note: 1. If the BRG count source is switched, set the UiBRG register again. 24.2.5 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1) b4 UiIRS 0 b3 RI 0 b2 RE 0 b1 TI 1 b0 TE 0 R/W R/W R R/W R R/W R/W — Address 00A5h (U0C1), 0165h (U1C1) Bit b7 b6 b5 Symbol — — UiRRM After Reset 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TE TI RE RI UiIRS UiRRM — — Bit Name Transmission enable bit Function 0: Transmission disabled 1: Transmission enabled Transmit buffer empty flag 0: Data in the UiTB register 1: No data in the UiTB register Reception enable bit 0: Reception disabled 1: Reception enabled 0: No data in the UiRB register Reception complete flag (1) 1: Data in the UiRB register UARTi transmit interrupt source 0: Transmit buffer empty (TI = 1) select bit 1: Transmission completed (TXEPT = 1) UARTi continuous receive mode 0: Continuous receive mode disabled 1: Continuous receive mode enabled enable bit (2) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Notes: 1. The RI bit is set to 0 when the higher byte of the UiRB register is read. 2. In UART mode, set the UiRRM bit to 0 (continuous receive mode disabled). REJ09B0441-0010 Rev.0.10 Page 498 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.2.6 UARTi Receive Buffer Register (UiRB) (i = 0 or 1) b2 — X b10 — X b1 — X b9 — X b0 — X b8 — X R/W R Address 00A7h to 00A6h (U0RB), 0167h to 0166h (U1RB) Bit b7 b6 b5 b4 b3 Symbol — — — — — After Reset X X X X X Bit Symbol After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b15 SUM X b14 PER X b13 FER X Bit Name — b12 OER X b11 — X Symbol — — — — — — — — — — — — OER FER PER SUM Function Receive data (D7 to D0) — Receive data (D8) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. R — Overrun error flag (1) Framing error flag (1) Parity error flag (1) Error sum flag (1) 0: No overrun error 1: Overrun error 0: No framing error 1: Framing error 0: No parity error 1: Parity error 0: No error 1: Error R R R R Note: 1. Bits SUM, PER, FER, and OER are set to 0 (no error) when either of the following is set: - Bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled). - The RE bit in the UiC1 register is set to 0 (reception disabled). The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are also set to 0 when the high-order byte of the UiRB register is read. Always read the UiRB register in 16-bit units. REJ09B0441-0010 Rev.0.10 Page 499 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.2.7 UART0 Pin Select Register (U0SR) b6 — 0 b5 — 0 b4 CLK0SEL0 0 b3 — 0 b2 b1 b0 RXD0SEL0 RXD0SEL1 TXD0SEL0 0 0 0 R/W R/W — R/W R/W Address 0188h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Function 0: TXD0 pin not used 1: TXD0 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. b3 b2 RXD0SEL0 RXD0 pin select bit 0 0: RXD0 pin not used RXD0SEL1 0 1: P13_2 assigned 1 0: P11_4 assigned 1 1: Do not set. CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used 1: CLK0 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — Symbol Bit Name TXD0SEL0 TXD0 pin select bit R/W — The U0SR register selects which pin is assigned as the UART0 input/output. To use the I/O pins for UART0, set this register. Set the U0SR register before setting the UART0 associated registers. Also, do not change the setting value of this register during UART0 operation. REJ09B0441-0010 Rev.0.10 Page 500 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.2.8 UART1 Pin Select Register (U1SR) b6 — 0 b5 — 0 b4 CLK1SEL0 0 b3 — 0 b2 RXD1SEL0 0 b1 — 0 b0 TXD1SEL0 0 R/W R/W — R/W — R/W — Address 0189h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Function 0: TXD1 pin not used 1: TXD1 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. RXD1SEL0 RXD1 pin select bit 0: RXD1 pin not used 1: RXD1 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. CLK1SEL0 CLK1 pin select bit 0: CLK1 pin not used 1: CLK1 pin used — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — Symbol Bit Name TXD1SEL0 TXD1 pin select bit The U1SR register selects which pin is assigned as the UART1 input/output. To use the I/O pins for UART1, set this register. Set the U1SR register before setting the UART1 associated registers. Also, do not change the setting value of this register during UART1 operation. REJ09B0441-0010 Rev.0.10 Page 501 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.3 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 24.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 24.3 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode (1). Table 24.2 Clock Synchronous Serial I/O Mode Specifications Item Transfer data format Transfer clocks Specification • Transfer data length: 8 bits • The CKDIR bit in the UiMR register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32, fC n = Value set in UiBRG register: 00h to FFh • The CKDIR bit is set to 1 (external clock): Input from the CLKi pin • To start transmission, the following requirements must be met: (1) - The TE bit in the UiC1 register is set to 1 (transmission enabled). - The TI bit in the UiC1 register is set to 0 (data in the UiTB register). • To start reception, the following requirements must be met: (1) - The RE bit in the UiC1 register is set to 1 (reception enabled). - The TE bit in the UiC1 register is set to 1 (transmission enabled). - The TI bit in the UiC1 register is set to 0 (data in the UiTB register). • For transmission, one of the following can be selected. - The UiIRS bit is set to 0 (transmit buffer empty): When data is transferred from the UiTB register to the UARTi transmit register (at start of transmission). - The UiIRS bit is set to 1 (transmission completed): When data transmission from the UARTi transmit register is completed. • For reception When data is transferred from the UARTi receive register to the UiRB register (at completion of reception). • Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receives the 7th bit of the next unit of data. • CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock. • LSB first, MSB first selection Whether data transmission/reception begins with bit 0 or begins with bit 7 can be selected. • Continuous receive mode selection Reception is enabled immediately by reading the UiRB register. Transmit start conditions Receive start conditions Interrupt request generation timing Error detection Selectable functions i = 0 or 1 Notes: 1. When an external clock is selected, the requirements must be met in either of the following states: - The external clock is held high when the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) - The external clock is held low when the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) 2. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. REJ09B0441-0010 Rev.0.10 Page 502 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) Table 24.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode (1) Register UiTB UiRB UiBRG UiMR UiC0 Bit b0 to b7 b0 to b7 OER b0 to b7 SMD2 to SMD0 CKDIR CLK0, CLK1 TXEPT NCH CKPOL UFORM TE TI RE RI UiIRS UiRRM Function Set data transmission. Receive data can be read. Overrun error flag Set the transfer rate. Set to 001b. Select an internal clock or external clock. Select the count source for the UiBRG register. Transmit register empty flag Select the output format of the TXDi pin. Select the transfer clock polarity. Select LSB first or MSB first. Set to 1 to enable transmission/reception Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select the UARTi transmit interrupt source. Set to 1 to use continuous receive mode. UiC1 i = 0 or 1 Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. REJ09B0441-0010 Rev.0.10 Page 503 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) Table 24.4 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. After UARTi (i = 0 or 1) operating mode is selected, the TXDi pin outputs a high-level signal until transfer starts. (When the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 24.4 I/O Pin Functions in Clock Synchronous Serial I/O Mode Pin Name TXD0 (P13_1) RXD0 (P13_2) CLK0 (P13_3) TXD1 (P4_0) RXD1 (P4_1) CLK1 (P4_2) Selection Method TXD0SEL0 bit in U0SR register = 1 For reception only: P13_1 can be used as a port by setting TXD0SEL0 bit = 0. Serial data input Bits RXD0SEL1 and RXD0SEL0 in U0SR register = 01b PD13_2 bit in PD3 register = 0 For transmission only: P13_2 can be used as a port by setting bits RXD0SEL1 to RXD0SEL0 = 00b. Transfer clock output CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 0 Transfer clock input CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 1 PD13_3 bit in PD3 register = 0 Serial data output TXD1SEL0 bit in U1SR register = 1 For reception only: P4_0 can be used as a port by setting TXD1SEL0 bit = 0. Serial data input Bits RXD0SEL1 and RXD0SEL0 in U1SR register = 10b PD4_1 bit in PD4 register = 0 For transmission only: P4_1 can be used as a port by setting bits RXD0SEL1 to RXD0SEL0 = 00b. Transfer clock output CLK1SEL0 bit in U1SR register = 1 CKDIR bit in U1MR register = 0 Transfer clock input CLK1SEL0 bit in U1SR register = 1 CKDIR bit in U1MR register = 0 PD4_2 bit in PD4 register = 0 Function Serial data output REJ09B0441-0010 Rev.0.10 Page 504 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) • Transmit Timing Example (Internal Clock Selected) TC Transfer clock TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 Data set in UiTB register Data transfer from UiTB register to UARTi transmit register TCLK Pulsing stops because TE bit is set to 0. CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TXEPT bit in UiC0 register 1 0 IR bit in SiTIC register 1 0 Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: TC = TCLK = 2(n+1)/fi • CKDIR bit in UiMR register = 0 (internal clock) fi: Frequency of UiBRG count source (f1, f8, f32, fC) • CKPOL bit in UiC0 register = 0 n: Value set in UiBRG register (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) • UiIRS bit in UiC1 register = 0 (interrupt request generation when the transmit buffer is empty) • Receive Timing Example (External Clock Selected) RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 1 0 Data transfer from UiTB register to UARTi transmit register 1/fEXT Dummy data set in UiTB register CLKi Received data capture RXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 RI bit in UiC1 register 1 0 1 0 Data transfer from UARTi receive register to UiRB register Data read from UiRB register IR bit in SiRIC register Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • CKDIR bit in UiMR register = 1 (external clock) • CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) The following should be met when a high-level is applied to the CLKi pin before receiving data: • TE bit in UiC1 register = 1 (transmission enabled) • RE bit in UiC1 register = 1 (reception enabled) • Dummy data write to the UiTB register fEXT: Frequency of external clock i = 0 or 1 Figure 24.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode REJ09B0441-0010 Rev.0.10 Page 505 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.3.1 Polarity Select Function Figure 24.4 shows the Transfer Clock Polarity. The CKPOL bit in the UiC0 (i = 0 or 1) register can be used to select the transfer clock polarity. • CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) CLKi (1) TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 • CKPOL bit in UiC0 register = 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) CLKi (2) TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Notes: 1. The CLKi pin level is high during no transfer. 2. The CLKi pin level is low during no transfer. i = 0 or 1 Figure 24.4 Transfer Clock Polarity 24.3.2 LSB First/MSB First Select Function Figure 24.5 shows the Transfer Format. The UFORM bit in the UiC0 (i = 0 or 1) register can be used to select the transfer format. • UFORM bit in UiC0 register = 0 (LSB first) (1) CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 • UFORM bit in UiC0 register = 1 (MSB first) CLKi (1) TXDi D7 D6 D5 D4 D3 D2 D1 D0 RXDi D7 D6 D5 D4 D3 D2 D1 D0 Note: 1. The above applies under the following condition: CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock). i = 0 or 1 Figure 24.5 Transfer Format REJ09B0441-0010 Rev.0.10 Page 506 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.3.3 Continuous Receive Mode Continuous receive mode is selected by setting the UiRRM bit in the UiC1 register (i = 0 or 1) to 1 (continuous receive mode enabled). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a program. REJ09B0441-0010 Rev.0.10 Page 507 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.4 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data transmission and reception after setting the desired transfer rate and transfer data format. Table 24.5 lists the UART Mode Specifications, and Table 24.6 lists the Registers Used and Settings in UART Mode. Table 24.5 UART Mode Specifications Item Transfer data formats Transfer clocks Transmit start conditions Receive start conditions Interrupt request generation timing Specification • Character bits (transfer data): Selectable from 7, 8 or 9 bits • Start bit: 1 bit • Parity bit: Selectable from odd, even, or none • Stop bits: Selectable from 1 or 2 bits • The CKDIR bit in the UiMR register is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32, fC n = Value set in UiBRG register: 00h to FFh • The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1)) fEXT: Input from CLKi pin, n = Value set in UiBRG register: 00h to FFh • To start transmission, the following requirements must be met: - The TE bit in the UiC1 register is set to 1 (transmission enabled). - The TI bit in the UiC1 register is set to 0 (data in the UiTB register). • To start reception, the following requirements must be met: - The RE bit in the UiC1 register is set to 1 (reception enabled). - Start bit detection • For transmission, one of the following can be selected. - The UiIRS bit is set to 0 (transmit buffer empty): When data is transferred from the UiTB register to the UARTi transmit register (at start of transmission). - The UiIRS bit is set to 1 (transfer completed): When data transmission from the UARTi transmit register is completed. • For reception When data is transferred from the UARTi receive register to the UiRB register (at completion of reception). • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receive the bit one before the last stop bit of the next unit of data. • Framing error This error occurs when the set number of stop bits is not detected. • Parity error This error occurs when parity is enabled, and the number of 1’s in the parity and character bits do not match the set number of 1’s. • Error sum flag This flag is set is set to 1 if an overrun, framing, or parity error occurs. Error detection i = 0 or 1 Note: 1. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. REJ09B0441-0010 Rev.0.10 Page 508 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) Table 24.6 Registers Used and Settings in UART Mode Register UiTB UiRB UiBRG UiMR Bit b0 to b8 b0 to b8 Set transmit data. (1) Function UiC0 UiC1 Receive data can be read. (2) OER, FER, PER, SUM Error flag b0 to b7 Set the transfer rate. SMD2 to SMD0 Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Set to 110b when transfer data is 9 bits long. CKDIR Select an internal clock or external clock. STPS Select the stop bit(s). PRY, PRYE Select whether parity is included and whether odd or even. CLK0, CLK1 Select the count source for the UiBRG register. TXEPT Transmit register empty flag NCH Select the output format of the TXDi pin. CKPOL Set to 0. UFORM Select LSB first or MSB first when transfer data is 8 bits long. Set to 0 when transfer data is 7 bits or 9 bits long. TE Set to 1 to enable transmission. TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Reception complete flag UiIRS Select the UARTi transmit interrupt source. UiRRM Set to 0. i = 0 or 1 Notes: 1. The bits used for transmission/receive data are as follows: - Bits b0 to b6 when transfer data is 7 bits long - Bits b0 to b7 when transfer data is 8 bits long - Bits b0 to b8 when transfer data is 9 bits long 2. The contents of the following are undefined: - Bits b7 and b8 when the transfer data is 7 bits long - Bit b8 when the transfer data is 8 bits long REJ09B0441-0010 Rev.0.10 Page 509 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) Table 24.7 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the TXDi pin outputs a high-level signal until transfer starts. (When the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 24.7 I/O Pin Functions in UART Mode Pin name TXD0 (P13_1) RXD0 (P13_2) CLK0 (P13_3) TXD1 (P4_0) RXD1 (P4_1) CLK1 (P4_2) Selection Method TXD0SEL0 bit in U0SR register = 1 For reception only: P13_1 can be used as a port by setting TXD0SEL0 bit = 0. Serial data input RXD0SEL0 bit in U0SR register = 1 PD13_2 bit in PD3 register = 0 For transmission only: P13_2 can be used as a port by setting RXD0SEL0 bit = 0. Programmable I/O port CLK0SEL0 bit in U0SR register = 0 (CLK0 pin not used) Transfer clock input CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 1 PD13_3 bit in PD3 register = 0 Serial data output TXD1SEL0 bit in U1SR register = 1 For reception only: P4_0 can be used as a port by setting TXD1SEL0 bit = 0. Serial data input RXD1SEL0 bit in U1SR register = 1 PD4_1 bit in PD4 register = 0 For transmission only: P4_1 can be used as a port by setting RXD1SEL0 bit = 0. Programmable I/O port CLK1SEL0 bit in U1SR register = 0 (CLK1 pin not used) Transfer clock input CLK1SEL0 bit in U1SR register = 1 CKDIR bit in U1MR register = 0 PD4_2 bit in PD4 register = 0 Function Serial data output REJ09B0441-0010 Rev.0.10 Page 510 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) • Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) TC Transfer clock TE bit in 1 UiC1 register 0 Data set in UiTB register TI bit in 1 UiC1 register 0 Data transfer from UiTB register to UARTi transmit register Start bit Parity Stop bit bit Pulsing stops because TE bit is set to 0. TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 TXEPT bit in 1 UiC0 register 0 IR bit in 1 SiTIC register 0 Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • PRYE bit in UiMR register = 1 (parity enabled) • STPS bit in UiMR register = 0 (one stop bit) • UiIRS bit in UiC1 register = 1 (interrupt request generation when transmission is completed) TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32, fC) fEXT: Frequency of UiBRG count source (external clock) n: Value set in UiBRG register i = 0 or 1 • Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits) TC Transfer clock TE bit in UiC1 register TI bit in UiC1 register 1 0 Data set in UiTB register 1 0 Data transfer from UiTB register to UARTi transmit register Start bit Stop Stop bit bit TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 TXEPT bit in UiC0 register 1 0 IR bit in 1 SiTIC register 0 Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • PRYE bit in UiMR register = 0 (parity disabled) • STPS bit in UiMR register = 1 (two stop bits) • UiIRS bit in UiC1 register = 0 (interrupt request generation when the transmit buffer is empty) TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32, fC) fEXT: Frequency of UiBRG count source (external clock) n: Value set in UiBRG register i = 0 or 1 Figure 24.6 Transmit Timing in UART Mode REJ09B0441-0010 Rev.0.10 Page 511 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) • Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit) UiBRG output RE bit in UiC1 register RXDi 1 0 Stop bit Start bit D0 D1 D7 “L” is determined. Transfer clock Received data capture Reception starts when a transfer clock is generated at the falling edge of the start bit. RI bit in UiC1 register IR bit in SiRIC register 1 0 1 0 Data transfer from UARTi receive register to UiRB register Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • PRYE bit in UiMR register = 0 (parity disabled) • STPS bit in UiMR register = 0 (one stop bit) i = 0 or 1 Figure 24.7 Receive Timing in UART Mode REJ09B0441-0010 Rev.0.10 Page 512 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.4.1 Bit Rate In UART mode, the bit rate is the frequency (divided by the UiBRG register (i = 0 or 1)) divided by 16. UART mode • Internal clock selected Setting value of UiBRG register = fj Bit rate × 16 −1 fj: Count source frequency of UiBRG register (f1, f8, f32, or fC) • External clock selected Setting value of UiBRG register = fEXT Bit rate × 16 −1 fEXT: Count source frequency of UiBRG register (external clock) i = 0 or 1 Figure 24.8 Formula for Calculating Setting Value of UiBRG Register (i = 0 or 1) Table 24.8 Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 38400 57600 115200 Bit Rate Setting Example in UART Mode (Internal Clock Selected) System Clock = 20 MHz UiBRG Setting Actual Time Setting Error (bps) Value (%) 129 (81h) 1201.92 0.16 64 (40h) 2403.85 0.16 32 (20h) 4734.85 -1.36 129 (81h) 9615.38 0.16 86 (56h) 14367.82 -0.22 64 (40h) 19230.77 0.16 42 (2Ah) 29069.77 0.94 32 (20h) 37878.79 -1.36 21 (15h) 56818.18 -1.36 10 (0Ah) 113636.36 -1.36 System Clock = 18.432 MHz (1) UiBRG Setting Actual Time Setting Error (bps) Value (%) 119 (77h) 1200.00 0.00 59 (3Bh) 2400.00 0.00 29 (1Dh) 4800.00 0.00 119 (77h) 9600.00 0.00 79 (4Fh) 14400.00 0.00 59 (3Bh) 19200.00 0.00 39 (27h) 28800.00 0.00 29 (1Dh) 38400.00 0.00 19 (13h) 57600.00 0.00 9 (09h) 115200.00 0.00 System Clock = 8 MHz UiBRG Actual Setting Setting Time Error Value (bps) (%) 51 (33h) 1201.92 0.16 25 (19h) 2403.85 0.16 12 (0Ch) 4807.69 0.16 51 (33h) 9615.38 0.16 34 (22h) 14285.71 -0.79 25 (19h) 19230.77 0.16 16 (10h) 29411.76 2.12 12 (0Ch) 38461.54 0.16 8 (08h) 55555.56 -3.55 − − − UiBRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 i = 0 or 1 Note: 1. For the high-speed on-chip oscillator, the correction value of the FRA4 register should be written into the FRA1 register and the correction value of the FRA5 register should be written into the FRA3 register. This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in the FRA2 register are set to 000b (divide-by-2 mode). REJ09B0441-0010 Rev.0.10 Page 513 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) 24.5 Notes on Serial Interface (UARTi (i = 0 or 1)) • When reading data from the UiRB (i = 0 or 1) register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Program example to read the receive buffer register: MOV.W 00A6H,R0 ; Read the U0RB register • When writing data to the UiTB register in clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first and then the low-order byte, in 8-bit units. Program example to write to the transmit buffer register: MOV.B #XXH,00A3H ; Write to the high-order byte of the U0TB register MOV.B #XXH,00A2H ; Write to the low-order byte of the U0TB register REJ09B0441-0010 Rev.0.10 Page 514 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25. Serial Interface (UART2) The serial interface consists of three channels, UART0 to UART2. This chapter describes UART2. 25.1 Introduction UART2 has a dedicated timer to generate a transfer clock and operate independently. Figure 25.1 shows a Block Diagram of UART2. Figure 25.2 shows a Block Diagram of UART2 Transmit/Receive Unit. Table 25.1 lists the UART 2 Pin Configuration. UART2 supports the following modes: • • • • Clock synchronous serial I/O mode Clock asynchronous serial I/O mode (UART mode) Special mode 1 (I2C mode) Multiprocessor communication function DF2EN = 1 RXD2 DF2EN = 0 Digital filter RXD polarity switch circuit 1/16 UART reception SMD2 to SMD0 Receive clock TXD polarity switch circuit TXD2 Clock source selection CLK1 to CLK0 f1 f8 f32 fC = 00b = 01b = 10b = 11b CKDIR CKDIR internal =0 = 010b, 100b, 101b, 110b = 001b Reception control circuit U2BRG register Clock synchronous type 1/16 UART transmission = 010b, 100b, 101b, 110b = 001b Transmit/ receive unit 1/(n+1) CKDIR =1 CKDIR external Transmission control circuit Transmit clock Clock synchronous type Clock synchronous type (internal clock selected) 1/2 CKDIR = 0 CKDIR = 1 CKPOL CLK Clock synchronous type (internal clock selected) Clock synchronous type (external clock selected) CLK2 polarity switch circuit CTS/RTS disabled CTS/RTS selected RTS2 CTS/RTS disabled CRD = 0 CRD = 1 CTS2/RTS2 CRS = 1 CRS = 0 CTS2 VSS SMD0 to SMD2, CKDIR: Bits in U2MR register CLK0, CLK1, CKPOL, CRD, CRS: Bits in U2C0 register DF2EN: Bit in URXDF register n: Value set in U2BRG register Figure 25.1 Block Diagram of UART2 REJ09B0441-0010 Rev.0.10 Page 515 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) RXD2 RXD data inversion circuit Not inverted IOPOL = 0 IOPOL = 1 Inverted Clock synchronous type 1SP STPS = 0 PAR Clock disabled synchronous PRYE = 0 type I2 C UART (7 bits) UART (8 bits) UART (7 bits) UART2 receive register SP STPS = 1 SP 2SP PAR PRYE = 1 PAR enabled UART I2C UART (9 bits) I2 C Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 U2RB register Logic inversion circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic inversion circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 U2TB register UART (8 bits) UART (9 bits) I2 C 2SP STPS = 1 PAR enabled UART PRYE = 1 SMD = 1 UART (9 bits) I2 C Clock synchronous type SP SP STPS = 0 PAR 1SP SMD = 0 PRYE = 0 I2 C PAR Clock disabled UART2 transmit register UART (7 bits) UART (8 bits) synchronous type UART (7 bits) Error signal output disabled Not inverted IOPOL = 0 U2ERE = 0 Clock synchronous type TXD2 SP: Stop bit PAR: Parity bit SMD0 to SMD2, STPS, PRYE, IOPOL, CKDIR: Bits in U2MR register CLK0, CLK1, CKPOL, CRD, CRS: Bits in U2C0 register U2ERE: Bit in U2C1 register U2ERE = 1 IOPOL = 1 Inverted Error signal output enabled Error signal output circuit TXD data inversion circuit Figure 25.2 Block Diagram of UART2 Transmit/Receive Unit Table 25.1 UART 2 Pin Configuration Pin Name Assigned Pin TXD2 P11_1, P11_2 RXD2 P11_1, P11_2 CLK2 P11_0 P11_3 CTS2 RTS2 SCL2 SDA2 P11_3 P11_1, P11_2 P11_1, P11_2 I/O Output Input I/O Input Output I/O I/O Function Serial data output Serial data input Transfer clock I/O Transmission control input Reception control input I2C mode clock I/O I2C mode data I/O REJ09B0441-0010 Rev.0.10 Page 516 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2 25.2.1 Registers UART2 Transmit/Receive Mode Register (U2MR) b6 PRYE 0 b5 PRY 0 b4 STPS 0 b3 CKDIR 0 b2 SMD2 0 b1 SMD1 0 Function b2 b1 b0 Address 00A8h Bit b7 Symbol IOPOL After Reset 0 Bit b0 b1 b2 Symbol SMD0 SMD1 SMD2 b0 SMD0 0 R/W R/W R/W R/W Bit Name Serial I/O mode select bit b3 b4 b5 CKDIR STPS PRY Internal/external clock select bit Stop bit length select bit Odd/even parity select bit b6 b7 PRYE IOPOL Parity enable bit TXD, RXD I/O polarity switch bit 0 0 0: Serial interface disabled 0 0 1: Clock synchronous serial I/O mode 0 1 0: I2C mode 1 0 0: UART mode, transfer data 7 bits long 1 0 1: UART mode, transfer data 8 bits long 1 1 0: UART mode, transfer data 9 bits long Other than above: Do not set. 0: Internal clock 1: External clock 0: One stop bit 1: Two stop bits Enabled when PRYE = 1 0: Odd parity 1: Even parity 0: Parity disabled 1: Parity enabled 0: Not inverted 1: Inverted R/W R/W R/W R/W R/W 25.2.2 UART2 Bit Rate Register (U2BRG) b6 — X b5 — X b4 — X b3 — X b2 — X b1 — X b0 — X Setting Range 00h to FFh R/W W Address 00A9h Bit b7 Symbol — After Reset X Bit Function b7 to b0 If the setting value is n, U2BRG divides the count source by n+1. Write to the U2BRG register while transmission and reception stop. Use the MOV instruction to write to this register. Set bits CLK1 to CLK0 in the U2C0 register before writing to the U2BRG register. REJ09B0441-0010 Rev.0.10 Page 517 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.3 UART2 Transmit Buffer Register (U2TB) b5 — X b13 — X b4 — X b12 — X b3 — X b11 — X b2 — X b10 — X b1 — X b9 — X b0 — X b8 MPTB X R/W W Address 00ABh to 00AAh Bit b7 b6 Symbol — — After Reset X X Bit Symbol After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 b8 b15 — X b14 — X Symbol — — — — — — — — MPTB Function Transmit data (D7 to D0) b9 b10 b11 b12 b13 b14 b15 — — — — — — — Transmit data (D8) (1) [When the multiprocessor communication function is not used] Transmit data (D8) [When the multiprocessor communication function is used] • To transfer an ID, set the MPTB bit to 1. • To transfer data, set the MPTB bit to 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. W — Note: 1. Set bits b0 to b7 after setting the MPTB bit. REJ09B0441-0010 Rev.0.10 Page 518 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.4 UART2 Transmit/Receive Control Register 0 (U2C0) b6 CKPOL 0 b5 NCH 0 b4 CRD 0 b3 TXEPT 1 b2 CRS 0 b1 CLK1 0 Function b1 b0 Address 00ACh Bit b7 Symbol UFORM After Reset 0 Bit b0 b1 Symbol CLK0 CLK1 b0 CLK0 0 R/W R/W R/W Bit Name U2BRG count source select bit (1) b2 CRS CTS/RTS function select bit b3 TXEPT Transmit register empty flag 0 0: f1 selected 0 1: f8 selected 1 0: f32 selected 1 1: fC selected Enabled when CRD = 0 0: CTS function selected 1: RTS function selected 0: Data in the transmit register (transmission in progress) 1: No data in the transmit register (transmission completed) 0: CTS/RTS function enabled 1: CTS/RTS function disabled 0: Pins TXD2/SDA2, SCL2 set as CMOS output 1: Pins TXD2/SDA2, SCL2 set as N-channel open-drain output 0: Transmit data output at the falling edge and receive data input at the rising edge of the transfer clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the transfer clock 0: LSB first 1: MSB first R/W R b4 b5 CRD NCH CTS/RTS disable bit Data output select bit R/W R/W b6 CKPOL CLK polarity select bit R/W b7 UFORM Transfer format select bit (2) R/W Notes: 1. If bits CLK1 to CLK0 are switched, set the U2BRG register again. 2. The UFORM bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), or set to 101b (UART mode, transfer data 8 bits long). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I2C mode), and to 0 when bits SMD2 to SMD0 are set to 100b (UART mode, transfer data 7 bits long) or 110b (UART mode, transfer data 9 bits long). REJ09B0441-0010 Rev.0.10 Page 519 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.5 UART2 Transmit/Receive Control Register 1 (U2C1) b6 U2LCH 0 b5 U2RRM 0 b4 U2IRS 0 b3 RI 0 b2 RE 0 b1 TI 1 b0 TE 0 R/W R/W R R/W R R/W R/W R/W R/W Address 00ADh Bit b7 Symbol U2ERE After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol TE TI RE RI U2IRS Bit Name Transmission enable bit Transmit buffer empty flag Reception enable bit Reception complete flag UART2 transmit interrupt source select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit (1) U2ERE Error signal output enable bit Function 0: Transmission disabled 1: Transmission enabled 0: Data in the U2TB register 1: No data in the U2TB register 0: Reception disabled 1: Reception enabled 0: No data in the U2RB register 1: Data in the U2RB register 0: Transmit buffer empty (TI = 1) 1: Transmission completed (TXEPT = 1) 0: Continuous receive mode disabled 1: Continuous receive mode enabled 0: Not inverted 1: Inverted 0: Output disabled 1: Output enabled Note: 1. The U2LCH bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), 100b (UART mode, transfer data 7 bits long), or 101b (UART mode, transfer data 8 bits long). Set the U2LCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, transfer data 9 bits long). REJ09B0441-0010 Rev.0.10 Page 520 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.6 UART2 Receive Buffer Register (U2RB) b5 — X b13 FER X b4 — X b12 OER X b3 — X b11 ABT X b2 — X b10 — X b1 — X b9 — X Function Receive data (D7 to D0) b0 — X b8 MPRB X R/W R Address 00AFh to 00AEh Bit b7 b6 Symbol — — After Reset X X Bit Symbol After Reset Bit b0 b1 b2 b3 b4 b5 b6 b7 b8 b15 SUM X b14 PER X Symbol — — — — — — — — MPRB Bit Name — — b9 b10 b11 b12 b13 b14 b15 — — ABT OER FER PER SUM Receive data (D8) (2) [When the multiprocessor communication function is not used] Receive data (D8) [When the multiprocessor communication function is used] • When the MPRB bit is set to 0, received D0 to D7 are data fields. • When the MPRB bit is set to 1, received D0 to D7 are ID fields. Nothing is assigned. If necessary, set to 0. When read, the content is 0. R — R R R R R Arbitration lost detect flag (1) 0: Not detected (won) 1: Detected (lost) (2) 0: No overrun error Overrun error flag 1: Overrun error 0: No framing error Framing error flag (2, 3) 1: Framing error 0: No parity error Parity error flag (2, 3) 1: Parity error 0: No error Error sum flag (2, 3) 1: Error Notes: 1. The ABT bit is set to 0 by writing 0 by a program. (Writing 1 has no effect.) 2. When bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled) or the RE bit in the U2C1 register is set to 0 (reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 by reading the lower byte of the U2RB register. 3. These error flags are disabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or to 010b (I2C mode). When read, the contents are undefined. REJ09B0441-0010 Rev.0.10 Page 521 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.7 UART2 Digital Filter Function Select Register (URXDF) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 DF2EN 0 b1 — 0 b0 — 0 R/W — R/W — Address 00B0h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — DF2EN RXD2 digital filter enable bit (1) 0: RXD2 digital filter disabled 1: RXD2 digital filter enabled — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — — Note: 1. The RXD2 digital filter can be used only in clock asynchronous serial I/O (UART) mode. When bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or 010b (I2C mode), set the DF2EN bit to 0 (RXD2 digital filter disabled). 25.2.8 UART2 Special Mode Register 5 (U2SMR5) b6 — 0 b5 — 0 b4 MPIE 0 b3 — 0 b2 — 0 b1 — 0 b0 MP 0 R/W R/W — Address 00BBh Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function MP Multiprocessor communication 0: Multiprocessor communication disabled enable bit 1: Multiprocessor communication enabled (1) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — MPIE Multiprocessor communication When the MP bit is set to 1 (multiprocessor control bit communication enabled), this bit is enabled. When the MPIE bit is set to 1, the following will result: • Receive data in which the multiprocessor bit is 0 is ignored. The settings of the RI bit in the U2C1 register and bits OER and FER in the U2RB register to 1 are disabled. • On receiving receive data in which the multiprocessor bit is 1, the MPIE bit is set to 0 and receive operation other than multiprocessor communication is performed. — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — Reserved bit Set to 0. R/W — R/W Note: 1. When the MP bit is set to 1 (multiprocessor communication enabled), the settings of bits PRY and PRYE in the U2MR register are disabled. If bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), set the MP bit to 0 (multiprocessor communication disabled). REJ09B0441-0010 Rev.0.10 Page 522 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.9 UART2 Special Mode Register 4 (U2SMR4) b6 SCLHI 0 b5 ACKC 0 b4 ACKD 0 b3 b2 b1 b0 STSPSEL STPREQ RSTAREQ STAREQ 0 0 0 0 Function 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start 0: Start and stop conditions not output 1: Start and stop conditions output 0: ACK 1: NACK 0: Serial interface data output 1: ACK data output 0: Disabled 1: Enabled 0: SCL hold low disabled 1: SCL hold low enabled R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 00BCh Bit b7 Symbol SWC9 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name STAREQ Start condition generate bit (1) RSTAREQ Restart condition generate bit (1) STPREQ Stop condition generate bit (1) STSPSEL SCL, SDA output select bit ACKD ACKC SCLHI SWC9 ACK data bit ACK data output enable bit SCL output stop enable bit SCL wait bit 3 Note: 1. This bit is set to 0 when the condition is generated. 25.2.10 UART2 Special Mode Register 3 (U2SMR3) Address 00BDh Bit b7 Symbol DL2 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 DL1 0 b5 DL0 0 b4 — X b3 NODC 0 b2 — X b1 CKPH 0 b0 — X R/W — R/W — R/W — R/W R/W R/W Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. CKPH Clock phase set bit 0: No clock delay 1: With clock delay — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NODC Clock output select bit 0: CLK2 set as CMOS output 1: CLK2 set as N-channel open-drain output — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. b7 b6 b5 DL0 SDA2 digital delay setup bit (1, 2) 0 0 0: No delay DL1 0 0 1: 1 or 2 cycles of U2BRG count source DL2 0 1 0: 2 or 3 cycles of U2BRG count source 0 1 1: 3 or 4 cycles of U2BRG count source 1 0 0: 4 or 5 cycles of U2BRG count source 1 0 1: 5 or6 cycles of U2BRG count source 1 1 0: 6 or 7 cycles of U2BRG count source 1 1 1: 7 or 8 cycles of U2BRG count source Notes: 1. Bits DL2 to DL0 are used to generate a delay in SDA2 output digitally in I2C mode. In other than I2C mode, set these bits to 000b (no delay). 2. The amount of delay varies with the load on pins SCL2 and SDA2. When an external clock is used, the amount of delay increases by about 100 ns. REJ09B0441-0010 Rev.0.10 Page 523 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.11 UART2 Special Mode Register 2 (U2SMR2) Address 00BEh Bit b7 Symbol — After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 SDHI 0 b5 SWC2 0 b4 STAC 0 b3 ALS 0 b2 SWC 0 b1 CSC 0 b0 IICM2 0 R/W R/W R/W R/W R/W R/W R/W R/W — Symbol Bit Name IICM2 I2C mode select bit 2 CSC Clock synchronization bit SWC ALS STAC SWC2 SDHI — Function Refer to Table 25.12 I2C Mode Functions. 0: Disabled 1: Enabled SCL wait output bit 0: Disabled 1: Enabled SDA output stop bit 0: Disabled 1: Enabled UART2 initialization bit 0: Disabled 1: Enabled SCL wait output bit 2 0: Transfer clock 1: Low-level output SDA output disable bit 0: Enabled 1: Disabled (high impedance) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. 25.2.12 UART2 Special Mode Register (U2SMR) Address 00BFh Bit b7 Symbol — After Reset X Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 SSS 0 b5 ACSE 0 b4 ABSCS 0 b3 — 0 b2 BBS 0 b1 ABC 0 Function mode b0 IICM 0 R/W R/W R/W R/W R/W R/W R/W R/W — 0: Other than 1: I2C mode ABC Arbitration lost detection flag 0: Update per bit control bit 1: Update per byte (1) BBS 0: Stop condition detected Bus busy flag 1: Start condition detected (busy) — Reserved bit Set to 0. ABSCS Bus collision detection sampling clock 0: Rising edge of transfer clock select bit 1: Underflow signal of Timer RA (2) ACSE Auto clear function select bit of 0: No auto clear function transmission enable bit 1: Auto clear at bus collision occurrence SSS Transmit start condition select bit 0: Not synchronized to RXD2 1: Synchronized to RXD2 (2) — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Symbol Bit Name 2C mode select bit IICM I I2C Notes: 1. The BBS bit is set to 0 by writing 0 by a program (Writing 1 has no effect). 2. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXD2). REJ09B0441-0010 Rev.0.10 Page 524 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.13 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Bit b7 Symbol — After Reset 0 Bit b0 b1 b6 — 0 b5 b4 RXD2SEL1 RXD2SEL0 0 0 b3 — 0 b2 — 0 b1 b0 TXD2SEL1 TXD2SEL0 0 0 Function b1 b0 Symbol Bit Name TXD2SEL0 TXD2/SDA2 pin select bit TXD2SEL1 b2 b3 b4 b5 — — RXD2SEL0 RXD2/SCL2 pin select bit RXD2SEL1 0 0: TXD2/SDA2 pin not used 0 1: P11_2 assigned 1 0: P11_1 assigned 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. b5 b4 R/W R/W R/W — R/W R/W b6 b7 — — 0 0: RXD2/SCL2 pin not used 0 1: P11_1 assigned 1 0: P11_2 assigned 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — The U2SR0 register selects which pin is assigned as the UART2 input/output. To use the I/O pins for UART2, set this register. Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. REJ09B0441-0010 Rev.0.10 Page 525 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.2.14 UART2 Pin Select Register 1 (U2SR1) Address 018Bh Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 — 0 b5 — 0 b4 CTS2SEL0 0 b3 — 0 b2 — 0 b1 — 0 b0 CLK2SEL0 0 R/W R/W — Symbol Bit Name CLK2SEL0 CLK2 pin select bit — — — CTS2SEL0 CTS2/RTS2 pin select bit — — — Function 0: CLK2 pin not used 1: CLK2 pin used Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0: CTS2/RTS2 pin not used 0: CTS2/RTS2 pin used Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W — The U2SR1 register selects which pin is assigned as the UART2 input/output. To use the I/O pins for UART2, set this register. Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. REJ09B0441-0010 Rev.0.10 Page 526 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.3 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 25.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 25.3 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode. Table 25.2 Clock Synchronous Serial I/O Mode Specifications Specification Transfer data length: 8 bits • The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1)) fj = f1, f8, f32, fC n = Value set in U2BRG register: 00h to FFh • The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin Selectable from the CTS function, RTS function, or CTS/RTS function disabled. To start transmission, the following requirements must be met: (1) • The TE bit in the U2C1 register is set to 1 (transmission enabled) • The TI bit in the U2C1 register is set to 0 (data in the U2TB register) • If the CTS function is selected, input to the CTS2 pin is low. To start reception, the following requirements must be met: (1) • The RE bit in the U2C1 register is set to 1 (reception enabled). • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). For transmission, one of the following conditions can be selected. • The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty): When data is transferred from the U2TB register to the UART2 transmit register (at start of transmission). • The U2IRS bit is set to 1 (transmission completed): When data transmission from the UART2 transmit register is completed. For reception • When data is transferred from the UART2 receive register to the U2RB register (at completion of reception). Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives the 7th bit of the next unit of data. • CLK polarity selection Transfer data I/O can be selected to occur synchronously with the rising or falling edge of the transfer clock. • LSB first, MSB first selection Whether data transmission/reception begins with bit 0 or begins with bit 7 can be selected. • Continuous receive mode selection Receive operation is enabled immediately by reading the U2RB register. • Serial data logic switching This function inverts the logic value of transmit/receive data. Item Transfer data format Transfer clock Transmission/reception control Transmit start conditions Receive start conditions Interrupt request generation timing Error detection Selectable functions Notes: 1. If an external clock is selected, the requirements must be met in either of the following states: - The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) - The external clock is held low when the CKPOL bit in the U2C0 register is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) 2. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC register does not change to 1 (interrupt requested). REJ09B0441-0010 Rev.0.10 Page 527 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register U2TB (1) Bit b0 to b7 b0 to b7 OER b0 to b7 SMD2 to SMD0 CKDIR IOPOL CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2RRM U2LCH U2ERE b0 to b7 b0 to b7 b0 to b2 NODC b4 to b7 b0 to b7 DF2EN MP Set transmit data. Function Receive data can be read. Overrun error flag Set the transfer rate. Set to 001b. Select an internal clock or external clock. Set to 0. Select the count source for the U2BRG register. Select either CTS or RTS to use the function. Transmit register empty flag Select the CTS or RTS function enabled or disabled. Select the output format of the TXD2 pin. Select the transfer clock polarity. Select LSB first or MSB first. Set to 1 to enable transmission/reception. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select the UART2 transmit interrupt source Set to 1 to use continuous receive mode. Set to 1 to use inverted data logic. Set to 0. Set to 0. Set to 0. Set to 0. Select the clock output format. Set to 0. Set to 0. Set to 0. Set to 0. U2RB (1) U2BRG U2MR (1) U2C0 U2C1 U2SMR U2SMR2 U2SMR3 U2SMR4 URXDF U2SMR5 Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. REJ09B0441-0010 Rev.0.10 Page 528 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.4 lists the Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output Pin Function Not Selected). After UART2 operating mode is selected, the TXD2 pin outputs a high-level signal until transfer starts. (When N-channel open-drain output is selected, this pin is in the high-impedance state.) Figure 25.3 shows the Transmit and Receive Timing in Clock Synchronous Serial I/O Mode. Table 25.4 Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output Pin Function Not Selected) Pin Name Function TXD2 Serial data output (P11_1 or P11_2) Selection Method • When TXD2 (P11_1) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 10b (P11_1) • When TXD2 (P11_2) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 01b (P11_2) • For reception only: P11_1 and P11_2 can be used as ports by setting TXD2SEL1 to TXD2SEL0 to 00b. • When RXD2 (P11_1) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P11_1) PD11_1 bit in PD11 register = 0 • When RXD2 (P11_2) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P11_2) PD11_2 bit in PD11 register = 0 • For transmission only: P11_1 and P11_2 can be used as ports by setting RXD2SEL1 to RXD2SEL0 to 00b. RXD2 Serial data input (P11_1 or P11_2) CLK2 (P11_0) CTS2/RTS2 (P11_3) Transfer clock output CLK2SEL0 bit in U2SR1 register = 1 CKDIR bit in U2MR register = 0 Transfer clock input CLK2SEL0 bit in U2SR1 register = 1 CKDIR bit in U2MR register = 1 PD11_0 bit in PD11 register = 0 CTS2SEL0 bit in U2SR1 register = 1 CTS input CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 0 PD11_3 bit in PD11 register = 0 CTS2SEL0 bit in U2SR1 register = 1 RTS output CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 1 I/O port CTS2SEL0 bit in U2SR1 register = 0 REJ09B0441-0010 Rev.0.10 Page 529 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) (1) Transmit Timing Example (Internal Clock Selected) TC Transfer clock TE bit in U2C1 register TI bit in U2C1 register CTS2 1 0 1 0 “H” “L” Data transfer from U2TB register to UART2 transmit register Data set in U2TB register TCLK Pulsing stops because CTS2 is “H”. Pulsing stops because TE bit is set to 0. CLK2 TXD2 TXEPT flag in U2C0 register IR bit in S2TIC register 1 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • CKDIR bit in U2MR register = 0 (internal clock) • CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected) • CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) • U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty) TC = TCLK = 2(n+1)/fj fj: Frequency of U2BRG count source (f1, f8, f32, fC) n: Value set in U2BRG register (2) Receive Timing Example (External Clock Selected) RE bit in U2C1 register TE bit in U2C1 register TI bit in U2C1 register RTS2 CLK2 Received data capture 1 0 1 0 1 0 “H” “L” Data transfer from U2TB register to UART2 transmit register Dummy data set in U2TB register 1/fEXT “L” by reading U2RB register RXD2 RI bit in U2C1 register IR bit in S2RIC register D0 D1 D2 D3 D4 D5 D6 D7 Data transfer from UART2 receive register 1 to U2RB register 0 1 0 D0 D1 D2 D3 D4 D5 D6 Data read from U2RB register D7 D0 D1 D2 D3 D4 D5 D6 Set to 0 when an interrupt request is acknowledged or by a program. OER flag in U2RB register 1 0 Make sure the following conditions are met when the CLK2 pin input is high before receiving data: • TE bit in U2C0 register = 1 (transmission enabled) • RE bit in U2C1 register = 1 (reception enabled) • Dummy data write to the U2TB register The above applies under the following conditions: • CKDIR bit in U2MR register = 1 (external clock) • CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected) • CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) fEXT: Frequency of external clock Figure 25.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode REJ09B0441-0010 Rev.0.10 Page 530 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.3.1 Measure for Dealing with Communication Errors If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below: • Resetting the U2RB register (1) Set the RE bit in the U2C1 register to 0 (reception disabled). (2) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode). (4) Set the RE bit in the U2C1 register to 1 (reception enabled). • Resetting the U2TB register (1) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled). (2) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode). (3) Write 1 to the TE bit in the U2C1 register (transmission enabled), regardless of the TE bit value of the U2C2 register. 25.3.2 CLK Polarity Select Function The CKPOL bit in the U2C0 register can be used to select the transfer clock polarity. Figure 25.4 shows the Transfer Clock Polarity. (1) CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) CLK2 TXD2 RXD2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 High-level output from the CLK2 pin during no transfer D7 D7 (2) CKPOL bit in U2C0 register = 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) Low-level output from the CLK2 pin during no transfer CLK2 TXD2 RXD2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 The above applies under the following conditions: • UFORM bit in U2C0 register = 0 (LSB first) • U2LCH bit in U2C1 register = 0 (not inverted) Figure 25.4 Transfer Clock Polarity REJ09B0441-0010 Rev.0.10 Page 531 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.3.3 LSB First/MSB First Select Function The UFORM bit in the U2C0 register can be used to select the transfer format. Figure 25.5 shows the Transfer Format. (1) UFORM Bit in U2C0 Register = 0 (LSB first) CLK2 TXD2 RXD2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (2) UFORM Bit in U2C0 Register = 1 (MSB first) CLK2 TXD2 RXD2 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 The above applies under the following conditions: • CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) • U2LCH bit in U2C1 register = 0 (not inverted) Figure 25.5 Transfer Format 25.3.4 Continuous Receive Mode In continuous receive mode, receive operation is enabled by reading the receive buffer register. If this mode is selected, writing dummy data to the transmit buffer register is not required to enable receive operation. However, a dummy reading of the receive buffer register is required when starting transmission. When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register is set to 0 (data in the U2TB register) by reading the U2RB register. When the U2RRM bit is set to 1, do not write dummy data to the U2TB register by a program. REJ09B0441-0010 Rev.0.10 Page 532 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.3.5 Serial Data Logic Switching Function When the U2LCH bit in the U2C1 register is set to 1 (inverted), the data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received data has its logic inverted when read from the U2RB register. Figure 25.6 shows the Serial Data Logic Switching. (1) U2LCH Bit in U2C1 Register = 0 (not inverted) Transfer Clock TXD2 (not inverted) “H” “L” “H” “L” D0 D1 D2 D3 D4 D5 D6 D7 (2) U2LCH Bit in U2C1 Register = 1 (inverted) Transfer Clock TXD2 (inverted) “H” “L” “H” “L” D0 D1 D2 D3 D4 D5 D6 D7 The above applies under the following conditions: • CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock) • UFORM bit in U2C0 register = 0 (LSB first) Figure 25.6 Serial Data Logic Switching REJ09B0441-0010 Rev.0.10 Page 533 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.3.6 CTS/RTS Function The CTS function is used to start transmit and receive operation when a low-level signal is applied to the CTS2/RTS2 pin. Transmit and receive operation begins when the CTS2/RTS2 pin is held low. If the input level is switched to high during a transmit or receive operation, the operation stops before the next data. For the RTS function, the CTS2/RTS2 pin outputs a low-level signal when the MCU is ready for a receive operation. The output level goes high at the first falling edge of the CLK2 pin. • The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled) The CTS2/RTS2 pin operates as the programmable I/O function. • The CRD bit = 0, CRS bit = 0 (CTS function selected) The CTS2/RTS2 pin operates as the CTS function. • The CRD bit = 0, CRS bit = 1 (RTS function selected) The CTS2/RTS2 pin operates as the RTS function. REJ09B0441-0010 Rev.0.10 Page 534 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.4 Clock Asynchronous Serial I/O (UART) Mode In UART mode, data is transmitted and received after setting the desired transfer rate and transfer data format. Table 25.5 lists the UART Mode Specifications. Table 25.6 lists the Registers Used and Settings in UART Mode. Table 25.5 UART Mode Specifications Specification • Character bits (transfer data): Selectable from 7, 8, or 9 bits • Start bit:1 bit • Parity bit: Selectable from odd, even, or none • Stop bits: Selectable from 1 bit or 2 bits • The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1)) fj = f1, f8, f32, fC n = Value set in U2BRG register: 00h to FFh • The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1)) fEXT: Input from CLK2 pin n: Value set in U2BRG register: 00h to FFh Item Transfer data format Transfer clock Transmission/reception control Selectable from the CTS function, RTS function, or CTS/RTS function disabled. Transmit start conditions To start transmission, the following requirements must be met: • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). • If the CTS function is selected, input to the CTS2 pin is low. Receive start conditions To start reception, the following requirements must be met: • The RE bit in the U2C1 register is set to 1 (reception enabled). • Start bit detection Interrupt request generation For transmission, one of the following conditions can be selected. timing • The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty): When data is transferred from the U2TB register to the UART2 transmit register (at start of transmission). • The U2IRS bit is set to 1 (transmission completed): When data transmission from the UART2 transmit register is completed. For reception • When data is transferred from the UART2 receive register to the U2RB register (at completion of reception). Error detection • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives the bit one before the last stop bit of the next unit of data. • Framing error (2) This error occurs when the set number of stop bits is not detected. • Parity error (2) This error occurs when if parity is enabled, the number of 1’s in the parity and character bits does not match the set number of 1’s. • Error sum flag This flag is set to 1 if an overrun, framing, or parity error occurs. Selectable functions • LSB first, MSB first selection Whether data transmission/reception begins with bit 0 or begins with bit 7 can be selected. • Serial data logic switching This function inverts the logic of transmit/receive data. Start and stop bits are not inverted. • TXD, RXD I/O polarity switching This function inverts the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O data are inverted. • RAD2 digital filter selection The digital filter for the RXD2 input signal can be enabled or disabled. Notes: 1. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC register remains unchanged. 2. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UART2 receive register to the U2RB register. REJ09B0441-0010 Rev.0.10 Page 535 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.6 Registers Used and Settings in UART Mode Register U2TB U2RB U2BRG U2MR Bit b0 to b8 b0 to b8 Set transmit data. (1) Function U2C0 Receive data can be read. (1, 2) OER, FER, PER, SUM Error flag b0 to b7 Set the transfer rate. SMD2 to SMD0 Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Set to 110b when transfer data is 9 bits long. CKDIR Select an internal clock or external clock. STPS Select the stop bit(s). PRY, PRYE Select whether parity is included and whether odd or even. IOPOL Select the polarities of the TXD/RXD input/output. CLK0, CLK1 Select the count source for the U2BRG register. CRS Select CTS or RTS to use the function. TXEPT CRD NCH CKPOL UFORM Transmit register empty flag Select the CTS or RTS function enabled or disabled. Select the output format of the TXD2 pin. Set to 0. Select LSB first or MSB first when transfer data is 8 bits long. Set to 0 when transfer data is 7 or 9 bits long. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select the UART2 transmit interrupt source. Set to 0. Set to 1 to use inverted data logic. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Select the digital filter disabled or enabled. Set to 0. U2C1 U2SMR U2SMR2 U2SMR3 U2SMR4 URXDF U2SMR5 TE TI RE RI U2IRS U2RRM U2LCH U2ERE b0 to b7 b0 to b7 b0 to b7 b0 to b7 DF2EN MP Notes: 1. The bits used for transmit/receive data are as follows: - Bits b0 to b6 when transfer data is 7 bits long - Bits b0 to b7 when transfer data is 8 bits long - Bits b0 to b8 when transfer data is 9 bits long 2. The contents of the following are undefined: - Bits b7 and b8 when transfer data is 7 bits long - Bit b8 when transfer data is 8 bits long REJ09B0441-0010 Rev.0.10 Page 536 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.7 lists the I/O Pin Functions in UART Mode. After UART2 operating mode is selected, the TXD2 pin outputs a high-level signal until transfer starts. (When Nchannel open-drain output is selected, this pin is in the high-impedance state.) Figure 25.7 shows the Transmit Timing in UART Mode. Figure 25.8 shows the Receive Timing in UART Mode. Table 25.7 I/O Pin Functions in UART Mode Pin Name Function TXD2 Serial data output (P11_1 or P11_2) Selection Method • When TXD2 (P11_1) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 10b (P11_1) • When TXD2 (P11_2) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 01b (P11_2) • For reception only: P11_1 and P11_2 can be used as ports by setting TXD2SEL1 to TXD2SEL0 to 00b. • When RXD2 (P11_1) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P11_1) • When RXD2 (P11_2) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P11_2) PD11_2 bit in PD11 register = 0 • For transmission only: P11_1 and P11_2 can be used as ports by setting RXD2SEL1 to RXD2SEL0 to 00b. RXD2 Serial data input (P11_1 or P11_2) CLK2 (P11_0) I/O port Transfer clock input CTS2/RTS2 (P11_3) CTS input RTS output I/O port CLK2SEL0 bit in U2SR1 register = 0 CLK2SEL0 bit in U2SR1 register = 1 CKDIR bit in U2MR register = 1 PD11_0 bit in PD11 register = 0 CTS2SEL0 bit in U2SR1 register = 1 CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 0 PD11_3 bit in PD11 register = 0 CTS2SEL0 bit in U2SR1 register = 1 CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 1 CTS2SEL0 bit in U2SR1 register = 0 REJ09B0441-0010 Rev.0.10 Page 537 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) (1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) TC Transfer clock TE bit in U2C1 register TI bit in U2C1 register 1 0 1 0 The transfer clock stops once because the CTS pin is “H” when the stop bit is verified. The transfer clock resumes running immediately after the CTS pin is verified to be “L”. Data set in U2TB register Data transfer from U2TB register to UART2 transmit register “H” CTS2 “L” Start bit Parity bit D0 D1 D2 D3 D4 D5 D6 D7 P SP Stop bit ST D0 D1 D2 D3 D4 Pulsing stops because TE bit is set to 0. D5 D6 D7 P SP ST D0 D1 TXD2 TXEPT bit in U2C0 register IR bit in S2TIC register 1 0 1 0 ST Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • PRYE bit in U2MR register = 1 (parity enabled) • STPS bit in U2MR register = 0 (one stop bit) • CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected) • U2IRS bit in U2C1 register = 1 (interrupt request generation when transmission is completed) TC = 16(n + 1)/fj or 16(n + 1)/fEXT fj: Frequency of U2BRG count source (f1, f8, f32, fC) fEXT: Frequency of U2BRG count source (external clock) n: Value set in U2BRG register (2) Transmit Timing Example When Transfer Data 9 Bits is Long (Parity Disabled, Two Stop Bits) TC Transfer clock TE bit in U2C1 register TI bit in U2C1 register 1 0 1 0 Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Data set in U2TB register Data transfer from U2TB register to UART2 transmit register Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 TXD2 TXEPT bit in U2C0 register IR bit in S2TIC register 1 0 1 0 ST Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • PRYE bit in U2MR register = 0 (parity disabled) • STPS bit in U2MR register = 1 (two stop bits) • CRD bit in U2C0 register = 1 (CTS/RTS function disabled) • U2IRS bit in U2C1 register = 0 (interrupt request generation when the transmit buffer is empty) TC = 16(n + 1)/fj or 16(n + 1)/fEXT fj: Frequency of U2BRG count source (f1, f8, f32, fC) fEXT: Frequency of U2BRG count source (external clock) n: Value set in U2BRG register Figure 25.7 Transmit Timing in UART Mode REJ09B0441-0010 Rev.0.10 Page 538 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Receive Timing Example When Transfer Data 8 Bits is Long (Parity Disabled, One Stop Bit) U2BRG count source RE bit in U2C1 register RXD2 1 0 Stop bit Start bit “L” is determined. Received data capture D0 D1 D7 Transfer clock RI bit in U2C1 register RTS2 IR bit in S2RIC register 1 0 “H” “L” 1 0 Reception starts when a transfer clock Data transfer from UART2 receive register to is generated at the falling edge U2RB register of the start bit. Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: • PRYE bit in U2MR register = 0 (parity disabled) • STPS bit in U2MR register = 0 (one stop bit) • CRD bit in U2C0 register = 0 (CTS2/RTS2 function enabled), CRS bit = 1 (RTS2 function selected) Figure 25.8 Receive Timing in UART Mode 25.4.1 Bit Rate In UART mode, the bit rate is the frequency divided by the U2BRG register divided by 16. Table 25.8 lists the Bit Rate Setting Example in UART Mode (Internal Clock Selected). Table 25.8 Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 38400 57600 115200 Note: Bit Rate Setting Example in UART Mode (Internal Clock Selected) System Clock = 20 MHz U2BRG Setting Actual Time Setting Error (bps) Value (%) 129 (81h) 1201.92 0.16 64 (40h) 2403.85 0.16 32 (20h) 4734.85 -1.36 129 (81h) 9615.38 0.16 86 (56h) 14367.82 -0.22 64 (40h) 19230.77 0.16 42 (2Ah) 29069.77 0.94 32 (20h) 37878.79 -1.36 21 (15h) 56818.18 -1.36 10 (0Ah) 113636.36 -1.36 System Clock = 18.432 MHz (1) U2BRG Setting Actual Time Setting Error (bps) Value (%) 119 (77h) 1200.00 0.00 59 (3Bh) 2400.00 0.00 29 (1Dh) 4800.00 0.00 119 (77h) 9600.00 0.00 79 (4Fh) 14400.00 0.00 59 (3Bh) 19200.00 0.00 39 (27h) 28800.00 0.00 29 (1Dh) 38400.00 0.00 19 (13h) 57600.00 0.00 9 (09h) 115200.00 0.00 System Clock = 8 MHz U2BRG Actual Setting Setting Time Error Value (bps) (%) 51 (33h) 1201.92 0.16 25 (19h) 2403.85 0.16 12 (0Ch) 4807.69 0.16 51 (33h) 9615.38 0.16 34 (22h) 14285.71 -0.79 25 (19h) 19230.77 0.16 16 (10h) 29411.76 2.12 12 (0Ch) 38461.54 0.16 8 (08h) 55555.56 -3.55 − − − U2BRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 1. For the high-speed on-chip oscillator, the correction value of the FRA4 register should be written into the FRA1 register and the correction value of the FRA5 register should be written into the FRA3 register. This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in the FRA2 register are set to 000b (divide-by-2 mode). REJ09B0441-0010 Rev.0.10 Page 539 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.4.2 Measure for Dealing with Communication Errors If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below: • Resetting the U2RB register (1) Set the RE bit in the U2C1 register to 0 (reception disabled). (2) Set the RE bit in the U2C1 register to 1 (reception enabled). • Resetting the U2TB register (1) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled). (2) Reset bits SMD2 to SMD0 in the U2MR register to 001b, 101b, and 110b. (3) Write 1 to the TE bit in the U2C1 register (transmission enabled), regardless of the TE bit value of the U2C1 register. 25.4.3 LSB First/MSB First Select Function As shown in Figure 25.9, the UFORM bit in the U2C0 register can be used to select the transfer format. This function is enabled when transfer data is 8 bits long. Figure 25.9 shows the Transfer Format. (1) UFORM Bit in U2C0 Register = 0 (LSB first) CLK2 TXD2 RXD2 ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (2) UFORM Bit in U2C0 Register = 1 (MSB first) CLK2 TXD2 RXD2 ST ST D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 P P SP SP ST: Start bit P: Parity bit SP: Stop bit The above applies under the following conditions: • CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) • U2LCH bit in U2C1 register = 0 (not inverted) • STPS bit in U2MR register = 0 (one stop bit) • PRYE bit in U2MR register = 1 (parity enabled) Figure 25.9 Transfer Format REJ09B0441-0010 Rev.0.10 Page 540 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.4.4 Serial Data Logic Switching Function The data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received data has its logic inverted when read from the U2RB register. Figure 25.10 shows the Serial Data Logic Switching. (1) U2LCH bit in U2C1 Register = 0 (not inverted) Transfer clock TXD2 (not inverted) “H” “L” “H” “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) U2LCH Bit in U2C1 Register = 1 (inverted) Transfer clock TXD2 (inverted) “H” “L” “H” “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP The above applies under the following conditions: • CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock) • UFORM bit in U2C0 register = 0 (LSB first) • STPS bit in U2MR register = 0 (one stop bit) • PRYE bit in U2MR register = 1 (parity enabled) ST: Start bit P: Parity bit SP: Stop bit Figure 25.10 Serial Data Logic Switching 25.4.5 TXD and RXD I/O Polarity Inverse Function This function inverts the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all I/O data (including bits for start, stop, and parity) are inverted. Figure 25.11 shows the TXD and RXD I/O Inversion. (1) IOPOL Bit in U2MR Register = 0 (not inverted) Transfer clock TXD2 (not inverted) RXD2 (not inverted) “H” “L” “H” “L” “H” “L” ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (2) IOPOL Bit in U2MR Register = 1 (inverted) Transfer clock TXD2 (not inverted) RXD2 (not inverted) “H” “L” “H” “L” “H” “L” ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP The above applies under the following conditions: • UFORM bit in U2C0 register = 0 (LSB first) • STPS bit in U2MR register = 0 (one stop bit) • PRYE bit in U2MR register = 1 (parity enabled) ST: Start bit P: Parity bit SP: Stop bit Figure 25.11 TXD and RXD I/O Inversion REJ09B0441-0010 Rev.0.10 Page 541 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.4.6 CTS/RTS Function The CTS function is used to start transmit operation when a low-level signal is applied to the CTS2/RTS2 pin. Transmit operation begins when the CTS2/RTS2 pin is held low. If the input level is switched to high during a transmit operation, the operation stops before the next data. When the RTS function is used, the CTS2/RTS2 pin outputs a low-level signal when the MCU is ready for a receive operation. The output level goes high at the first falling edge of the CLK2 pin. • The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled) The CTS2/RTS2 pin operates as the programmable I/O function. • The CRD bit = 0, CRS bit = 0 (CTS function selected) The CTS2/RTS2 pin operates as the CTS function. • The CRD bit = 0, CRS bit = 1 (RTS function selected) The CTS2/RTS2 pin operates as the RTS function. 25.4.7 RXD2 Digital Filter Select Function When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded latch circuits and a match detection circuit. The RXD2 input signal is sampled on the basic clock with a frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit when three latch outputs match. When the outputs do not match, the previous value is retained. In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise. Figure 25.12 shows a Block Diagram of RXD2 Digital Filter Circuit. Sampling clock C RXD2 input signal D Latch Q D C Q Latch D C Q Latch Match detection circuit URXDF register (DF2EN bit) Internal RXD2 input signal Internal basic clock period (1) Sampling clock Note: 1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1) (fj = f1, f8, f32, fC; n = setting value in the U2BRG register). When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1) (fEXT is input from the CLK2 pin. n = setting value in the U2BRG register). Figure 25.12 Block Diagram of RXD2 Digital Filter Circuit REJ09B0441-0010 Rev.0.10 Page 542 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.5 Special Mode 1 (I2C Mode) I2 C mode is provided for use as a simplified I2C interface compatible mode. Table 25.9 lists the I2C Mode Specifications. Tables 25.10 and 25.11 list the registers used in I2C mode and the settings. Table 25.12 lists the I2C Mode Functions, Figure 25.13 shows a Block Diagram of I2C Mode, and Figure 25.14 shows the Transfer to U2RB Register and Interrupt Timing. As shown in Table 25.12, the MCU is placed in I2C mode by setting bits SMD2 to SMD0 to 010b and the IICM bit to 1. Because SDA2 transmit output has a delay circuit attached, SDA2 output does not change state until SCL2 goes low and remains stably low. Table 25.9 I2C Mode Specifications Specification Transfer data length: 8 bits • Master mode The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1)) fj = f1, f8, f32, fC n = Value set in U2BRG register: 00h to FFh • Slave mode The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin To start transmission, the following requirements must be met: (1) • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). To start reception, the following requirements must be met: (1) • The RE bit in the U2C1 register is set to 1 (reception enabled). • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). Start/stop condition detection, no acknowledgement detection, or acknowledgement detection Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives the 8th bit of the next unit of data. • Arbitration lost Timing at which the ABT bit in the U2RB register is updated can be selected. • SDA2 digital delay No digital delay or a delay of 2 to 8 U2BRG count source clock cycles can be selected. • Clock phase setting With or without clock delay can be selected. Item Transfer data format Transfer clock Transmit start conditions Receive start conditions Interrupt request generation timing Error detection Selectable functions Notes: 1. If an external clock is selected, the requirements must be met while the external clock is held high. 2. If an overrun error occurs, the received data in the U2RB register will be undefined. The IR bit in the S2RIC register remains unchanged. REJ09B0441-0010 Rev.0.10 Page 543 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) SDA2 STSPSEL = 1 Delay circuit STSPSEL = 0 ACKC = 0 SDHI ACKD bit DQ T Start/stop condition generation block SDA (STSP) SCL (STSP) IICM2 = 1 DTC request (source number 15) UART2 transmit/NACK interrupt request IICM = 1 and IICM2 = 0 ACKC = 1 Transmit register UART2 ALS Arbitration Receive register UART2 IICM2 = 1 Start condition detection S R Q IICM = 1 and IICM2 = 0 UART2 receive/ACK interrupt request DTC request (source number 14) Bus busy NACK Stop condition detection DQ T DQ T SCL2 Falling edge detection IICM = 0 I/O port Q R Port register (1) Internal clock SWC2 External clock R S ACK 9th bit Start/stop condition detection interrupt request UART2 9th-bit falling edge SWC STSPSEL = 0 UART2 STSPSEL IICM = 1 =1 CLK control IICM: Bit in U2SMR register IICM2, SWC, ALS, SWC2, SDHI: Bits in U2SMR2 register STSPSEL, ACKD, ACKC: Bits in U2SMR4 register The above applies under the following conditions: • Bits SMD2 to SMD0 in U2MR register = 010b • IICM bit in U2SMR register = 1 Note: 1. When the IICM bit is set to 1, the pin level can be read even if the port direction bit corresponding to the SCL2 pin is set to 1 (output mode). Figure 25.13 Block Diagram of I2C Mode REJ09B0441-0010 Rev.0.10 Page 544 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.10 Register U2TB (1) Registers Used and Settings in I2C Mode (1) Bit Function Master Set transmit data. Receive data can be read. ACK or NACK is set in this bit. Arbitration lost detect flag Overrun error flag Set the transfer rate. Set to 010b. Set to 0. Set to 0. Select the count source for the U2BRG register. Disabled because CRD = 1. Transmit register empty flag Set to 1. Set to 1. Set to 0. Set to 1. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Disabled Set to 0. Set transmit data. Receive data can be read. ACK or NACK is set in this bit. Disabled Overrun error flag Disabled Set to 010b. Set to 1. Set to 0. Disabled Disabled because CRD = 1. Transmit register empty flag Set to 1. Set to 1. Set to 0. Set to 1. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Disabled Set to 0. Set to 1. Disabled Bus busy flag Set to 0. Refer to Table 25.12 I2C Mode Functions. Set to 0. Set to 1 to fix SCL2 output low at the falling edge of the 9th bit of clock. Set to 0. Set to 1 to initialize UART2 at start condition detection. Set to 1 to forcibly pull SCL2 output low. Set to 1 to disable SDA2 output. Set to 0. Slave b0 to b7 b0 to b7 b8 ABT OER U2BRG b0 to b7 U2MR (1) SMD2 to SMD0 CKDIR IOPOL U2C0 CLK0, CLK1 U2RB (1) CRS TXEPT CRD NCH CKPOL UFORM U2C1 TE TI RE RI U2IRS U2RRM, U2LCH, U2ERE U2SMR IICM Set to 1. ABC Select the timing at which an arbitration lost is detected. BBS Bus busy flag b3 to b7 Set to 0. U2SMR2 IICM2 Refer to Table 25.12 I2C Mode Functions. CSC Set to 1 to enable clock synchronization. SWC Set to 1 to fix SCL2 output low at the falling edge of the 9th bit of clock. ALS Set to 1 to stop SDA2 output when an arbitration lost is detected. STAC Set to 0. SWC2 SDHI b7 Set to 1 to forcibly pull SCL2 output low. Set to 1 to disable SDA2 output. Set to 0. Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in I2C mode. REJ09B0441-0010 Rev.0.10 Page 545 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.11 Register Registers Used and Settings in I2C Mode (2) Bit Set to 0. Refer to Table 25.12 I2C Mode Functions. Set the amount of SDA2 digital delay. Set to 1 to generate a start condition. Set to 1 to generate a restart condition. Set to 1 to generate a stop condition. Set to 1 to output each condition. Select ACK or NACK. Set to 1 to output ACK data. Set to 1 to stop SCL2 output when a stop condition is detected. Set to 0. Set to 0. Set to 0. Function Master Set to 0. Refer to Table 25.12 I2C Mode Functions. Set the amount of SDA2 digital delay. Set to 0. Set to 0. Set to 0. Set to 0. Select ACK or NACK. Set to 1 to output ACK data. Set to 0. Set to 1 to hold SCL2 low at the falling edge of the 9th bit of clock. Set to 0. Set to 0. Slave U2SMR3 b0, b2, b4, NODC CKPH DL0 to DL2 U2SMR4 STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 URXDF DF2EN U2SMR5 MP REJ09B0441-0010 Rev.0.10 Page 546 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.12 Function I2C Mode Functions Clock Synchronous Serial I/O Mode (SMD2 to SMD0 = 001b, IICM = 0) − I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) IICM2 = 0 (NACK/ACK interrupt) CKPH = 0 (No Clock Delay) CKPH = 1 (With Clock Delay) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (No Clock Delay) CKPH = 1 (With Clock Delay) Source of UART2 bus collision interrupt (1, 5) Source of UART2 transmit/ NACK2 interrupt (1, 6) Start condition detection or stop condition detection (Refer to Table 25.13 STSPSEL Bit Functions) No acknowledgment detection (NACK) Rising edge of SCL2 9th bit UART2 transmission Rising edge of SCL2 9th bit UART2 transmission Falling edge of SCL2 next to 9th bit UART2 transmission Transmission started or completed (selectable by U2IRS bit) Source of UART2 receive/ACK2 interrupt (1, 6) UART2 reception Acknowledgment detection (ACK) When 8th bit received Rising edge of SCL2 9th bit CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) UART2 reception Falling edge of SCL2 9th bit Timing for transferring data CKPOL = 0 (rising edge) Rising edge of SCL2 9th bit from UART receive shift CKPOL = 1 (falling edge) register to U2RB register UART2 transmission output delay TXD2/SDA2 functions RXD2/SCL2 functions CLK2 function Read of RXD2 and SCL2 pin levels Initial value of TXD2 and SDA2 outputs Initial and end values of SCL2 DTC source number 14 (6) No delay TXD2 output RXD2 input CLK2 input or output port selected Enabled when the corresponding port direction bit = 0 CKPOL = 0 (high) CKPOL = 1 (low) − Falling edge of SCL2 9th bit Falling and rising edges of SCL2 9th bit With delay SDA2 I/O SCL2 I/O − (Usable in I2C mode.) Enabled regardless of the content of the corresponding port direction bit. The value set in the port register before setting I2C mode. (2) High Low High Low UART2 reception Acknowledgment detection (ACK) When 8th bit received CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) UART2 transmission Transmission started or completed (selectable by U2IRS bit) The 1st to 8th bits of the received data are stored in bits b0 to b7 in the U2RB register. UART2 transmission Rising edge of SCL2 9th bit UART2 transmission Falling edge of SCL2 next to 9th bit UART2 reception Falling edge of SCL2 9th bit DTC source number 15 (6) UART2 transmission Rising edge of SCL2 9th bit UART2 transmission Falling edge of SCL2 next to 9th bit Storage of receive data The 1st to 8th bits of the received data are stored in bits b7 to b0 in the U2RB register. The 1st to 7th bits of the received data are stored in bits b6 to b0 in the U2RB register. 8th bit is stored in bit b8 in the U2RB register. The 1st to 8th bits are stored in bits b7 to b0 in the U2RB register. (3) Bits b6 to b0 in the U2RB register are read as bits b7 to b1. Bit b8 in the U2RB register is read as bit b0. (4) Read of receive data The U2RB register status is read. Notes: 1. 2. 3. 4. 5. 6. If the source of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). (Refer to 12.8 Notes on Interrupts.) If one of the bits listed below is changed, the interrupt source, the interrupt timing, and others change. Always be sure to set the IR bit to 0 (interrupt not requested) after changing these bits: Bits SMD2 to SMD0 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2 register, and the CKPH bit in the U2SMR3 register. Set the initial value of SDA2 output while bits SMD2 to SMD0 in the U2MR register are 000b (serial interface disabled). Second data transfer to the U2RB register (rising edge of SCL2 9th bit) First data transfer to the U2RB register (falling edge of SCL2 9th bit) Refer to Figure 25.16 STSPSEL Bit Functions. Refer to Figure 25.14 Transfer to U2RB Register and Interrupt Timing. REJ09B0441-0010 Rev.0.10 Page 547 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) ACK interrupt (DTC source number 14 request), NACK interrupt Transfer to U2RB register b15 b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0 ... U2RB register contents (2) IICM2 = 0, CKPH = 1 (with clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) ACK interrupt (DTC source number 14 request), NACK interrupt Transfer to U2RB register b15 b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0 ... U2RB register contents (3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) Transmit interrupt Receive interrupt (DTC source number 14 request) Transfer to U2RB register b15 b9 b8 D0 b7 D7 D6 D5 D4 D3 D2 b0 D1 ... U2RB register contents (4) IICM2 = 1, CKPH = 1 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) Transmit interrupt Receive interrupt (DTC source number 14 request) Transfer to U2RB register b15 b9 b8 D0 b7 D7 D6 D5 D4 D3 D2 b0 D1 Transfer to U2RB register b15 b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0 ... ... U2RB register contents U2RB register contents The above applies under the following condition: • CKDIR bit in U2MR register = 0 (master selected) Figure 25.14 Transfer to U2RB Register and Interrupt Timing REJ09B0441-0010 Rev.0.10 Page 548 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.5.1 Detection of Start and Stop Conditions Whether a start or a stop condition has been detected is determined. A start condition detect interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state. A stop condition detect interrupt request is generated when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state. Because the start and stop condition detect interrupts share an interrupt control register and vector, check the BBS bit in the U2SMR register to determine which interrupt source is requesting the interrupt. Figure 25.15 shows the Detection of Start and Stop Conditions. 5 cycles of f1 < Setting up duration 5 cycles of f1 < Holding duration Setting up duration SCL2 SDA2 Holding duration (Start condition) SDA2 (Stop condition) Figure 25.15 Detection of Start and Stop Conditions REJ09B0441-0010 Rev.0.10 Page 549 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.5.2 Output of Start and Stop Conditions A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start). A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start). A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to 1 (start). The output procedure is as follows: (1) Set the STAREQ, RSTAREQ, or STPREQ bit to 1 (start). (2) Set the STSPSEL bit in the U2SMR4 register to 1 (output). Table 25.13 lists the STSPSEL Bit Functions. Figure 25.16 shows the STSPSEL Bit Functions. Table 25.13 STSPSEL Bit Functions Function SCL2/SDA2 pin output Start/stop condition interrupt request generation timing STSPSEL = 0 Output of a transfer clock and data. Output of start/stop conditions is accomplished by a program using ports (no automatic generation by hardware) Generation of start/stop conditions STSPSEL = 1 Output of start/stop conditions according to bits STAREQ, RSTAREQ, and STPREQ Completion of start/stop condition generation (1) Slave Mode CKDIR = 1 (external clock) STSPSEL bit SCL2 SDA2 0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit Start condition detection interrupt Stop condition detection interrupt (2) Master Mode CKDIR = 0 (internal clock), CKPH = 1 (with clock delay) STSPSEL bit Set to 1 by Set to 0 by a program. a program. SCL2 SDA2 Set to 1 by a program. Set to 0 by a program. 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit Set STAREQ = 1 (start) Start condition detection interrupt Set STPREQ = 1 (start) Stop condition detection interrupt Figure 25.16 STSPSEL Bit Functions REJ09B0441-0010 Rev.0.10 Page 550 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.5.3 Arbitration Unmatching of the transmit data and SDA2 pin input data is checked in synchronization with the rising edge of SCL2. The ABC bit in the U2SMR register can be used to select the timing at which the ABT bit in the U2RB register is updated. If the ABC bit is set to 0 (update per bit), the ABT bit is set to 1 at the same time unmatching is detected during check, and is set to 0 when not detected. When the ABC bit is set to 1, if unmatching is ever detected, the ABT bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of the 9th bit. If the ABT bit needs to be updated per byte, set the ABT bit to 0 (not detected) after detecting acknowledge for the first byte, before transferring the next byte. Setting the ALS bit in the U2SMR2 register to 1 (SDA output stop enabled) causes an arbitration lost to occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit is set to 1 (unmatching detected). 25.5.4 Transfer Clock The transfer clock is used to transmit and receive data as is shown in Figure 25.14 Transfer to U2RB Register and Interrupt Timing. The CSC bit in the U2SMR2 register is used to synchronize an internally generated clock (internal SCL2) and an external clock supplied to the SCL2 pin. When the CSC bit is set to 1 (clock synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high, the internal SCL2 goes low. The value of the U2BRG register is reloaded and counting of the low-level intervals starts. When the internal SCL2 changes state from low to high while the SCL2 pin is low, counting stops. When the SCL2 pin goes high, counting restarts. In this way, the UART2 transfer clock is equivalent to AND of the internal SCL2 and the clock signal applied to the SCL2 pin. The transfer clock works from a half cycle before the falling edge of the internal SCL2 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The SWC bit in the U2SMR2 register can be used to select whether the SCL2 pin is fixed low or freed from low-level output at the falling edge of the 9th clock pulse. If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL2 output is turned off (placed in the high impedance state) when a stop condition is detected. Setting the SWC2 bit in the U2SMR2 register to 1 (low-level output) allows a low-level signal to be forcibly output from the SCL2 pin even during transmission or reception. Setting the SWC2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal. If the SWC9 bit in the U2SMR4 register is set to 1 (SCL hold low enabled) when the CKPH bit in the U2SMR3 register is 1, the SCL2 pin is fixed low at the falling edge of the clock pulse next to the 9th. Setting the SWC9 bit to 0 (SCL hold low disabled) frees the SCL2 pin from low-level output. 25.5.5 SDA Output The data written to bits b7 to b0 (D7 to D0) in the U2TB register is output in descending order from D7. The 9th bit (D8) is ACK or NACK. Set the initial value of SDA2 transmit output when IICM is set to 1 (I2C mode) and bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled). Bits DL2 to DL0 in the U2SMR3 register allow addition of no delays or a delay of two to eight U2BRG count source clock cycles to the SDA2 output. Setting the SDHI bit in the U2SMR2 register to 1 (SDA output disabled) forcibly places the SDA2 pin in the high impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transfer clock. This is because the ABT bit may be set to 1 (detected). REJ09B0441-0010 Rev.0.10 Page 551 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.5.6 SDA Input When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the U2RB register. The 9th bit (D8) is ACK or NACK. When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits b6 to b0 in the U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1, if the CKPH bit is 1, the same data as when the IICM2 bit is 0 can be read by reading the U2RB register after the rising edge of the 9th bit of the clock. 25.5.7 ACK and NACK When the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC bit in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA2 pin. When the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising edge of the 9th bit of the transmit clock. An ACK interrupt request is generated if the SDA2 pin is low at the rising edge of the 9th bit of the transmit clock. When ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC transfer can be activated by detection of an acknowledge. 25.5.8 Initialization of Transmission/Reception When a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial interface operates as described below. • The transmit shift register is initialized, and the contents of the U2TB register are transferred to the transmit shift register. In this way, the serial interface starts sending data when the next clock pulse is applied. However, the UART2 output value does not change state and remains the same as when a start condition was detected until the first bit of data is output in synchronization with the input clock. • The receive shift register is initialized, and the serial interface starts receiving data when the next clock pulse is applied. • The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the falling edge of the 9th clock. Note that when UART2 transmission/reception is started using this function, the TI bit does not change state. Select the external clock as the transfer clock to start UART2 transmission/reception with this setting. REJ09B0441-0010 Rev.0.10 Page 552 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.6 Multiprocessor Communication Function When the multiprocessor communication function is used, data transmission/reception can be performed between a number of processors sharing communication lines by asynchronous serial communication, in which a multiprocessor bit is added to the data. For multiprocessor communication, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle for specifying the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. When the multiprocessor bit is set to 1, the cycle is an ID transmission cycle; when the multiprocessor bit is set to 0, the cycle is a data transmission cycle. Figure 25.17 shows a Multiprocessor Communication Example Using Multiprocessor Format (Data AAh Transmission to Receiving Station A). The transmitting station first sends the ID code of the receiving station to perform communication as communication data with a 1 multiprocessor bit added. It then sends transmit data as communication data with a 0 multiprocessor bit added. When communication data in which the multiprocessor bit is 1 is received, the receiving station compares that data with its own ID. If they match, the data to be sent next is received. If they do not match, the receive station continues to skip communication data until data in which the multiprocessor bit is 1 is again received. UART2 uses the MPIE bit in the U2SMR5 register to implement this function. When the MPIE bit is set to 1, data transfer from the UART2 receive register to the U2RB register, receive error detection, and the settings of the status flags, the RI bit in the U2C1 register, bits FER and OER in the U2RB register, are disabled until data in which the multiprocessor bit is 1 is received. On receiving a receive character in which the multiprocessor bit is 1, the MPRB bit in the U2RB register is set to 1 and the MPIE in the U2SMR5 register bit is set to 0, thus normal reception is resumed. When the multiprocessor format is specified, the parity bit specification is invalid. All other bit settings are the same as those in normal asynchronous mode (UART mode). The clock used for multiprocessor communication is the same as that in normal asynchronous mode (UART mode). Figure 25.18 shows a Block Diagram of Multiprocessor Communication Function. Table 25.14 lists the Registers and Settings for Multiprocessor Communication Function. Transmitting station Communication line Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial data 01h (MPRB = 1) ID transmission cycle = receiving station specification AAh (MPRB = 0) Data transmission cycle = data transmission to receiving station specified by ID MPRB: Multiprocessor bit Figure 25.17 Multiprocessor Communication Example Using Multiprocessor Format (Data AAh Transmission to Receiving Station A) REJ09B0441-0010 Rev.0.10 Page 553 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Reception (5) 1SP DF2EN = 0 Clock synchronous type UART (7 bits) UART (8 bits) PRYE = 0 PAR disabled Clock synchronous type UART (7 bits) UART2 receive register SP DF2EN = 1 Digital filter 2SP SP PAR PAR enabled PRYE = 1 UART UART (9 bits) (2) (1) Clock synchronous type UART (8 bits) UART (9 bits) RXD2 0 0 0 0 0 0 0 MPRB D7 D6 D5 D4 D3 D2 D1 D0 U2RB register MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit MPTB (4) UART (9 bits) UART (3) D7 UART (8 bits) UART (9 bits) Clock synchronous type D6 D5 D4 D3 D2 D1 D0 register U2TB Transmission 2SP PAR enabled PRYE = 1 TXD2 UART2 transmit register SP SP 1SP PAR Clock PAR synchronous disabled PRYE = 0 type 0 UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits) (5) [Multiprocessor mode reception when MP = 1 (multiprocessor communication enabled)] (1) Clock asynchronous (7 bits): Received D7 is transferred to b8 in the U2RB register. (2) Clock asynchronous (8 bits): Received D8 is transferred to b8 in the U2RB register. [Multiprocessor mode transmission when MP = 1 (multiprocessor communication enabled)] (3) Clock asynchronous (7 bits): b8 in the U2TB register is transferred externally as transfer data D7. (4) Clock asynchronous (8 bits): b8 in the U2TB register is transferred externally as transfer data D8. [Multiprocessor mode transmission/reception] (5) PAR is disabled. SP: Stop bit PAR: Parity bit PRYE: Bit in U2MR register DF2EN: Bit in URXDF register MP: Bit in U2SMR5 register Figure 25.18 Block Diagram of Multiprocessor Communication Function REJ09B0441-0010 Rev.0.10 Page 554 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Table 25.14 Registers and Settings for Multiprocessor Communication Function Register U2TB (1) U2RB (2) U2BRG U2MR Bit b0 to b7 MPTB b0 to b7 MPRB OER, FER, SUM b0 to b7 SMD2 to SMD0 CKDIR STPS PRY, PRYE IOPOL CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2LCH U2ERE b0 to b7 b0 to b7 b0 to b7 b0 to b7 MP MPIE DF2EN U2C0 Function Set transmit data. Set to 0 or 1. Receive data can be read. Multiprocessor bit Error flag Set the transfer rate. Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Select an internal clock or external clock. Select the stop bit(s). Parity detection function disabled Set to 0. Select the U2BRG count source. CTS or RTS function disabled Transmit register empty flag Set to 0. Select the output format of the TXD2 pin. Set to 0. Set to 0. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select the UART2 transmit interrupt source. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Set to 1. Set to 1. Select the digital filter enabled or disabled. U2C1 U2SMR U2SMR2 U2SMR3 U2SMR4 U2SMR5 URXDF Notes: 1. Set the MPTB bit to 1 when the ID data frame is transmitted. Set this bit to 0 when the data frame is transmitted. 2. When the MPRB bit is set to 1, received D7 to D0 are ID fields. When this bit is set to 0, received D7 to D0 are data fields. REJ09B0441-0010 Rev.0.10 Page 555 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.6.1 Multiprocessor Transmission Figure 25.19 shows a Sample Flowchart of Multiprocessor Data Transmission. Set the MPBT bit in the U2TB register to 1 for ID transmission cycles. Set the MPBT bit in the U2TB register to 0 for data transmission cycles. Other operations are the same as in universal asynchronous receiver/transmitter mode (UART mode). Start (1) Read the TI bit in the U2C1 register (1) Read the U2C1 register to confirm that the TI bit is set to 1. Then set the MPBT bit in the U2TB register to 0 or 1 and write transmit data to the U2TB register. Writing data to the U2TB register sets the TI bit to 0 automatically. (2) When transmission completes, the TXEPT bit is set to 1 automatically. (3) To continue data transmission, read that the TI bit is 1 and write data tot the U2TB register. Writing data to the U2TB register sets the TI bit to 0 automatically. TI = 1? Yes Set the MPBT bit in the U2TB register No Write transmit data to the U2TB register Read the TXEPT bit in the U2C0 register No (2) TXEPT = 1? Yes (3) Continue data transmission? No Set the TE bit in the U2C1 register to 0 Yes End Figure 25.19 Sample Flowchart of Multiprocessor Data Transmission REJ09B0441-0010 Rev.0.10 Page 556 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.6.2 Multiprocessor Reception Figure 25.20 shows a Sample Flowchart of Multiprocessor Data Reception. When the MPIE bit in the U2SMR5 register is set to 1, communication data is ignored until data in which the multiprocessor bit is 1 is received. Communication data with a 1 multiprocessor bit added is transferred to the U2RB register as receive data. At this time, a reception complete interrupt request is generated. Other operations are the same as in universal asynchronous receiver/transmitter mode (UART mode). Figure 25.21 shows a Receive Operation Example during Multiprocessor Communication (with 8-Bit Data/Multiprocessor Bit/One Stop Bit). Start (1) Set the MPIE bit in the U2SMR5 register to 1 (1) Set the MPIE bit in the U2SMR5 register to 1. (2) When the MPRB bit is detected to be 1, the MPIE bit is set to 0 and a reception complete interrupt request can be generated. Read the U2C1 register to confirm that the RI bit is set to 1. If the RI bit is 1, read data in the receive shift register and compare the data with its own station ID. Reading data in the U2RB register sets the RI bit to 0 automatically. (3) When the data matches the own station ID, the next data reception starts. When the data does not match the ID, set the MPIE bit to 1 and the MCU enters the idle state. (4) Read the U2C1 register to confirm that the RI bit is set to 1. Then read data in the receive shift register. (5) To discontinue reception, set the RE bit in the U2C0 register to 0 to complete reception. To continue reception, restart the procedure from step (1). No Read the RI bit in the U2C1 register (2) RI = 1? Yes Read data in the receive shift register Yes No (3) Own station ID? No Read the RI bit in the U2C1 register (4) RI = 1? Yes Read receive data in the U2RB register (5) Continue data reception? No Set the RE bit in the U2C1 register to 0 Yes End Figure 25.20 Sample Flowchart of Multiprocessor Data Reception REJ09B0441-0010 Rev.0.10 Page 557 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) Start bit Receive data (ID1) MPRB Stop bit Receive data (DATA1) MPRB Marked state (Idle state) Serial data 1 0 D0 D1 1 frame D7 1 1 0 D0 D1 1 frame D7 0 1 1 MP bit in U2SMR5 register MPIE bit in U2SMR5 register RI bit in U2C1 register 1 1 0 1 0 U2RB register ID1 No reception complete interrupt request is generated. The U2RB register retains its state. MCU operation User processing Detect the MPRB bit and A reception complete interrupt request is set the MPIE bit to 0. generated. Set the RI bit to 0. Read data in the U2RB register. If data does not match own station ID, set the MPIE bit to 1 again. (a) When Data Does Not Match Own Station ID Start bit Receive data (ID2) MPRB Stop bit Receive data (DATA2) MPRB Marked state (Idle state) Serial data 1 0 D0 D1 1 frame D7 1 1 0 D0 D1 1 frame D7 0 1 1 MP bit in U2SMR5 register MPIE bit in U2SMR5 register RI bit in U2C1 register 1 1 0 1 0 U2RB register ID1 ID2 DATA2 MCU operation User processing A reception Set the RI bit to 0. Detect the MPRB bit and A reception Set the RI bit to 0. complete complete set the MPIE bit to 0. interrupt request interrupt request Read data in If data matches own is generated. Read data in Set the MPIE bit is generated. the U2RB register. station ID, continue the U2RB register. to 1 again. reception without any setting changes. (b) When Data Matches Own Station ID MPRB: Bit in U2RB register MPIE: Bit in U2SMR5 register Figure 25.21 Receive Operation Example during Multiprocessor Communication (with 8-Bit Data/Multiprocessor Bit/One Stop Bit) REJ09B0441-0010 Rev.0.10 Page 558 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.6.3 RXD2 Digital Filter Select Function When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit when three latch outputs match. When the outputs do not match, the previous value is retained. In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise. Figure 25.12 shows a Block Diagram of RXD2 Digital Filter Circuit. Sampling clock C RXD2 input signal D Latch Q D C Q Latch D C Q Latch Match detection circuit URXDF register (DF2EN bit) Internal RXD2 input signal Internal basic clock period (1) Sampling clock Note: 1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1) (fj = f1, f8, f32, fC; n = setting value in the U2BRG register). When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1) (fEXT is input from the CLK2 pin. n = setting value in the U2BRG register). Figure 25.22 Block Diagram of RXD2 Digital Filter Circuit REJ09B0441-0010 Rev.0.10 Page 559 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.7 25.7.1 Notes on Serial Interface (UART2) Clock Synchronous Serial I/O Mode Transmission/Reception 25.7.1.1 When the RTS function is used with an external clock, the RTS2 pin outputs a low-level signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high-level signal when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 25.7.1.2 Transmission If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock). • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). • If the CTS function is selected, input to the CTS2 pin is low. 25.7.1.3 Reception In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2associated registers for transmission even if the MCU is used for reception only. Dummy data is output from the TXD2 pin during reception. When an internal clock is selected, the shift clock is generated by setting the TE bit in the U2C1 register to 1 (transmission enabled) and setting dummy data in the U2TB register. When an external clock is selected, the shift clock is generated by setting the TE bit to 1 (transmission enabled), setting dummy data in the U2TB register, and inputting an external clock. If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an overrun error occurs, the IR bit in the S2RIC register remains unchanged. To receive data consecutively, set dummy data in the low-order byte in the U2TB register per each receive operation. If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1. • The RE bit in the U2C1 register is set to 1 (reception enabled). • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). REJ09B0441-0010 Rev.0.10 Page 560 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) 25.7.2 Clock Asynchronous Serial I/O (UART) Mode Transmission/Reception 25.7.2.1 When the RTS function is used with an external clock, the RTS2 pin outputs a low-level signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high-level signal when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 25.7.2.2 Transmission If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock). • The TE bit in the U2C1 register is set to 1 (transmission enabled) • The TI bit in the U2C1 register is set to 0 (data in the U2TB register) • If the CTS function is selected, input on the CTS2 pin is low. 25.7.3 Special Mode 1 (I2C Mode) To generate start, stop, and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before changing each condition generation bit (STAREQ, RSTAREQ, and STPREQ) from 0 to 1. REJ09B0441-0010 Rev.0.10 Page 561 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 26. Clock Synchronous Serial Interface 26. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock synchronous serial interface Synchronous serial communication unit (SSU) Clock synchronous communication mode 4-wire bus communication mode I2C bus Interface I2C bus interface mode Clock synchronous serial mode The clock synchronous serial interface uses the registers at addresses 0193h to 019Dh. Registers, bits, symbols, and functions vary even for the same addresses depending on the mode. Refer to the registers of each function for details. Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the options of the transfer clock, clock output format, and data output format. 26.1 Mode Selection The clock synchronous serial interface supports four modes. Table 26.1 lists the Mode Selections. Refer to 27. Synchronous Serial Communication Unit (SSU), 28. I2C bus Interface and the sections that follow for details of each mode. Table 26.1 IICSEL Bit in SSUIICSR Register 0 0 1 1 Mode Selections Bit 7 in 0198h (ICE Bit in ICCR1 Register) 0 0 1 1 Bit 0 in 019Dh (SSUMS Bit in SSMR2 Register, FS Bit in SAR Register) 0 1 0 1 Function Mode Synchronous serial communication unit I2C bus interface Clock synchronous communication mode 4-wire bus communication mode I2C bus interface mode Clock synchronous serial mode REJ09B0441-0010 Rev.0.10 Page 562 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27. Synchronous Serial Communication Unit (SSU) The synchronous serial communication unit (SSU) supports clock synchronous serial data communication. 27.1 Introduction Table 27.1 shows the Synchronous Serial Communication Unit Specifications. Figure 27.1 shows a Block Diagram of Synchronous Serial Communication Unit. Table 27.1 Synchronous Serial Communication Unit Specifications Specification • Transfer data length: 8 to 16 bits Continuous transmission and reception of serial data are enabled since both transmitter and receiver have buffer structures. Operating modes • Clock synchronous communication mode • 4-wire bus communication mode (including bidirectional communication) Master/slave device Selectable I/O pins SSCK (I/O): Clock I/O pin SSI (I/O): Data I/O pin SSO (I/O): Data I/O pin SCS (I/O): Chip-select I/O pin Transfer clocks • When the MSS bit in the SSCRH register is set to 0 (operation as a slave device), an external clock is selected (input from the SSCK pin). • When the MSS bit in the SSCRH register is set to 1 (operation as the master device), an internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4, output from the SSCK pin) is selected. • The clock polarity and the phase of SSCK can be selected. Receive error detection • Overrun error An overrun error occurs during reception and completes in error. While the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and when the next serial data reception is completed, the ORER bit is set to 1. Multimaster error • Conflict error When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus detection communication mode) and the MSS bit in the SSCRH register is set to 1 (operation as the master device) and when starting a serial communication, the CE bit in the SSSR register is set to 1 if a low-level signal applies to the SCS pin input. When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode), the MSS bit in the SSCRH register is set to 0 (operation as a slave device) and the SCS pin input changes state from low to high, the CE bit in the SSSR register is set to 1. Interrupt requests 5 interrupt requests (transmit end, transmit data empty, receive data full, overrun error, and conflict error) (1). Selectable functions • Data transfer direction Selectable MSB first or LSB first • SSCK clock polarity Selectable a low or high level when the clock stops • SSCK clock phase Selectable edges for data change and data download Note: 1. All sources use a single interrupt vector table for the synchronous serial communication unit. Item Transfer data format REJ09B0441-0010 Rev.0.10 Page 563 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) f1 Internal clock (f1/i) Internal clock generation circuit Multiplexer SSCK SSMR register SSCRL register SSCRH register SCS Transmit/receive control circuit SSER register SSSR register SSMR2 register SSTDR register Data bus SSO Selector SSI SSTRSR register SSRDR register Interrupt requests (TXI, TEI, RXI, OEI, and CEI) i = 4, 8, 16, 32, 64, 128, or 256 Figure 27.1 Block Diagram of Synchronous Serial Communication Unit Table 27.2 Pin Configuration of Synchronous Serial Communication Unit Pin Name SSI SCS SSCK SSO Assigned Pin P11_1 P11_3 P11_0 P11_2 I/O I/O I/O I/O I/O Data I/O Function Chip-select signal I/O Clock I/O Data I/O REJ09B0441-0010 Rev.0.10 Page 564 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2 27.2.1 Registers Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. REJ09B0441-0010 Rev.0.10 Page 565 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.2 SSU/IIC Pin Select Register (SSUIICSR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 IICSEL 0 R/W R/W — Address 018Ch Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IICSEL — — — — — — — Bit Name SSU/I2C bus switch bit Function 0: SSU function selected 1: I2C bus function selected Nothing is assigned. If necessary, set to 0. When read, the content is 0. REJ09B0441-0010 Rev.0.10 Page 566 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.3 SS Bit Counter Register (SSBR) b6 — 1 b5 — 1 b4 — 1 b3 BS3 1 b2 BS2 0 b1 BS1 0 Function b3 b2 b1 b0 Address 0193h Bit b7 Symbol — After Reset 1 Bit b0 b1 b2 b3 b0 BS0 0 R/W R/W R/W R/W R/W Symbol Bit Name BS0 SSU data transfer length set bit (1) BS1 BS2 BS3 b4 b5 b6 b7 — — — — 0 0 0 0: 16 bits 1 0 0 0: 8 bits 1 0 0 1: 9 bits 1 0 1 0: 10 bits 1 0 1 1: 11 bits 1 1 0 0: 12 bits 1 1 0 1: 13 bits 1 1 1 0: 14 bits 1 1 1 1: 15 bits Nothing is assigned. If necessary, set to 0. When read, the content is 1. — — — — Note: 1. Do not write to bits BS0 to BS3 during the SSU operation. Write to these bits when the RE bit in the SSER register is set to 0 (reception disabled) and the TE bit is set to 0 (transmission disabled). To set the SSBR register, set the RE bit in the SSER register to 0 and the TE bit to 0. Bits BS0 to BS3 (SSU Data Transfer Length Set Bit) From 8 to 16 bits can be used as the SSU data transfer length. 27.2.4 SS Transmit Data Register (SSTDR) b5 — 1 b13 — 1 b4 — 1 b12 — 1 b3 — 1 b11 — 1 b2 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 Address 0195h to 0194h Bit b7 b6 Symbol — — After Reset 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 Bit Symbol Function R/W b15 to b0 — This register stores transmit data. R/W When the SSTRSR register is detected as empty, the stored transmit data is transferred to the SSTRSR register and transmission starts. When the next transmit data is written to the SSTDR register during the data transmission from the SSTRSR register, continuous transmission is enabled. When the MLS bit in the SSMR register is set to 1 (transfer data with LSB first), the MSBLSB inverted data is read after writing to the SSTDR register. REJ09B0441-0010 Rev.0.10 Page 567 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.5 SS Receive Data Register (SSRDR) b5 — 1 b13 — 1 b4 — 1 b12 — 1 b3 — 1 b11 — 1 b2 — 1 b10 — 1 b1 — 1 b9 — 1 b0 — 1 b8 — 1 R/W R Address 0197h to 0196h Bit b7 b6 Symbol — — After Reset 1 1 Bit Symbol After Reset b15 — 1 b14 — 1 Bit Symbol Function (1) b15 to b0 — This register stores receive data. The receive data is transferred to the SSRDR register and the receive operation is completed when 1 byte of data has been received by the SSTRSR register. At this time, the next reception is enabled. Continuous reception is enabled using registers SSTRSR and SSRDR. Note: 1. When the ORER bit in the SSSR register is set to 1 (overrun error), the SSRDR register retains the data received before an overrun error occurs. When an overrun error occurs, the receive data is discarded. 27.2.6 SS Control Register H (SSCRH) b6 RSSTP 0 b5 MSS 0 b4 — 0 b3 — 0 b2 CKS2 0 b1 CKS1 0 Function b2 b1 b0 Address 0198h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b0 CKS0 0 R/W R/W R/W R/W Symbol Bit Name CKS0 Transfer clock select bit (1) CKS1 CKS2 b3 b4 b5 b6 b7 0: Operation as a slave device 1: Operation as the master device 0: Receive operation is continued after receiving 1 byte RSSTP Receive single stop bit (3) of data 1: Receive operation is completed after receiving 1 byte of data — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Master/slave device select bit (2) — — MSS 0 0 0: f1/256 0 0 1: f1/128 0 1 0: f1/64 0 1 1: f1/32 1 0 0: f1/16 1 0 1: f1/8 1 1 0: f1/4 1 1 1: Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. — R/W R/W — Notes: 1. The set clock is used when an internal clock is selected. 2. The SSCK pin functions as the transfer clock output pin when the MSS bit is set to 1 (operation as the master device). The MSS bit is set to 0 (operation as a slave device) when the CE bit in the SSSR register is set to 1 (conflict error occurs). 3. The RSSTP bit is disabled when the MSS bit is set to 0 (operation as a slave device). REJ09B0441-0010 Rev.0.10 Page 568 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.7 SS Control Register L (SSCRL) b6 — 1 b5 SOL 1 b4 SOLP 1 b3 — 1 b2 — 1 b1 SRES 0 b0 — 1 R/W — R/W Address 0199h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. SRES SSU control unit reset bit When 1 is written to this bit, the SSU control unit and the SSTRSR register are reset. The value of the SSU internal register (1) is retained. — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — When 0 is written to this bit, the output level can be SOLP SOL write protect bit (2) changed by the SOL bit. The SOLP bit remains unchanged even if 1 is written to it. When read, the content is 1. SOL Serial data output value setting bit When read 0: Serial data output is low 1: Serial data output is high When written (2, 3) 0: Data output is low after serial data output 1: Data output is high after serial data output — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — R/W R/W — — Notes: 1. Registers SSBR, SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR. 2. The data output after serial data output can be changed by writing to the SOL bit before or after transfer. When writing to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction. 3. Do not write to the SOL bit during data transfer. REJ09B0441-0010 Rev.0.10 Page 569 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.8 SS Mode Register (SSMR) b6 CPOS 0 b5 CPHS 0 b4 — 1 b3 BC3 0 b2 BC2 0 b1 BC1 0 Function b3 b2 b1 b0 Address 019Ah Bit b7 Symbol MLS After Reset 0 Bit b0 b1 b2 b3 b0 BC0 0 R/W R R R R Symbol Bit Name BC0 Bit counter 3 to 0 BC1 BC2 BC3 b4 b5 — CPHS b6 b7 CPOS MLS 0 0 0 0: 16 bits left 0 0 0 1: 1 bit left 0 0 1 0: 2 bits left 0 0 1 1: 3 bits left 0 1 0 0: 4 bits left 0 1 0 1: 5 bits left 0 1 1 0: 6 bits left 0 1 1 1: 7 bits left 1 0 0 0: 8 bits left 1 0 0 1: 9 bits left 1 0 1 0: 10 bits left 1 0 1 1: 11 bits left 1 1 0 0: 12 bits left 1 1 0 1: 13 bits left 1 1 1 0: 14 bits left 1 1 1 1: 15 bits left Nothing is assigned. If necessary, set to 0. When read, the content is 1. 0: Data change at odd edges SSCK clock phase select bit (1) (Data download at even edges) 1: Data change at even edges (Data download at odd edges) 0: High when clock stops SSCK clock polarity select bit (1) 1: Low when clock stops MSB first/LSB first select bit 0: Transfer data with MSB first 1: Transfer data with LSB first — R/W R/W R/W Note: 1. Refer to 27.3.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of bits CPHS and CPOS. REJ09B0441-0010 Rev.0.10 Page 570 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.9 SS Enable Register (SSER) b6 TEIE 0 b5 RIE 0 b4 TE 0 b3 RE 0 b2 — 0 b1 — 0 b0 CEIE 0 R/W R/W — R/W R/W R/W Address 019Bh Bit b7 Symbol TIE After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function CEIE Conflict error interrupt enable bit 0: Conflict error interrupt request disabled 1: Conflict error interrupt request enabled — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — RE Reception enable bit 0: Reception disabled 1: Reception enabled TE Transmission enable bit 0: Transmission disabled 1: Transmission enabled RIE Receive interrupt enable bit 0: Receive data full and overrun error interrupt requests disabled 1: Receive data full and overrun error interrupt requests enabled TEIE Transmit end interrupt enable bit 0: Transmit end interrupt request disabled 1: Transmit end interrupt request enabled TIE Transmit interrupt enable bit 0: Transmit data empty interrupt request disabled 1: Transmit data empty interrupt request enabled R/W R/W REJ09B0441-0010 Rev.0.10 Page 571 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.10 SS Status Register (SSSR) Address 019Ch Bit b7 Symbol TDRE After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b6 TEND 0 b5 RDRF 0 b4 — 0 b3 — 0 b2 ORER 0 b1 — 0 b0 CE 0 R/W R/W — R/W — R/W R/W Symbol Bit Name CE Conflict error flag (1) — ORER — — RDRF TEND Function 0: No conflict error 1: Conflict error (2) Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0: No overrun error Overrun error flag (1) 1: Overrun error (3) Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 TDRE Receive data register full flag (1, 4) 0: No data in the SSRDR register 1: Data in the SSRDR register 0: TDRE bit is set to 0 when transmitting the last bit of Transmit end flag (1, 5) transmit data 1: TDRE bit is set to 1 when transmitting the last bit of transmit data 0: No data transferred from registers SSTDR to Transmit data empty flag (1, 5, 6) SSTRSR 1: Data transferred from registers SSTDR to SSTRSR R/W Notes: 1. Writing 1 to the CE, ORER, RDRF, TEND, or TDRE bit is disabled. To set any of these bits to 0, first read 1 then write 0. 2. When the serial communication is started while the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode) and the MSS bit in the SSCRH register is set to 1 (operation as the master device), the CE bit is set to 1 if a low-level signal is applied to the SCS pin input. Refer to 27.5.4 SCS Pin Control and Arbitration for more information. When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode), the MSS bit in the SSCRH register is set to 0 (operation as a slave device) and the SCS pin input changes the level from low to high during transfer, the CE bit is set to 1. 3. Indicates when an overrun error occurs during reception and completes in error. If the next serial data receive operation is completed while the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the ORER bit is set to 1 (overrun error), receive operation is disabled while the bit remains 1. Transmit operation is also disabled while the MSS bit is set to 1 (operation as the master device). 4. The RDRF bit is set to 0 when reading the data from the SSRDR register. 5. Bits TEND and TDRE are set to 0 when writing data to the SSTDR register. 6. The TDRE bit is set to 1 when the TE bit in the SSER register is set to 1 (transmission enabled). To access the SSSR register successively, insert one or more NOP instructions between the instructions used for access. REJ09B0441-0010 Rev.0.10 Page 572 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.2.11 SS Mode Register 2 (SSMR2) Address 019Dh Bit b7 Symbol BIDE After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 SCKS 0 b5 CSS1 0 b4 CSS0 0 b3 SCKOS 0 b2 SOOS 0 b1 CSOS 0 b0 SSUMS 0 R/W R/W R/W R/W R/W R/W R/W Symbol Bit Name SSUMS SSU mode select bit (1) SCS pin open-drain output select bit SOOS Serial data open-drain output select bit (1) SCKOS SSCK pin open-drain output select bit CSS0 SCS pin select bit (2) CSS1 CSOS Function 0: Clock synchronous communication mode 1: 4-wire bus communication mode 0: CMOS output 1: N-channel open-drain output 0: CMOS output (5) 1: N-channel open-drain output 0: CMOS output 1: N-channel open-drain output b5 b4 b6 b7 SCKS BIDE SSCK pin select bit Bidirectional mode enable bit (1, 4) 0 0: Function as a port 0 1: Function as the SCS input pin 1 0: Function as the SCS output pin (3) 1 1: Function as the SCS output pin (3) 0: Function as a port 1: Function as the serial clock pin 0: Standard mode (communication using 2 pins of data input and data output) 1: Bidirectional mode (communication using 1 pin of data input and data output) R/W R/W Notes: 1. Refer to 27.3.2.1 Association between Data I/O Pins and SS Shift Register for information on the combinations of data I/O pins. 2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 when the SSUMS bit is set to 0 (clock synchronous communication mode). 3. This bit functions as the SCS input pin before starting transfer. 4. The BIDE bit is disabled when the SSUMS bit is set to 0 (clock synchronous communication mode). 5. When the SOOS bit is set to 0 (CMOS output), set the port direction register bits corresponding to pins SSI and SSO to 0 (input mode). REJ09B0441-0010 Rev.0.10 Page 573 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.3 27.3.1 Common Items for Multiple Modes Transfer Clock The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4) and an external clock. To use the synchronous serial communication unit, set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin. When the MSS bit in the SSCRH register is set to 1 (operation as the master device), an internal clock can be selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs a clock at the transfer rate selected by bits CKS0 to CKS2 in the SSCRH register. When the MSS bit in the SSCRH register is set to 0 (operation as a slave device), an external clock can be selected and the SSCK pin functions as input. 27.3.1.1 Association between Transfer Clock Polarity, Phase, and Data The association between the transfer clock polarity, phase, and data changes according to the combination of the SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register. Figure 27.2 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data. Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register. When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is set to 0, transfer is started from the MSB and proceeds to the LSB. REJ09B0441-0010 Rev.0.10 Page 574 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) • SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edges), and CPOS bit = 0 (“H” when clock stops) SSCK SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7 • SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edges) SSCK CPOS = 0 (“H” when clock stops) SSCK CPOS = 1 (“L” when clock stops) SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7 SCS • SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edges) SSCK CPOS = 0 (“H” when clock stops) SSCK CPOS = 1 (“L” when clock stops) SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7 SCS CPHS, CPOS: Bits in SSMR register SSUMS: Bit in SSMR2 register Figure 27.2 Association between Transfer Clock Polarity, Phase, and Transfer Data REJ09B0441-0010 Rev.0.10 Page 575 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.3.2 SS Shift Register (SSTRSR) The SSTRSR register is a shift register for transmitting and receiving serial data. When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to 0 (MSB first), bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register. When the MLS bit is set to 1 (LSB first), bit 7 in the SSTDR register is transferred to bit 0 in the SSTRSR register. 27.3.2.1 Association between Data I/O Pins and SS Shift Register The connection between the data I/O pins and the SSTRSR register (SS shift register) changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection also changes according to the BIDE bit in the SSMR2 register. Figure 27.3 shows the Association between Data I/O Pins and SSTRSR Register. • SSUMS = 0 (clock synchronous communication mode) • SSUMS = 1 (4-wire bus communication mode), BIDE = 0 (standard mode), and MSS = 1 (operation as the master device) SSTRSR register SSO SSTRSR register SSO SSI SSI • SSUMS = 1 (4-wire bus communication mode), BIDE = 0 (standard mode), and MSS = 0 (operation as a slave device) • SSUMS = 1 (4-wire bus communication mode) and BIDE = 1 (bidirectional mode) SSTRSR register SSO SSTRSR register SSO SSI SSI Figure 27.3 Association between Data I/O Pins and SSTRSR Register REJ09B0441-0010 Rev.0.10 Page 576 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.3.3 Interrupt Requests The synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial communication unit interrupt vector table, determining interrupt sources by flags is required. Table 27.3 shows the Interrupt Requests of Synchronous Serial Communication Unit. Table 27.3 Interrupt Requests of Synchronous Serial Communication Unit Interrupt Request Transmit data empty Transmit end Receive data full Overrun error Conflict error Abbreviation TXI TEI RXI OEI CEI Generation Condition TIE = 1 and TDRE = 1 TEIE = 1 and TEND = 1 RIE = 1 and RDRF = 1 RIE = 1 and ORER = 1 CEIE = 1 and CE = 1 CEIE, RIE, TEIE, TIE: Bits in SSER register ORER, RDRF, TEND, TDRE: Bits in SSSR register If the generation conditions in Table 27.3 are met, an interrupt request of the synchronous serial communication unit is generated. Set each interrupt source to 0 by the synchronous serial communication unit interrupt routine. However, bits TDRE and TEND are automatically set to 0 by writing transmit data to the SSTDR register and the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register. If the TDRE bit is further set to 0 (data not transferred from registers SSTDR to SSTRSR), additional 1 byte may be transmitted. REJ09B0441-0010 Rev.0.10 Page 577 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.3.4 Communication Modes and Pin Functions The synchronous serial communication unit switches the functions of the I/O pins in each communication mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register. Table 27.4 shows the Association between Communication Modes and I/O Pins. Table 27.4 Association between Communication Modes and I/O Pins Communication Mode Clock synchronous communication mode Bit Setting SSUMS BIDE MSS 0 Disabled 0 TE 0 1 RE 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 SSI Input − (1) Input Input − (1) Input − Output (1) Pin State SSO − (1) Output SSCK Input Input Input Output Output Output Input Input Input Output Output Output Input Input Output Output Output − Output (1) 1 0 1 4-wire bus communication mode 1 0 0 0 1 Output Input − (1) Input − Output (1) 1 0 1 Output Input − Input (1) 4-wire bus (bidirectional) communication mode (2) 1 1 0 1 0 1 0 1 − (1) Output Input Output Input Output − (1) − (1) − (1) Notes: 1. This pin can be used as a programmable I/O port. 2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode. SSUMS, BIDE: Bits in SSMR2 register MSS: Bit in SSCRH register TE, RE: Bits in SSER register REJ09B0441-0010 Rev.0.10 Page 578 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.4 27.4.1 Clock Synchronous Communication Mode Initialization in Clock Synchronous Communication Mode Figure 27.4 shows Initialization in Clock Synchronous Communication Mode. Before data transmission or reception, set the TE bit in the SSER register to 0 (transmission disabled) and the RE bit to 0 (reception disabled), and initialize the synchronous serial communication unit. Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format. Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR register. Start SSER register RE bit ← 0 TE bit ← 0 SSUMS bit ← 0 SSMR2 register SSMR register CPHS bit ← 0 CPOS bit ← 0 Set the MLS bit SSCRH register Set the MSS bit SCKS bit ← 1 Set the SOOS bit SSMR2 register SSCRH register Set bits CKS0 to CKS2 Set the RSSTP bit ORER bit ← 0 (1) SSSR register SSER register RE bit ← 1 (receive) TE bit ← 1 (transmit) Set bits RIE, TEIE, and TIE End Note: 1. Write 0 after reading 1 to set the ORER bit to 0. Figure 27.4 Initialization in Clock Synchronous Communication Mode REJ09B0441-0010 Rev.0.10 Page 579 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.4.2 Data Transmission Figure 27.5 shows an Example of Synchronous Serial Communication Unit Operation during Data Transmission (Clock Synchronous Communication Mode). During data transmission, the synchronous serial communication unit operates as described below. When the synchronous serial communication unit is set as the master device, it outputs a synchronous clock and data. When the synchronous serial communication unit is set as a slave device, it outputs data synchronized with the input clock. When the TE bit is set to 1 (transmission enabled) before writing the transmit data to the SSTDR register, the TDRE bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1 at this time, a TXI interrupt request is generated. When one frame of data is transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND bit in the SSSR register is set to 1 (TDRE bit is set to 1 when the last bit of the transmit data is transmitted) and the state is retained. When the TEIE bit in the SSER register is set to 1 (transmit-end interrupt request enabled) at this time, a TEI interrupt request is generated. The SSCK pin is fixed high after transmitend. Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm that the ORER bit is set to 0 before transmission. Figure 27.6 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode). The data transfer length can be set from 8 to 16 bits using the SSBR register. • SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at odd edges), CPOS = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) SSCK SSO b0 b1 b7 b0 b1 b7 1 frame TDRE bit in SSSR register 1 0 1 0 TXI interrupt request generation 1 frame TEI interrupt request generation TEND bit in SSSR register Program processing Write data to the SSTDR register. BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register SSUMS: Bit in SSMR2 register Figure 27.5 Example of Synchronous Serial Communication Unit Operation during Data Transmission (Clock Synchronous Communication Mode) REJ09B0441-0010 Rev.0.10 Page 580 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) Start Initialization (1) Read the TDRE bit in the SSSR register TDRE = 1? Yes No (1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0. Write transmit data to the SSTDR register Data transmission continues? No (3) Read the TEND bit in the SSSR register (3) When data transmission is completed, the TEND bit is set to 1. Set the TEND bit to 0 and the TE bit to 0 and end transmit mode. (2) Yes (2) Determine whether data transmission continues. TEND = 1? Yes SSSR register No TEND bit ← 0 (1) SSER register TE bit ← 0 End Note: 1. Write 0 after reading 1 to set the TEND bit to 0. Figure 27.6 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode) REJ09B0441-0010 Rev.0.10 Page 581 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.4.3 Data Reception Figure 27.7 shows an Example of Synchronous Serial Communication Unit Operation during Data Reception (Clock Synchronous Communication Mode). During data reception, the synchronous serial communication unit operates as described below. When the synchronous serial communication unit is set as the master device, it outputs a synchronous clock and inputs data. When the synchronous serial communication unit is set as a slave device, it inputs data synchronized with the input clock. When the synchronous serial communication unit is set as the master device, it outputs a receive clock and starts receiving by performing dummy read from the SSRDR register. After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI interrupt requests enabled) at this time, an RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (receive operation is completed after receiving 1 byte of data). The synchronous serial communication unit outputs a clock for receiving 8 bits of data and stops. After that, set the RE bit in the SSER register to 0 (reception disabled) and the RSSTP bit to 0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR register is read while the RE bit is set to 1 (reception enabled), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed. Confirm that the ORER bit is set to 0 before restarting reception. Figure 27.8 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode). The data transfer length can be set from 8 to 16 bits using the SSBR register. • SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) SSCK SSI b0 b7 b0 1 frame b7 b0 b7 1 frame RDRF bit in SSSR register 1 0 1 0 RXI interrupt request generation RXI interrupt request generation RXI interrupt request generation Dummy read the SSRDR register. Read data from the SSRDR register. Read data from the SSRDR register. RSSTP bit in SSCRH register Program processing Set the RSSTP bit to 1. BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register SSUMS: Bit in SSMR2 register Figure 27.7 Example of Synchronous Serial Communication Unit Operation during Data Reception (Clock Synchronous Communication Mode) REJ09B0441-0010 Rev.0.10 Page 582 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) Start Initialization (1) Dummy read the SSRDR register (2) Last data received? No Yes (1) After setting each register in the synchronous serial communication unit register, a dummy read from the SSRDR register is performed and the receive operation is started. (2) Determine whether it is the last 1 byte of data to be received. If so, set to stop after the data is received. Read the ORER bit in the SSSR register Yes (3) ORER = 1? No Read the RDRF bit in the SSSR register (3) If a receive error occurs, perform error processing (6) after reading the ORER bit. Then set the ORER bit to 0. Transmission/reception cannot be restarted while the ORER bit is set to 1. (4) No RDRF = 1? Yes (4) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. When the SSRDR register is read, the RDRF bit is automatically set to 0. Read receive data in the SSRDR register (5) SSCRH register RSSTP bit ← 1 (5) Before the last 1 byte of data is received, set the RSSTP bit to 1 and stop after the data is received. Read the ORER bit in the SSSR register (6) ORER = 1? No Yes Read the RDRF in the SSSR register (7) Confirm that the RDRF bit is set to 1. When the receive operation is completed, set the RSSTP bit to 0 and the RE bit to 0 before reading the last 1 byte of data. If the SSRDR register is read before setting the RE bit to 0, the receive operation is restarted again. Overrun error processing No RDRF = 1? (7) Yes SSCRH register RSSTP bit ← 0 SSER register RE bit ← 0 Read receive data in the SSRDR register End Figure 27.8 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode) REJ09B0441-0010 Rev.0.10 Page 583 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.4.3.1 Data Transmission/Reception Data transmission/reception is an operation combining data transmission and reception which were described earlier. Transmission/reception is started by writing data to the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped. Before switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (TE = RE = 1), set the TE bit to 0 and RE bit to 0 once. After confirming that the TEND bit is set to 0 (TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1. Figure 27.9 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode). The data transfer length can be set from 8 to 16 bits using the SSBR register. REJ09B0441-0010 Rev.0.10 Page 584 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) Start Initialization (1) Read the TDRE bit in the SSSR register TDRE = 1? Yes No (1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0. Write transmit data to the SSTDR register (2) Read the RDRF bit in the SSSR register No RDRF = 1? Yes Read receive data from the SSRDR register (2) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read receive data in the SSRDR register. When the SSRDR register is read, the RDRF bit is automatically set to 0. (3) Data transmission continues? No Yes (3) Determine whether data transmission continues. (4) Read the TEND bit in the SSSR register (4) When the data transmission is completed, the TEND bit in the SSSR register is set to 1. TEND = 1? Yes (5) SSSR register No TEND bit ← 0 (1) (5) Set the TEND bit to 0, and bits RE and TE (6) in the SSER register to 0 before ending transmit/receive mode. (6) SSER register RE bit ← 0 TE bit ← 0 End Note: 1. Write 0 after reading 1 to set the TEND bit to 0. Figure 27.9 Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode) REJ09B0441-0010 Rev.0.10 Page 585 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.5 Operation in 4-Wire Bus Communication Mode In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication. This mode includes bidirectional mode in which the data input line and data output line function as a single pin. The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the BIDE bit in the SSMR2 register. For details, refer to 27.3.2.1 Association between Data I/O Pins and SS Shift Register. In this mode, the clock polarity, phase, and data settings are performed by using bits CPOS and CPHS in the SSMR register. For details, refer to 27.3.1.1 Association between Transfer Clock Polarity, Phase, and Data. When this MCU is set as the master device, the chip select line controls output. When the synchronous serial communication unit is set as a slave device, the chip select line controls input. When it is set as the master device, the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as input by setting bits CSS1 and CSS0 in the SSMR2 register to 01b. In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed MSB first. REJ09B0441-0010 Rev.0.10 Page 586 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.5.1 Initialization in 4-Wire Bus Communication Mode Figure 27.10 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive operation, set the TE bit in the SSER register to 0 (transmission disabled), the RE bit in the SSER register to 0 (reception disabled), and initialize the synchronous serial communication unit. Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format. Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR register. Start SSER register RE bit ← 0 TE bit ← 0 SSUMS bit ← 1 SSMR2 register (1) SSMR register Set bits CPHS and CPOS MLS bits ← 0 (1) The MLS bit is set to 0 for MSB-first transfer. The clock polarity and phase are set by bits CPHS and CPOS. SSCRH register Set the MSS bit (2) Set the BIDE bit to 1 in bidirectional mode and set the I/O of the SCS pin by bits CSS0 and CSS1. SSMR2 register (2) SCKS bit ← 1 Set bits SOOS, CSS0 to CSS1, and BIDE SSCRH register Set bits CKS0 to CKS2 Set the RSSTP bit ORER bit ← 0 (1) SSSR register SSER register RE bit ← 1 (receive) TE bit ← 1 (transmit) Set bits RIE, TEIE, and TIE End Note: 1. Write 0 after reading 1 to set the ORER bit to 0. Figure 27.10 Initialization in 4-Wire Bus Communication Mode REJ09B0441-0010 Rev.0.10 Page 587 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.5.2 Data Transmission Figure 27.11 shows an Example of Synchronous Serial Communication Unit Operation during Data Transmission (4-Wire Bus Communication Mode). During the data transmit operation, the synchronous serial communication unit operates as described below. When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a slave device, it outputs data in synchronization with the input clock while the SCS pin is low-input state. When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmission enabled), the TDRE bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1 at this time, the TXI interrupt request is generated. After one frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1, TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set to 1) and the state is retained. When the TEIE bit in the SSER register is set to 1 (transmit-end interrupt request enabled) at this time, the TEI interrupt request is generated. The SSCK pin remains high after transmitend and the SCS pin is held high. When transmitting continuously while the SCS pin is held low, write the next transmit data to the SSTDR register before transmitting the 8th bit. Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm that the ORER bit is set to 0 before transmission. In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while the SCS pin is placed in high-impedance state when operating as the master device. The SSI pin is placed in high-impedance state while the SCS pin is high-input state when operating as a slave device. The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 27.6 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)). The data transfer length can be set from 8 to 16 bits using the SSBR register. REJ09B0441-0010 Rev.0.10 Page 588 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) • CPHS bit = 0 (data change at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) High-impedance SCS (output) SSCK SSO b7 b6 1 frame b0 b7 b6 1 frame b0 TDRE bit in SSSR register 1 0 1 0 Write data to the SSTDR register. TXI interrupt request generation TEI interrupt request generation TXI interrupt request generation TEND bit in SSSR register Program processing • CPHS bit = 1 (data change at even edges). CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) High-impedance SCS (output) SSCK SSO b7 b6 1 frame b0 b7 1 frame b6 b0 TDRE bit in SSSR register 1 0 1 0 Write data to the SSTDR register. TXI interrupt request generation TEI interrupt request generation TXI interrupt request generation TEND bit in SSSR register Program processing BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register Figure 27.11 Example of Synchronous Serial Communication Unit Operation during Data Transmission (4-Wire Bus Communication Mode) REJ09B0441-0010 Rev.0.10 Page 589 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.5.3 Data Reception Figure 27.12 shows an Example of Synchronous Serial Communication Unit Operation during Data Reception (4-Wire Bus Communication Mode). During data reception, the synchronous serial communication unit operates as described below. When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is set as a slave device, it outputs data synchronized with the input clock while the SCS pin is low-input state. When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a dummy read from the SSRDR register. After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI interrupt requests enabled) at this time, an RXI interrupt request is generated. When the SSRDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (receive operation is completed after receiving 1-byte data). The synchronous serial communication unit outputs a clock for receiving 8 bits of data and stops. After that, set the RE bit in the SSER register to 0 (reception disabled) and the RSSTP bit to 0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR register is read while the RE bit is set to 1 (reception enabled), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed. Confirm that the ORER bit is set to 0 before restarting reception. The timing at which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the SSMR register. Figure 27.12 shows when bits RDRF and ORER are set to 1. When the CPHS bit is set to 1 (data download at odd edges), bits RDRF and ORER are set to 1 at some point during the frame. The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 27.8 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)). The data transfer length can be set from 8 to 16 bits using the SSBR register. REJ09B0441-0010 Rev.0.10 Page 590 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) • CPHS bit = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) SCS (output) High-impedance SSCK SSI b7 1 frame b0 b7 1 frame b0 b7 b0 RDRF bit in SSSR register 1 0 1 0 Dummy read the SSRDR register. Read data from the SSRDR register. RXI interrupt request generation RXI interrupt request generation RSSTP bit in SSCRH register RXI interrupt request generation Program processing Set the RSSTP bit to 1. Read data from the SSRDR register. • CPHS bit = 1 (data download at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) High-impedance SCS (output) SSCK SSI b7 1 frame b0 b7 1 frame b0 b7 b0 RDRF bit in SSSR register 1 0 1 0 Dummy read the SSRDR register. BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register RXI interrupt request generation RXI interrupt request generation RSSTP bit in SSCRH register RXI interrupt request generation Program processing Read data from the SSRDR register. Set the RSSTP bit to 1. Read data from the SSRDR register. Figure 27.12 Example of Synchronous Serial Communication Unit Operation during Data Reception (4-Wire Bus Communication Mode) REJ09B0441-0010 Rev.0.10 Page 591 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.5.4 SCS Pin Control and Arbitration When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode) and the CSS1 bit is set to 1 (function as the SCS output pin), set the MSS bit in the SSCRH register to 1 (operation as the master device) and check the arbitration of the SCS pin before starting serial transfer. If the synchronous serial communication unit detects that the synchronized internal SCS signal is held low in this period, the CE bit in the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operation as a slave device). Figure 27.13 shows the Arbitration Check Timing. Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error) before starting transmission. SCS input Internal SCS (synchronization) MSS bit in SSCRH register 1 0 Transfer start CE Write data to the SSTDR register. High-impedance SCS output Maximum time of SCS internal synchronization During arbitration detection Figure 27.13 Arbitration Check Timing REJ09B0441-0010 Rev.0.10 Page 592 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 27. Synchronous Serial Communication Unit (SSU) 27.6 Notes on Synchronous Serial Communication Unit To use the synchronous serial communication unit, set the IICSEL bit in the SSUIICSR register to 0 (SSU function selected). REJ09B0441-0010 Rev.0.10 Page 593 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28. I2C bus Interface The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips I2C bus. 28.1 Introduction Table 28.1 lists the I2C bus Interface Specifications. Figure 28.1 shows a Block Diagram of I2C bus interface, and Figure 28.2 shows the External Circuit Connection Example of Pins SCL and SDA. Table 28.2 lists the I2C bus Interface Pin Configuration. * I2C bus is a trademark of Koninklijke Philips Electronics N. V. Table 28.1 I2C bus Interface Specifications Item Specification Communication formats • I2C bus format - Selectable as master/slave device - Continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) - Start/stop conditions are automatically generated in master mode. - Automatic loading of the acknowledge bit during transmission - Bit synchronization/wait function (In master mode, the state of the SCL signal is monitored per bit and the timing is synchronized automatically. If the transfer is not possible yet, the SCL signal goes low and the interface stands by.) - Support for direct drive of pins SCL and SDA (N-channel open-drain output) • Clock synchronous serial format - Continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) I/O pins SCL (I/O): Serial clock I/O pin SDA (I/O): Serial data I/O pin Transfer clocks • When the MST bit in the ICCR1 register is set to 0 External clock (input from the SCL pin) • When the MST bit in the ICCR1 register is set to 1 Internal clock selected by bits CKS0 to CKS3 in the ICCR1 register (output from the SCL pin) Receive error detection • Overrun error detection (clock synchronous serial format) Indicates an overrun error during reception. When the last bit of the next unit of data is received while the RDRF bit in the ICSR register is set to 1 (data in the ICDRR register), the AL bit is set to 1. 2C bus format .................................. 6 sources (1) Interrupt sources •I Transmit data empty (including when slave address matches), transmit end, receive data full (including when slave address matches), arbitration lost, NACK detection, and stop condition detection • Clock synchronous serial format ...... 4 sources (1) Transmit data empty, transmit end, receive data full, and overrun error 2C bus format Selectable functions •I - Selectable output level for the acknowledge signal during reception • Clock synchronous serial format - Selectable MSB first or LSB first as the data transfer direction Note: 1. All sources use a single interrupt vector table for the I2C bus interface. REJ09B0441-0010 Rev.0.10 Page 594 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface f1 Transfer clock generation circuit Output control Transmit/receive control circuit Noise canceller ICDRT register Output control SAR register ICDRS register Data bus SCL ICCR1 register ICCR2 register ICMR register SDA Noise canceller Address comparison circuit ICDRR register Bus state determination circuit Arbitration determination circuit ICIER register ICSR register Interrupt generation circuit Interrupt request (TXI, TEI, RXI, STPI, NAKI) Figure 28.1 Block Diagram of I2C bus interface Table 28.2 I2C bus Interface Pin Configuration Pin Name SCL SDA Assigned Pin P11_0 P11_2 Clock I/O Data I/O Function REJ09B0441-0010 Rev.0.10 Page 595 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface VCC VCC SCL SCL input SCL output SCL SDA SDA input SDA output SCL (Master) SCL input SCL output SCL input SCL output SCL SDA SDA SDA input SDA output (Slave 1) SDA input SDA output (Slave 2) SDA Figure 28.2 External Circuit Connection Example of Pins SCL and SDA REJ09B0441-0010 Rev.0.10 Page 596 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2 28.2.1 Registers Module Standby Control Register (MSTCR) b6 b5 b4 b3 MSTTRG MSTTRC MSTTRD MSTIIC 0 0 0 0 b2 — 0 b1 — 0 b0 — 0 R/W — Address 0008h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — 0: Active MSTIIC SSU, I2C bus standby bit 1: Standby (1) MSTTRD Timer RD standby bit 0: Active 1: Standby (2) MSTTRC Timer RC standby bit 0: Active 1: Standby (3) MSTTRG Timer RG standby bit 0: Active 1: Standby (4) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. R/W R/W R/W R/W — Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. 28.2.2 SSU/IIC Pin Select Register (SSUIICSR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 IICSEL 0 R/W R/W — Address 018Ch Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol IICSEL — — — — — — — Bit Name SSU/I2C bus switch bit Function 0: SSU function selected 1: I2C bus function selected Nothing is assigned. If necessary, set to 0. When read, the content is 0. REJ09B0441-0010 Rev.0.10 Page 597 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.3 IIC bus Transmit Data Register (ICDRT) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W R/W Address 0194h Bit b7 Symbol — After Reset 1 Bit b7 to b0 Function This register stores transmit data. When the ICDRS register is detected as empty, the stored transmit data is transferred to the ICDRS register and transmission starts. When the next transmit data is written to the ICDRT register during the data transmission from the ICDRS register, continuous transmission is enabled. When the MLS bit in the ICMR register is set to 1 (data transfer with LSB first), the MSB-LSB inverted data is read after writing to the ICDRT register. 28.2.4 IIC bus Receive Data Register (ICDRR) b6 — 1 b5 — 1 b4 — 1 b3 — 1 b2 — 1 b1 — 1 b0 — 1 R/W R Address 0196h Bit b7 Symbol — After Reset 1 Bit b7 to b0 Function This register stores receive data. When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR register and the next receive operation is enabled. REJ09B0441-0010 Rev.0.10 Page 598 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.5 IIC bus Control Register 1 (ICCR1) b6 RCVD 0 b5 MST 0 b4 TRS 0 b3 CKS3 0 b2 CKS2 0 b1 CKS1 0 Function b3 b2 b1 b0 Address 0198h Bit b7 Symbol ICE After Reset 0 Bit b0 b1 b2 b3 b0 CKS0 0 R/W R/W R/W R/W R/W Symbol Bit Name CKS0 Transmit clock select bit 3 to 0 (1) CKS1 CKS2 CKS3 0 0 0 0: f1/28 0 0 0 1: f1/40 0 0 1 0: f1/48 0 0 1 1: f1/64 0 1 0 0: f1/80 0 1 0 1: f1/100 0 1 1 0: f1/112 0 1 1 1: f1/128 1 0 0 0: f1/56 1 0 0 1: f1/80 1 0 1 0: f1/96 1 0 1 1: f1/128 1 1 0 0: f1/160 1 1 0 1: f1/200 1 1 1 0: f1/224 1 1 1 1: f1/256 b5 b4 b4 b5 b6 TRS MST RCVD Transmission/reception select bit (2, 3, 6) Master/slave select bit (5, 6) Reception disable bit b7 ICE I2C bus interface enable bit 0 0: Slave Receive Mode (4) 0 1: Slave Transmit Mode 1 0: Master Receive Mode 1 1: Master Transmit Mode After reading the ICDRR register while the TRS bit is set to 0, 0: Next receive operation continues 1: Next receive operation disabled 0: This module is halted (Pins SCL and SDA are set to the port function) 1: This module is enabled for transfer operations (Pins SCL and SDA are in the bus drive state) R/W R/W R/W R/W Notes: 1. Set according to the necessary transfer rate in master mode. Refer to Table 28.3 Transfer Rate Examples for the transfer rate. This bit is used for maintaining the setup time in transmit mode of slave mode. The time is 10Tcyc when the CKS3 bit is set to 0 and 20Tcyc when the CKS3 bit is set to 1. (1Tcyc = 1/f1(s)) 2. Rewrite the TRS bit between transfer frames. 3. When the first 7 bits after the start condition in slave receive mode match the slave address set in the SAR register and the 8th bit is set to 1, the TRS bit is set to 1. 4. In master mode with the I2C bus format, if arbitration is lost, bits MST and TRS are set to 0 and the IIC enters slave receive mode. 5. When an overrun error occurs in master receive mode with the clock synchronous serial format, the MST bit is set to 0 and the I2C bus enters slave receive mode. 6. In multimaster operation, use the MOV instruction to set bits TRS and MST. REJ09B0441-0010 Rev.0.10 Page 599 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.6 IIC bus Control Register 2 (ICCR2) b6 SCP 1 b5 SDAO 1 b4 SDAOP 1 b3 SCLO 1 b2 — 1 b1 IICRST 0 b0 — 1 R/W — R/W Address 0199h Bit b7 Symbol BBSY After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 1. IICRST I2C bus control block reset bit When hang-up occurs due to communication failure during the I2C bus interface operation, writing 1 resets the control block of the I2C bus interface without setting ports or initializing registers. — Nothing is assigned. If necessary, set to 0. When read, the content is 1. SCLO SCL monitor flag 0: SCL pin is set to low 1: SCL pin is set to high SDAOP SDAO write protect bit When rewriting the SDAO bit, write 0 simultaneously (1). When read, the content is 1. SDAO SDA output value control bit When read 0: SDA pin output is held low 1: SDA pin output is held high When written (1, 2) 0: SDA pin output is changed to low 1: SDA pin output is changed to high-impedance (High-level output via an external pull-up resistor) SCP Start/stop condition generation When writing to the to BBSY bit, write 0 simultaneously (3). disable bit When read, the content is 1. Writing 1 is invalid. BBSY Bus busy bit (4) When read: 0: Bus is released (SDA signal changes from low to high while SCL signal is held high) 1: Bus is occupied (SDA signal changes from high to low while SCL signal is held high) When written (3): 0: Stop condition generated 1: Start condition generated — R R/W R/W R/W R/W Notes: 1. When rewriting the SDAO bit, write 0 to the SDAOP bit simultaneously using the MOV instruction. 2. Do not write to the SDAO bit during a transfer operation. 3. Enabled in master mode. When writing to the BBSY bit, write 0 to the SCP bit simultaneously using the MOV instruction. Execute the same way when a start condition is regenerated. 4. Disabled when the clock synchronous serial format is used. REJ09B0441-0010 Rev.0.10 Page 600 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.7 IIC bus Mode Register (ICMR) b6 WAIT 0 b5 — 0 b4 — 1 b3 BCWP 1 b2 BC2 0 b1 BC1 0 b0 BC0 0 R/W R/W R/W R/W Address 019Ah Bit b7 Symbol MLS After Reset 0 Bit b0 b1 b2 Symbol Bit Name BC0 Bit counter 2 to 0 BC1 BC2 Function I2C bus format (Read: Number of remaining transfer bits; Write: Number of next transfer data bits). (1, 2) b2 b1 b0 0 0 0: 9 bits (3) 0 0 1: 2 bits 0 1 0: 3 bits 0 1 1: 4 bits 1 0 0: 5 bits 1 0 1: 6 bits 1 1 0: 7 bits 1 1 1: 8 bits Clock synchronous serial format (Read: Number of remaining transfer bits; Write: Always 000b). b2 b1 b0 b3 b4 b5 b6 BCWP — — WAIT b7 MLS 0 0 0: 8 bits 0 0 1: 1 bit 0 1 0: 2 bits 0 1 1: 3 bits 1 0 0: 4 bits 1 0 1: 5 bits 1 1 0: 6 bits 1 1 1: 7 bits BC write protect bit When rewriting bits BC0 to BC2, write 0 simultaneously. (2, 4) When read, the content is 1. Nothing is assigned. If necessary, set to 0. When read, the content is 1. Reserved bit Set to 0. 0: No wait states Wait insertion bit (5) (Data and the acknowledge bit are transferred successively) 1: Wait state (After the clock of the last data bit falls, a low-level period is extended for two transfer clocks) MSB first/LSB first select 0: Data transfer with MSB first (6) bit 1: Data transfer with LSB first R/W — R/W R/W R/W Notes: 1. Rewrite between transfer frames. When writing values other than 000b, write when the SCL signal is low. 2. When writing to bits BC0 to BC2, write 0 to the BCWP bit simultaneously using the MOV instruction. 3. After data including the acknowledge bit is transferred, these bits are automatically set to 000b. When a start condition is detected, these bits are automatically set to 000b. 4. Do not rewrite when the clock synchronous serial format is used. 5. The setting value is valid in master mode with the I2C bus format. It is invalid in slave mode with the I2C bus format or when the clock synchronous serial format is used. 6. Set to 0 when the I2C bus format is used. REJ09B0441-0010 Rev.0.10 Page 601 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.8 IIC bus Interrupt Enable Register (ICIER) b6 TEIE 0 b5 RIE 0 b4 NAKIE 0 b3 STIE 0 b2 ACKE 0 b1 ACKBR 0 b0 ACKBT 0 R/W R/W R Address 019Bh Bit b7 Symbol TIE After Reset 0 Bit b0 b1 Symbol Bit Name ACKBT Transmit acknowledge select bit ACKBR Receive acknowledge bit b2 ACKE Acknowledge bit detection select bit b3 b4 STIE NAKIE Stop condition detection interrupt enable bit NACK receive interrupt enable bit b5 RIE Receive interrupt enable bit b6 b7 TEIE TIE Transmit end interrupt enable bit Transmit interrupt enable bit Function 0: In receive mode, 0 is transmitted as the acknowledge bit. 1: In receive mode, 1 is transmitted as the acknowledge bit. 0: In transmit mode, the acknowledge bit received from the receive device is set to 0. 1: In transmit mode, the acknowledge bit received from the receive device is set to 1. 0: Content of the receive acknowledge bit is ignored and continuous transfer is performed. 1: When the receive acknowledge bit is set to 1, continuous transfer is halted. 0: Stop condition detection interrupt request disabled 1: Stop condition detection interrupt request enabled (2) 0: NACK receive interrupt request and arbitration lost/ overrun error interrupt request disabled 1: NACK receive interrupt request and arbitration lost/ overrun error interrupt request (1) 0: Receive data full and overrun error interrupt request disabled 1: Receive data full and overrun error interrupt request enabled (1) 0: Transmit end interrupt request disabled 1: Transmit end interrupt request enabled 0: Transmit data empty interrupt request disabled 1: Transmit data empty interrupt request enabled R/W R/W R/W R/W R/W R/W Notes: 1. An overrun error interrupt request is generated when the clock synchronous format is used. 2. Set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit in the ICSR register is set to 0. REJ09B0441-0010 Rev.0.10 Page 602 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.9 IIC bus Status Register (ICSR) b6 TEND 0 b5 RDRF 0 b4 NACKF 0 b3 STOP X b2 AL 0 b1 AAS 0 b0 ADZ 0 R/W R/W R/W Address 019Ch Bit b7 Symbol TDRE After Reset 0 Bit b0 b1 Symbol Bit Name ADZ General call address recognition flag (1, 2) AAS Slave address recognition flag (1) b2 AL Arbitration lost flag/ overrun error flag (1) b3 b4 b5 b6 STOP Stop condition detection flag (1) NACKF No acknowledge detection flag (1, 4) RDRF Receive data register full flag (1, 5) TEND Transmit end flag (1, 6) b7 TDRE Transmit data empty flag (1, 6) Function This flag is set to 1 when a general call address is detected. This flag is set to 1 when the first frame immediately after the start condition matches bits SVA0 to SVA6 in the SAR register in slave receive mode (slave address detection and general call address detection). I2C bus format: This flag indicates that arbitration has been lost in master mode. This flag is set to 1 (3) when: • The internal SDA signal and SDA pin level do not match at the rising edge of the SCL signal in master transmit mode • The SDA pin is held high at start condition detection in master transmit/receive mode Clock synchronous format: This flag indicates an overrun error. This flag is set to 1 when: • The last bit of the next unit of data is received while the RDRF bit is set to 1 This flag is set to 1 when a stop condition is detected after the frame is transferred. This flag is set to 1 when no ACKnowledge is detected from the receive device after transmission. This flag is set to 1 when receive data is transferred from registers ICDRS to ICDRR. I2C bus format: This flag is set to 1 at the rising edge of the 9th clock cycle of the SCL signal while the TDRE bit is set to 1. Clock synchronous format: This flag is set to 1 when the last bit of the transmit frame is transmitted. This flag is set to 1 when: • Data is transferred from registers ICDRT to ICDRS and the CDRT register is empty • The TRS bit in the ICCR1 register is set to 1 (transmit mode) • A start condition is generated (including retransmission) • Slave receive mode is changed to slave transmit mode R/W R/W R/W R/W R/W R/W Notes: 1. Each bit is set to 0 by reading 1 before writing 0. 2. This flag is enabled in slave receive mode with the I2C bus format. 3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface monitors the SDA pin and the data which the I2C bus Interface transmits is different, the AL flag is set to 1 and the bus is occupied by another master. 4. The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1, transfer is halted). 5. The RDRF bit is set to 0 when data is read from the ICDRR register. 6. Bits TEND and TDRE are set to 0 when data is written to the ICDRT register. When accessing the ICSR register successively, insert one or more NOP instructions between the instructions used for access. REJ09B0441-0010 Rev.0.10 Page 603 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.2.10 Slave Address Register (SAR) Address 019Dh Bit b7 Symbol SVA6 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 b6 SVA5 0 b5 SVA4 0 b4 SVA3 0 b3 SVA2 0 b2 SVA1 0 b1 SVA0 0 b0 FS 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Symbol Bit Name FS Format select bit SVA0 SVA1 SVA2 SVA3 SVA4 SVA5 SVA6 Slave address 6 to 0 Function 0: I2C bus format 1: Clock synchronous serial format Set an address different from that of the other slave devices connected to the I2C bus. When the 7 high-order bits of the first frame transmitted after the start condition match bits SVA0 to SVA6 in slave mode of the I2C bus format, the MCU operates as a slave device. 28.2.11 IIC bus Shift Register (ICDRS) Bit Symbol b7 — b6 — b5 — b4 — b3 — b2 — b1 — b0 — Bit b7 to b0 Function This register transmits and receives data. During transmission, data is transferred from registers ICRDT to ICDRS and transmitted from the SDA pin. During reception, data is transferred from registers ICDRS to the ICDRR after 1 byte of data is received. R/W — REJ09B0441-0010 Rev.0.10 Page 604 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.3 28.3.1 Common Items for Multiple Modes Transfer Clock When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin. Table 28.3 lists Transfer Rate Examples. Table 28.3 Transfer Rate Examples ICCR1 Register Transfer Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz 0 0 0 0 f1/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 f1/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 0 f1/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 f1/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 1 0 0 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 f1/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 1 0 f1/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 0 f1/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz 1 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 0 f1/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 f1/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz 1 f1/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz 1 0 f1/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz 1 f1/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz REJ09B0441-0010 Rev.0.10 Page 605 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.3.2 I 2C Interrupt Requests The bus interface has six interrupt requests when the I2C bus format is used and four interrupt requests when the clock synchronous serial format is used. Table 28.4 lists the Interrupt Requests of I2C bus Interface. Because these interrupt requests are allocated at the I2C bus interface interrupt vector table, the source must be determined bit by bit. Table 28.4 Interrupt Requests of I2C bus Interface Format Interrupt Request Transmit data empty Transmit end Receive data full Stop condition detection NACK detection Arbitration lost/overrun error TXI TEI RXI STPI NAKI Generation Condition TIE = 1 and TDRE = 1 TEIE = 1 and TEND = 1 RIE = 1 and RDRF = 1 STIE = 1 and STOP = 1 NAKIE = 1 and AL = 1 (or NAKIE = 1 and NACKF = 1) I2C bus Enabled Enabled Enabled Enabled Enabled Enabled Clock Synchronous Serial Enabled Enabled Enabled Disabled Disabled Enabled STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register When generation conditions listed in Table 28.4 are met, an interrupt request of the I2C bus interface is generated. Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. However, bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is automatically set to 0 by reading the ICDRR register. In particular, the TDRE bit is set to 0 when transmit data is written to the ICDRT register and set to 1 when data is transferred from the ICDRT register to the ICDRS register. If the TDRE bit is further set to 0, additional 1 byte may be transmitted. Also, set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit is set to 0. REJ09B0441-0010 Rev.0.10 Page 606 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.4 28.4.1 I2C bus Interface Mode I2C bus Format When the FS bit in the SAR register is set to 0, the I2C bus format is used for communication. Figure 28.3 shows the I2C bus Format and Bus Timing. The first frame following the start condition consists of 8 bits. (1) I2C bus format (a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Number of transfer bits (n = 1 to 8) Number of transfer frames (m = 1 or more) (b) I2C bus format When Start Condition is Retransmitted (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 Upper: Number of transfer bits (n1, n2 = 1 to 8) Lower: Number of transfer frames (m1, m2 = 1 or more) (2) I2C bus timing SDA SCL 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 S SLA R/W A DATA A Legend: S : Start condition The master device changes the SDA signal from high to low while the SCL signal is held high. SLA : Slave address R/W : Indicates the direction of data transmission/reception Data is transmitted when: R/W value is 1: From the slave device to the master device R/W value is 0: From the master device to the slave device A : Acknowledge The receive device sets the SDA signal to low. DATA : Transmit/receive data P : Stop condition The master device changes the SDA signal from low to high while the SCL signal is held high. DATA A P Figure 28.3 I2C bus Format and Bus Timing REJ09B0441-0010 Rev.0.10 Page 607 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 28.4 and 28.5 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode). The transmit procedure and operation in master transmit mode are as follows: (1) Set the STOP bit in the ICSR register to 0 for initialization, and set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then, set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). (2) After confirming that the bus is released by reading the BBSY bit in the ICCR2 register, set bits TRS and MST in the ICCR1 register to master transmit mode. Then, write 1 to the BBSY bit and 0 to the SCP bit with the MOV instruction (start condition generated). This will generate a start condition. (3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 again. (4) When 1 byte of data transmission is completed while the TDRE bit is set to 1, the TEND bit in the ICSR register is set to 1 at the rising edge of the 9th clock cycle of the transmit clock. After confirming that the slave device is selected by reading the ACKBR bit in the ICIER register, write the 2nd byte of data to the ICDRT register. Since the slave device is not acknowledged when the ACKBR bit is set to 1, generate a stop condition. Stop condition generation is enabled by writing 0 to the BBSY bit and 0 to the SCP bit with the MOV instruction. The SCL signal is fixed low until data is ready or a stop condition is generated. (5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1. (6) When the number of bytes to be transmitted is written to the ICDRT register, wait until the TEND bit is set to 1 while the TDRE bit is set to 1. Or wait for NACK (NACKF bit in ICSR register = 1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1, transfer is halted). Then, generate a stop condition before setting the TEND bit or the NACKF bit to 0. (7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode. REJ09B0441-0010 Rev.0.10 Page 608 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 SDA (master output) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 Slave address SDA (slave output) R/W A TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRT register Address + R/W Data 1 Data 2 ICDRS register Address + R/W Data 1 Program processing (2) Instruction for start condition generation (3) Write data to the ICDRT register (1st byte). (4) Write data to the ICDRT register (5) Write data to the ICDRT register (3rd byte). (2nd byte). Figure 28.4 Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1) SCL (master output) 9 1 2 3 4 5 6 7 8 9 SDA (master output) b7 b6 b5 b4 b3 b2 b1 b0 SDA (slave output) A A/A TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRT register Data n ICDRS register Data n Program processing (3) Write data to the ICDRT register. (6) Generate a stop condition and set the TEND bit to 0. (7) Set to slave receive mode. Figure 28.5 Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2) REJ09B0441-0010 Rev.0.10 Page 609 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figures 28.6 and 28.7 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode). The receive procedure and operation in master receive mode are as follows: (1) After setting the TEND bit in the ICSR register to 0, set the TRS bit in the ICCR1 register to 0 to switch from master transmit mode to master receive mode. Then set the TDRE bit in the ICSR register to 0. (2) Dummy reading the ICDRR register starts receive operation. The receive clock is output in synchronization with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock. (3) When one frame of data reception is completed, the RDRF bit in the ICSR register is set to 1 at the rising edge of the 9th clock cycle of the receive clock. If the ICDRR register is read at this time, the received data can be read and the RDRF bit is set to 0 simultaneously. (4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If reading the ICDRR register is delayed by another process and the 8th clock cycle falls while the RDRF bit is set to 1, the SCL signal is fixed low until the ICDRR register is read. (5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (next receive operation disabled) before reading the ICDRR register, stop condition generation is enabled after the next receive operation. (6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop condition. (7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (next receive operation continues). (8) Return to slave receive mode. REJ09B0441-0010 Rev.0.10 Page 610 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface Master transmit mode SCL (master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 1 SDA (master output) A SDA (slave output) A b7 b6 b5 b4 b3 b2 b1 b0 b7 TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 1 0 1 0 TRS bit in ICCR1 register RDRF bit in ICSR register ICDRS register Data 1 ICDRR register Data 1 Program processing (1) Set the TDRE bit to 0 after setting bits TEND and TRS to 0. (2) Read the ICDRR register. (3) Read the ICDRR register. Figure 28.6 Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1) REJ09B0441-0010 Rev.0.10 Page 611 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface SCL (master output) 9 1 2 3 4 5 6 7 8 9 SDA (master output) A A/A SDA (slave output) b7 b6 b5 b4 b3 b2 b1 b0 RDRF bit in ICSR register 1 0 1 0 RCVD bit in ICCR1 register ICDRS register Data n-1 Data n ICDRR register Data n-1 Data n Program processing (6) Generate a stop condition. (5) Read the ICDRR register after setting the RCVD bit to 1. (7) Set the RCVD bit to 0 after reading the ICDRR register. (8) Set to slave receive mode. Figure 28.7 Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2) REJ09B0441-0010 Rev.0.10 Page 612 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal. Figures 28.8 and 28.9 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode). The transmit procedure and operation in slave transmit mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled), and set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Then, set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the first frame after detecting the start condition, the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle. If the 8th bit of data (R/W) is 1 at this time, bits TRS and TDRE in the ICSR register are set to 1, and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by writing transmit data to the ICDRT register every time the TDRE bit is set to 1. (3) When the TDRE bit in the ICDRT register is set to 1 after the last transmit data is written to the ICDRT register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the TEND bit is set to 1, set the TEND bit to 0. (4) Set the TRS bit to 0 and dummy read the ICDRR register to end the process. This will release the SCL signal. (5) Set the TDRE bit to 0. REJ09B0441-0010 Rev.0.10 Page 613 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface Slave receive mode SCL (master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 9 1 SDA (master output) A SCL (slave output) SDA (slave output) A b7 b6 b5 b4 b3 b2 b1 b0 b7 TDRE bit in ICSR register 1 0 1 0 1 0 TEND bit in ICSR register TRS bit in ICCR1 register ICDRT register Data 1 Data 2 Data 3 ICDRS register Data 1 Data 2 ICDRR register Program processing (1) Write data to the ICDRT register (data 1). (2) Write data to the ICDRT register (data 2). (2) Write data to the ICDRT register (data 3). Figure 28.8 Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1) REJ09B0441-0010 Rev.0.10 Page 614 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface Slave receive mode Slave transmit mode SCL (master output) 9 1 2 3 4 5 6 7 8 9 SDA (master output) A A SCL (slave output) SDA (slave output) b7 b6 b5 b4 b3 b2 b1 b0 TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 1 0 TRS bit in ICCR1 register ICDRT register Data n ICDRS register Data n ICDRR register Program processing (3) Set the TEND bit to 0. (4) Dummy read the ICDRR register after setting the TRS bit to 0. (5) Set the TDRE bit to 0. Figure 28.9 Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2) REJ09B0441-0010 Rev.0.10 Page 615 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 28.10 and 28.11 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode). The receive procedure and operation in slave receive mode are as follows: (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled), and set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Then, set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the first frame after detecting the start condition, the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, dummy read the ICDRR register (the read data is unnecessary because it indicates the slave address and R/W). (3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is set to 1, the SCL signal is fixed low until the ICDRR register is read. The setting change of the acknowledge signal returned to the master device before reading the ICDRR register takes affect from the following transfer frame. (4) Reading the last byte is also performed by reading the ICDRR register. REJ09B0441-0010 Rev.0.10 Page 616 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface SCL (master output) 9 1 2 3 4 5 6 7 8 9 1 SDA (master output) b7 b6 b5 b4 b3 b2 b1 b0 b7 SCL (slave output) SDA (slave output) A A RDRF bit in ICSR register 1 0 ICDRS register Data 1 Data 2 ICDRR register Data 1 Program processing (2) Dummy read the ICDRR register. (2) Read the ICDRR register. Figure 28.10 Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (1) SCL (master output) 9 1 2 3 4 5 6 7 8 9 SDA (master output) b7 b6 b5 b4 b3 b2 b1 b0 SCL (slave output) SDA (slave output) A A RDRF bit in ICSR register 1 0 ICDRS register Data 1 Data 2 ICDRR register Data 1 Program processing (3) Set the ACKBT bit to 1. (3) Read the ICDRR register. (4) Read the ICDRR register. Figure 28.11 Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (2) REJ09B0441-0010 Rev.0.10 Page 617 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.5 28.5.1 Clock Synchronous Serial Mode Clock Synchronous Serial Format When the FS bit in the SAR register is set to 1, the clock synchronous serial format is used for communication. Figure 28.12 shows the Transfer Format of Clock Synchronous Serial Format. When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin. When the MST bit is set to 0, the external clock is input. The transfer data is output between successive falling edges of the SCL clock, and data is determined at the rising edge of the SCL clock. MSB first or LSB first can be selected as the order of the data transfer by setting the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register during transfer standby. SCL SDA b0 b1 b2 b3 b4 b5 b6 b7 Figure 28.12 Transfer Format of Clock Synchronous Serial Format REJ09B0441-0010 Rev.0.10 Page 618 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.5.2 Transmit Operation In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 28.13 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode). The transmit procedure and operation in transmit mode are as follows: (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the ICCR1 register and the MST bit (initial setting). (2) Set the TRS bit in the ICCR1 register to 1 to select transmit mode. This will set the TDRE bit in the ICSR register is to 1. (3) After confirming that the TDRE bit is set to 1, write transmit data to the ICDRT register. Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1. Continuous transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. To switch from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1. SCL 1 2 7 8 1 7 8 1 SDA (output) b0 b1 b6 b7 b0 b6 b7 b0 TRS bit in ICCR1 register 1 0 1 0 TDRE bit in ICSR register ICDRT register Data 1 Data 2 Data 3 ICDRS register Data 1 Data 2 Data 3 Program processing (3) Write data to the ICDRT register. (3) Write data to the ICDRT register. (3) Write data to (3) Write data to the ICDRT register. the ICDRT register. (2) Set the TRS bit to 1. Figure 28.13 Operating Timing in Transmit Mode (Clock Synchronous Serial Mode) REJ09B0441-0010 Rev.0.10 Page 619 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.5.3 Receive Operation In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 28.14 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode). The receive procedure and operation in receive mode are as follows: (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the ICCR1 register and the MST bit (initial setting). (2) Set the MST bit to 1 while the transfer clock is being output. This will start the output of the receive clock. (3) When the receive operation is completed, data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1. When the MST bit is set to 1, the clock is output continuously since the next byte of data is enabled for reception. Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is set to 1, an overrun is detected and the AL bit in the ICSR register is set to 1. At this time, the last receive data is retained in the ICDRR register. (4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (next receive operation disabled) and read the ICDRR register. The SCL signal is fixed high after the following byte of data reception is completed. SCL 1 2 7 8 1 7 8 1 2 SDA (input) b0 b1 b6 b7 b0 b6 b7 b0 MST bit in ICCR1 register 1 0 1 0 TRS bit in ICCR1 register RDRF bit in ICSR register 1 0 ICDRS register Data 1 Data 2 Data 3 ICDRR register Data 1 Data 2 Program processing (2) Set the MST bit to 1 (when the transfer clock is output). (3) Read the ICDRR register. (3) Read the ICDRR register. Figure 28.14 Operating Timing in Receive Mode (Clock Synchronous Serial Mode) REJ09B0441-0010 Rev.0.10 Page 620 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.6 Register Setting Examples Figures 28.15 to 28.18 show Register Setting Examples When Using I2C bus interface. Start Initial setting Read the BBSY bit in the ICCR2 register • Set the STOP bit in the ICSR register to 0. • Set the IICSEL bit in the SSUIICSR register to 1. • Set the MSTIIC bit in the MSTCR register to 0. (1) Determine the states of the SCL and SDA lines. (2) Set to master transmit mode. No (1) BBSY = 0? Yes ICCR1 register TRS bit ← 1 MST bit ← 1 SCP bit ← 0 BBSY bit ← 1 (2) (3) Generate a start condition. (4) Set the transmit data of the 1st byte (slave address + R/W). (5) Wait until 1 byte of data is transmitted. (6) Determine the ACKBR bit from the specified slave device. (7) Set the transmit data after 2nd byte (except the last byte). (8) Wait until the ICRDT register is empty. (9) Set the transmit data of the last byte. No (5) TEND = 1? (10) Wait until the last byte is transmitted. (11) Set the TEND bit to 0. (12) Set the STOP bit to 0. (6) (13) Generate a stop condition. (14) Wait until a stop condition is generated. (15) Set to slave receive mode. Set the TDRE bit to 0. No Master receive mode ICCR2 register (3) Write transmit data to the ICDRT register Read the TEND bit in the ICSR register (4) Yes Read the ACKBR bit in the ICIER register ACKBR = 0? Yes Transmit mode? Yes No Write transmit data to the ICDRT register Read the TDRE bit in the ICSR register (7) No (8) TDRE = 1? Yes No Last byte? (9) Yes Write transmit data to the ICDRT register Read the TEND bit in the ICSR register (10) TEND = 1? Yes ICSR register ICSR register ICCR2 register TEND bit ← 0 STOP bit ← 0 SCP bit ← 0 BBSY bit ← 0 (11) (12) (13) No Read the STOP bit in the ICSR register (14) STOP = 1? Yes ICCR1 register TRS bit ← 0 MST bit ← 0 (15) ICSR register TDRE bit ← 0 End No Figure 28.15 Register Setting Example in Master Transmit Mode (I2C bus Interface Mode) REJ09B0441-0010 Rev.0.10 Page 621 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface Master receive mode ICSR register ICCR1 register ICSR register ICIER register TEND bit ← 0 TRS bit ← 0 TDRE bit ← 0 ACKBT bit ← 0 (2) (3) (1) (1) Set the TEND bit to 0 and set to master receive mode. Set the TDRE bit to 0. (1,2) (2) Set the ACKBT bit to the transmit device. (3) Dummy read the ICDRR register. (1) (4) Wait until 1 byte is received. (5) Determine (last receive - 1). (6) Read the receive data. Read the RDRF bit in the ICSR register (4) RDRF = 1? (9) Wait until the last byte is received. Yes Yes Last receive - 1? No Read the ICDRR register (6) (5) (10) Set the STOP bit to 0. (11) Generate a stop condition. (12) Wait until a stop condition is generated. (13) Read the receive data of the last byte. (14) Set the RCVD bit to 0. ICIER register ICCR1 register ACKBT bit ← 1 (7) RCVD bit ← 1 (8) (15) Set to slave receive mode. (7) Set the ACKBT bit of the last byte and set continuous receive operation to disable (RCVD = 1). (2) (8) Read the receive data of (last byte - 1). (1) Dummy read the ICDRR register No Read the ICDRR register Read the RDRF bit in the ICSR register No (9) RDRF = 1? Yes ICSR register ICCR2 register STOP bit ← 0 SCP bit ← 0 BBSY bit ← 0 (10) (11) Read the STOP bit in the ICSR register No (12) STOP = 1? Yes Read the ICDRR register ICCR1 register ICCR1 register RCVD bit ← 0 MST bit ← 0 End (13) (14) (15) Notes: 1. Do not generate interrupts while processing steps (1) to (3). 2. For 1 byte of data reception, skip steps (2) to (6) after step (1) and jump to process step (7). Process step (8) is a dummy read from the ICDRR register. Figure 28.16 Register Setting Example in Master Receive Mode (I2C bus Interface Mode) REJ09B0441-0010 Rev.0.10 Page 622 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface Slave transmit mode ICSR register AAS bit ← 0 (1) Set the AAS bit to 0. (1) (2) Set the transmit data (except the last byte). Write transmit data to the ICDRT register Read the TDRE bit in the ICSR register (2) (3) Wait until the ICRDT register is empty. (4) Set the transmit data of the last byte. (5) Wait until the last byte is transmitted. No TDRE = 1? Yes No Last byte? (4) Yes Write transmit data to the ICDRT register Read the TEND bit in the ICSR register (3) (6) Set the TEND bit to 0. (7) Set to slave receive mode. (8) Dummy read the ICDRR register to release the SCL signal. (9) Set the TDRE bit to 0. No TEND = 1? Yes TEND bit ← 0 TRS bit ← 0 (5) ICSR register ICCR1 register (6) (7) (8) (9) Dummy read the ICDRR register ICSR register TDRE bit ← 0 End Figure 28.17 Register Setting Example in Slave Transmit Mode (I2C bus Interface Mode) REJ09B0441-0010 Rev.0.10 Page 623 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface Slave receive mode ICSR register AAS bit ← 0 (1) (2) (3) Dummy read the ICDRR register. Dummy read the ICDRR register (3) (4) Wait until 1 byte is received. (5) Determine (last receive - 1). Read the RDRF bit in the ICSR register (6) Read the receive data. No (4) RDRF = 1? (8) Read the receive data of (last byte - 1). Yes (9) Wait until the last byte is received. Yes Last receive - 1? No Read the ICDRR register (6) (5) (10) Read the receive data of the last byte. (7) Set the ACKBT bit of the last byte. (1) (1) Set the AAS bit to 0. (1) ICIER register ACKBT bit ← 0 (2) Set the ACKBT bit to the transmit device. ICIER register ACKBT bit ← 1 (7) (8) Read the ICDRR register Read the RDRF bit in the ICSR register No (9) RDRF = 1? Yes Read the ICDRR register End (10) Note: 1. For 1 byte of data reception, skip steps (2) to (6) after (1) and jump to process step (7). Process step (8) is a dummy read from the ICDRR register. Figure 28.18 Register Setting Example in Slave Receive Mode (I2C bus Interface Mode) REJ09B0441-0010 Rev.0.10 Page 624 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.7 Noise Canceller The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure 28.19 shows a Block Diagram of Noise Canceller. The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal (or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit. When they do not match, the former value is retained. f1 (sampling clock) C SCL or SDA input signal D Latch Q D C Q Latch Match detection circuit Internal SCL or SDA signal f1 period f1 (sampling clock) Figure 28.19 Block Diagram of Noise Canceller REJ09B0441-0010 Rev.0.10 Page 625 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.8 Bit Synchronization Circuit When the I2C bus interface is set to master mode, the high-level period may become shorter if: • The SCL signal is held low by a slave device. • The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line. Therefore, the SCL signal is monitored and communication is synchronized bit by bit. Figure 28.20 shows the Bit Synchronization Circuit Timing and Table 28.5 lists the Time between Changing SCL Signal from Low-Level Output to High-Impedance and Monitoring SCL Signal. Reference clock of SCL monitor timing SCL VIH Internal SCL Figure 28.20 Bit Synchronization Circuit Timing Table 28.5 Time between Changing SCL Signal from Low-Level Output to High-Impedance and Monitoring SCL Signal ICCR1 Register CKS3 0 1 1Tcyc = 1/f1(s) CKS2 0 1 0 1 SCL Monitoring Time 7.5Tcyc 19.5Tcyc 17.5Tcyc 41.5Tcyc REJ09B0441-0010 Rev.0.10 Page 626 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 28. I2C bus Interface 28.9 Notes on I2C bus Interface To use the I2C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I2C bus interface function selected). REJ09B0441-0010 Rev.0.10 Page 627 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0. 29.1 Introduction The hardware LIN has the features listed below. Figure 29.1 shows the Hardware LIN Block Diagram. Master mode • Synch Break generation • Bus collision detection Slave mode • Synch Break detection • Synch Field measurement • Control function for Synch Break and Synch Field signal inputs to UART0 • Bus collision detection Note: 1. The wake-up function is detected using INT1. Hardware LIN RXD0 pin Synch Field control circuit TIOSEL = 0 RXD data LSTART bit SBE bit LINE bit RXD0 input control circuit TIOSEL = 1 Interrupt control circuit UART0 Bits BCIE, SBIE, and SFIE UART0 transfer clock UART0 TE bit Timer RA output pulse MST bit TXD0 pin LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register TIOSEL: Bit in TRAIOC register TE: Bit in U0C1 register UART0 TXD data Timer RA underflow signal Timer RA interrupt Timer RA Bus collision detection circuit Figure 29.1 Hardware LIN Block Diagram REJ09B0441-0010 Rev.0.10 Page 628 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.2 Input/Output Pins Table 29.1 lists the Hardware LIN Pin Configuration. Table 29.1 Hardware LIN Pin Configuration Name Receive data input Transmit data output Pin Name RXD0 TXD0 Assigned Pin P11_4 P13_1 I/O Input Output Function Receive data input for the hardware LIN Transmit data output for the hardware LIN Note: 1. To use the hardware LIN, set the TXD0SEL0 bit in the U0SR register to 1 and bits RXD0SEL1 to RXD0SEL0 to 10b. 29.3 Registers The hardware LIN contains the following registers: • LIN Control Register 2 (LINCR2) • LIN Control Register (LINCR) • LIN Status Register (LINST) 29.3.1 LIN Control Register 2 (LINCR2) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 BCE 0 R/W R/W R/W Address 0105h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function BCE Bus collision detection enable bit during Sync Break 0: Bus collision detection disabled transmission 1: Bus collision detection enabled — Reserved bits Set to 0. — — — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — — REJ09B0441-0010 Rev.0.10 Page 629 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.3.2 LIN Control Register (LINCR) b6 MST 0 b5 SBE 0 b4 LSTART 0 b3 RXDSF 0 b2 BCIE 0 b1 SBIE 0 b0 SFIE 0 R/W R/W Address 0106h Bit b7 Symbol LINE After Reset 0 Bit b0 Symbol Bit Name SFIE Synch Field measurement-complete interrupt enable bit b1 b2 b3 b4 Synch Break detection interrupt enable bit BCIE Bus collision detection interrupt enable bit RXDSF RXD0 input status flag LSTART Synch Break detection start bit (1) SBIE b5 SBE b6 MST RXD0 input unmasking timing select bit (enabled only in slave mode) LIN operation mode setting bit (2) b7 LINE LIN operation start bit Function 0: Synch Field measurement-complete interrupt disabled 1: Synch Field measurement-complete interrupt enabled 0: Synch Break detection interrupt disabled 1: Synch Break detection interrupt enabled 0: Bus collision detection interrupt disabled 1: Bus collision detection interrupt enabled 0: RXD0 input enabled 1: RXD0 input disabled When 1 is written, timer RA input is enabled and RXD0 input is disabled. When read, the content is 0. 0: Unmasked after Synch Break detection 1: Unmasked after Synch Field measurement is completed 0: Slave mode (Synch Break detection circuit operation) 1: Master mode (timer RA output OR’ed with TXD0) 0: LIN operation stops 1: LIN operation starts (3) R/W R/W R R/W R/W R/W R/W Notes: 1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts. 2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once. 3. Inputs to timer RA and UART0 are disabled immediately after the LINE bit is set to 1 (LIN operation starts). (Refer to Figure 29.3 Header Field Transmission Flowchart Example (1) and Figure 29.7 Header Field Reception Flowchart Example (2).) 29.3.3 LIN Status Register (LINST) b6 — 0 b5 B2CLR 0 b4 B1CLR 0 b3 B0CLR 0 b2 BCDCT 0 b1 SBDCT 0 b0 SFDCT 0 R/W R R R R/W R/W R/W — Address 0107h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name SFDCT Synch Field measurement-complete flag SBDCT Synch Break detection flag BCDCT B0CLR B1CLR B2CLR — — Function When this bit is set to 1, Synch Field measurement is completed. when this bit is set to 1, Synch Break is detected or Synch Break generation is completed. Bus collision detection flag When this bit is set to 1, bus collision is detected. SFDCT flag clear bit When 1 is written, the SFDCT bit is set to 0. When read, the content is 0. SBDCT flag clear bit When 1 is written, the SBDCT bit is set to 0. When read, the content is 0. BCDCT flag clear bit When 1 is written, the BCDCT bit is set to 0. When read, the content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. REJ09B0441-0010 Rev.0.10 Page 630 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.4 29.4.1 Functional Description Master Mode Figure 29.2 shows an Operating Example during Header Field Transmission in master mode. Figures 29.3 and 29.4 show Examples of Header Field Transmission Flowchart. During header field transmission, the hardware LIN operates as follows: (1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a low-level signal is output from the TXD0 pin for the period set in registers TRAPRE and TRA for timer RA. (2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. (3) The hardware LIN transmits 55h via UART0. (4) After the hardware LIN completes transmitting 55h, it transmits an ID field via UART0. (5) After the hardware LIN completes transmitting the ID field, it performs communication for a response field. Synch Break Synch Field IDENTIFIER TXD0 pin 1 0 1 is written to the B1CLR bit in the LINST register. 1 0 Set to 0 when an interrupt request is acknowledged or by a program. 1 0 (1) (2) (3) (4) (5) SBDCT flag in LINST register IR bit in TRAIC register The above applies under the following conditions: LINE = 1, MST = 1, SBIE = 1 Figure 29.2 Operating Example during Header Field Transmission REJ09B0441-0010 Rev.0.10 Page 631 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN Timer RA Set to timer mode Bits TMOD2 to TMOD0 in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ← 1 Timer RA Assign the TRAIO pin to P11_4 Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b UART0 Assign the RXD0 pin to P11_4 Bits RXD0SEL1 to RXD0SEL0 in U0SR register ← 10b INT1 Assign the INT1 pin to P11_4 INT4SEL0 bit in INTSR register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register UART0 Set to transmit/receive mode (Transfer data 8 bits long, internal clock, 1 stop bit, parity disabled) U0MR register Set the BRG count source (f1, f8, f32) Bits CLK0 and CLK1 in U0C0 register Set the bit rate U0BRG register (1) (1) (1) Set the TIOSEL bit in the TRAIOC register to 1 to select the hardware LIN function. If the wake-up function is not necessary, the setting of the INT4 pin can be omitted. Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. (1) UART0 (1) UART0 (1) Set the BRG count source and the U0BRG register as appropriate for the bit rate. Hardware LIN Set the LIN operation to stop LINCR register LINE bit ← 0 Hardware LIN Set to master mode. MST bit in LINCR register ← 1 Hardware LIN Set bus collision detection to enable BCE bit in LINCR2 register ← 1 Hardware LIN Set the LIN operation to start LINE bit in LINCR register ← 1 Hardware LIN Set interrupts to enable (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register (1) (1) (1) (1) In master mode, the Synch Field measurement-completed interrupt cannot be used. Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ← 1 A Note: 1. When the previous communication completes normally and header field transmission is performed again with the same settings, the above settings can be omitted. Figure 29.3 Header Field Transmission Flowchart Example (1) REJ09B0441-0010 Rev.0.10 Page 632 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN A Timer RA Set the timer to start counting TSTART bit in TRACR register ← 1 Read the count status flag TCSTF flag in TRACR register NO A Synch Break for timer RA is generated. After writing 1 to the TSTART bit, if registers TRAPRE and TRA for timer RA are not read or the register settings are not changed, reading 1 from the TCSTF flag can be omitted. Zero or one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. A timer RA interrupt can be used to end Synch Break generation. One or two cycles of the CPU clock are required after Synch Break generation ends before the SBDCT flag is set to 1. After a Synch Break for timer RA is generated, set the timer to stop counting. After writing 0 to the TSTART bit, if registers TRAPRE and TRA for timer RA are not read or the register settings are not changed, reading 0 from the TCSTF flag can be omitted. Zero or one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0. The Synch Field is transmitted. Timer RA TCSTF = 1? YES Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register NO SBDCT = 1? YES Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Read the count status flag TCSTF flag in TRACR register NO Timer RA TCSTF = 0? YES UART0 Communication via UART0 TE bit in U0C1 register ← 1 U0TB register ← 0055h UART0 Communication via UART0 U0TB register ← ID field The ID field is transmitted. Figure 29.4 Header Field Transmission Flowchart Example (2) REJ09B0441-0010 Rev.0.10 Page 633 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.4.2 Slave Mode Figure 29.5 shows an Operating Example during Header Field Reception in slave mode. Figures 29.6 through 29.8 show examples of Header Field Reception Flowchart. During header field reception, the hardware LIN operates as follows: (1) When 1 is written to the LSTART bit in the LINCR register for the hardware LIN, Synch Break detection is enabled. (2) When a low-level signal is input for a duration equal to or longer than the period set in timer RA, the hardware LIN detected it as a Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. Then the hardware LIN transits to the Synch Field measurement. (3) The hardware LINA receives a Synch Field (55h) and measures the period of the start bit and bits 0 to 6 is using timer RA. At this time, whether to input the Synch Field signal to RXD0 of UART0 can be selected by the SBE bit in the LINCR register. (4) When the Synch Field measurement is completed, the SFDCT flag in the LINST register is set to 1. If the SFIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. (5) After the Synch Field measurement is completed, a transfer rate is calculated from the timer RA count value. The rate is set in UART0 and registers TRAPRE and TRA for timer RA are set again. Then the hardware LIN receives an ID field via UART0. (6) After the hardware LIN completes receiving the ID field, it performs communication for a response field. Synch Break Synch Field IDENTIFIER RXD0 pin 1 0 1 0 1 0 1 0 1 0 1 0 (1) (2) (3) (4) (5) (6) 1 is written to the B1CLR bit in the LINST register. This period is measured. RXD0 input for UART0 RXDSF flag in LINCR register SBDCT flag in LINST register SFDCT flag in LINST register IR bit in TRAIC register 1 is written to the LSTART bit in the LINCR register. The flag is set to 0 after Synch Field measurement is completed. 1 is written to the B0CLR bit in the LINST register. Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the above conditions: LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1 Figure 29.5 Operating Example during Header Field Reception REJ09B0441-0010 Rev.0.10 Page 634 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN Timer RA Set to pulse width measurement mode Bits TMOD2 to TMOD0 in TRAMR register ←011b Timer RA Set the pulse width measurement level to low TEDGSEL bit in TRAIOC register ← 0 Timer RA Assign the TRAIO pin to P11_4 Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b UART0 Assign the RXD0 pin to P11_4 Bits RXD0SEL1 to RXD0SEL0 in U0SR register ← 10b INT1 Assign the INT1 pin to P11_4 INT4SEL0 bit in INTSR register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set the LIN operation to stop LINE bit in LINCR register ← 0 Set to slave mode MST bit in LINCR register ← 0 Set the LIN operation to start LINE bit in LINCR register ← 1 Set the RXD0 input unmasking timing (After Synch Break detection, or after Synch Field measurement) SBE bit in LINCR register (1) (1) (1) Set the TIOSEL bit in the TRAIOC register to 1 to select the hardware LIN function. If the wake-up function is not necessary, the setting of the INT4 pin can be omitted. (1) (1) Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. (1) Hardware LIN (1) Hardware LIN (1) Hardware LIN (1) Select the timing at which to unmask the RXD0 input for UART0. If the RXD0 input is chosen to be unmasked after Synch Break detection, the Synch Field signal is also input to UART0. Hardware LIN Set interrupts to enable (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register (1) A Note: 1. When the previous communication completes normally and header field reception is performed again with the same settings, the above settings can be omitted. Figure 29.6 Header Field Reception Flowchart Example (1) REJ09B0441-0010 Rev.0.10 Page 635 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN A Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, and B0CLR in LINST register ← 1 Timer RA Set pulse width measurement to start TSTART bit in TRACR register ← 1 Read the count status flag TCSTF flag in TRACR register NO Zero or one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. Wait until the RXD0 input to UART0 for the hardware LIN is masked. After writing 1 to the LSTART bit, do not apply a “L” level to the RXD pin until 1 is read from the RXDSF flag. Otherwise, the signal applied during this time will be input directly to UART0. One or two cycles of the CPU clock and zero or one cycle of the timer RA count source are required after the LSTART bit is set to 1 before the RXDSF flag is set to 1. After this, input to timer RA and UART0 is enabled. A Synch Break for the hardware LIN is detected. A timer RA interrupt can be used. When a Synch Break is detected, timer RA is reloaded with the initially set count value. Even if the duration of the input “L” level is shorter than the set period, timer RA is reloaded with the initially set count value. Wait until the next “L” level is input. One or two cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1. When the SBE bit in the LINCR register is set to 0 (unmasked after Synch Break detected), timer RA can be used in timer mode after the SBDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0. Wait until timer RA starts counting. Timer RA TCSTF = 1? YES Hardware LIN Set Synch Break detection to start LSTART bit in LINCR register ← 1 Hardware LIN Read the RXD0 input status flag RXDSF flag in LINCR register NO RXDSF = 1? YES Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register NO SBDCT = 1? YES B Figure 29.7 Header Field Reception Flowchart Example (2) REJ09B0441-0010 Rev.0.10 Page 636 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN B YES Hardware LIN Read the Synch Field measurementcomplete flag SFDCT flag in LINST register NO SFDCT = 1? YES UART0 A Synch Field for the hardware LIN is measured. A timer RA interrupt can be used. (The SBDCT flag is set when the timer RA counter underflows.) When the SBE bit in the LINCR register is set to 1 (unmasked after Synch Filed measurement completed), timer RA can be used in timer mode after the SFDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0. Set the UART0 communication rate U0BRG register Timer RA Set the Synch Break width again TRAPRE register TRA register UART0 Communication via UART0 Clock asynchronous serial interface (UART) mode ID field reception Set a communication rate based on the Synch Field measurement result. Communication is performed via UART0. (The SBDCT flag is set when the timer RA counter underflows.) Figure 29.8 Header Field Reception Flowchart Example (3) REJ09B0441-0010 Rev.0.10 Page 637 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.4.3 Bus Collision Detection Function The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in U0C1 register = 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register to 1 (bus collision detection enabled). Figure 29.9 shows an Operating Example When Bus Collision is Detected. TXD0 pin 1 0 1 0 1 0 Set to 1 by a program. 1 0 Set to 1 by a program. 1 0 1 is written to the B2CLR bit in the LINST register. 1 0 1 0 Set to 0 when an interrupt request is acknowledged or by a program. RXD0 pin Transfer clock LINE bit in LINCR register TE bit in U0C1 register BCDCT flag in LINST register IR bit in TRAIC register Figure 29.9 Operating Example When Bus Collision is Detected REJ09B0441-0010 Rev.0.10 Page 638 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.4.4 Hardware LIN End Processing Figure 29.10 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing: • When the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes. • When the bus collision detection function is not used Perform hardware LIN end processing after header field transmission and reception complete. Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Read the count status flag TCSTF flag in TRACR register NO Set the timer to stop counting. Zero or one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 1. Timer RA TCSTF = 0? YES UART0 Transmission completes via UART0 When the bus collision detection function is not used, UART0 transmission completion processing is not required. Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, and B0CLR in LINST register ← 1 Hardware LIN Set the LIN operation to stop LINE bit in LINCR register ← 0 After clearing the hardware LIN status flags, stop the hardware LIN operation. Figure 29.10 Example of Hardware LIN Communication Completion Flowchart REJ09B0441-0010 Rev.0.10 Page 639 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.5 Interrupt Requests There are four interrupt requests generated by the hardware LIN: Synch Break detection, completion of Synch Break generation, completion of Synch Field measurement, and bus collision detection. These interrupts are shared with timer RA. Table 29.2 lists the Hardware LIN Interrupt Requests. Table 29.2 Hardware LIN Interrupt Requests Interrupt Request Synch Break detection Status Flag Interrupt Source Generated when timer RA underflows after the low-level duration for the RXD0 input is measured. Or when a lowlevel signal is input for a duration longer than the Synch Break period during communication. Generated when the low-level output to TXD0 for the duration set by timer RA is completed. SBDCT Completion of Synch Break generation Completion of Synch Field measurement Bus collision detection BCDCT SFDCT Generated when measurement for 6 bits of the Lynch Field by timer RA is completed. Generated when the RXD0 input and TXD0 output values are different at the data latch timing while UART0 is enabled for transmission. REJ09B0441-0010 Rev.0.10 Page 640 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 29. Hardware LIN 29.6 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point. REJ09B0441-0010 Rev.0.10 Page 641 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares pins P0_0 to P0_7, P1_0 to P1_3, and P13_0 to P13_7. 30.1 Introduction Table 30.1 lists the A/D Converter Performance. Figure 30.1 shows the A/D Converter Block Diagram. Table 30.1 A/D Converter Performance Item A/D conversion method Analog input voltage (1) Operating clock φAD (2) Resolution Absolute accuracy Performance Successive approximation (with capacitive coupling amplifier) 0 V to AVCC fAD, fAD divided by 2, fAD divided by 4, fAD divided by 8 (fAD = f1 or fOCO-F) 8 bits or 10 bits selectable AVCC = Vref = 5 V, φAD = 20 MHz • 8-bit resolution ±2 LSB • 10-bit resolution ±3 LSB AVCC = Vref = 3.3 V, φAD = 16 MHz • 8-bit resolution ±2 LSB • 10-bit resolution ±5 LSB AVCC = Vref = 3.0 V, φAD = 10 MHz • 8-bit resolution ±2 LSB • 10-bit resolution ±5 LSB AVCC = Vref = 2.2 V, φAD = 5 MHz • 8-bit resolution ±2 LSB • 10-bit resolution ±5 LSB One-shot mode, repeat mode 0, repeat mode 1, single sweep mode, and repeat sweep mode 20 pins (AN0 to AN19) • Software trigger • Timer RD • Timer RC • External trigger (Refer to 30.3.3 A/D Conversion Start Conditions.) Minimum 43 φAD cycles Operating modes Analog input pins A/D conversion start conditions Conversion rate per pin (3) (φAD = fAD) Notes: 1. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. 2. When 4.0 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 20 MHz or below. When 3.2 V ≤ AVCC < 4.0 V, the frequency of φAD must be 16 MHz or below. When 3.0 V ≤ AVCC < 3.2 V, the frequency of φAD must be 10 MHz or below. When 2.2 V ≤ AVCC < 3.0 V, the frequency of φAD must be 5 MHz or below. The frequency of φAD must be 2 MHz or above. 3. The conversion rate per pin is minimum 43 φAD cycles for 8-bit and 10-bit resolution. REJ09B0441-0010 Rev.0.10 Page 642 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter CKS2 = 1 fOCO-F f1 CKS2 = 0 fAD 1/2 1/2 1/2 CKS1 to CKS0 = 00b = 01b = 10b = 11b φAD VREF AVSS Software trigger Timer RD trigger Timer RC trigger ADTRG ADSTBY = 0 ADSTBY = 1 ADCAP1 to ADCAP0 = 00b = 01b = 10b = 11b Analog circuit Trigger Successive conversion register SCAN1 to SCAN0 CH2 to CH0 AD0 register AD1 register AD2 register AD3 register AD4 register AD5 register AD6 register AD7 register ADGSEL1 to ADGSEL0 Vin Vref Decoder Comparator Data bus P13_0/AN0 P13_1/AN1 P13_2/AN2 P13_3/AN3 P0_0/AN4 P0_1/AN5 P0_2/AN6 P0_3/AN7 P0_4/AN8 P0_5/AN9 P0_6/AN10 P0_7/AN11 P1_0/AN12 P1_1/AN13 P1_2/AN14 P1_3/AN15 P13_4/AN16 P13_5/AN17 P13_6/AN18 P13_7/AN19 CH2 to CH0=000b CH2 to CH0=001b CH2 to CH0=010b CH2 to CH0=011b CH2 to CH0=100b CH2 to CH0=101b CH2 to CH0=110b CH2 to CH0=111b CH2 to CH0=000b CH2 to CH0=001b CH2 to CH0=010b CH2 to CH0=011b CH2 to CH0=100b CH2 to CH0=101b CH2 to CH0=110b CH2 to CH0=111b ADGSEL1 to ADGSEL0 =00b =01b =10b CH2 to CH0=000b CH2 to CH0=001b CH2 to CH0=010b CH2 to CH0=011b ADEX0 = 0 OCVREFAN = 0 On-chip reference voltage (OCVREF) OCVREFAN = 1 (Note 1) ADEX0 = 1 ADDDAEN = 0 ADDDAEL ADDDAEN = 1 CKS0 to CKS2, ADCAP0, ADCAP1: Bits in ADMOD register CH0 to CH2, SCAN0, SCAN1, ADGSEL0, ADGSEL1: Bits in ADINSEL register ADEX0, ADSTBY, ADDDAEN, ADDDAEL: Bits in ADCON1 register OCVREFAN: Bit in OCVREFCR register Note: 1. When the on-chip reference voltage is used as analog input, first set the ADEX0 bit to 1 (on-chip reference voltage selected) and then set the OCVREFAN bit to 1 (on-chip reference voltage and analog input are connected). When the on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected). Figure 30.1 A/D Converter Block Diagram REJ09B0441-0010 Rev.0.10 Page 643 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.2 30.2.1 Registers On-Chip Reference Voltage Control Register (OCVREFCR) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 OCVREFAN 0 Address 0026h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function R/W OCVREFAN On-chip reference voltage to 0: On-chip reference voltage and analog input are cut off R/W 1: On-chip reference voltage and analog input are analog input connect bit (1) connected — Set to 0. R/W Reserved bits — — — — — — Note: 1. When the on-chip reference voltage is used as analog input, first set the ADEX0 bit in the ADCON1 register to 1 (on-chip reference voltage selected) and then set the OCVREFAN bit to 1 (on-chip reference voltage and analog input are connected). When the on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected). Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the OCVREFCR register. If the content of the OCVREFCR register is rewritten during A/D conversion, the conversion result is undefined. REJ09B0441-0010 Rev.0.10 Page 644 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.2.2 A/D Register i (ADi) (i = 0 to 7) Address 00C1h to 00C0h (AD0), 00C3h to 00C2h (AD1), 00C5h to 00C4h (AD2), 00C7h to 00C6h (AD3), 00C9h to 00C8h (AD4), 00CBh to 00CAh (AD5), 00CDh to 00CCh (AD6), 00CFh to 00CEh (AD7) Bit b7 b6 b5 b4 b3 b2 b1 Symbol — — — — — — — After Reset X X X X X X X Bit Symbol After Reset b15 — 0 b14 — 0 b13 — 0 b12 — 0 b11 — 0 Function Bit b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 10-bit mode (BITS bit in ADCON1 register = 1) 8 low-order bits in A/D conversion result b10 — 0 b9 — X b0 — X b8 — X 8-bit mode (BITS bit in ADCON1 register = 0) A/D conversion result R/W R 2 high-order bits in A/D conversion result When read, the content is 0. R — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bit When read, the content is undefined. R If the contents of the ADCON1, ADMOD, ADINSEL, or OCVREFCR register are written during A/D conversion, the conversion result is undefined. When using the A/D converter in 10-bit mode, repeat mode 0, repeat mode 1, or repeat sweep mode, access the ADi register in 16-bit units. Do not access it in 8-bit units. REJ09B0441-0010 Rev.0.10 Page 645 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.2.3 A/D Mode Register (ADMOD) b5 MD2 0 b4 MD1 0 b3 MD0 0 b2 CKS2 0 b1 CKS1 0 b0 CKS0 0 R/W R/W R/W Address 00D4h Bit b7 b6 Symbol ADCAP1 ADCAP0 After Reset 0 0 Bit b0 b1 Symbol Bit Name CKS0 Division select bit CKS1 Function b1 b0 b2 b3 b4 b5 CKS2 MD0 MD1 MD2 Clock source select bit (1) A/D operating mode select bit 0 0: fAD divided by 8 0 1: fAD divided by 4 1 0: fAD divided by 2 1 1: fAD divided by 1 (no division) 0: f1 selected 1: fOCO-F selected b5 b4 b3 R/W R/W R/W R/W 0 0 0: One-shot mode 0 0 1: Do not set. 0 1 0: Repeat mode 0 0 1 1: Repeat mode 1 1 0 0: Single sweep mode 1 0 1: Do not set. 1 1 0: Repeat sweep mode 1 1 1: Do not set. b7 b6 b6 b7 ADCAP0 A/D conversion trigger ADCAP1 select bit 0 0: A/D conversion starts by software trigger (ADST bit in ADCON0 register) 0 1: A/D conversion starts by conversion trigger from timer RD 1 0: A/D conversion starts by conversion trigger from timer RC 1 1: A/D conversion starts by external trigger (ADTRG) R/W R/W Note: 1. When the CKS2 bit is changed, wait for three φAD cycles or more before starting A/D conversion. If the content of the ADMOD register is rewritten during A/D conversion, the conversion result is undefined. REJ09B0441-0010 Rev.0.10 Page 646 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.2.4 A/D Input Select Register (ADINSEL) b4 SCAN0 0 b3 — 0 b2 CH2 0 b1 CH1 0 b0 CH0 0 R/W R/W R/W R/W R/W R/W R/W Address 00D5h Bit b7 b6 b5 Symbol ADGSEL1 ADGSEL0 SCAN1 After Reset 1 1 0 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name CH0 Analog input pin select bit CH1 CH2 — Reserved bit SCAN0 A/D sweep pin count select bit SCAN1 Function Refer to Table 30.2 Analog Input Pin Selection Set to 0. b5 b4 0 0: 2 pins 0 1: 4 pins 1 0: 6 pins 1 1: 8 pins b7 b6 b6 b7 ADGSEL0 A/D input group select bit ADGSEL1 0 0: Port P13_0 to P13_3 and port P0_0 to P0_3 groups selected 0 1: Port P0_4 to P0_7 and port P1_0 to P1_3 groups selected 1 0: Port P13_4 to P13_7 group selected 1 1: Port group not selected R/W R/W If the content of the ADINSEL register is rewritten during A/D conversion, the conversion result is undefined. Table 30.2 Analog Input Pin Selection Bits CH2 to CH0 000b 001b 010b 011b 100b 101b 110b 111b Bits ADGSEL1 to ADGSEL0 = 00b AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Bits ADGSEL1 to ADGSEL0 = 01b AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Bits ADGSEL1 to ADGSEL0 = 10b AN16 AN17 AN18 AN19 Do not set. REJ09B0441-0010 Rev.0.10 Page 647 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.2.5 A/D Control Register 0 (ADCON0) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 ADST 0 R/W R/W — Address 00D6h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name ADST A/D conversion start flag — — — — — — — Function 0: A/D conversion stops 1: A/D conversion starts Nothing is assigned. If necessary, set to 0. When read, the content is 0. ADST Bit (A/D Conversion Start Flag) [Conditions for setting to 1] When A/D conversion starts and while A/D conversion is in progress. [Condition for setting to 0] When A/D conversion stops. 30.2.6 A/D Control Register 1 (ADCON1) b4 BITS 0 b3 — 0 b2 — 0 b1 — 0 b0 ADEX0 0 R/W R/W R/W Address 00D7h Bit b7 b6 b5 Symbol ADDDAEL ADDDAEN ADSTBY After Reset 0 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol ADEX0 — — — BITS Bit Name Function Extended analog input pin select bit (1) 0: Extended analog input pin not selected 1: On-chip reference voltage selected (2) Reserved bits Set to 0. 8-/10-bit mode select bit ADSTBY A/D standby bit (3) ADDDAEN A/D open-circuit detection assist function enable bit (4) ADDDAEL A/D open-circuit detection assist method select bit (4) 0: 8-bit mode 1: 10-bit mode 0: A/D operation stops (standby) 1: A/D operation enabled 0: Disabled 1: Enabled 0: Discharge before conversion 1: Precharge before conversion R/W R/W R/W R/W Notes: 1. When the on-chip reference voltage is used as analog input, first set the ADEX0 bit to 1 (on-chip reference voltage selected) and then set the OCVREFAN bit in the OCVREFCR register to 1 (on-chip reference voltage and analog input are connected). When the on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected). 2. Do not set in single sweep mode or repeat sweep mode. 3. When the ADSTBY bit is changed from 0 (A/D operation stops) to 1 (A/D operation enabled), wait for one φAD cycle or more before starting A/D conversion. 4. To enable the A/D open-circuit detection assist function, select the conversion start state with the ADDDAEL bit after setting the ADDDAEN bit to 1 (enabled). The conversion result for an open circuit varies with external circuits. Careful evaluation should be performed according to the system before using this function. If the content of the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. REJ09B0441-0010 Rev.0.10 Page 648 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.3 30.3.1 Common Items for Multiple Modes Input/Output Pins The analog input shares pins P0_0 to P0_7, P1_0 to P1_3, and P13_0 to P13_7 in AN0 to AN19. To use the ANi (i = 0 to 19) pin as input, set the corresponding port direction bit to 0 (input mode). After changing the A/D operating mode, select an analog input pin again. 30.3.2 A/D Conversion Cycles Figure 30.2 shows the Timing Diagram of A/D Conversion. Figure 30.3 shows the A/D Conversion Cycles (φAD = fAD). A/D conversion execution time Start process Open-circuit detection Open-circuit detection Charging time Conversion time of 1st bit 2nd bit End process Start process Sampling time 15 φAD cycles Comparison time Comparison Comparison time time * Repeat until conversion ends …… Comparison End process time Figure 30.2 Timing Diagram of A/D Conversion A/D conversion execution time Conversion time at the 2nd bit and the follows Start process Open-circuit detection Conversion time at the 1st bit End process Conversion time (Minimum) (1) 43 φAD Start process (Minimum) 1 φAD Open-circuit detection Charging time Disabled: 0 φAD Enabled: 2 φAD Sampling time 15 φAD Comparison time 2.5 φAD Comparison time 2.5 φAD End process 2 φAD Note: 1. The conversion time (minimum) is 43 φAD for 8-bit and 10-bit resolution. Figure 30.3 A/D Conversion Cycles (φAD = fAD) REJ09B0441-0010 Rev.0.10 Page 649 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter Table 30.3 shows the Number of Cycles for A/D Conversion Items. The A/D conversion time is defined as follows: The start process time varies depending on which φAD is selected. When 1 (A/D conversion starts) is written to the ADST bit in the ADCON0 register, an A/D conversion starts after the start process time has elapsed. Reading the ADST bit before the A/D conversion returns 0 (A/D conversion stops). In the modes where an A/D conversion is performed on multiple pins or multiple times, the between-execution process time is inserted between the A/D conversion execution time for one pin and the next A/D conversion time. In one-shot mode and single sweep mode, the ADST bit is set to 0 during the end process time and the last A/D conversion result is stored in the ADi register. • In on-shot mode Start process time + A/D conversion execution time + end process time • When two pins are selected in single sweep mode Start process time + (A/D conversion execution time + between-execution process time + A/D conversion execution time) + end process time Table 30.3 Number of Cycles for A/D Conversion Items A/D Conversion Item φAD = fAD φAD = fAD divided by 2 φAD = fAD divided by 4 φAD = fAD divided by 8 A/D conversion Open-circuit detection disabled execution time Open-circuit detection enabled Between-execution process time End process time Start process time Number of Cycles 1 or 2 fAD cycles 2 or 3 fAD cycles 3 or 4 fAD cycles 5 or 6 fAD cycles 40 φAD cycles 42 φAD cycles 1 φAD cycle 2 or 3 fAD cycles REJ09B0441-0010 Rev.0.10 Page 650 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.3.3 A/D Conversion Start Conditions A software trigger, trigger from timer RD or timer RC, and external trigger are used as A/D conversion start triggers. Figure 30.4 shows the Block Diagram of A/D Conversion Start Control Unit. ADCAP1 to ADCAP0 = 00b IMFj (TRDSRk register) IMFj (TRCSR register) ADTRG pin PD4_5 ADST ADTRGjkE ADTRGjE INT0EN = 01b = 10b = 11b A/D conversion start trigger j = A, B, C, D k = 0 or 1 ADCAP0, ADCAP1: Bits in ADMOD register ADST: Bit in ADCON0 register ADTRGjkE: Bit in TRDADCR register ADTRGjE: Bit in TRCADCR register INT0EN: Bit in INTEN register IMFj: Bit in TRDSRk register IMFj: Bit in TRCSR register PD4_5: Bit in PD4 register Figure 30.4 Block Diagram of A/D Conversion Start Control Unit 30.3.3.1 Software Trigger A software trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software trigger). The A/D conversion starts when the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). 30.3.3.2 Trigger from Timer RD This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 01b (timer RD). To use this function, make sure the following conditions are met: • Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 01b (timer RD). • Timer RD is used in the output compare function (timer mode, PWM mode, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode). • The ADTRGjkE bit (j = A, B, C, D, k = 0 or 1) in the TRDADCR register is set to 1 (A/D trigger occurs at compare match with TRDGRjk register). • The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). When the IMFj bit in the TRDSRk register is changed from 0 to 1 under the above conditions, A/D conversion starts. Refer to 21. Timer RD, 21.4 Output Compare Function, 21.5 PWM Mode, 21.6 Reset Synchronous PWM Mode, 21.7 Complementary PWM Mode, 21.8 PWM3 Mode for the details of timer RD and the output compare function (timer mode, PWM mode, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode). REJ09B0441-0010 Rev.0.10 Page 651 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.3.3.3 Trigger from Timer RC This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 10b (timer RC). To use this function, make sure the following conditions are met: • Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 10b (timer RC). • Timer RC is used in the output compare function (timer mode, PWM mode, and PWM2 mode). • The ADTRGjE bit (j = A, B, C, D) in the TRCADCR register is set to 1 (A/D trigger occurs at compare match with TRCGRj register). • The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). When the IMFj bit in the TRCSR register is changed from 0 to 1 under the above conditions, A/D conversion starts. Refer to 20. Timer RC, 20.5 Timer Mode (Output Compare Function), 20.6 PWM Mode, 20.7 PWM2 Mode for the details of timer RC and the output compare function (timer mode, PWM mode, and PWM2 mode). 30.3.3.4 External Trigger This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 11b (external trigger (ADTRG)). To use this function, make sure the following conditions are met: • Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 11b (external trigger (ADTRG)). • The INT7EN bit in the INTEN register is set to 1 ((INT7 input enabled)). • The port direction register is set to input: When the INT7SEL0 bit in the INTSR register is 0, the PD3_7 bit in the PD3 register is set to 0 (input mode). When the INT7SEL0 bit in the INTSR register is 1, the PD11_7 bit in the PD11 register is set to 0 (input mode) • The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). When the ADTRG pin input is changed from high to low under the above conditions, A/D conversion starts. REJ09B0441-0010 Rev.0.10 Page 652 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.3.4 A/D Conversion Result The A/D conversion result is stored in the ADi register (i = 0 to 7). The register where the result is stored varies depending on the A/D operating mode used. The contents of the ADi register are undefined after reset. Values cannot be written to the ADi register. In repeat mode 0, no interrupt request is generated. After the first AD conversion is completed, determine if the A/D conversion time has elapsed by a program. In one-shot mode, repeat mode 1, single sweep mode, and repeat sweep mode, an interrupt request is generated at certain times, such as when an A/D conversion completes (the IR bit in the ADIC register is set to 1). However, in repeat mode 1 and repeat sweep mode, A/D conversion continues after an interrupt request is generated. Read the ADi register before the next A/D conversion is completed, since at completion the ADi register is rewritten with the new value. In one-shot mode and single sweep mode, when bits ADCAP1 to ADCAP0 in the ADMOD register is set to 00b (software trigger), the ADST bit in the ADCON0 register is used to determine whether the A/D conversion or sweep has completed. During an A/D conversion operation, if the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program to forcibly terminate A/D conversion, the conversion result of the A/D converter is undefined and no interrupt is generated. If the ADST bit is set to 0 by a program, do not use the value of the ADi register. 30.3.5 Low-Current-Consumption Function When the A/D converter is not used, power consumption can be reduced by setting the ADSTBY bit in the ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow. To use the A/D converter, set the ADSTBY bit to 1 (A/D operation enabled) and wait for one φAD cycle or more before setting the ADST bit in the ADCON0 register to 1 (A/D conversion starts). Do not write 1 to bits ADST and ADSTBY at the same time. Also, do not set the ADSTBY bit to 0 (A/D operation stops (standby)) during the A/D conversion. 30.3.6 Extended Analog Input Pins In one-shot mode, repeat mode 0, and repeat mode 1, the on-chip reference voltage (OCVREF) can be used as analog input. Any variation in VREF can be confirmed using the on-chip reference voltage. Use the ADEX0 bit in the ADCON1 register and the OCVREFAN bit in the OCVREFCR register to select the on-chip reference voltage. The A/D conversion result of the on-chip reference voltage in one-shot mode or in repeat mode 0 is stored in the AD0 register. 30.3.7 A/D Open-Circuit Detection Assist Function To suppress influences of the analog input voltage leakage from the previously converted channel during A/D conversion operation, a function is incorporated to fix the electric charge on the chopper amp capacitor to the predetermined state (AVCC or GND) before starting conversion. This function enables more reliable detection of an open circuit in the wiring connected to the analog input pins. Figure 30.5 shows the A/D Open-Circuit Detection Example on AVCC Side (Precharge before Conversion Selected) and Figure 30.6 shows the A/D Open-Circuit Detection Example on AVSS Side (Discharge before Conversion Selected). REJ09B0441-0010 Rev.0.10 Page 653 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter ON Precharge External circuit example (1) Precharge control signal ADDDAEN R OFF Discharge control signal Analog input ANi i = 0 to 19 Chopper amp capacitor Open C Note: 1. The conversion result for an open circuit varies with external circuits. Careful evaluation should be performed before using this function. Figure 30.5 A/D Open-Circuit Detection Example on AVCC Side (Precharge before Conversion Selected) OFF Precharge control signal ADDDAEN External circuit example (1) Analog input ANi i = 0 to 19 Open R C Discharge ON Discharge control signal Chopper amp capacitor Note: 1. The conversion result for an open circuit varies with external circuits. Careful evaluation should be performed before using this function. Figure 30.6 A/D Open-Circuit Detection Example on AVSS Side (Discharge before Conversion Selected) REJ09B0441-0010 Rev.0.10 Page 654 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.4 One-Shot Mode In one-shot mode, the input voltage to one pin selected from among AN0 to AN19 or OCVREF is A/D converted once. Table 30.4 lists the One-Shot Mode Specifications. Table 30.4 One-Shot Mode Specifications Item Function Resolution A/D conversion start conditions A/D conversion stop conditions Interrupt request generation timing Analog input pin Storage resisters for A/D conversion result Specification The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted once. 8 bits or 10 bits selectable • Software trigger • Timer RD • Timer RC • External trigger (Refer to 30.3.3 A/D Conversion Start Conditions) • A/D conversion completes (when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software trigger), the ADST bit in the ADCON0 register is set to 0.) • Set the ADST bit to 0. When A/D conversion completes. One pin is selectable from among AN0 to AN19 or OCVREF. AD0 register: AN0, AN8, AN16, OCVREF AD1 register: AN1, AN9, AN17 AD2 register: AN2, AN10, AN18 AD3 register: AN3, AN11, AN19 AD4 register: AN4, AN12 AD5 register: AN5, AN13 AD6 register: AN6, AN14 AD7 register: AN7, AN15 Read the register among AD0 to AD7 corresponding to the selected pin. Reading of A/D conversion result REJ09B0441-0010 Rev.0.10 Page 655 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.5 Repeat Mode 0 In repeat mode 0, the input voltage to one pin selected from among AN0 to AN19 or OCVREF is A/D converted repeatedly. Table 30.5 lists the Repeat Mode 0 Specifications. Table 30.5 Repeat Mode 0 Specifications Item Function Resolution A/D conversion start conditions A/D conversion stop conditions Interrupt request generation timing Analog input pin Storage resisters for A/D conversion result Specification The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted repeatedly. 8 bits or 10 bits selectable • Software trigger • Timer RD • Timer RC • External trigger (Refer to 30.3.3 A/D Conversion Start Conditions) Set the ADST bit in the ADCON0 register to 0 Not generated One pin is selectable from among AN0 to AN19 or OCVREF. AD0 register: AN0, AN8, AN16, OCVREF AD1 register: AN1, AN9, AN17 AD2 register: AN2, AN10, AN18 AD3 register: AN3, AN11, AN19 AD4 register: AN4, AN12 AD5 register: AN5, AN13 AD6 register: AN6, AN14 AD7 register: AN7, AN15 Read the register among AD0 to AD7 corresponding to the selected pin. Reading of A/D conversion result REJ09B0441-0010 Rev.0.10 Page 656 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.6 Repeat Mode 1 In repeat mode 1, the input voltage to one pin selected from among AN0 to AN19 or OCVREF is A/D converted repeatedly. Table 30.6 lists the Repeat Mode 1 Specifications. Figure 30.7 shows an Operating Example in Repeat Mode 1. Table 30.6 Repeat Mode 1 Specifications Item Function Resolution A/D conversion start conditions A/D conversion stop condition Interrupt request generation timing Analog input pin Storage resisters for A/D conversion result Specification The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted repeatedly. 8 bits or 10 bits selectable • Software trigger • Timer RD • Timer RC • External trigger (Refer to 30.3.3 A/D Conversion Start Conditions) Set the ADST bit in the ADCON0 register to 0. When the A/D conversion result is stored in the AD7 register. One pin is selectable from among AN0 to AN19 or OCVREF. AD0 register: 1st A/D conversion result, 9th A/D conversion result... AD1 register: 2nd A/D conversion result, 10th A/D conversion result... AD2 register: 3rd A/D conversion result, 11th A/D conversion result... AD3 register: 4th A/D conversion result, 12th A/D conversion result... AD4 register: 5th A/D conversion result, 13th A/D conversion result... AD5 register: 6th A/D conversion result, 14th A/D conversion result... AD6 register: 7th A/D conversion result, 15th A/D conversion result... AD7 register: 8th A/D conversion result, 16th A/D conversion result... Read registers AD0 to AD7. Reading of A/D conversion result REJ09B0441-0010 Rev.0.10 Page 657 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter ADST bit in ADCON0 register 1 0 Successive conversion register 1st 2nd 3rd 4th 5th 6th 7th 8th 9th AD0 register Undefined 1st A/D conversion result 9th A/D conversion result AD1 register Undefined 2nd A/D conversion result AD2 register Undefined 3rd A/D conversion result AD3 register Undefined 4th A/D conversion result AD4 register Undefined 5th A/D conversion result AD5 register Undefined 6th A/D conversion result AD6 register Undefined 7th A/D conversion result AD7 register Undefined 8th A/D conversion result Set to 0 when an interrupt request is acknowledged, or set by a program. IR bit in ADIC register 1 0 The above applies under the following condition: Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (A/D conversion starts by software trigger). Figure 30.7 Operating Example in Repeat Mode 1 REJ09B0441-0010 Rev.0.10 Page 658 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.7 Single Sweep Mode In single sweep mode, the input voltage to two, four, six, or eight pins selected from among AN0 to AN19 are A/D converted one-by-one. Table 30.7 lists the Single Sweep Mode Specifications. Figure 30.8 shows an Operating Example in Single Sweep Mode. Table 30.7 Single Sweep Mode Specifications Item Function Resolution A/D conversion start conditions A/D conversion stop conditions Interrupt request generation timing Analog input pins Storage resisters for A/D conversion result Reading of A/D conversion result Specification The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted one-by-one. 8 bits or 10 bits selectable • Software trigger • Timer RD • Timer RC • External trigger (Refer to 30.3.3 A/D Conversion Start Conditions) • If 2 pins are selected, when A/D conversion of the 2 selected pins completes. (The ADST bit in the ADCON0 register is set to 0.) • If 4 pins are selected, when A/D conversion of the 4 selected pins completes. (The ADST bit is set to 0.) • If 6 pins are selected, when A/D conversion of the 6 selected pins completes. (The ADST bit is set to 0.) • If 8 pins are selected, when A/D conversion of the 8 selected pins completes. (The ADST bit is set to 0.) • Set the ADST bit to 0. • If 2 pins are selected, when A/D conversion of the 2 selected pins completes. • If 4 pins are selected, when A/D conversion of the 4 selected pins completes. • If 6 pins are selected, when A/D conversion of the 6 selected pins completes. • If 8 pins are selected, when A/D conversion of the 8 selected pins completes. AN0 and AN1 (2 pins), AN8 and AN9 (2 pins), AN16 and AN17 (2 pins) AN0 to AN3 (4 pins), AN8 to AN11 (4 pins), AN16 to AN19 (4 pins), AN0 to AN5 (6 pins), AN8 to AN13 (6 pins), AN0 to AN7 (8 pins), AN8 to AN15 (8 pins), (Selectable by bits SCAN1 to SCAN0 and bits ADGSEL1 to ADGSEL0.) AD0 register: AN0, AN8, AN16, OCVREF AD1 register: AN1, AN9, AN17 AD2 register: AN2, AN10, AN18 AD3 register: AN3, AN11, AN19 AD4 register: AN4, AN12 AD5 register: AN5, AN13 AD6 register: AN6, AN14 AD7 register: AN7, AN15 Read the register among AD0 to AD7 corresponding to the selected pin. REJ09B0441-0010 Rev.0.10 Page 659 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter ADST bit in ADCON0 register 1 0 Successive conversion register AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AD0 register Undefined AN0 in A/D conversion result AD1 register Undefined AN1 in A/D conversion result AD2 register Undefined AN2 in A/D conversion result AD3 register Undefined AN3 in A/D conversion result AD4 register Undefined AN4 in A/D conversion result AD5 register Undefined AN5 in A/D conversion result AD6 register Undefined AN6 in A/D conversion result AD7 register Undefined AN7 in A/D conversion result Set to 0 when an interrupt request is acknowledged, or set by a program. IR bit in ADIC register 1 0 The above applies under the following conditions: • Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (A/D conversion starts by software trigger). • Bits SCAN1 to SCAN0 in the ADINSEL register are set to 11b (8 pins), bits ADGSEL1 to ADGSEL0 are set to 00b (AN0, AN1, AN2, AN3, AN4, AN5, AN6, and AN7). Figure 30.8 Operating Example in Single Sweep Mode REJ09B0441-0010 Rev.0.10 Page 660 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.8 Repeat Sweep Mode In repeat sweep mode, the input voltage to two, four, six, or eight pins selected from among AN0 to AN19 are A/D converted repeatedly. Table 30.8 lists the Repeat Sweep Mode Specifications. Figure 30.9 shows an Operating Example in Repeat Sweep Mode. Table 30.8 Repeat Sweep Mode Specifications Item Function Resolution A/D conversion start conditions A/D conversion stop condition Interrupt request generation timing Specification The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted repeatedly. 8 bits or 10 bits selectable • Software trigger • Timer RD • Timer RC • External trigger (Refer to 30.3.3 A/D Conversion Start Conditions) Set the ADST bit in the ADCON0 register to 0 • If 2 pins are selected, when A/D conversion of the 2 selected pins completes. • If 4 pins are selected, when A/D conversion of the 4 selected pins completes. • If 6 pins are selected, when A/D conversion of the 6 selected pins completes. • If 8 pins are selected, when A/D conversion of the 8 selected pins completes. AN0 and AN1 (2 pins), AN8 and AN9 (2 pins), AN16 and AN17 (2 pins) AN0 to AN3 (4 pins), AN8 to AN11 (4 pins), AN16 to AN19 (4 pins), AN0 to AN5 (6 pins), AN8 to AN13 (6 pins), AN0 to AN7 (8 pins), AN8 to AN15 (8 pins), (Selectable by bits SCAN1 to SCAN0 and bits ADGSEL1 to ADGSEL0.) AD0 register: AN0, AN8, AN16, OCVREF AD1 register: AN1, AN9, AN17 AD2 register: AN2, AN10, AN18 AD3 register: AN3, AN11, AN19 AD4 register: AN4, AN12 AD5 register: AN5, AN13 AD6 register: AN6, AN14 AD7 register: AN7, AN15 Read the register among AD0 to AD7 corresponding to the selected pin. Analog input pins Storage resisters for A/D conversion result Reading of A/D conversion result REJ09B0441-0010 Rev.0.10 Page 661 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter ADST bit in ADCON0 register 1 0 Successive conversion register AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AD0 register Undefined AN0 in A/D conversion result AN0 in A/D conversion result AD1 register Undefined AN1 in A/D conversion result AD2 register Undefined AN2 in A/D conversion result AD3 register Undefined AN3 in A/D conversion result AD4 register Undefined AN4 in A/D conversion result AD5 register Undefined AN5 in A/D conversion result AD6 register Undefined AN6 in A/D conversion result AD7 register Undefined AN7 in A/D conversion result Set to 0 when an interrupt request is acknowledged, or set by a program. IR bit in ADIC register 1 0 The above applies under the following conditions: • Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (A/D conversion starts by software trigger). • Bits SCAN1 to SCAN0 in the ADINSEL register are set to 11b (8 pins), bits ADGSEL1 to ADGSEL0 are set to 00b (AN0, AN1, AN2, AN3, AN4, AN5, AN6, and AN7). Figure 30.9 Operating Example in Repeat Sweep Mode REJ09B0441-0010 Rev.0.10 Page 662 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.9 Internal Equivalent Circuit of Analog Input Figure 30.10 shows the Internal Equivalent Circuit of Analog Input. VCC VCC VSS AVCC Parasitic diode AN0 ON resistor TBD kΩ SW1 Parasitic diode Wiring resistor TBD kΩ ON resistor TBD kΩ Analog input voltage SW2 VIN ON resistor Approx. TBD kΩ SW3 C = Approx.TBD pF AMP Sampling control signal VSS i ladder-type switches i ladder-type wiring resistors SW4 i = 20 ON resistor Wiring resistor TBD kΩ TBD kΩ AN19 SW1 AVSS Chopper-type amplifier b6 b7 ADINSEL ADINSEL register register ADINSEL register b0 b1 b2 b4 b5 A/D successive conversion register Reference control signal VREF Vref Resistor ladder AVSS SW5 A/D conversion interrupt request Comparison voltage ON resistor TBD kΩ Comparison reference voltage (Vref) generator Sampling Com parison Connect to SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress. Their status varies as shown by the waveforms in the left diagrams. Control signal for SW2 Connect to Connect to SW4 conducts only when A/D conversion is not in progress. Connect to Control signal for SW3 SW5 conducts when compare operation is in progress. Note: 1. Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. Figure 30.10 Internal Equivalent Circuit of Analog Input REJ09B0441-0010 Rev.0.10 Page 663 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.10 Output Impedance of Sensor during A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C in Figure 30.11 has to be completed within the period specified as the sampling time T. Let the output impedance of the sensor equivalent circuit be R0, the internal resistance of the MCU be R, the precision (error) of the A/D converter be X, and the resolution of the A/D converter be Y (Y is 1024 in 10-bit mode, and 256 in 8-bit mode). 1 – -------------------------C ( R0 + R )  VC = VIN  1 – e  t VC is generally    And when t = T, X X VC = VIN – --- VIN = VIN  1 – ---   Y Y 1 – --------------------------T C ( R0 + R ) = X --e Y 1 – -------------------------- T = ln X --C ( R0 + R ) Y Hence, T R0 = – ------------------- – R X C • ln --Y Figure 30.11 shows an example of Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1 LSB, the impedance R0 can be obtained if the voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in the time T. (0.1/1024) means that the drop in A/D precision, due to insufficient capacitor charge, is limited to 0.1 LSB during A/D conversion in 10-bit mode. Actual error, however, is the value of absolute precision added to 0.1 LSB. T = TBD µs when f(φAD) = TBD MHz. The output impedance R0 allowing sufficient charging of the capacitor C within the time T is determined as follows: T = TBD µs, R = TBD kΩ, C = TBD pF, X = 0.1, and Y = 1024. Hence, TBD R0 = – ----------------------------------- – TBD ≈ TBD 0.1 TBD • ln ----------1024 Thus, the allowable output impedance R0 of the sensor equivalent circuit, resulting in a precision (error) of 0.1 LSB or less, is approximately TBD kΩ. maximum. MCU Sensor equivalent circuit R0 VIN C (TBD pF) VC R (TBD kΩ) Note: 1. The capacity of the terminal is assumed to be TBD pF. Figure 30.11 Analog Input Pin and External Sensor Equivalent Circuit REJ09B0441-0010 Rev.0.10 Page 664 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 30. A/D Converter 30.11 Notes on A/D Converter • Write to the ADMOD, ADINSEL, ADCON0 (other than the ADST bit), ADCON1, or OCVREFCR register must • be performed while A/D conversion is stopped (before a trigger occurs). To use the A/D converter in repeat mode 0, repeat mode 1, or repeat sweep mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select fOCO-F as φAD. Connect 0.1 µF capacitor between pins VREF and AVSS. Do not enter stop mode during A/D conversion. Do not enter wait mode during A/D conversion regardless of the state of the CM02 bit in the CM0 register (1: Peripheral function clock stops in wait mode or 0: Peripheral function clock does not stop in wait mode). Do not set the FMSTP bit in the FMR0 register to 1 (flash memory stops) during A/D conversion. • • • • REJ09B0441-0010 Rev.0.10 Page 665 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 31. D/A Converter 31. D/A Converter The D/A converters are 8-bit R-2R type units. There are two independent D/A converters. 31.1 Introduction D/A conversion is performed by writing a value to the DAi register (i = 0 or 1). To output the conversion result, set the DAiE bit in the DACON register to 1 (output enabled). Before using D/A conversion, set the corresponding bits PD13_0 and PD13_1 in the PD13 register to 0 (input mode). The output analog voltage (V) is determined by the setting value n (n: decimal) of the DAi register. V = Vref × n/ 256 (n = 0 to 255) Vref: Reference voltage Table 31.1 lists the D/A Converter Specifications. Figure 31.1 shows the D/A Converter Block Diagram and Figure 31.2 shows the D/A Converter Equivalent Circuit. Table 31.1 D/A Converter Specifications Item D/A conversion method Resolution Analog output pins Performance R-2R method 8 bits 2 (DA0 and DA1) DA0 register 0 Data bus R-2R resistor ladder 1 DA0 DA0E bit DA1 register 0 R-2R resistor ladder 1 DA1 DA1E bit Figure 31.1 D/A Converter Block Diagram REJ09B0441-0010 Rev.0.10 Page 666 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 31. D/A Converter DAiE bit R DAi 1 2R MSB DAi register 2R 2R 2R 2R 2R 2R 2R LSB 0 R R R R R R R 2R 0 1 AVSS VREF (2) i = 0 or 1 Notes: 1. The above applies when the value of the DAi register is 2Ah. 2. VREF is not affected by the setting of the VCUT bit in the ADCON1 register. Figure 31.2 D/A Converter Equivalent Circuit REJ09B0441-0010 Rev.0.10 Page 667 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 31. D/A Converter 31.2 31.2.1 Registers D/Ai Register (DAi) (i = 0 or 1) b4 — 0 b3 — 0 b2 — 0 b1 — 0 b0 — 0 R/W R/W Address 00D8h (DA0), 00D9h (DA1) Bit b7 b6 b5 Symbol — — — After Reset 0 0 0 Bit Function b7-b0 Output value of D/A conversion Setting Range 00h to FFh When the D/A converter is not used, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to prevent current from flowing into the R-2R resistor ladder to reduce unnecessary current consumption. 31.2.2 D/A Control Register (DACON) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 — 0 b1 DA1E 0 b0 DA0E 0 R/W R/W R/W — Address 00DCh Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name DA0E D/A0 output enable bit DA1E — — — — — — Function 0: Output disabled 1: Output enabled D/A1 output enable bit 0: Output disabled 1: Output enabled Nothing is assigned. If necessary, set to 0. When read, the content is 0. When the D/A converter is not used, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to prevent current from flowing into the R-2R resistor ladder to reduce unnecessary current consumption. REJ09B0441-0010 Rev.0.10 Page 668 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32. Comparator A Comparator A compares a reference input voltage and an analog input voltage. Comparator A1 and comparator A2 are independent of each other. Note that these comparators share the voltage detection circuit with voltage monitor 1 and voltage monitor 2. Either comparator A1 and comparator A2 or voltage monitor 1 and voltage monitor 2 can be selected to use the voltage detection circuit. 32.1 Introduction The comparison result of the reference input voltage and analog input voltage can be read by software. The result also can be output from the VCOUTi (i = 1 or 2) pin. An input voltage to the LVREF pin can be selected as the reference input voltage. Also, the comparator A1 interrupt and comparator A2 interrupt can be used. Table 32.1 lists the Comparator A Specifications, Figure 32.1 shows the Comparator A Block Diagram, and Table 32.2 lists the Comparator A Pin Configuration. Table 32.1 Comparator A Specifications Comparator A1 Input voltage to the LVCMP1 pin Input voltage to the LVREF pin Comparator A2 Input voltage to the LVCMP2 pin Item Analog input voltage Reference input voltage Comparison target Comparison result monitor Interrupt Digital Switching Filter enable/disable Sampling time Comparison result output Whether passing thorough the reference input voltage by rising or falling. The VW1C3 bit in the VW1C register The VCA13 bit in the VCA1 register Whether higher or lower than the reference input voltage. Comparator A1 interrupt Comparator A2 interrupt (non-makable or maskable selectable) (non-makable or maskable selectable) Interrupt request at: Interrupt request at: Reference input voltage > Reference input voltage > input voltage to the LVCMP1 pin input voltage to the LVCMP2 pin and/or and/or Input voltage to the LVCMP1 pin > Input voltage to the LVCMP2 pin > reference input voltage reference input voltage Supported (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8 Output from the LVCOUT1 pin (Whether the comparison result output is inverted or not can be selected.) Output from the LVCOUT2 pin (Whether the comparison result output is inverted or not can be selected.) REJ09B0441-0010 Rev.0.10 Page 669 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A VCA22 0 Shared with voltage monitor 1 circuit VW1F1 to VW1F0 = 00b fOCO-S = 01b fOCO-S/2 = 10b fOCO-S/4 = 11b VCA26 fOCO-S/8 Sampling clock CM1POR Pin output selection circuit CM1OE LVCMP1 1 + VW1C3 VW1C1 0 1 Edge Digital filter VW1C2 Non-maskable interrupts Maskable interrupts 0 1 LVCOUT1 VCA21 0 1 selection circuit VCA24 0 Shared with voltage monitor 2 VW2F1 to VW2F0 circuit = 00b fOCO-S = 01b fOCO-S/2 = 10b fOCO-S/4 = 11b VCA27 fOCO-S/8 Sampling clock VW1C0 IRQ1SEL CM2POR LVCMP2 1 + - VW2C1 0 1 CM2OE Digital filter VW2C2 0 1 LVCOUT2 VCA23 1 VCA13 Edge selection circuit Non-maskable interrupts Maskable interrupts LVREF 0 VW2C0 IRQ2SEL VCA13: Bit in VCA1 register VCA21, VCA22, VCA23, VCA24, VCA26, VCA27: Bits in VCA2 register VW1C0 to VW1C3, VW1F0, VW1F1: Bits in VW1C register VW2C0, VW2C2, VW2F0, VW2F1: Bits in VW2C register CM1POR, CM2POR, CM1OE, CM2OE, IRQ1SEL, IRQ2SEL: Bits in CMPA register Figure 32.1 Table 32.2 Comparator A Block Diagram Comparator A Pin Configuration Pin Name LVCMP1 LVCOUT1 LVCMP2 LVCOUT2 LVREF I/O Input Output Input Output Input Function Comparator A1 analog pin Comparator A1 comparison result output pin Comparator A2 analog pin Comparator A2 comparison result output pin Comparator reference voltage pin REJ09B0441-0010 Rev.0.10 Page 670 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.2 32.2.1 Registers Voltage Monitor Circuit/Comparator A Control Register (CMPA) b6 — 0 b5 IRQ2SEL 0 b4 IRQ1SEL 0 b3 CM2OE 0 b2 CM1OE 0 b1 CM2POR 0 b0 CM1POR 0 R/W R/W Address 0030h Bit b7 Symbol COMPSEL After Reset 0 Bit b0 Symbol CM1POR b1 b2 b3 b4 b5 b6 b7 Function 0: Non-inverted comparator A1 comparison result is output to LVCOUT1. 1: Inverted comparator A1 comparison result is output to LVCOUT1. CM2POR LVCOUT2 output polarity 0: Non-inverted Comparator A2 comparison result is select bit output to LVCOUT2. 1: Inverted comparator A2 comparison result is output to LVCOUT2. CM1OE LVCOUT1 output enable bit 0: Output disabled 1: Output enabled CM2OE LVCOUT2 output enable bit 0: Output disabled 1: Output enabled IRQ1SEL Voltage monitor 1/comparator A1 0: Non-maskable interrupt interrupt type select bit 1: Maskable interrupt IRQ2SEL Voltage monitor 2/comparator A2 0: Non-maskable interrupt interrupt type select bit 1: Maskable interrupt — Reserved bit Set to 0. COMPSEL Voltage monitor/comparator A 0: Bits IRQ1SEL and IRQ2SEL disabled interrupt type selection enable bit 1: Bits IRQ1SEL and IRQ2SEL enabled Bit Name LVCOUT1 output polarity select bit R/W R/W R/W R/W R/W R/W R/W REJ09B0441-0010 Rev.0.10 Page 671 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 VCAC2 0 b1 VCAC1 0 b0 — 0 R/W — R/W R/W — Address 0031h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. When read, the content is 0. VCAC1 Comparator A1 circuit edge select bit (1) 0: One edge 1: Both edges VCAC2 Comparator A2 circuit edge select bit (2) 0: One edge 1: Both edges — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — — — — Notes: 1. When the VCA1 bit is set to 0 (one edge), the VW1C7 bit in the VW1C register is enabled. Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. When the VCA2 bit is set to 0 (one edge), the VW2C7 bit in the VW2C register is enabled. Set the VW2C7 bit after setting the VCAC2 bit to 0. 32.2.3 Voltage Detect Register 1 (VCA1) b6 — 0 b5 — 0 b4 — 0 b3 VCA13 1 b2 — 0 b1 — 0 b0 — 0 R/W R/W Address 0033h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function — Set to 0. Reserved bits — — VCA13 Comparator A2 signal monitor flag (1) 0: LVCMP2 < reference voltage 1: LVCMP2 ≥ reference voltage or comparator A2 circuit disabled — Set to 0. Reserved bits — — — R R/W Note: 1. When the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled), the VCA13 bit is enabled. When the VCA27 bit in the VCA2 register is set to 0 (comparator A2 circuit disabled), the VCA13 bit is set to 1 (VCMP2 ≥ reference voltage). REJ09B0441-0010 Rev.0.10 Page 672 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.2.4 Voltage Detect Register 2 (VCA2) b2 VCA22 0 0 b1 VCA21 0 0 b0 VCA20 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0034h Bit b7 b6 b5 b4 b3 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 After Reset The LVDAS bit in the OFS register is set to 1. 0 0 0 0 0 After Reset The LVDAS bit in the OFS register is set to 0. 0 0 1 0 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name VCA20 Internal power low consumption enable bit (1) VCA21 Comparator A1 reference voltage input select bit VCA22 LVCMP1 comparison voltage external input select bit VCA23 Comparator A2 reference voltage input select bit VCA24 LVCMP2 comparison voltage external input select bit VCA25 Voltage detection 0 enable bit (3) VCA26 VCA27 Voltage detection 1/comparator A1 enable bit (4) Voltage detection 2/comparator A2 enable bit (5) Function 0: Low consumption disabled 1: Low consumption enabled (2) 0: Internal reference voltage 1: LVREF pin input voltage 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage 0: Internal reference voltage 1: LVREF pin input voltage 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 10.7 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. REJ09B0441-0010 Rev.0.10 Page 673 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.2.5 Voltage Monitor 1 Circuit Control Register (VW1C) b6 — 0 b5 VW1F1 0 b4 VW1F0 0 b3 VW1C3 1 b2 VW1C2 0 b1 VW1C1 1 b0 VW1C0 0 R/W R/W R/W Address 0039h Bit b7 Symbol VW1C7 After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function VW1C0 Comparator A1 interrupt enable bit (1) 0: Disabled 1: Enabled 0: Digital filter enable mode VW1C1 Comparator A1 digital filter (digital filter circuit enabled) disable mode select bit (2) 1: Digital filter disable mode (digital filter circuit disabled) [Condition for setting to 0] VW1C2 Comparator A1 interrupt flag (3, 4) 0 is written. [Condition for setting to 1] When an interrupt request is generated. VW1C3 Comparator A1 signal monitor flag (3) 0: LVCMP1 < reference voltage 1: LVCMP1 ≥ reference voltage or comparator A1 circuit disabled b5 b4 VW1F0 Sampling clock select bit 0 0: fOCO-S divided by 1 VW1F1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 — Reserved bit Set to 0. 0: When LVCMP1 reaches reference voltage VW1C7 Comparator A1 interrupt or above. generation condition select bit (5) 1: When LVCMP1 reaches reference voltage or below. R/W R R/W R/W R/W R/W Notes: 1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit enabled). Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (comparator A1 circuit disabled). To set the VW1C0 bit to 1 (enabled), follow the procedure shown in Table 32.3 Procedure for Setting Bits Associated with Comparator A1 Interrupt. 2. To use the comparator A1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit. 3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit enabled). 4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the VCAC1 bit to 0, set the VW1C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW1C register. Rewriting the VW1C register may set the VW1C2 bit to 1. After rewriting this register, set the VW1C2 bit to 0. REJ09B0441-0010 Rev.0.10 Page 674 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.2.6 Voltage Monitor 2 Circuit Control Register (VW2C) b6 VW2C6 0 b5 VW2F1 0 b4 VW2F0 0 b3 VW2C3 0 b2 VW2C2 0 b1 VW2C1 1 b0 VW2C0 0 R/W R/W R/W Address 003Ah Bit b7 Symbol VW2C7 After Reset 1 Bit b0 b1 Symbol Bit Name VW2C0 Comparator A2 interrupt enable bit (1) VW2C1 b2 VW2C2 b3 b4 b5 VW2C3 VW2F0 VW2F1 b6 b7 VW2C6 VW2C7 Function 0: Disabled 1: Enabled Comparator A2 digital filter disable mode 0: Digital filter enable mode (digital filter circuit enabled) select bit (2) 1: Digital filter disable mode (digital filter circuit disabled) [Condition for setting to 0] Comparator A2 interrupt flag (3, 4) 0 is written. [Condition for setting to 1] When an interrupt request is generated. 0: Not detected WDT detection monitor flag (4) 1: Detected b5 b4 Sampling clock select bit 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 Reserved bit Set to 0. 0: When LVCMP2 reaches reference voltage Comparator A2 interrupt or above. generation condition select bit (5) 1: When LVCMP2 reaches reference voltage or below. R/W R/W R/W R/W R/W R/W Notes: 1. The VW2C0 is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled). Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (comparator A2 circuit disabled). To set the VW1C0 bit to 1 (enabled), follow the procedure shown in Table 32.4 Procedure for Setting Bits Associated Comparator A2 Interrupt. 2. To use the comparator A2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit. 3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the VCAC2 bit to 0, set the VW2C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0. REJ09B0441-0010 Rev.0.10 Page 675 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.3 32.3.1 Monitoring Comparison Results Monitoring Comparator A1 Once the following settings are made, the comparison result of comparator A1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 36. Electrical Characteristics). (1) Set the VCA21 bit in the VCA2 register to 1 (LVREF pin input voltage). (2) Set the VCA22 bit in the VCA2 register to 1 (LVCMP1 pin input voltage). (3) Set the VCA26 bit in the VCA2 register to 1 (comparator A1 circuit enabled). 32.3.2 Monitoring Comparator A2 Once the following settings are made, the comparison result of comparator A2 can be monitored by the VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 36. Electrical Characteristics). (1) Set the VCA23 bit in the VCA2 register to 1 (LVREF pin input voltage). (2) Set the VCA24 bit in the VCA2 register to 1 (LVCMP2 pin input voltage). (3) Set the VCA27 bit in the VCA2 register to 1 (comparator A2 circuit enabled). REJ09B0441-0010 Rev.0.10 Page 676 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.4 Functional Description Comparator A1 and comparator A2 operate independently. The comparison result of the reference input voltage and analog input voltage can be read by software. The result can also be output from the LVCOUTi (i = 1 or 2) pin. An input voltage to the LVREF pin can be used as the reference input voltage. The comparator A1 interrupt or the comparator A2 interrupt can be used by selecting nonmaskable or maskable for each interrupt type. 32.4.1 Comparator A1 Table 32.3 lists the Procedure for Setting Bits Associated with Comparator A1 Interrupt, Figure 32.2 shows an Operating Example of Comparator A1 (Digital Filter Enabled), and Figure 32.3 shows an Operating Example of Comparator A1 (Digital Filter Disabled). Table 32.3 Procedure for Setting Bits Associated with Comparator A1 Interrupt Step 1 2 3 4 5 6 7 (1) 8 9 10 11 12 When Using Digital Filter When Using No Digital Filter Set the COMPSEL bit in the CMPA register to 1 (bits IRQ1SEL and IRQ2SEL enabled). Set the VCA21 bit in the VCA2 register to 1 (LVREF pin input voltage) and the VCA22 bit to 1 (LVCMP1 pin input voltage). Set the VCA26 bit in the VCA2 register to 1 (comparator A1 circuit enabled). Wait for td(E-A). Select the interrupt type by the IRQ1SEL bit in the CMPA register. Select the sampling clock of the digital filter by Set the VW1C1 bit in the VW1C register to 1 bits VW1F0 and VW1F1 in the VW1C (digital filter disabled). register. Set the VW1C1 bit in the VW1C register to 0 − (digital filter enabled). Select the interrupt request timing by the VCAC1 bit in the VCAC register and the VW1C7 bit in the VW1C register. Set the VW1C2 bit in the VW1C register to 0. Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on). Wait for 2 cycles of the sampling clock of − (No wait time required) the digital filter. Set the VW1C0 bit in the VW1C register to 1 (comparator A1 interrupt enabled). Note: 1. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction). REJ09B0441-0010 Rev.0.10 Page 677 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A LVCMP1 Reference voltage (LVREF) 1 VW1C3 bit 0 Sampling clock of digital filter × 2 cycles 1 VW1C2 bit 0 Set to 0 by a program. VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) Set to 0 when an interrupt request is acknowledged or by a program. IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 Sampling clock of digital filter × 2 cycles LVCOUT1 output (CM1POR = 0) 1 0 Set to 0 by a program. 1 VW1C2 bit 0 VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when LVCMP1 reaches reference voltage or above) IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT1 output (CM1POR = 0) 1 VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when LVCMP1 reaches reference voltage or below) VW1C2 bit 0 IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 by a program. Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT1 output (CM1POR = 1) VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register CM1POR, IRQ1SEL: Bits in CMPA register The above applies when: • VCA26 bit in VCA2 register = 1 (comparator A1 circuit enabled) • VW1C0 bit in VW1C register = 1 (comparator A1 interrupt enabled) • CM1OE bit in CMPA register = 1 (output enabled) • VCA22 bit in VCA2 register = 1 (LVCMP1 pin input voltage) • COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) Figure 32.2 Operating Example of Comparator A1 (Digital Filter Enabled) REJ09B0441-0010 Rev.0.10 Page 678 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A LVCMP1 Reference voltage (LVREF) 1 VW1C3 bit 0 Set to 0 by a program. 1 VW1C2 bit 0 VW1C1 bit is set to 1 (digital filter disabled) and VCAC1 bit is set to 1 (both edges) IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 by a program. 1 VW1C2 bit VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when LVCMP1 reaches reference voltage or above) 0 IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 when an interrupt request is acknowledged or by a program. Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT1 output (CM1POR = 0) LVCOUT1 output (CM1POR = 0) 1 VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when LVCMP1 reaches reference voltage or below) VW1C2 bit 0 IR bit in VCMP1IC register (IRQ1SEL = 1) LVCOUT1 output (CM1POR = 1) 1 0 1 0 Set to 0 by a program. Set to 0 when an interrupt request is acknowledged or by a program. VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register CM1POR, IRQ1SEL: Bits in CMPA register The above applies under when: • VCA26 bit in VCA2 register = 1 (comparator A1 circuit enabled) • VW1C0 bit in VW1C register = 1 (comparator A1 interrupt enabled) • CM1OE bit in CMPA register = 1 (output enabled) • VCA22 bit in VCA2 register = 1 (LVCMP1 pin input voltage) • COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) Figure 32.3 Operating Example of Comparator A1 (Digital Filter Disabled) REJ09B0441-0010 Rev.0.10 Page 679 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.4.2 Comparator A2 Table 32.4 lists the Procedure for Setting Bits Associated Comparator A2 Interrupt, Figure 32.4 shows an Operating Example of Comparator A2 (Digital Filter Enabled), and Figure 32.5 shows an Operating Example of Comparator A2 (Digital Filter Disabled). Table 32.4 Procedure for Setting Bits Associated Comparator A2 Interrupt Step 1 2 3 4 5 6 7 (1) 8 9 10 11 12 When Using Digital Filter When Using No Digital Filter Set the COMPSEL bit in the CMPA register to 1 (bits IRQ1SEL and IRQ2SEL enabled). Set the VCA23 bit in the VCA2 register to 1 (LVREF pin input voltage) and the VCA24 bit to 1 (LVCMP2 pin input voltage). Set the VCA27 bit in the VCA2 register to 1 (comparator A2 circuit enabled). Wait for td(E-A). Select the interrupt type by the IRQ2SEL bit in the CMPA register. Select the sampling clock of the digital filter by Set the VW2C1 bit in the VW2C register to 1 bits VW2F0 and VW2F1 in the VW2C register. (digital filter disabled). Set the VW2C1 bit in the VW2C register to 0 − (digital filter enabled). Select the interrupt request timing by the VCAC2 bit in the VCAC register and the VW2C7 bit in the VW2C register. Set the VW2C2 bit in the VW2C register to 0. Set the CM14 bit in the CM1 register to 0 (low- − speed on-chip oscillator on). − (No wait time required) Wait for 2 cycles of the sampling clock of the digital filter. Set the VW2C0 bit in the VW2C register to 1 (comparator A2 interrupt enabled). Note: 1. When the VW2C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction). REJ09B0441-0010 Rev.0.10 Page 680 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A LVCMP2 Reference voltage (LVREF) 1 VCA13 bit 0 Sampling clock of digital filter × 2 cycles 1 VW2C2 bit 0 Set to 0 by a program. VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) Set to 0 when an interrupt request is acknowledged or by a program. IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 Sampling clock of digital filter × 2 cycles LVCOUT2 output (CM2POR = 0) 1 0 Set to 0 by a program. 1 VW2C2 bit 0 VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when LVCMP2 reaches reference voltage or above) IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT2 output (CM2POR = 0) 1 VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when LVCMP2 reaches reference voltage or below) VW2C2 bit 0 IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 by a program. Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT2 output (CM2POR = 1) VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register CM2POR, IRQ2SEL: Bits in CMPA register The above applies when: • VCA27 bit in VCA2 register = 1 (comparator A2 circuit enabled) • VW2C0 bit in VW2C register = 1 (comparator A2 interrupt enabled) • CM2OE bit in CMPA register = 1 (output enabled) • VCA24 bit in VCA2 register = 1 (LVCMP2 pin input voltage) • COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) Figure 32.4 Operating Example of Comparator A2 (Digital Filter Enabled) REJ09B0441-0010 Rev.0.10 Page 681 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A VCMP2 Reference voltage (LVREF) 1 VCA13 bit 0 Set to 0 by a program. 1 VW2C2 bit 0 VW2C1 bit is set to 1 (digital filter disabled) and VCAC2 bit is set to 1 (both edges) IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 by a program. 1 VW2C2 bit VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when LVCMP2 reaches reference voltage or above) 0 IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 when an interrupt request is acknowledged or by a program. Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT2 output (CM2POR = 0) LVCOUT2 output (CM2POR = 0) 1 VW2C2 bit VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when LVCMP2 reaches reference voltage or below) 0 IR bit in VCMP2IC register (IRQ2SEL = 1) LVCOUT2 output (CM2POR = 1) 1 0 1 0 Set to 0 by a program. Set to 0 when an interrupt request is acknowledged or by a program. VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register CM2POR, IRQ2SEL: Bits in CMPA register The above applies when: • VCA27 bit in VCA2 register = 1 (comparator A2 circuit enabled) • VW2C0 bit in VW2C register = 1 (comparator A2 interrupt enabled) • CM2OE bit in CMPA register = 1 (output enabled) • VCA24 bit in VCA2 register = 1 (LVCMP2 pin input voltage) • COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) Figure 32.5 Operating Example of Comparator A2 (Digital Filter Disabled) REJ09B0441-0010 Rev.0.10 Page 682 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 32. Comparator A 32.5 Comparator A1 and Comparator A2 Interrupts Comparator A generates an interrupt request from two sources, comparator A1 and comparator A2. Non-maskable or maskable can be selected for each interrupt type. Refer to 12. Interrupts for details of interrupts. 32.5.1 Non-Maskable Interrupts When the COMPSEL bit in the CMPA register is set to 1 (bits IRQ1SEL and IRQ2SEL enabled) and the IRQiSEL (i = 1 or 2) is set to 0, the comparator Ai interrupt functions as a non-maskable interrupt. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time, a non-maskable interrupt request for comparator Ai is generated. 32.5.2 Maskable Interrupts When the COMPSEL bit in the CMPA register is set to 1 (bits IRQ1SEL and IRQ2SEL enabled) and the IRQiSEL (i = 1 or 2) is set to 1, the comparator Ai interrupt functions as a maskable interrupt. The comparator Ai interrupt uses the corresponding VCMPiIC register (bits IR and ILVL0 to ILVL2) and a single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time, the IR bit in the VCMPiIC register is set to 1 (interrupt requested). Refer to 12.3 Interrupt Control for the VCMPiIC register and 12.1.5.2 Relocatable Vector Tables for interrupt vectors. REJ09B0441-0010 Rev.0.10 Page 683 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B 33. Comparator B Comparator B compares a reference input voltage and an analog input voltage. Comparator B1 and comparator B3 are independent of each other. 33.1 Introduction The comparison result of the reference input voltage and analog input voltage can be read by software. An input to the IVREFi (i = 1 or 3) pin can be used as the reference input voltage. Table 33.1 lists the Comparator B Specifications, Figure 33.1 shows the Comparator B Block Diagram, and Table 33.2 lists the I/O Pins. Table 33.1 Comparator B Specifications Item Analog input voltage Reference input voltage Comparison result Interrupt request generation timing Selectable function Specification Input voltage to the IVCMPi pin Input voltage to the IVREFi pin Read from the INTiCOUT bit in the INTCMP register When the comparison result changes. • Digital filter function Whether the digital filter is applied or not and the sampling frequency can be selected. i = 1 or 3 INT3F1 to INT3F0 f1 = 01b Sampling clock f8 = 10b f32 = 11b INT3EN To INT3 interrupt INT3 INT3CP0 = 0 Digital filter (matches 3 times) INT3F1 to INT3F0 = other than 00b INT3PL = 0 = 00b INT3PL = 1 Both edge detection circuit INT1EN To INT1 interrupt IVCMP3 IVREF3 + - INT3CP0 = 1 Monitor flag IVCMP1 IVREF1 + - Monitor flag INT1CP0 = 1 INT1F1 to INT1F0 = other than 00b INT1PL = 0 = 00b INT1PL = 1 INT1F1 to INT1F0 f1 =01b f8 =10b Sampling clock f32 =11b Both edge detection circuit Digital filter (matches 3 times) INT1 INT1CP0 = 0 INT1CP0, INT1COUT, INT3CP0, INT3COUT: Bits in INTCMP register INT1EN, INT1PL, INT3EN, INT3PL: Bits in INTEN register INT1F0, INT1F1, INT3F0, INT3F1: Bits in INTF register Figure 33.1 Comparator B Block Diagram REJ09B0441-0010 Rev.0.10 Page 684 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B Table 33.2 I/O Pins Pin Name IVCMP1 IVREF1 IVCMP3 IVREF3 I/O Input Input Input Input Function Comparator B1 analog pin Comparator B1 reference voltage pin Comparator B3 analog pin Comparator B3 reference voltage pin REJ09B0441-0010 Rev.0.10 Page 685 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B 33.2 33.2.1 Registers Comparator B Control Register 0 (INTCMP) b6 — 0 b5 — 0 b4 b3 INT3CP0 INT1COUT 0 0 b2 — 0 b1 — 0 b0 INT1CP0 0 R/W R/W R/W R Address 01F8h Bit b7 Symbol INT3COUT After Reset 0 Bit b0 b1 b2 b3 Symbol INT1CP0 — — INT1COUT Comparator B1 monitor flag Bit Name Function Comparator B1 operation enable bit 0: Comparator B1 operation disabled 1: Comparator B1 operation enabled Reserved bits Set to 0. b4 b5 b6 b7 INT3CP0 — — INT3COUT Comparator B3 monitor flag 0: IVCMP1 < IVREF1 or comparator B1 operation disabled 1: IVCMP1 > IVREF1 Comparator B3 operation enable bit 0: Comparator B3 operation disabled 1: Comparator B3 operation enabled Reserved bits Set to 0. 0: IVCMP3 < IVREF3 or comparator B3 operation disabled 1: IVCMP3 > IVREF3 R/W R/W R 33.2.2 External Input Enable Register 0 (INTEN) b6 INT3EN 0 b5 INT2PL 0 b4 INT2EN 0 b3 INT1PL 0 b2 INT1EN 0 b1 INT0PL 0 Function 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges 0: Disabled 1: Enabled 0: One edge 1: Both edges b0 INT0EN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 01FAh Bit b7 Symbol INT3PL After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name INT0EN INT0 input enable bit INT0PL INT0 input polarity select bit (1, 2) INT1EN INT1 input enable bit INT1PL INT1 input polarity select bit (1, 2) INT2EN INT2 input enable bit INT2PL INT2 input polarity select bit (1, 2) INT3EN INT3 input enable bit INT3PL INT3 input polarity select bit (1, 2) Notes: 1. To set the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 12.8.4 Changing Interrupt Sources. REJ09B0441-0010 Rev.0.10 Page 686 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B 33.2.3 INT Input Filter Select Register 0 (INTF) b6 INT3F0 0 b5 INT2F1 0 b4 INT2F0 0 b3 INT1F1 0 b2 INT1F0 0 b1 INT0F1 0 Function b1 b0 Address 01FCh Bit b7 Symbol INT3F1 After Reset 0 Bit b0 b1 b0 INT0F0 0 R/W R/W R/W Symbol Bit Name INT0F0 INT0 input filter select bit INT0F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b3 b2 b2 b3 INT1F0 INT1 input filter select bit INT1F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b5 b4 R/W R/W b4 b5 INT2F0 INT2 input filter select bit INT2F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling b7 b6 R/W R/W b6 b7 INT3F0 INT3 input filter select bit INT3F1 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W R/W REJ09B0441-0010 Rev.0.10 Page 687 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B 33.3 Functional Description Comparator B1 and comparator B3 operate independently. Their operations are the same. Table 33.3 lists the Procedure for Setting Registers Associated with Comparator B. Table 33.3 Procedure for Setting Registers Associated with Comparator B Step Register Bit Setting Value 1 Select the function of pins IVCMPi and IVREFi. Refer to 7.5 Port Settings. However, set registers and bits other than listed in step 2 and the following steps. 2 INTF Select whether to enable or disable the filter. Select the sampling clock. 3 INTCMP INTiCP0 1 (operation enabled) 4 Wait for comparator stability time (TBD µs max.) 5 INTEN INTiEN When using an interrupt: 1 (interrupt enabled) INTiPL When using an interrupt: Select the input polarity. 6 INTiIC ILVL0 to ILVL2 When using an interrupt: Select the interrupt priority level. IR When using an interrupt: 0 (no interrupt requested: initialization) i = 1 or 3 Figure 33.2 shows an Operating Example of Comparator Bi (i = 1 or 3). If the analog input voltage is higher than the reference input voltage, the INTiCOUT bit in the INTCMP register is set to 1. If the analog input voltage is lower than the reference input voltage, the INTiCOUT bit is set to 0. To use the comparator Bi interrupt, set the INTiEN bit in the INTEN register to 1 (interrupt enabled). If the comparison result changes at this time, a comparator Bi interrupt request is generated. Refer to 3 3.4 Comparator B1 and Comparator B3 Interrupts for details of interrupts. Analog input voltage (V) Reference input voltage 0 INTiCOUT bit in INTCMP register 1 0 Set to 0 by a program. IR bit in INTiIC register 1 0 The above applies under the following conditions: Bits INTiF1 to INTiF0 in INTF register = 00b (no filter) INTiPL bit in INTEN register = 0 (both edges) i = 1 or 3 Figure 33.2 Operating Example of Comparator Bi (i = 1 or 3) REJ09B0441-0010 Rev.0.10 Page 688 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B 33.3.1 Comparator Bi Digital Filter (i = 1 or 3) Comparator Bi can use the same digital filter as the INTi input. The sampling clock can be selected by bits INTiF0 and INTiF1 in the INTF register. The INTiCOUT signal output from comparator Bi is sampled every sampling clock. When the level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested). Figure 33.3 shows the Configuration of Comparator Bi Digital Filter, and Figure 33.4 shows an Operating Example of Comparator Bi Digital Filter. INTiF1 to INTiF0 f1 f8 f32 = 01b = 10b = 11b INTiEN INTiCP0 = 0 Sampling clock INTi INTiCP0 = 1 Digital filter (matches 3 times) INTiF1 to INTiF0 = other than 00b To INTi interrupt INTiPL = 0 = 00b Both edge detection circuit INTiCOUT IVCMPi IVREFi + - INTiPL = 1 INTiCP0, INTiCOUT: Bits in INTCMP register INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register i = 1 or 3 Figure 33.3 Configuration of Comparator Bi Digital Filter INTiCOUT signal Sampling timing IR bit in INTiIC register Set to 0 by a program. Note: 1. The above applies when: Bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter used). i =1 or 3 Figure 33.4 Operating Example of Comparator Bi Digital Filter REJ09B0441-0010 Rev.0.10 Page 689 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 33. Comparator B 33.4 Comparator B1 and Comparator B3 Interrupts Comparator B generates an interrupt request from two sources, comparator B1 and comparator B3. The comparator Bi (i = 1 or 3) interrupt uses the same INTiIC register (bits IR and ILVL0 to ILVL2) as the INTi (i = 1 or 3) and a single vector. To use the comparator Bi interrupt, set the INTiEN bit in the INTEN register to 1 (interrupt enabled). In addition, the polarity can be selected by the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. Inputs can also be passed through the digital filter with three different sampling clocks. REJ09B0441-0010 Rev.0.10 Page 690 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34. LCD Drive Control Circuit A liquid crystal display (LCD) drive control circuit is integrated on chip. A maximum of 56 pins can be used for segment output and 8 pins for common output. Up to 416 pixels of an LCD display can be controlled. Segment output pins, common output pins, and the capacity connect pins CL1 and CL2 for the voltage multiplier are shared with the I/O port functions. When the LCD display function is not used, these pins are used as I/O ports. Pins VL1 to VL4 are used as the power supply pins for the LCD drive control circuit. The number of these LCD display function pins varies for each group. Table 34.1 lists the LCD Display Function Pins Provided for Each Group. This chapter applies to the R8C/L3AA Group and R8C/L3AB Group, which have the maximum number of LCD display function pins. For other groups, note that only the pins listed in Table 34.1 are provided. Table 34.1 Shared I/O Port LCD Display Function Pins Provided for Each Group L36A, L36B Group Common output: Max. 8 Segment output: Max. 32 − − − − − − − − − − − − − − − L35A, L35B Group Common output: Max. 4 Segment output: Max. 24 − − − − − − − − − − L38A, L38B Group Common output: Max. 8 Segment output: Max. 48 − − − L3AA, L3AB Group Common output: Max. 8 Segment output: Max. 56 P0 P1 P2 P3 P4 P5 P6 P7 P12 − − − − SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 11 10 9 8 15 14 13 12 11 10 9 8 SEG SEG SEG SEG 23 22 21 20 - SEG SEG SEG SEG 23 22 21 20 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 23 22 21 20 19 18 17 16 23 22 21 20 19 18 17 16 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 27 26 25 24 31 30 29 28 27 26 25 24 31 30 29 28 27 26 25 24 31 30 29 28 27 26 25 24 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 39 38 37 36 35 34 33 32 39 38 37 36 35 34 33 32 39 38 37 36 35 34 33 32 39 38 37 36 35 34 33 32 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − SEG SEG SEG SEG 43 42 41 40 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 51 50 49 48 47 46 45 44 51 50 49 48 47 46 45 44 COM COM COM COM 0 1 2 3 − − − − COM COM COM COM SEG SEG SEG SEG COM COM COM COM SEG SEG SEG SEG COM COM COM COM SEG SEG SEG SEG 0 1 2 3 55 54 53 52 0 1 2 3 55 54 53 52 0 1 2 3 55 54 53 52 − − − − CL2 CL1 − − − − − − CL2 CL1 − − − − − − CL2 CL1 − − CL2 CL1 VL1 VL2 − VL4 VL1 VL2 VL3 VL4 VL1 VL2 VL3 VL4 VL1 VL2 VL3 VL4 Notes: 1. The symbol “-” indicates there is no LCD display function. 2. SEG52 to SEG55 can be used as COM7 to COM4. 3. The R8C/L35A Group and R8C/L35B Group do not have the VL3 pin. The available bias settings are 1/3 bias, 1/2 bias, or static. REJ09B0441-0010 Rev.0.10 Page 691 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.1 Introduction Table 34.2 lists the Specification Overview of LCD Drive Control Circuit (1) and Table 34.3 lists the Specification Overview of LCD Drive Control Circuit (2). Figure 34.1 shows a Block Diagram of LCD Drive Control Circuit. Table 34.2 Specification Overview of LCD Drive Control Circuit (1) Specification Max. 56 pins (SEG0 to SEG55) • Pins SEG0 to SEG51 can be individually controlled for use as an I/O port or a segment output pin. • Pins SEG52 to SEG55 can be individually controlled for use as an I/O port or a common output/segment output pin. Max. 8 pins (COM0 to COM7) • The common output pins can be selected. • Pins COM0 to COM3 can be used I/O ports when not in use as common output pins. • Pins COM4 to COM7 can be individually controlled for use as an I/O port or a segment output pin when not in use as a common output pin. Duty Static 1/2 1/3 1/4 1/8 Common Pin COM0 COM0, COM1 COM0 to COM2 COM0 to COM3 COM0 to COM7 Maximum Number of Display Pixels 56 dots or 8-segment LCD 7 digits 112 dots or 8-segment LCD 14 digits 168 dots or 8-segment LCD 21 digits 224 dots or 8-segment LCD 28 digits 416 dots or 8-segment LCD 52 digits Item Segment output Common output Frame frequency Frame frequency f(FR) = Frequency of LCD clock n × division ratio Notes: n = 32 when f32 is selected n = 4 when fC−LCD is selected LCD clock source: bits LCKS0 to LCKS1 Division ratio: bits LPSC0 to LPSC2 Bias control Note: The R8C/L35A Group and R8C/L35B Group do not have the VL3 pin. The 1/4 bias value cannot be used. External division resistors or the internal voltage multiplier can be used (1) When external division resistors are used • The LCD drive voltage is applied to LCD power supply pins VL1 to VL4 using external division resistors. • The following voltage values are applied to LCD power supply pins VL1 to VL4 based on the bias values set by the LCR0 register. Voltage Value VL4 = VLCD VL3 = 3/4 VLCD VL2 = 2/4 VLCD VL1 = 1/4 VLCD 1/3 bias VL4 = VLCD VL3 = VL2 = 2/3 VLCD VL1 = 1/3 VLCD 1/2 bias VL4 = VLCD VL1 = VL2 = VL3 = 1/2 VLCD VLCD: Maximum value of supply voltage for LCD panel Bias Value 1/4 bias LCD display data register LCD display control data register (2) When the internal voltage multiplier is used 1/4 or 1/2 bias selected: Based on the VL1 voltage, two times the voltage is generated at the VL2 pin, three times the voltage at the VL3 pin, and four times the voltage at the VL4 pin. 1/3 bias selected: Based on the VL1 voltage, two times the voltage is generated at pins VL2 and VL3, and three time the voltage at the VL4 pin. The VL1 voltage can be generated internally or input externally. LCD display data is set in the LCD display data register. 56 bytes When a bit is set to 1, the corresponding segment is turned on. When a bit is set to 0, the corresponding segment is turned off. 56 bytes When a bit is set to 1, the corresponding segment is turned off or inverted. Turning off or inversion is selected by setting the LRVRS bit. REJ09B0441-0010 Rev.0.10 Page 692 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit Table 34.3 Specification Overview of LCD Drive Control Circuit (2) Specification • SEG0 to SEG55: High impedance • COM0 to COM7: High impedance • CL1 to CL2: High impedance • VL1 to VL4: High impedance Item Pin status at after reset Data bus =00b =01b f32 fC-LCD Divide-by-32 Divide-by-4 LPSC0 to LPSC2 Divider Common driver COM0 COM1 COM2 COM3 LCKS0 to LCKS1 Common driver LCR3 Common driver LCR2 Common driver Common/segment driver Common/segment driver LCR0 Common/segment driver Common/segment driver Segment driver Segment voltage control circuit Segment driver SEG53/COM6 Common voltage control circuit LCD base clock (Internal signal) LCR1 SEG55/COM4 SEG54/COM5 LRA0L LRA1L LRA2L LRA0 LRA1 SEG52/COM7 SEG51 SEG50 LCD display data register LCD display data RAM LRA55L LCD display control data register LRA55H Segment driver SEG0 LRA2 LSTAT = 0 LSTAT = 1 VL4 VL3 LSE0 to LSE7 LCD drive voltage control circuit VL2 VL1 CL2 CL1 Figure 34.1 Block Diagram of LCD Drive Control Circuit REJ09B0441-0010 Rev.0.10 Page 693 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2 34.2.1 Registers LCD Control Register (LCR0) b6 LDSPE 0 b5 LBAS1 0 b4 LBAS0 0 b3 LWAV 0 b2 LDTY2 0 b1 LDTY1 0 Function b2 b1 b0 Address 0200h Bit b7 Symbol LSTAT After Reset 0 Bit b0 b1 b2 Symbol LDTY0 LDTY1 LDTY2 b0 LDTY0 0 R/W R/W R/W R/W Bit Name Duty Select Bit b3 b4 b5 LWAV LBAS0 LBAS1 LCD waveform control select bit Bias select bit 0 0 0: Static (COM0 used) 0 0 1: 1/2 duty (COM0 and COM1 used) 0 1 0: 1/3 duty (COM0 to COM2 used) 0 1 1: 1/4 duty (COM0 to COM3 used) 1 0 0: 1/8 duty (COM0 to COM7 used) 1 0 1: Do not set. 1 1 0: Do not set. 1 1 1: Do not set. 0: Segment panel control waveform 1: Dot matrix panel control waveform b5 b4 R/W R/W R/W b6 b7 LDSPE LSTAT LCD display enable bit LCD drive start bit 0 0: 1/2 bias 0 1: 1/3 bias 1 0: 1/4 bias 1 1: Do not set. 0: LCD off 1: LCD on 0: Drive starts 1: Drive stops R/W R/W REJ09B0441-0010 Rev.0.10 Page 694 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2.2 LCD Bias Control Register (LCR1) b6 LVURS 0 b5 LVWT1 0 b4 LVWT0 0 b3 LVLS3 0 b2 LVLS2 0 b1 LVLS1 0 b0 LVLS0 0 R/W R/W R/W R/W R/W Address 0201h Bit b7 Symbol LVUPE After Reset 0 Bit b0 b1 b2 b3 Symbol LVLS0 LVLS1 LVLS2 LVLS3 Bit Name VL1 internally-generated voltage select bit b3 b2 b1 b0 Function LBAS1 to LBAS0 = 00b/10b (1/2, 1/4 bias) LBAS1 to LBAS0 = 01b (1/3 bias) 0 0 0 0 : VL1 = 0 0 0 1 : VL1 = 0 0 1 0 : VL1 = 0 0 1 1 : VL1 = 0 1 0 0 : VL1 = 0 1 0 1 : VL1 = 0 1 1 0 : VL1 = 0 1 1 1 : VL1 = 1 0 0 0 : VL1 = 1 0 0 1 : VL1 = 1 0 1 0 : VL1 = 1 0 1 1 : VL1 = 1 1 0 0 : VL1 = 1 1 0 1 : VL1 = 1 1 1 0 : VL1 = 1 1 1 1 : VL1 = Voltage multiplier wait time select bit b5 b4 1.120 V 1.159 V 1.200 V 1.244 V 1.292 V 1.344 V 1.120 V 1.120 V 1.120 V 1.120 V 1.120 V 1.120 V 1.120 V 1.120 V 1.120 V 1.120 V Other than LDTY2 to LDTY0 = 010b (other than 1/3 duty) 1.120 V 1.159 V 1.200 V 1.244 V 1.292 V 1.344 V 1.400 V 1.461 V 1.527 V 1.600 V 1.680 V 1.768 V 1.120 V 1.120 V 1.120 V 1.120 V LDTY2 to LDTY0 = 010b (1/3 duty) b4 b5 LVWT0 LVWT1 R/W R/W b6 b7 LVURS LVUPE 0 0 : Wait time = f(FR) × 64 counts 0 1 : Wait time = f(FR) × 32 counts 1 0 : Wait time = f(FR) × 16 counts 1 1 : Wait time = f(FR) × 8 counts Voltage multiplier reference 0: VL1 externally-input voltage voltage source select bit 1: VL1 internally-generated voltage Voltage multiplier enable bit 0: Voltage multiplier disabled 1: Voltage multiplier enabled × 48 counts × 24 counts × 12 counts × 6 counts R/W R/W REJ09B0441-0010 Rev.0.10 Page 695 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2.3 LCD Display Control Register (LCR2) b6 — 0 b5 — 0 b4 LRVRS 0 b3 LDSPC 0 Function Other than LDTY2 to LDTY0 = 010b (other than 1/3 duty) b2 b1 b0 Address 0202h Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 Symbol LDFR0 LDFR1 LDFR2 b2 LDFR2 0 b1 LDFR1 0 b0 LDFR0 0 R/W R/W R/W R/W Bit Name Data display control interval select bit LDTY2 to LDTY0 = 010b (1/3 duty) b3 b4 b5 b6 b7 LDSPC LRVRS — — — 0 0 0: Display control interval = f(FR) 0 0 1: Display control interval = f(FR) 0 1 0: Display control interval = f(FR) 0 1 1: Display control interval = f(FR) 1 0 0: Display control interval = f(FR) 1 0 1: Do not set. 1 1 0: Do not set. 1 1 1: Display control interval = LCD data display 0: Data display control disabled control enable bit 1: Data display control enabled LCD display control 0: On/off display mode select bit 1: Inverted display Reserved bits Set to 0. × 16 counts × 32 counts × 64 counts × 128 counts × 256 counts × 12 counts × 24 counts × 48 counts × 96 counts × 192 counts Static Static R/W R/W R/W R/W R/W 34.2.4 LCD Clock Control Register (LCR3) b6 LCKS0 0 b5 — 0 b4 — 0 b3 — 0 b2 LPSC2 0 b1 LPSC1 0 Function b2 b1 b0 Address 0203h Bit b7 Symbol LCKS1 After Reset 0 Bit b0 b1 b2 Symbol LPSC0 LPSC1 LPSC2 b0 LPSC0 0 R/W R/W R/W R/W Bit Name Division ratio select bit b3 b4 b5 b6 b7 — — — LCKS0 LCKS1 Reserved bits 0 0 0: Divide-by-2 0 0 1: Divide-by-4 0 1 0: Divide-by-8 0 1 1: Divide-by-16 1 0 0: Divide-by-32 1 0 1: Divide-by-64 1 1 0: Divide-by-128 1 1 1: Do not set. Set to 0. — LCD clock source select bit b7 b6 0 0: f32 0 1: fC-LCD 1 0: Do not set. 1 1: Do not set. R/W R/W REJ09B0441-0010 Rev.0.10 Page 696 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2.5 LCD Port Select Register 0 (LSE0) b6 LSE06 0 b5 LSE05 0 b4 LSE04 0 b3 LSE03 0 b2 LSE02 0 b1 LSE01 0 Function 0: Port P0_0 1: SEG0 0: Port P0_1 1: SEG1 0: Port P0_2 1: SEG2 0: Port P0_3 1: SEG3 0: Port P0_4 1: SEG4 0: Port P0_5 1: SEG5 0: Port P0_6 1: SEG6 0: Port P0_7 1: SEG7 b0 LSE00 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0206h Bit b7 Symbol LSE07 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE00 LSE01 LSE02 LSE03 LSE04 LSE05 LSE06 LSE07 Bit Name LCD port select bit 0 LCD port select bit 1 LCD port select bit 2 LCD port select bit 3 LCD port select bit 4 LCD port select bit 5 LCD port select bit 6 LCD port select bit 7 34.2.6 LCD Port Select Register 1 (LSE1) b6 LSE14 0 b5 LSE13 0 b4 LSE12 0 b3 LSE11 0 b2 LSE10 0 b1 LSE09 0 Function 0: Port P1_0 1: SEG8 0: Port P1_1 1: SEG9 0: Port P1_2 1: SEG10 0: Port P1_3 1: SEG11 0: Port P1_4 1: SEG12 0: Port P1_5 1: SEG13 0: Port P1_6 1: SEG14 0: Port P1_7 1: SEG15 b0 LSE08 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0207h Bit b7 Symbol LSE15 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE08 LSE09 LSE10 LSE11 LSE12 LSE13 LSE14 LSE15 Bit Name LCD port select bit 8 LCD port select bit 9 LCD port select bit 10 LCD port select bit 11 LCD port select bit 12 LCD port select bit 13 LCD port select bit 14 LCD port select bit 15 REJ09B0441-0010 Rev.0.10 Page 697 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2.7 LCD Port Select Register 2 (LSE2) b6 LSE22 0 b5 LSE21 0 b4 LSE20 0 b3 LSE19 0 b2 LSE18 0 b1 LSE17 0 Function 0: Port P2_0 1: SEG16 0: Port P2_1 1: SEG17 0: Port P2_2 1: SEG18 0: Port P2_3 1: SEG19 0: Port P2_4 1: SEG20 0: Port P2_5 1: SEG21 0: Port P2_6 1: SEG22 0: Port P2_7 1: SEG23 b0 LSE16 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0208h Bit b7 Symbol LSE23 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE16 LSE17 LSE18 LSE19 LSE20 LSE21 LSE22 LSE23 Bit Name LCD port select bit 16 LCD port select bit 17 LCD port select bit 18 LCD port select bit 19 LCD port select bit 20 LCD port select bit 21 LCD port select bit 22 LCD port select bit 23 34.2.8 LCD Port Select Register 3 (LSE3) b6 LSE30 0 b5 LSE29 0 b4 LSE28 0 b3 LSE27 0 b2 LSE26 0 b1 LSE25 0 Function 0: Port P3_0 1: SEG24 0: Port P3_1 1: SEG25 0: Port P3_2 1: SEG26 0: Port P3_3 1: SEG27 0: Port P3_4 1: SEG28 0: Port P3_5 1: SEG29 0: Port P3_6 1: SEG30 0: Port P3_7 1: SEG31 b0 LSE24 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 0209h Bit b7 Symbol LSE31 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE24 LSE25 LSE26 LSE27 LSE28 LSE29 LSE30 LSE31 Bit Name LCD port select bit 24 LCD port select bit 25 LCD port select bit 26 LCD port select bit 27 LCD port select bit 28 LCD port select bit 29 LCD port select bit 30 LCD port select bit 31 REJ09B0441-0010 Rev.0.10 Page 698 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2.9 LCD Port Select Register 4 (LSE4) b6 LSE38 0 b5 LSE37 0 b4 LSE36 0 b3 LSE35 0 b2 LSE34 0 b1 LSE33 0 Function 0: Port P4_0 1: SEG32 0: Port P4_1 1: SEG33 0: Port P4_2 1: SEG34 0: Port P4_3 1: SEG35 0: Port P4_4 1: SEG36 0: Port P4_5 1: SEG37 0: Port P4_6 1: SEG38 0: Port P4_7 1: SEG39 b0 LSE32 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 020Ah Bit b7 Symbol LSE39 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE32 LSE33 LSE34 LSE35 LSE36 LSE37 LSE38 LSE39 Bit Name LCD port select bit 32 LCD port select bit 33 LCD port select bit 34 LCD port select bit 35 LCD port select bit 36 LCD port select bit 37 LCD port select bit 38 LCD port select bit 39 34.2.10 LCD Port Select Register 5 (LSE5) Address 020Bh Bit b7 Symbol LSE47 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE40 LSE41 LSE42 LSE43 LSE44 LSE45 LSE46 LSE47 b6 LSE46 0 b5 LSE45 0 b4 LSE44 0 b3 LSE43 0 b2 LSE42 0 b1 LSE41 0 Function 0: Port P5_0 1: SEG40 0: Port P5_1 1: SEG41 0: Port P5_2 1: SEG42 0: Port P5_3 1: SEG43 0: Port P6_0 1: SEG44 0: Port P6_1 1: SEG45 0: Port P6_2 1: SEG46 0: Port P6_3 1: SEG47 b0 LSE40 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name LCD port select bit 40 LCD port select bit 41 LCD port select bit 42 LCD port select bit 43 LCD port select bit 44 LCD port select bit 45 LCD port select bit 46 LCD port select bit 47 REJ09B0441-0010 Rev.0.10 Page 699 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.2.11 LCD Port Select Register 6 (LSE6) Address 020Ch Bit b7 Symbol LSE55 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE48 LSE49 LSE50 LSE51 LSE52 LSE53 LSE54 LSE55 b6 LSE54 0 b5 LSE53 0 b4 LSE52 0 b3 LSE51 0 b2 LSE50 0 b1 LSE49 0 Function 0: Port P6_4 1: SEG48 0: Port P6_5 1: SEG49 0: Port P6_6 1: SEG50 0: Port P6_7 1: SEG51 0: Port P7_0 1: SEG52 or COM7 0: Port P7_1 1: SEG53 or COM6 0: Port P7_2 1: SEG54 or COM5 0: Port P7_3 1: SEG55 or COM4 b0 LSE48 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name LCD port select bit 48 LCD port select bit 49 LCD port select bit 50 LCD port select bit 51 LCD port select bit 52 LCD port select bit 53 LCD port select bit 54 LCD port select bit 55 34.2.12 LCD Port Select Register 7 (LSE7) Address 020Dh Bit b7 Symbol — After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol LSE56 LSE57 LSE58 LSE59 LSE60 — — — b6 — 0 b5 — 0 b4 LSE60 0 b3 LSE59 0 b2 LSE58 0 b1 LSE57 0 b0 LSE56 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name LCD port select bit 56 LCD port select bit 57 LCD port select bit 58 LCD port select bit 59 LCD port select bit 60 Reserved bits Function 0: Port P7_4 1: COM3 0: Port P7_5 1: COM2 0: Port P7_6 1: COM1 0: Port P7_7 1: COM0 0: Ports P12_2 and P12_3 1: CL1 and CL2 Set to 0. REJ09B0441-0010 Rev.0.10 Page 700 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.3 Data Registers The LCD display data register (LRAL) and the LCD display control data register (LRAH) are available as data registers. When 1 is written to a bit in the LCD display data register, the corresponded segment of the LCD panel is turned on, when a bit is set to 0, the corresponding segment is turned off. When 1 is written to a bit in the LCD display control data register while the LDSPC bit in the LCR2 register is set to 1, the corresponding segment of the LCD panel is operated (turned on/off or inverted) as specified by the LRVRS bit, for the interval selected by bits LDFR0 to LDFR2. bit 7 Symbol LRA0L LRA1L LRA2L LRA3L LRA4L LRA5L LRA6L LRA7L LRA8L LRA9L LRA10L LRA11L LRA12L LRA13L LRA14L LRA15L LRA16L LRA17L LRA18L LRA19L LRA20L LRA21L LRA22L LRA23L LRA24L LRA25L LRA26L LRA27L LRA28L LRA29L LRA30L LRA31L LRA32L LRA33L LRA34L LRA35L LRA36L LRA37L LRA38L LRA39L LRA40L LRA41L LRA42L LRA43L LRA44L LRA45L LRA46L LRA47L Address bit6 bit5 bit4 bit3 bit2 bit1 bit0 Symbol Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LRA48L LRA49L LRA50L LRA51L LRA52L LRA53L LRA54L LRA55L LRA56L LRA57L LRA58L LRA59L LRA60L LRA61L LRA62L LRA63L LRA64L LRA65L LRA66L LRA67L LRA68L LRA69L LRA70L LRA71L LRA72L LRA73L LRA74L LRA75L LRA76L LRA77L LRA78L LRA79L LRA80L LRA81L LRA82L LRA83L LRA84L LRA85L LRA86L LRA87L LRA88L LRA89L LRA90L LRA91L LRA92L LRA93L LRA94L LRA95L 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 Do not set. Figure 34.2 LCD Display Data Register REJ09B0441-0010 Rev.0.10 Page 701 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit bit7 Symbol LRA0H LRA1H LRA2H LRA3H LRA4H LRA5H LRA6H LRA7H LRA8H LRA9H LRA10H LRA11H LRA12H LRA13H LRA14H LRA15H LRA16H LRA17H LRA18H LRA19H LRA20H LRA21H LRA22H LRA23H LRA24H LRA25H LRA26H LRA27H LRA28H LRA29H LRA30H LRA31H LRA32H LRA33H LRA34H LRA35H LRA36H LRA37H LRA38H LRA39H LRA40H LRA41H LRA42H LRA43H LRA44H LRA45H LRA46H LRA47H Address bit6 bit5 bit4 bit3 bit2 bit1 bit0 Symbol LRA48H LRA49H LRA50H LRA51H LRA52H LRA53H LRA54H LRA55H LRA56H LRA57H LRA58H LRA59H LRA60H LRA61H LRA62H LRA63H LRA64H LRA65H LRA66H LRA67H LRA68H LRA69H LRA70H LRA71H LRA72H LRA73H LRA74H LRA75H LRA76H LRA77H LRA78H LRA79H LRA80H LRA81H LRA82H LRA83H LRA84H LRA85H LRA86H LRA87H LRA88H LRA89H LRA90H LRA91H LRA92H LRA93H LRA94H LRA95H Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 Do not set. Figure 34.3 LCD Display Control Data Register REJ09B0441-0010 Rev.0.10 Page 702 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.4 LCD Drive Control Table 34.4 shows an outline of the LCD drive control procedure. Table 34.4 LCD Drive Control Procedure and Status of Segment and Common Pins Procedure Status of Segment and Common Pins Reset LSE0 to LSE7 register setting • Select segment output pins LCD display data register initial value setting • Set the initial value for the data output from the SEG pins LCD display control register initial value setting • Set the initial value for the SEG pin control • I/O port (input) • High-impedance state (Depending on the pull-up control registers) • High-impedance LCR3 register setting • LCKS1 to LCKS0: Select the LCD clock source • LPSC2 to LPSC0: Select the division ratio LCR2 register setting • LDSPC: Enable LCD data display control • LDFR2 to LDFR0: Select the LCD data display control interval Division resistor connected externally VL1 to VL4 Voltage multiplier used LCR1 register setting • LVUPE: Enable the voltage multiplier • LVURS: Select the reference voltage for the voltage multiplier • LVWT1 to LVWT0: Select the wait time for the voltage multiplier • LVLS3 to LVLS0: Select the VL1 internally-generated reference voltage LCR0 register setting • LSTAT: Start LCD control • LDSPE: Enable LCD display • LBAS1 to LBAS0: Select the bias • LWAV: Select LCD waveform control • LDTY2 to LDTY0: Select the duty LCD display data register setting • Set the data output from the SEG pins LCR2 register setting • LDSPC: Enable LCD data display control • LDFR2 to LDFR0: Select the LCD data display control interval At start of LCD control • When the LDSPE bit is set to 0, the segment and common pins output a low-level signal. • When the LDSPE bit is set to 1 and the LVUPE bit is set to 0, the segment and common pins output the content of the LCD display data register. • When the LDSPE bit is set to 1 and the LVUPE bit is set to 1, the segment and common pins output the content of the LCD display data register after the time specified by bits LVWT0 and LVWT1 has elapsed. REJ09B0441-0010 Rev.0.10 Page 703 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.4.1 Segment Output Pin Selection All of the segment output pins SEG0 to SEG55 and common output pins COM0 to COM7 are shared with I/O ports. Since all these pins function as I/O ports after a reset, set the corresponding LSEi bit (i = 00 to 59) bit to 1 for the pins to be used as segment output and common output for LCD displays. Set the corresponding LSEi bit to 0 (I/O port) for the pins not to be used as segment output and common output. If these pins are not used as I/O ports, perform unassigned pin handling for I/O ports (refer to Table 7.24 Unassigned Pin Handling). 34.4.2 LCD Clock Selection Either f32 or fC-LCD is selected as the LCD clock source by setting bits LCKS0 and LCKS1. The division ratio is selected from a range of divide-by-1 to divide-by-64 by setting bits LPSC0 to LPSC2. 34.4.3 LCD Data Display Control The LCD data display control function is used to turn on or off, or to invert an LCD display. This function is enabled by setting the LDSPC bit to 1. A display is turned on or off by setting the LRVRS bit to 0 and inverted by setting the bit to 1. The interval for turning on/off or inversion is selected by bits LDFR0 to LDFR2. 34.4.4 Bias Control The bias is controlled by connecting external division resistors to LCD power supply pins VL1 to VL4 or by using the voltage multiplier. Figure 34.4 shows the Pin Connection and Voltage Levels when Division Resistors are Connected Externally. Figure 34.5 shows the Pin Connection and Voltage Levels when Voltage Multiplier is Used. To connect division resistors externally, set the LVUPE bit to 0. Leave pins CL1 and CL2 open by setting the LSE60 bit to 1. These pins can also be used as I/O ports by setting the LSE60 bit to 0. To use the voltage multiplier, set the LVUPE bit to 1. Select the reference voltage VL1 for the voltage multiplier to input externally or generate one internally by using the LVURS bit. Connect the voltage multiplier capacitor between pins CL1 and CL2. To generate the voltage internally, select the VL1 voltage value by setting bits LVLS0 to LVLS3. The wait time for the voltage multiplier is selected from the count source × 8 to count source × 64 using bits LVW0 and LVW1. Contrast adjustment Contrast adjustment Contrast adjustment VL4 VL3 VL2 CL2 (1) Open CL1 (1) Open VL1 VLCD R4 3/4 VLCD R3 2/4 VLCD R2 VL4 VL3 VL2 CL2 (1) Open CL1 (1) Open VLCD R4 2/3 VLCD 2/3 VLCD R2 VL4 VL3 VL2 CL2 (1) Open CL1 (1) Open VLCD R4 1/2 VLCD 1/2 VLCD 1/4 VLCD R1 VL1 1/3 VLCD R1 VL1 1/2 VLCD R1 1/4 bias selected 1/3 bias selected 1/2 bias selected Note: 1. Pins CL1 and CL2 can be used as I/O ports. Figure 34.4 Pin Connection and Voltage Levels when Division Resistors are Connected Externally REJ09B0441-0010 Rev.0.10 Page 704 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit VL4 VL3 VL2 CL2 CL1 VL1 (1) 4VL1 3VL1 VL4 VL3 3VL1 2VL1 2VL1 2VL1 VL2 CL2 CL1 VL1 (1) 1/4 bias selected 1/2 bias selected 1/3 bias selected Note: 1. When VL1 is generated internally (LVURS = 1). When LVURS is 0, supply VL1 externally. Figure 34.5 Pin Connection and Voltage Levels when Voltage Multiplier is Used 34.4.5 LCD Data Display The bias is selected by setting bits LBAS0 and LBAS1, and the duty is selected by setting bits LDTY0 to LDTY2. Either a segment panel control waveform or a dot matrix panel control waveform is selected by setting the LWAV bit. An LCD display is enabled by setting the LDSPE bit to 1, and the display is started by setting LSTAT bit to 1. The LCD display contents are changed by rewriting the contents of the LCD display data register and the LCR2 register. 34.4.6 Pin Status in Stop Mode The status of the LCD display function pins selected by bits LSE00 to LSE60 in registers LSE0 to LSE7 are shown below. LCD control is restarted by means of the same operation as that used to make LCR0 register settings, as shown the LCD drive control procedure in Table 34.4. Table 34.5 LCD Display Function Pin Status in Stop Mode Pin Name SEG0 to SEG55 COM0 to COM7 CL1 and CL2 VL1 Pin Status Outputs a low-level signal. Outputs a low-level signal. Outputs a low-level signal. • When external division resistors are used (the voltage multiplier is disabled by setting the LVUPE bit in the LCR1 register to 0) High-impedance state. • When the voltage multiplier is used with the VL1 externally-input voltage (the LVUPE bit is set to 1 and the LVURS bit is set to 0) High-impedance state. • When the voltage multiplier is used with the VL1 internally-generated voltage (the LVUPE bit is set to 1 and the LVURS bit is set to 1) Outputs the internally-generated voltage. High-impedance state VL2 to VL4 REJ09B0441-0010 Rev.0.10 Page 705 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.4.7 Pin Status in Power-Off Mode The status of the LCD display function pins selected by bits LSE00 to LSE60 in registers LSE0 to LSE7 are shown in Table 34.6. The operation is started from a reset as shown in Table 34.4. Table 34.6 LCD Display Function Pin Status in Power-Off Mode Pin Name SEG0 to SEG55 COM0 to COM7 CL1 and CL2 VL1 to VL4 Outputs a low-level signal. High-impedance state High-impedance state Pin Status REJ09B0441-0010 Rev.0.10 Page 706 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.5 34.5.1 LCD Drive Waveform Segment Panel Control Waveform Figures 34.6 to 34.17 show the LCD drive waveform corresponding to each duty and bias for segment panel control (LWAV = 0). One frame LCD base clock (Internal signal) VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS -VL1 -VL2 -VL3 -VL4 VL4 VL3 VL2 VL1 VSS -VL1 -VL2 -VL3 -VL4 COM0 On COM1 Off COM2 Off COMn Off COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 COM0 SEG0 COM1-SEG0 COM0-SEG0 Note: 1. n = 3 when 1/4 duty is selected, and n = 7 when 1/8 duty is selected. Figure 34.6 LCD Drive Waveform (LWAV = 0, 1/4, 1/8 duty, 1/4 bias) REJ09B0441-0010 Rev.0.10 Page 707 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit LCD base clock (Internal signal) One frame COM1 COM0 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 On COM1 Off COM2 Off COM0 Off COM1 On COM2 Off COM0 Off COM1 On COM2 On SEG0 Figure 34.7 LCD Drive Waveform (LWAV = 0, 1/3 duty, 1/4 bias) One frame LCD base clock (Internal signal) COM1 COM0 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 On COM1 Off COM0 Off COM1 Off COM0 On COM1 Off COM0 Off COM1 On COM0 On SEG0 Figure 34.8 LCD Drive Waveform (LWAV = 0, 1/2 duty, 1/4 bias) One frame LCD base clock (Internal signal) COM1 Not functional COM0 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 On COM0 Off COM0 Off COM0 Off COM0 On COM0 Off COM0 Off COM0 On COM0 On SEG0 Figure 34.9 LCD Drive Waveform (LWAV = 0, Static, 1/4 bias) REJ09B0441-0010 Rev.0.10 Page 708 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit One frame LCD base clock (Internal signal) VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS -VL1 -VL2 -VL4 VL4 VL2 VL1 VSS -VL1 -VL2 -VL4 COM0 On COM1 Off COM2 Off COMn Off COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 COM0 SEG0 COM1-SEG0 COM0-SEG0 Note: 1. n = 3 when 1/4 duty is selected, and n = 7 when 1/8 duty is selected. Figure 34.10 LCD Drive Waveform (LWAV = 0, 1/4, 1/8 duty, 1/3 bias) REJ09B0441-0010 Rev.0.10 Page 709 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit LCD base clock (Internal signal) One frame COM1 VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS COM0 On COM1 Off COM2 Off COM0 Off COM1 On COM2 Off COM0 Off COM1 On COM2 On COM0 SEG0 Figure 34.11 LCD Drive Waveform (LWAV = 0, 1/3 duty, 1/3 bias) One frame LCD base clock (Internal signal) COM1 VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS COM0 On COM1 Off COM0 Off COM1 Off COM0 On COM1 Off COM0 Off COM1 On COM0 On COM0 SEG0 Figure 34.12 LCD Drive Waveform (LWAV = 0, 1/2 duty, 1/3 bias) One frame LCD base clock (Internal signal) COM1 Not functional COM0 VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS COM0 On COM0 Off COM0 Off COM0 Off COM0 On COM0 Off COM0 Off COM0 On COM0 On SEG0 Figure 34.13 LCD Drive Waveform (LWAV = 0, Static, 1/3 bias) REJ09B0441-0010 Rev.0.10 Page 710 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit One frame LCD base clock (Internal signal) VL4 COM1 VL2 VSS VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS VL4 VL2 COM1-SEG0 VSS -VL2 -VL4 VL4 VL2 COM0-SEG0 VSS -VL2 -VL4 COM0 On COM1 Off COM2 Off COMn Off COM0 On COM1 Off COM2 Off COMn On COM0 On Note: 1. n = 3 when 1/4 duty is selected, and n = 7 when 1/8 duty is selected. Figure 34.14 LCD Drive Waveform (LWAV = 0, 1/4, 1/8 duty, 1/2 bias) REJ09B0441-0010 Rev.0.10 Page 711 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit LCD base clock (Internal signal) One frame VL4 COM1 VL2 VSS VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS COM0 On COM1 Off COM2 Off COM0 Off COM1 On COM2 Off COM0 Off COM1 On COM2 On Figure 34.15 LCD Drive Waveform (LWAV = 0, 1/3 duty, 1/2 bias) One frame LCD base clock (Internal signal) VL4 COM1 VL2 VSS VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS COM0 On COM1 Off COM0 Off COM1 Off COM0 On COM1 Off COM0 Off COM1 On COM0 On Figure 34.16 LCD Drive Waveform (LWAV = 0, 1/2 duty, 1/2 bias) One frame LCD base clock (Internal signal) COM1 Not functional VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS COM0 On COM0 Off COM0 Off COM0 Off COM0 On COM0 Off COM0 Off COM0 On COM0 On Figure 34.17 LCD Drive Waveform (LWAV = 0, Static, 1/2 bias) REJ09B0441-0010 Rev.0.10 Page 712 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.5.2 Dot Matrix Panel Control Waveform Figures 34.18 to 34.29 show the LCD drive waveform corresponding to each duty and bias for dot matrix panel control (LWAV = 1). One frame LCD base clock (Internal signal) VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS -VL1 -VL2 -VL3 -VL4 VL4 VL3 VL2 VL1 VSS -VL1 -VL2 -VL3 -VL4 COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 COM0 SEG0 COM1-SEG0 COM0-SEG0 Note: 1. n = 3 when 1/4 duty is selected, and n = 7 when 1/8 duty is selected. Figure 34.18 LCD Drive Waveform (LWAV = 1, 1/4, 1/8 duty, 1/4 bias) REJ09B0441-0010 Rev.0.10 Page 713 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit LCD base clock (Internal signal) One frame COM1 COM0 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 On COM1 On COM2 Off COM0 On COM1 On COM2 Off COM0 Off COM1 Off COM2 On SEG0 Figure 34.19 LCD Drive Waveform (LWAV = 1, 1/3 duty, 1/4 bias) One frame LCD base clock (Internal signal) COM1 COM0 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 On COM1 Off COM0 On COM1 Off COM0 On COM1 Off COM0 On COM1 Off COM0 Off SEG0 Figure 34.20 LCD Drive Waveform (LWAV = 1, 1/2 duty, 1/4 bias) One frame LCD base clock (Internal signal) COM1 Not functional COM0 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 On COM0 On COM0 Off COM0 Off COM0 On COM0 On COM0 Off COM0 Off COM0 On SEG0 Figure 34.21 LCD Drive Waveform (LWAV = 1, Static, 1/4 bias) REJ09B0441-0010 Rev.0.10 Page 714 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit One frame LCD base clock (Internal signal) VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS -VL1 -VL2 -VL4 VL4 VL2 VL1 VSS -VL1 -VL2 -VL4 COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 COM0 SEG0 COM1-SEG0 COM0-SEG0 Note: 1. n = 3 when 1/4 duty is selected, and n = 7 when 1/8 duty is selected. Figure 34.22 LCD Drive Waveform (LWAV = 1, 1/4, 1/8 duty, 1/3 bias) REJ09B0441-0010 Rev.0.10 Page 715 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit LCD base clock (Internal signal) One frame COM1 VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS COM0 On COM1 On COM2 Off COM0 On COM1 On COM2 Off COM0 Off COM1 Off COM2 On COM0 SEG0 Figure 34.23 LCD base clock (Internal signal) LCD Drive Waveform (LWAV = 1, 1/3 duty, 1/3 bias) One frame COM1 VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS COM0 On COM1 Off COM0 On COM1 Off COM0 On COM1 Off COM0 On COM1 Off COM0 Off COM0 SEG0 Figure 34.24 LCD Drive Waveform (LWAV = 1, 1/2 duty, 1/3 bias) One frame LCD base clock (Internal signal) COM1 Not functional COM0 VL4 VL2 VL1 VSS VL4 VL2 VL1 VSS COM0 On COM0 On COM0 Off COM0 Off COM0 On COM0 On COM0 Off COM0 Off COM0 On SEG0 Figure 34.25 LCD Drive Waveform (LWAV = 1, Static, 1/3 bias) REJ09B0441-0010 Rev.0.10 Page 716 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit One frame LCD base clock (Internal signal) VL4 COM1 VL2 VSS VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS VL4 VL2 COM1-SEG0 VSS -VL2 -VL4 VL4 VL2 COM0-SEG0 VSS -VL2 -VL4 COM0 On COM1 Off COM2 Off COMn On COM0 On COM1 Off COM2 Off COMn On COM0 On Note: 1. n = 3 when 1/4 duty is selected, and n = 7 when 1/8 duty is selected. Figure 34.26 LCD Drive Waveform (LWAV = 1, 1/4, 1/8 duty, 1/2 bias) REJ09B0441-0010 Rev.0.10 Page 717 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit LCD base clock (Internal signal) One frame VL4 COM1 VL2 VSS VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS COM0 On COM1 On COM2 Off COM0 On COM1 On COM2 Off COM0 Off COM1 Off COM2 On Figure 34.27 LCD Drive Waveform (LWAV = 1, 1/3 duty, 1/2 bias) One frame LCD base clock (Internal signal) VL4 COM1 VL2 VSS VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS COM0 On COM1 Off COM0 On COM1 Off COM0 On COM1 Off COM0 On COM1 Off COM0 Off Figure 34.28 LCD Drive Waveform (LWAV = 1, 1/2 duty, 1/2 bias) One frame LCD base clock (Internal signal) COM1 Not functional VL4 COM0 VL2 VSS VL4 SEG0 VL2 VSS COM0 On COM0 On COM0 Off COM0 Off COM0 On COM0 On COM0 Off COM0 Off COM0 On Figure 34.29 LCD Drive Waveform (LWAV = 1, Static, 1/2 bias) REJ09B0441-0010 Rev.0.10 Page 718 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 34. LCD Drive Control Circuit 34.6 34.6.1 Notes on LCD Drive Control Circuit Voltage Multiplier The voltage multiplier boosts the VL1 pin voltage by charging/discharging the capacitor connected between pins CL1 and CL2. As a result, the expected level from the VL4 pin may not achieved when driving a large LCD panel. An external power source is recommended to obtain a stable power supply in these cases. 34.6.2 When Division Resistors are Connected Externally Set the resistor value between pins VL4 and VCC (the total of R1 to R4 as shown in Figure 34.4) to the highest value 100 kΩ or more. REJ09B0441-0010 Rev.0.10 Page 719 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35. Flash Memory The flash memory can perform in the following three rewrite modes: CPU rewrite mode, standard serial I/O mode, and parallel I/O mode. 35.1 Introduction Table 35.1 lists the Flash Memory Version Performance. (Refer to the specifications in Table 1.1 and Table 1.2 for items not listed in Table 35.1.) Table 35.1 Flash Memory Version Performance Specification 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) Refer to Figure 35.1. Byte units Block erase Program and erase control by software commands Rewrite protect control in block units by the lock bit Individual rewrite protect control on blocks A, B, C, and D by bits FMR14, FMR15, FMR16, and FMR17 in the FMR1 register 8 commands 1,000 times 10,000 times Standard serial I/O mode supported Parallel I/O mode supported Item Flash memory operating mode Division of erase blocks Programming method Erasure method Programming and erasure control method (1) Rewrite control Blocks 0 to 6 method (Program ROM) Blocks A, B, C, and D (Data flash) Number of commands Blocks 0 to 6 Programming and erasure endurance (2) (Program ROM) Blocks A, B, C, and D (Data flash) ID code check function ROM code protection Notes: 1. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. 2. Definition of programming and erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 1,000 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1-Kbyte block, and then the block is erased, the programing/ erasure endurance still stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing program operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. Table 35.2 Flash Memory Rewrite Mode CPU Rewrite Mode Standard Serial I/O Mode User ROM area is rewritten using a dedicated serial programmer. User ROM Standard boot program Parallel I/O Mode User ROM area is rewritten using a dedicated parallel programmer. User ROM – Flash Memory Rewrite Mode Function User ROM area is rewritten by executing software commands from the CPU. Rewritable area User ROM Rewrite programs User program REJ09B0441-0010 Rev.0.10 Page 720 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.2 Memory Map The flash memory contains a user ROM area and a boot ROM area (reserved area). Figures 35.1 shows the Flash Memory Block Diagrams of R8C/L35A, L36A, L38A, L3AA, R8C/L35B, L36B, L38B, and L3AB Groups. The user ROM area contains program ROM and data flash. Program ROM: Flash memory mainly used for storing programs Data flash: Flash memory mainly used for storing data to be rewritten (Data flash is not provided in the following groups: R8C/L35B, L36B, L38B, and L3AB.) The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode, standard serial I/O mode, or parallel I/O mode. The rewrite control program (standard boot program) for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area is allocated separately from the user ROM area. REJ09B0441-0010 Rev.0.10 Page 721 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory ROM 48 KB product 03000h Block A: 1 Kbyte Block B: 1 Kbyte Data flash Block C: 1 Kbyte 03FFFh 04000h Block 4: 16 Kbytes 07FFFh 08000h Block 3: 16 Kbytes 0BFFFh 0C000h 0DFFFh 0E000h 0F000h 0FFFFh Program ROM 0BFFFh 0C000h 0DFFFh 0E000h 0F000h 0FFFFh 10000h 11FFFh 12000h 13FFFh 07FFFh 08000h Block D: 1 Kbyte 03FFFh 04000h 03000h ROM 64 KB product Block A: 1 Kbyte Block B: 1 Kbyte Block C: 1 Kbyte Block D: 1 Kbyte Data flash Block 4: 16 Kbytes Block 3: 16 Kbytes Program ROM Block 2: 8 Kbytes Block 1: 4 Kbytes Block 0: 4 Kbytes Block 5: 8 Kbytes Block 5: 8 Kbytes User ROM area Block 2: 8 Kbytes Block 1: 4 Kbytes Block 0: 4 Kbytes User ROM area ROM 96 KB product 03000h Block A: 1 Kbyte Block B: 1 Kbyte Data flash Block C: 1 Kbyte 03FFFh 04000h Block 4: 16 Kbytes 07FFFh 08000h Block 3: 16 Kbytes 0BFFFh 0C000h 0DFFFh 0E000h 0FFFFh 10000h 11FFFh 12000h 13FFFh 14000h 0BFFFh 0C000h 0DFFFh 0E000h Program ROM Block 5: 8 Kbytes Block 6: 8 Kbytes 0FFFFh 10000h 11FFFh 12000h 13FFFh 14000h Block D: 1 Kbyte 03FFFh 04000h 03000h ROM 128 KB product Block A: 1 Kbyte Block B: 1 Kbyte Data flash Block C: 1 Kbyte Block D: 1 Kbyte Block 3: 32 Kbytes Block 2: 8 Kbytes Block 0: 8 Kbytes Block 2: 8 Kbytes Block 0: 8 Kbytes Block 5: 8 Kbytes Block 6: 8 Kbytes Program ROM Block 7: 32 Kbytes Block 7: 32 Kbytes 1BFFFh User ROM area 1BFFFh 1C000h Block 8: 32 Kbytes 23FFFh User ROM area Note: 1. Data flash is not provided in the following groups: R8C/L35B, L36B, L38B, and L3AB. Figure 35.1 Flash Memory Block Diagrams of R8C/L35A, L36A, L38A, L3AA, R8C/L35B, L36B, L38B, and L3AB Groups REJ09B0441-0010 Rev.0.10 Page 722 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.3 Functions to Prevent Flash Memory from being Rewritten Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily. 35.3.1 ID Code Check Function The ID code check function is used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes sent from the serial programmer or the on-chip debugging emulator and the 7-byte ID codes written in the flash memory are checked to see if they match. If the ID codes do not match, the commands sent from the serial programmer or the on-chip debugging emulator are not accepted. For details of the ID code check function, refer to 13. ID Code Areas. REJ09B0441-0010 Rev.0.10 Page 723 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.3.2 ROM Code Protect Function The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased using the OFS register in parallel I/O mode. Refer to 14. Option Function Select Area for details of the OFS register. The ROM code protect function is enabled by writing 1 to the ROMCR bit and writing 0 to the ROMCP1 bit. This prevents the content of the on-chip flash memory from being read or rewritten. Once ROM code protection is enabled, the content of the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protection, erase the block including the OFS register using CPU rewrite mode or standard serial I/O mode. 35.3.3 Option Function Select Register (OFS) b6 LVDAS 1 b5 b4 b3 b2 VDSEL1 VDSEL0 ROMCP1 ROMCR 1 1 1 1 b1 — 1 b0 WDTON 1 (Note 1) R/W R/W R/W R/W R/W Address 0FFFFh Bit b7 Symbol CSPROINI When shipping 1 Bit b0 b1 b2 b3 b4 b5 Symbol Bit Name WDTON Watchdog timer start select bit — Reserved bit ROMCR ROM code protect disable bit ROMCP1 ROM code protect bit VDSEL0 Voltage detection 0 level select bit (2) VDSEL1 Function 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset Set to 1. 0: ROM code protect disabled 1: ROMCP1 bit enabled 0: ROM code protect enabled 1: ROM code protect disabled b5 b4 b6 b7 LVDAS Voltage detection 0 circuit start bit (3) CSPROINI Count source protection mode after reset select bit R/W 0 0: 3.80 V selected (Vdet0_3) R/W 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) 0: Voltage monitor 0 reset enabled after reset R/W 1: Voltage monitor 0 reset disabled after reset 0: Count source protection mode enabled after reset R/W 1: Count source protection mode disabled after reset Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. REJ09B0441-0010 Rev.0.10 Page 724 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer. Execute the software command only to blocks in the user ROM area. The flash module has an erase-suspend function which halts the erase operation temporarily during an erase operation in CPU rewrite mode. During erase-suspend, the user ROM area can be read by a program. Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode. Table 35.3 lists the Differences between EW0 Mode and EW1 Mode. Table 35.3 Differences between EW0 Mode and EW1 Mode EW0 Mode Single-chip mode User ROM EW1 Mode Single-chip mode User ROM Item Operating mode Rewrite control program allocatable area Rewrite control program executable areas RAM (The rewrite control program must User ROM or RAM be transferred before being executed.) However, the program can be executed in the program ROM area when rewriting the data flash area. User ROM User ROM However, blocks which contain the rewrite control program are excluded. Software command Read status register command cannot be • Program and block erase commands restrictions executed. cannot be executed to any block which contains the rewrite control program. • Read status register command cannot be executed. Mode after program or block Read array mode Read array mode erase CPU state during The CPU operates. • The CPU operates while the data flash programming and area is being programmed or block block erasure erased. • The CPU is put in a hold state while the program ROM area is being programmed or block erased. (I/O ports retain the states before the command execution). Flash memory Read bits FST7, FMT5, and FMT4 in Read bits FST7, FMT5, and FMT4 in status detection the FST register by a program. the FST register by a program. Conditions for entering • Set bits FMR20 and FMR21 in the • Set bits FMR20 and FMR21 in the FMR2 program-suspend FMR2 register to 1 by a program. register to 1 by a program (while rewriting • Set bits FMR20 and FMR22 in the the data flash area). FMR2 register to 1 and the enabled • Set bits FMR20 and FMR22 in the FMR2 maskable interrupt is generated. register to 1 and the enabled maskable interrupt is generated. CPU clock 20 MHz 20 MHz Rewritable area REJ09B0441-0010 Rev.0.10 Page 725 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.1 Flash Memory Status Register (FST) b6 FST6 0 b5 FST5 0 b4 FST4 0 b3 — 0 b2 LBDATA X b1 BSYAEI 0 b0 RDYSTI 0 R/W R/W R/W R — R R R R Address 01B2h Bit b7 Symbol FST7 After Reset 1 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name RDYSTI Flash ready status interrupt request flag (1) BSYAEI Flash access error interrupt request flag (2) LBDATA LBDATA monitor flag — FST4 FST5 FST6 FST7 Function 0: No flash ready status interrupt request 1: Flash ready status interrupt request 0: No flash access error interrupt request 1: Flash access error interrupt request 0: Locked 1: Not locked Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0: No program error Program error status flag (3) 1: Program error (3) 0: No erase error Erase error status flag 1: Erase error Erase-suspend status flag 0: Other than erase-suspend 1: During erase-suspend Ready/busy status flag 0: Busy 1: Ready Notes: 1. The RDYSTI bit cannot be set to 1 (flash ready status interrupt request) by a program. In parallel I/O mode, this bit is fixed to 0 (no flash ready status interrupt request). 2. The BSYAEI bit cannot be set to 1 (flash access error interrupt request) by a program. In parallel I/O mode, this bit is fixed to 0 (no flash access error interrupt request). 3. This bit is also set to 1 (error) when a command error occurs. RDYSTI Bit (Flash Ready Status Flag Interrupt Request Flag) When the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled) and autoprogramming or auto-erasure completes, or erase-suspend mode is entered, the RDYSTI bit is set to 1 (flash ready status interrupt request). During interrupt handling, set the RDYSTI bit to 0 (no flash ready status interrupt request). [Condition for setting to 0] Set to 0 by an interrupt handling program. [Condition for setting to 1] When the flash memory status changes from busy to ready while the RDYSTIE bit in the FRMR0 register is set to 1, the RDYSTI bit is set to 1. The status is changed from busy to ready by the following operations: erasing/writing to the flash memory, suspend acknowledgement, forcible termination, completion of the lock bit program, and completion of the read lock bit status. REJ09B0441-0010 Rev.0.10 Page 726 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory BYSAEI Bit (Flash Access Error Interrupt Request Flag) The BYSAEI bit is set to 1 (flash access error interrupt request) when the BSYAEIE bit in the FMR0 register is set to 1 (flash access error interrupt enabled) and the block during auto-programming/auto-erasure is accessed. This bit is also set to 1 if an erase or program error occurs when the CMDERIE bit in the FMR0 register is set to 1 (erase/write error interrupt enabled). During interrupt handling, set the BSYAEI bit to 0 (no flash access error interrupt request). [Conditions for setting to 0] (1) Set to 0 by an interrupt handling program. (2) Execute the status clear instruction. [Conditions for setting to 1] (1) Read or write the area that is being erased/written when the BSYAEIE bit in the FRMR0 register is set to 1 and while the flash memory is busy. Or, read the data flash area while erasing/writing to the program ROM area. (Note that the read value is undefined in both cases. Writing has no effect.) (2) If an erase or program error occurs when the CMDERIE bit in the FMR0 register is set to 1 (erase/write error interrupt enabled). LBDATA Bit (LBDATA Monitor Flag) This is a read-only bit indicating the lock bit status. To confirm the lock bit status, execute the read lock bit status command and read the LBDATA bit after the FST7 bit is set to 1 (ready). The condition for updating this bit is when the program, erase, read lock bit status commands are generated. When the read lock bit status command is input, the FST7 bit is set to 0 (busy). At the time when the FST7 bit is set to 1 (ready), the lock bit status is stored in the LBDATA bit. The data in the LBDATA bit is retained until the next command is input. FST4 Bit (Program Error Status Flag) This is a read-only bit indicating the auto-programming status. The bit is set to 1 if a program error occurs; otherwise, it is set to 0. For details, refer to the description in 35.4.17 Full Status Check. FST5 Bit (Erase Error Status Flag) This is a read-only bit indicating the status of auto-programming or the blank check command. The bit is set to 1 if an erase error or blank check error occurs; otherwise, it is set to 0. Refer to 35.4.17 Full Status Check for details. FST6 Bit (Erase Suspend Status Flag) This is a read-only bit indicating the suspend status. The bit is set to 1 when an erase-suspend request is acknowledged and a suspend status is entered; otherwise, it is set to 0. FST7 Bit (Ready/Busy Status Flag) This is a read-only bit indicating the operating status of the flash memory. The bit is set to 0 during program and erase operations; otherwise, it is set to 1. REJ09B0441-0010 Rev.0.10 Page 727 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.2 Flash Memory Control Register 0 (FMR0) b3 FMSTP 0 b2 FMR02 0 b1 FMR01 0 Function Set to 0. b0 — 0 R/W R/W R/W R/W R/W Address 01B4h Bit b7 b6 b5 b4 Symbol RDYSTIE BSYAEIE CMDERIE CMDRST After Reset 0 0 0 0 Bit b0 b1 b2 b3 Symbol — FMR01 FMR02 FMSTP Bit Name Reserved bit CPU rewrite mode select bit (1) b4 CMDRST b5 b6 b7 CMDERIE BSYAEIE RDYSTIE 0: CPU rewrite mode disabled 1: CPU rewrite mode enabled (1) 0: EW0 mode EW1 mode select bit 1: EW1 mode 0: Flash memory operates Flash memory stop bit (2) 1: Flash memory stops (Low-power consumption state, flash memory initialization) (3) When the CMDRST bit is set to 1, the erase/write Erase/write sequence reset bit sequence is reset and erasure/writing can be forcibly stopped. When read, the content is 0. Erase/write error interrupt enable bit 0: Erase/write error interrupt disabled 1: Erase/write error interrupt enabled Flash access error interrupt enable bit 0: Flash access error interrupt disabled 1: Flash access error interrupt enabled Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled 1: Flash ready status interrupt enabled R/W R/W R/W R/W Notes: 1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. 2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in the FST register is set to 1 (ready). 3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the FST register is set to 0 (busy). FMR01 Bit (CPU Rewrite Mode Select Bit) When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software commands. FMR02 Bit (EW1 Mode Select Bit) When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected. REJ09B0441-0010 Rev.0.10 Page 728 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory FMSTP Bit (Flash Memory Stop Bit) This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1. Write to the FMSTP bit by a program transferred to the RAM. To reduce the power consumption further in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stopped), and low-speed clock mode (XIN clock stopped), set the FMSTP bit to 1. Refer to 10.7.10 Stopping Flash Memory for details. When entering stop mode or wait mode while CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on when exiting stop or wait mode. CMDRST Bit (Erase/Write Sequence Reset Bit) This bit is used to initialize the flash memory sequence and forcibly stop a program or erase command. The user ROM area can be read while the flash memory sequence is being initialized. For addresses and blocks which the program or erase command is forcibly stopped by the CMDRST bit, execute a block erasure again and ensure it completes normally. The time from when the command is forcibly stopped and until reading is enabled is some hundreds µs where the suspend response time is 10 ms. CMDERIE Bit (Erase/Write Interrupt Enable Bit) This bit enables an flash command error interrupt to be generated if a program or block erase error occurs. When the CMDERIE bit is set to 1 (erase/write error interrupt enabled) and erasure/writing is performed, an interrupt is generated if an erase or program error occurs. If a flash command error interrupt is generated, execute the clear status register command during interrupt handling. BSYAEIE Bit (Flash Access Error Interrupt Enable Bit) This bit enables a flash access error interrupt to be generated if the flash memory during rewriting is accessed. RDYSTIE Bit (Flash Ready Status Interrupt Enable Bit) This bit enables a flash ready status error interrupt to be generated when the status of the flash memory sequence changes from the busy to ready status. REJ09B0441-0010 Rev.0.10 Page 729 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.3 Flash Memory Control Register 1 (FMR1) b6 FMR16 0 b5 FMR15 0 b4 FMR14 0 b3 FMR13 0 b2 FMR12 0 b1 FMR11 0 b0 FMR10 0 R/W — — — R/W R/W Address 01B5h Bit b7 Symbol FMR17 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name Function FMR10 Nothing is assigned. If necessary, set to 0. When read, the content is 0. FMR11 FMR12 FMR13 Lock bit disable select bit (1) 0: Lock bit enabled 1: Lock bit disabled FMR14 Data flash block A rewrite 0: Rewrite enabled (software command acceptable) 1: Rewrite disabled (software command not acceptable, disable bit (2) no error occurred) 0: Rewrite enabled (software command acceptable) FMR15 Data flash block B rewrite 1: Rewrite disabled (software command not acceptable, disable bit (2) no error occurred) 0: Rewrite enabled (software command acceptable) FMR16 Data flash block C rewrite 1: Rewrite disabled (software command not acceptable, disable bit (2) no error occurred) 0: Rewrite enabled (software command acceptable) FMR17 Data flash block D rewrite 1: Rewrite disabled (software command not acceptable, disable bit (2) no error occurred) R/W R/W R/W Notes: 1. To set the FMR13 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. 2. To set this bit to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and writing 0. FMR13 Bit (Lock Bit Disable Select Bit) When the FMR13 bit is set to 1 (lock bit disabled), the lock bit is disabled. When the FMR13 bit is set to 0, the lock bit is enabled. Refer to 35.4.10 Data Protect Function for the details of the lock bit. The FMR13 bit enables the lock bit function only and the lock bit data does not change. However, when a block erase command is executed while the FMR13 bit is set to 1, the lock bit data set to 0 (locked) changes to 1 (not locked) after erasure completes. [Conditions for setting to 0] The FMR13 bit is set to 0 when one of the following conditions is met: • Completion of the program command • Completion of the erase command • Generation of a command error • The FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled). • The FMSTP bit in the FMR0 register is set to 1 (flash memory stops). • The CMDRST bit in the FMR0 register is set to 1 (erasure/writing stopped). [Condition for setting to 1] Set to 1 by a program. REJ09B0441-0010 Rev.0.10 Page 730 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory FMR14 Bit (Data Flash Block A Rewrite Disable Bit) When the FMR 14 bit is set to 0, data flash block A accepts program and block erase commands. FMR15 Bit (Data Flash Block B Rewrite Disable Bit) When the FMR 15 bit is set to 0, data flash block B accepts program and block erase commands. FMR16 Bit (Data Flash Block C Rewrite Disable Bit) When the FMR 16 bit is set to 0, data flash block C accepts program and block erase commands. FMR17 Bit (Data Flash Block D Rewrite Disable Bit) When the FMR 17 bit is set to 0, data flash block D accepts program and block erase commands. REJ09B0441-0010 Rev.0.10 Page 731 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.4 Flash Memory Control Register 2 (FMR2) b6 — 0 b5 — 0 b4 — 0 b3 — 0 b2 FMR22 0 b1 FMR21 0 b0 FMR20 0 R/W R/W R/W R/W — R/W R/W R/W R/W Address 01B6h Bit b7 Symbol FMR27 After Reset 0 Bit b0 b1 b2 b3 b4 b5 b6 b7 Symbol Bit Name FMR20 Erase-suspend enable bit (1) Function 0: Erase-suspend disabled 1: Erase-suspend enabled FMR21 Erase-suspend request bit 0: Erase restart 1: Erase-suspend request 0: Erase-suspend request disabled by interrupt request FMR22 Interrupt request suspend 1: Erase-suspend request enabled by interrupt request request enable bit (1) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Reserved bits Set to 0. — — 0: Low-consumption-current read mode disabled FMR27 Low-consumption-current 0: Low-consumption-current read mode enabled read mode enable bit (1) Note: 1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. FMR20 Bit (Erase-Suspend Enable Bit) When the FMR20 bit is set to 1 (enabled), the erase-suspend function is enabled. FMR21 Bit (Erase-Suspend Request Bit) When the FMR21 bit is set to 1, erase-suspend mode is entered. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request) when an interrupt request for the enabled interrupt is generated, and erase-suspend mode is entered. To restart autoerasure, set the FMR21 bit to 0 (erase restart). [Condition for setting to 0] Set to 0 by a program. [Conditions for setting to 1] • The FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request) when an interrupt is generated. • Set to 1 by a program. FMR22 Bit (Interrupt Request Suspend-Request Enable Bit) When the FMR 22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request) at the time an interrupt request is generated during auto-erasure. Set the FMR22 bit to 1 when using erase-suspend while rewriting the user ROM area in EW1 mode. FMR27 Bit (Low-Power-Current Read Mode Enable Bit) When the FMR 27 bit is set to 1 (low-consumption-current read mode enabled) in low-speed clock mode (XIN clock stopped) or low-speed on-chip oscillator mode (XIN clock stopped), power consumption when reading the flash memory can be reduced. Refer to 10.7.11 Low-Current-Consumption Read Mode for details. REJ09B0441-0010 Rev.0.10 Page 732 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.5 EW0 Mode When the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), the MCU enters CPU rewrite mode and software commands can be accepted. At this time, the FMR02 bit in the FMR0 register is set to 0 so that EW0 mode is selected. Software commands are used to control program and erase operations. The FST register or the status register can be used to confirm whether programming or erasure has completed. To enter erase-suspend during auto-erasure, set the FMR20 bit to 1 (erase-suspend enabled) and the FMR21 bit to 1 (erase-suspend request). Wait for td(SR-SUS) and ensure that the FST6 bit in the FST register is set to 1 (during erase-suspend) before accessing the flash memory. Auto-erasure can be restarted by setting the FMR21 bit in the FMR2 register to 0 (erase restart). 35.4.6 EW1 Mode After the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), EW1 mode is selected by setting the FMR02 bit is set to 1. The FST register can be used to confirm whether programming and erasure has completed. Do not execute the read status register command in EW1 mode. To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the FMR20 bit in the FMR2 register to 1 (suspend enabled). To enter erase-suspend while auto-erasing the user ROM area, set the FMR22 bit in the FMR2 register to 1 (erase-suspend request enabled by interrupt request). Also, the interrupt to enter program-suspend must be enabled beforehand. When an interrupt request is generated, the FMR21 bit in the FMR2 register is automatically set to 1 (erasesuspend request) and auto-erasure suspends after td(SR-SUS). After interrupt handling completes, set the FMR21 bit to 0 (erase restart) to restart auto-erasure. 35.4.7 Suspend Operation Figure 35.2 shows the Suspend Operation Timing. Data ROM Erase Suspend (readable) Data read Suspend (readable) Program Suspend (readable) Erase User ROM User program Issue Command User program Set FMR21 bit to 1 User program Flash ready interrupt handling Issue Command User program Flash ready Set interrupt FMR21 handling bit to 0 User program Flash ready interrupt handling User program FMR21 bit in FMR2 register FST7 bit in FST register FST6 bit in FST register RDYSTI bit in FST register td(SR-SUS) 1 is set automatically. 1 is set automatically. 1 is set automatically. Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. Figure 35.2 Suspend Operation Timing REJ09B0441-0010 Rev.0.10 Page 733 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.8 How to Set and Exit Each Mode Figure 35.3 shows How to Set and Exit EW0 Mode and Figure 35.4 shows How to Set and Exit EW0 Mode (When Rewriting Data Flash) and EW1 Mode. EW0 Mode Execution Procedure (When Rewriting User ROM) Rewrite control program After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) (1) Transfer the rewrite mode program that uses CPU rewrite mode to RAM Execute software commands Jump to the rewrite control program transferred to the RAM (The subsequent process is executed by the rewrite control program in the RAM) Write 0 (CPU rewrite mode disabled) to the FMR01 bit Jump to the specified address in the flash memory FMR01: Bit in FMR0 register Note: To set the FMR01 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. Writing to the FMR01 bit must be performed in the RAM. Figure 35.3 How to Set and Exit EW0 Mode EW0 Mode Execution Procedure (When Rewriting Data Flash) EW1 Mode Execution Procedure Program in ROM After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) (1) After writing 0 to the FMR02 bit, write 1 (EW1 mode) (2) Execute software commands Write 0 (CPU rewrite mode disabled) to the FMR01 bit FMR01, FMR02: Bits in FMR0 register Notes: 1. To set the FMR01 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. 2. Not required when rewriting the data flash in EW0 mode. Figure 35.4 How to Set and Exit EW0 Mode (When Rewriting Data Flash) and EW1 Mode REJ09B0441-0010 Rev.0.10 Page 734 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.9 BGO (BackGround Operation) Function When the program ROM area is specified while a program or block erase operation to the data flash, array data can be read. This eliminates the need for writing software commands. Access time is the same as for normal read operations. Figure 35.5 shows the BGO Function. Time Data flash Erase/program Program ROM Read Read Read Read Figure 35.5 BGO Function REJ09B0441-0010 Rev.0.10 Page 735 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.10 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR13 bit in the FMR1 register is set to 0 (lock bit enabled). The lock bit can be used to disable (lock) programming or erasing each block. This prevents data from being written or erased inadvertently. A block status changes according to the lock bit as follows: • When the lock bit data is set to 0: locked (the block cannot be programmed or erased) • When the lock bit data is set to 1: not locked (the block can be programmed and erased) The lock bit data is set to 0 (locked) by executing the lock bit program command and to 1 (not locked) by erasing the block. No commands can be used to set only the lock bit data to 1. The lock bit data can be read using the read lock bit status command. When the FMR13 bit is set to 1 (lock bit disabled), the lock bit function is disabled and all blocks are not locked (each lock bit data remains unchanged). The lock bit function is enabled by setting the FMR13 bit to 0 (the lock bit data is retained). When the block erase command is executed while the FMR13 bit is set to 1, the target block is erased regardless of the lock bit status. The lock bit of the erase target block is set to 1 after auto-erasure completes. Refer to 35.4.11 Software Commands for the details of individual commands. The FMR13 bit is set to 0 after auto-erasure completes. This bit is also set to 0 if one of the following conditions is met. To erase or program a different locked block, set the FMR 13 bit to 1 again and execute the block erase or program command. • The FST7 bit in the FST register changes from 0 (busy) to 1 (ready). • An incorrect command is input. • The FMR01 bit in the FMR0 register is set to 0 (CPU mode disabled). • The FMSTP bit in the FM0 register is set to 1 (flash memory stops). Figure 35.6 shows the FMR13 Bit Operation Timing. Erase start Operation FST7 bit (Ready/busy status flag) FMR13 bit (Lock bit disable select bit) 1 0 Erase Erase completion 0 is set at the rising edge of the FST7 bit. 1 0 Set to 1 by a program. Lock bit enabled FST7: Bit in FST register FMR13: Bit in FMR1 register Figure 35.6 FMR13 Bit Operation Timing REJ09B0441-0010 Rev.0.10 Page 736 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.11 Software Commands The software commands are described below. Read or write commands and data in 8-bit units. Table 35.4 Software Commands Command Read array Read status register Clear status register Program Block erase Lock bit program Read lock bit status Block blank check Mode Write Write Write Write Write Write Write Write First Bus Cycle Address × × × WA × BT × × Data FFh 70h 50h 40h 20h 77h 71h 25h Mode Read Write Write Write Write Write Second Bus Cycle Address Data × WA BA BT BT BA SRD WD D0h D0h D0h D0h SRD: Status register data WA: Write address WD: Write data BA: Any block address BT: Starting block address ×: Any address in the user ROM area 35.4.11.1 Read Array Command The read array command is used to read the flash memory. When FFh is written in the first bus cycle, the MCU enters read array mode. When the read address is input in the following bus cycles, the content of the specified address can be read in 8-bit units. Since read array mode remains until another command is written, the contents of multiple addresses can be read continuously. In addition, the MCU enters read array mode after a reset. 35.4.11.2 Read Status Register Command The read status register command is used to read the status register. When 70h is written in the first bus cycle, the status register can be read in the second bus cycle. When reading the status register, read the same address as the address value in the first bus cycle. In CPU rewrite mode, do not execute this command. Read status register mode remains until the next read array command is written. 35.4.11.3 Clear Status Register Command The clear status register command is used to set the status register to 0. When 50h is written in the first bus cycle, bits FST4 and FST5 in the FST register and bits SR4 and SR5 in the status register are set to 0. If the clear status register is input in read array mode, the MCU enters read array mode after the status register is set to 0. REJ09B0441-0010 Rev.0.10 Page 737 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.11.4 Program Command The program command is used to write data to the flash memory in 1-byte units. When 40h is written in the first bus cycle and data is written in the second bus cycle to the write address, autoprogramming (data program and verify operation) starts. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. The FST7 bit in the FST register can be used to confirm whether auto-programming has completed. The FST7 bit is set to 0 during auto-programming and is set to 1 when auto-programming completes. After auto-programming has completed, the auto-program result can be confirmed by the FST4 bit in the FST register (refer to 35.4.17 Full Status Check). Do not write additions to the already programmed addresses. The program command targeting each block in the program ROM can be disabled using the lock bit. The following commands are not accepted under the following conditions: • Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1 (rewrite disabled). • Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled). • Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled). • Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled). Figure 35.7 shows a Program Flowchart (Flash Ready Status Interrupt Disabled) and Figure 35.8 shows a Program Flowchart (Flash Ready Status Interrupt Enabled). In EW1 mode, do not execute this command to any address where a rewrite control program is allocated. When RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled), a flash ready status interrupt can be generated upon completion of auto-programming. The auto-program result can be confirmed by reading the FST register during the interrupt routine. Start Write the command code 40h Write data to the write address FST7 = 1? No Yes Full status check Program completed FST7: Bit in FST register Figure 35.7 Program Flowchart (Flash Ready Status Interrupt Disabled) REJ09B0441-0010 Rev.0.10 Page 738 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Start Flash ready status interrupt RDYSTIE = 1 Status check Write the command code 40h RDYSTI = 0 I = 1 (interrupt enabled) REIT Write data to the write address Program completed RDYSTI: Bit in FST register RDYSTIE: Bit in FMR0 register Figure 35.8 Program Flowchart (Flash Ready Status Interrupt Enabled) REJ09B0441-0010 Rev.0.10 Page 739 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.11.5 Block Erase Command When 20h is written in the first bus cycle and then D0h is written in the second bus cycle to any block address, auto-erasure (erase and erase verify operation) starts in the specified block. The FST7 bit in the FST register can be used to confirm whether auto-erasure has completed. The FST7 bit is set to 0 during auto-erasure and is set to 1 when auto-erasure completes. After auto-erasure has completed, the auto-erase result can be confirmed by the FST5 bit in the FST register. (Refer to 35.4.17 Full Status Check). The block erase command targeting each block in the program ROM can be disabled using the lock bit. The following commands are not accepted under the following conditions: • Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1 (rewrite disabled). • Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled). • Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled). • Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled). Figure 35.9 shows the Block Erase Flowchart (Flash Ready Status Interrupt Disabled), Figure 35.10 shows the Block Erase Flowchart (Flash Ready Status Interrupt Disabled and Suspend Enabled), and Figure 35.11 shows the Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled). In EW1 mode, do not execute this command to any block where a rewrite control program is allocated. While the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled), a flash ready status interrupt can be generated upon completion of auto-erasure. While the RDYSTIE bit is set to 1 and the FMR20 bit in the FMR2 register is set to 1 (erase-suspend enabled), a flash ready status interrupt is generated when the FMR21 bit is set to 1 (erase-suspend request) and auto-erasure suspends. The auto-erase result can be confirmed by reading the FST register during the interrupt routine. REJ09B0441-0010 Rev.0.10 Page 740 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Start Write the command code 20h Write D0h to any block address FST7 = 1? No Yes Full status check Block erase completed FST7: Bit in FST register Figure 35.9 Block Erase Flowchart (Flash Ready Status Interrupt Disabled) REJ09B0441-0010 Rev.0.10 Page 741 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Start Maskable interrupt (1) FMR20 = 1 FMR21 = 1 (2) Write the command code 20h FST6 = 1? Yes Access the flash memory No I = 1 (interrupt enabled) Write D0h to any block address FMR21 = 0 FST7 = 1? No REIT Yes Full status check I: Flag in CPU register FST6, FST7: Bits in FST register FMR20, FMR21: Bits in FMR2 register Block erase completed Notes: 1. The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other the erase target area. 2. td(SR-SUS) is required until suspend is acknowledged after the FMR21 bit is set to 1. The interrupt to enter suspend must be enabled beforehand. Figure 35.10 Block Erase Flowchart (Flash Ready Status Interrupt Disabled and Suspend Enabled) REJ09B0441-0010 Rev.0.10 Page 742 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Start Maskable interrupt (1) RDYSTIE = 1 FMR21 = 1 (2) FMR20 = 1 REIT Write the command code 20h I = 1 (interrupt enabled) Write D0h to any block address Block erase completed Flash ready status interrupt (1, 3) FST6 = 1? Yes Access the flash memory No Full status check FMR21 = 0 RDYSTI = 0 I: Flag in CPU register RDYSTI, FST6: Bits in FST register RDYSTIE: Bit in FMR0 register FMR20, FMR21: Bits in FMR2 register REIT Notes: 1. The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other the erase target area. 2. td(SR-SUS) is required until suspend is acknowledged after the FMR21 bit is set to 1. The interrupt to enter suspend must be enabled beforehand. 3. When auto-erasure suspends, a flash ready status interrupt is generated. Figure 35.11 Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled) REJ09B0441-0010 Rev.0.10 Page 743 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.11.6 Lock Bit Program Command This command is used to set the lock bit of any block in the program ROM area to 0 (locked). When 77h is written in the first bus cycle and D0h is written in the second bus cycle to the starting block address, 0 is written to the lock bit of the specified block. Make sure the address value in the first bus cycle is the same address as the starting block address specified in the second bus cycle. Figure 35.12 shows the Lock Bit Program Flowchart. The lock bit status (lock bit data) can be read using the read lock bit status command. The FST7 bit in the FST register can be used to confirm whether writing to the lock bit has completed. Refer to 35.4.10 Data Protect Function for the lock bit function and how to set the lock bit to 1 (not locked). Start Write the command code 77h Write D0h to the starting block address FST7 = 1? No Yes Full status check Completed FST7: Bit in FST register Figure 35.12 Lock Bit Program Flowchart REJ09B0441-0010 Rev.0.10 Page 744 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.11.7 Read Lock Bit Status Command This command is used to read the lock bit status of any address in the program ROM area. When 71h written in the first bus cycle and D0h is written in the second cycle to the starting block address, the lock bit status of the specified block is stored in the LBDATA bit in the FST register. After the FST7 bit in the FST register has been set to 1 (ready), read the LBDATA bit. Figure 35.13 shows the Read Lock Bit Status Flowchart. Start Write the command code 71h Write D0h to the starting block address FST7 = 1? Yes No No LBDATA = 1? Yes Block not locked Block locked LBDATA, FST7: Bits in FST register Figure 35.13 Read Lock Bit Status Flowchart REJ09B0441-0010 Rev.0.10 Page 745 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.11.8 Block Blank Check Command This command is used to confirm that all addresses in any block are blank data FFh. When 25h is written in the first bus cycle and D0h is written in the second bus cycle to any block address, blank checking starts in the specified block. The FST7 bit in the FST register can be used to confirm whether blank checking has completed. The FST7 bit is set to 0 during the blank-check period and set to 1 when blank checking completes. After blank checking has completed, the blank-check result can be confirmed by the FST5 bit in the FST register. (Refer to 35.4.17 Full Status Check.). Figure 35.14 shows the Block Blank Check Flowchart. Start Write the command code 25h Write D0h to the starting block address FST7 = 1? Yes No No FST5 = 0? Yes Blank Not blank FST5, FST7: Bits in FST register Figure 35.14 Block Blank Check Flowchart REJ09B0441-0010 Rev.0.10 Page 746 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.12 Status Register The status register indicates the operating status of the flash memory and whether erasure or programming has completed normally or terminated in error. The status of the status register can be read by using the FST register. 35.4.13 Sequence Status The clear sequence status bit indicates the operating status of the flash memory. This bit is set to 0 (busy) during auto-programming and auto-erasure. It is set to 1 (ready) when these operations complete. 35.4.14 Erase Status Refer to 35.4.17 Full Status Check. 35.4.15 Program Status Refer to 35.4.17 Full Status Check. 35.4.16 Suspend Status The suspend status bit indicates the suspend status of the flash memory commands. This bit is set to 1 (during erase-suspend) while auto-erasure suspends and set to 0 (other than erase-suspend) when auto-erasure restarts. Table 35.5 lists the Status Register. Table 35.5 Status Register Status Register Bit SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) SR5 (D5) SR6 (D6) SR7 (D7) FST Register Bit − − − − FST4 Status Name Reserved Reserved Reserved Reserved Program status Erase status/ blank check Suspend status Sequencer status Content 0 − − − − Completed normally Completed normally Other than erase-suspend Busy 1 − − − − Terminated in error Terminated in error During erase-suspend Ready Value After Reset − − − − 0 0 0 1 FST5 FST6 FST7 D0 to D7: Indicate the data bus which is read when the read status register command is executed. Bits FST4 (SR4) and FST5 (SR5) are set to 0 by executing the clear status command. When the FST4 bit (SR4) or FST5 bit (SR5) is set to 1, the program and block erase commands cannot be accepted. REJ09B0441-0010 Rev.0.10 Page 747 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.4.17 Full Status Check If an error occurs, bits FST4 and FST5 in the FST register are set to 1, indicating the occurrence of an error. The execution result can be confirmed by checking these status bits (full status check). Table 35.6 lists the Errors and FST Register Status. Figure 35.15 shows the Full Status Check and Handling Procedure for Individual Errors. Table 35.6 Errors and FST Register Status FST Register (Status Register) Status Error FST5 (SR5) FST4 (SR4) 1 1 Command sequence error Error Occurrence Condition 1 0 0 1 • When a command is not written correctly. • When data other than valid data (i.e., D0h or FFh) is written in the second bus cycle of the block erase command. (1) Erase error When the block erase command is executed, but autoerasure does not complete correctly. Blank check error When the blank check command is executed and data other than blank data FFh is read. Program error When the program command is executed, but autoprogramming does not complete correctly. Note: 1. When FFh is written in the second bus cycle of these commands, the MCU enters read array mode. At the same time, the command code written in the first bus cycle is invalid. REJ09B0441-0010 Rev.0.10 Page 748 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Command sequence error Full status check Execute the clear status register command (Set the status flags to 0) FST4 = 1 and FST5 = 1? No Yes Command sequence error Check if the command is properly input Re-execute the command FST5 = 1? No Yes Erase error/ blank check error Erase error/ blank check error Execute the clear status register command (Set the status flags to 0) FST4 = 1? No Yes Program error Is the lock bit disabled? or Is the command executed on the data flash area? No Set the FMR13 bit to 1 Yes Erase command Re-execution times ≤ 3 times? Yes No The erasure target block cannot be used Full status check completed Re-execute the block erase command Note: 1. To rewrite to the address where the program error occurs, ensure that the full status check completes normally and write to the address after the block erase command is executed. Program error Execute the clear status register command (Set the status flags to 0) Is the lock bit disabled? or Is the command executed on the data flash area? No Set the FMR13 bit to 1 Yes Specify an address other than the write address where the error occurs (1) as the program address Re-execute the program command FST4, FST5: Bits in FST register FMR13: Bit in FMR1 register Figure 35.15 Full Status Check and Handling Procedure for Individual Errors REJ09B0441-0010 Rev.0.10 Page 749 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.5 Standard Serial I/O Mode In standard serial I/O mode, a serial programmer which supports the MCU can be used to rewrite the user ROM area while the MCU is mounted on-board. There are three types of standard serial I/O modes: • Standard serial I/O mode 1 .................Clock synchronous serial I/O used to connect to a serial programmer • Standard serial I/O mode 2 .................Clock asynchronous serial I/O used to connect to a serial programmer • Standard serial I/O mode 3 .................Special clock asynchronous serial I/O used to connect to a serial programmer Standard serial I/O mode 2 and standard serial I/O mode 3 can be used for the MCU. Refer to Appendix 2. Connection Examples with M16C Flash Starter for examples of connecting to a serial programmer. Contact the serial programmer manufacturer for more information. Refer to the user’s manual included with your serial programmer for instructions. Table 35.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2) and Figure 35.16 shows Pin Handling in Standard Serial I/O Mode 2. Table 35.8 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3) and Figure 35.17 shows Pin Handling in Standard Serial I/O Mode 3. After handling the pins shown in Table 35.8 and rewriting the flash memory using the programmer, apply a highlevel signal to the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode. 35.5.1 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match. Refer to 13. ID Code Areas for details of the ID code check. REJ09B0441-0010 Rev.0.10 Page 750 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Table 35.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Pin VCC, VSS RESET P12_0/XIN P12_1/XOUT XCIN XCOUT P0 to P7 P10, P11, P12_2 to P12_3 P13_0, P13_3 to P13_7 VREF MODE P13_2 P13_1 Name Power supply input Reset input I/O I Description Apply the guaranteed programming and erasure voltage to the VCC pin and 0 V to the VSS pin. Reset input pin P12_0 input/clock input I Connect a ceramic resonator or crystal oscillator P12_1 input/clock output I/O between pins XIN and XOUT. Clock input I Connect a crystal oscillator between pins XCIN and Clock output I/O XCOUT. Input ports P0 to P7 I Input a high- or low-level signal or leave open. Input ports P10 to P12 I Input a high- or low-level signal or leave open. Input port P13 Reference voltage MODE TXD output RXD input I I I/O O I Input a high- or low-level signal or leave open. Input a high-level signal. Input a low-level signal. Serial data output pin Serial data input pin MCU Data output TXD VCC/AVCC Data input RXD MODE User reset signal RESET VSS/AVSS XIN XOUT Connect an oscillator (2) Notes: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the MODE input with a switch. 2. When operating with the on-chip oscillator clock, it is not necessary to connect an oscillation circuit. Refer to Appendix 2 Connection Examples with M16C Flash Starter. Figure 35.16 Pin Handling in Standard Serial I/O Mode 2 REJ09B0441-0010 Rev.0.10 Page 751 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Table 35.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) Pin VCC, VSS RESET P12_0/XIN P12_1/XOUT XCIN XCOUT P0 to P7 P10 to P13 VREF MODE Name Power supply input Reset input I/O I Description Apply the guaranteed programming and erasure voltage to the VCC pin and 0 V to the VSS pin. Reset input pin P12_0 input/clock input I If an external oscillator is connected, connect a P12_1 input/clock I/O ceramic resonator or crystal oscillator between pins XIN and XOUT. output Clock input I If an external oscillator is connected, connect a Clock output I/O crystal oscillator between pins XCIN and XCOUT. Input ports P0 to P7 I Input a high- or low-level signal or leave open. Input ports P10 to P13 I Input a high- or low-level signal or leave open. Reference voltage I Input a high-level signal. MODE I/O Serial data I/O pin. Connect the pin to a programmer. MCU MODE I/O MODE VCC/AVCC Reset input RESET User reset signal VSS/AVSS Notes: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with the on-chip oscillator clock, it is not necessary to connect an oscillation circuit. Figure 35.17 Pin Handling in Standard Serial I/O Mode 3 REJ09B0441-0010 Rev.0.10 Page 752 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.6 Parallel I/O Mode Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. Use a parallel programmer which supports the MCU. Contact the parallel programmer manufacturer for more information. Refer to the user’s manual included with your parallel programmer for instructions. In parallel I/O mode, the user ROM areas shown in Figure 35.1 can be rewritten. 35.6.1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read and rewritten. (Refer to the 35.3.2 ROM Code Protect Function.) REJ09B0441-0010 Rev.0.10 Page 753 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.7 35.7.1 Notes on Flash Memory CPU Rewrite Mode Prohibited Instructions 35.7.1.1 The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK. 35.7.1.2 Table 35.9 Mode EW0 Erase/ Write Target Data flash Non-Maskable Interrupts CPU Rewrite Mode Interrupts (1) Status During auto-erasure (suspend enabled) Maskable Interrupt • Address Match • Address Break (Note 1) Tables 35.9 and 35.10 list CPU Rewrite Mode Interrupts (1) and (2), respectively. EW1 During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming Program During auto-erasure ROM (suspend enabled) During auto-erasure (suspend disabled) During auto-programming Data During auto-erasure flash (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0 (erase restart). Interrupt handling is executed while auto-erasure or auto-programming is being performed. Usable by allocating a vector in RAM. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming Program During auto-erasure ROM (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0. Interrupt handling is executed while auto-erasure or auto-programming is being performed. Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Autoerasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes. While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. During auto-erasure Auto-erasure and auto-programming have priority and interrupt requests are put on (suspend disabled standby. Interrupt handling is executed after auto-erase and auto-program complete. or FMR22 = 0) During auto-programming FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. REJ09B0441-0010 Rev.0.10 Page 754 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory Table 35.10 Erase/ Write Target CPU Rewrite Mode Interrupts (2) • Watchdog Timer • Undefined Instruction • Oscillation Stop Detection • INTO Instruction • Voltage Monitor 2 • BRK Instruction • Voltage Monitor 1 • Single Step (Note 1) • NMI (Note 1) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0 (erase restart). Interrupt handling is executed while auto-erasure or auto-programming is being performed. Mode Status EW0 Data flash During auto-erasure (suspend enabled) Program ROM During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming During auto-erasure (suspend enabled) During auto-erasure (suspend disabled) During auto-programming EW1 Data flash During auto-erasure (suspend enabled) Program ROM During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming During auto-erasure (suspend enabled) When an interrupt request is acknowledged, Not usable during auto-erasure or auto-erasure or auto-programming is forcibly auto-programming. stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-programming after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0. Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming When an interrupt request is acknowledged, Not usable during auto-erasure or auto-erasure or auto-programming is forcibly auto-programming. stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. REJ09B0441-0010 Rev.0.10 Page 755 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 35. Flash Memory 35.7.1.3 How to Access To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. • The FMR01 or FMR02 bit in the FMR0 register • The FMR13 bit in the FMR1 register • The FMR20, FMR22, or FMR 27 bit in the FMR2 register To set one of the following bits to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and writing 0. • The FMR14, FMR15, FMR16, or FMR17 bit in the FMR1 register 35.7.1.4 Rewriting User ROM Area In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode. 35.7.1.5 Programming Do not write additions to the already programmed address. 35.7.1.6 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend. When the FST7 in the FST register is set to 0 (busy (during programming or erasure execution), do not enter to stop mode or wait mode. 35.7.1.7 Programming and Erasure Voltage for Flash Memory To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. REJ09B0441-0010 Rev.0.10 Page 756 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 36. Electrical Characteristics 36. Electrical Characteristics TBD REJ09B0441-0010 Rev.0.10 Page 757 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37. Usage Notes 37.1 37.1.1 Notes on Clock Generation Circuit Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used when the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b. 37.1.2 Oscillation Circuit Constants Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system. To use the MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled) and connect the feedback resistor to the chip externally. REJ09B0441-0010 Rev.0.10 Page 758 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.2 37.2.1 Notes on Power Control Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least four NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. • Program example to enter stop mode BCLR 1, FMR0; CPU rewrite mode disabled BSET 0, PRCR; Protect disabled FSET I; Enable interrupt BSET 0, CM1; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP 37.2.2 Wait Mode To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least four NOP instructions after the WAIT instruction. • Program example to execute the WAIT instruction BCLR 1, FMR0; CPU rewrite mode disabled FSET I; Enable interrupt WAIT; Wait mode NOP NOP NOP NOP 37.2.3 Power-Off Mode To enter power-off mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then access the POMCR0 register. A period of a few microseconds is required between accessing the POMCR0 register and entering power-off mode. As the CPU continues to operate during this period, insert the NOP and the WAIT instructions to stop the program. • Program example to enter power-off mode (when timer RE and the low-speed clock is enabled) BCLR 1, FMR0; CPU rewrite mode disabled MOV. B #08H, POMCR0; Select power-off 0 and WKUP1 input enabled MOV. B #88H, POMCR0; Fixed value MOV. B #15H, POMCR0; Fixed value MOV. B #92H, POMCR0; Fixed value MOV. B #25H, POMCR0; Fixed value NOP; NOP; NOP; NOP; Enter power-off mode WAIT; Wait mode REJ09B0441-0010 Rev.0.10 Page 759 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.3 37.3.1 Notes on Interrupts Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the IR bit for the acknowledged interrupt is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated. 37.3.2 SP Setting Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is acknowledged before setting a value in the SP, the program may run out of control. 37.3.3 External Interrupt, Key Input Interrupt Either the low-level width or high-level width shown in the Electrical Characteristics is required for the signal input to pins INT0 to INT7 and pins KI0 to KI7, regardless of the CPU clock. For details, refer to Table 36.XX (VCC = 5 V), Table 36.XX (VCC = 3 V), Table 36.XX (VCC = 1.8 V) External Interrupt INTi (i = 0 to 7) Input, Key Input Interrupt KIi (i = 0 to 7). REJ09B0441-0010 Rev.0.10 Page 760 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.3.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources. Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of the interrupt assigned to a software interrupt number. Therefore, if a mode change of a peripheral function involves the source, polarity, or timing of an interrupt, set the IR bit to 0 (no interrupt requested) after making these changes. Refer to the descriptions of the individual peripheral functions for related interrupts. Figure 37.1 shows a Procedure Example for Changing Interrupt Sources. Interrupt source change Disable interrupts (2, 3) Change interrupt sources (including the mode of peripheral functions) Set the IR bit to 0 (no interrupt request) using the MOV instruction (3) Enable interrupts (2, 3) Change completed IR bit: Bit in the interrupt control register bit for the interrupt whose source is to be changed Notes: 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt whose source is to be changed. 3. Refer to 12.8.5 Rewriting Interrupt Control Register for the instructions to use and related notes. Figure 37.1 Procedure Example for Changing Interrupt Sources REJ09B0441-0010 Rev.0.10 Page 761 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.3.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that register are generated. If an interrupt request may be generated, disable the interrupt before rewriting the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling the interrupt, be careful to choose appropriate instructions. Changing any bit other than the IR bit If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET. Changing the IR bit Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested). Use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to (b) regarding rewriting the contents of interrupt control registers using the sample programs. Examples 1 to 3 shows how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer. Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use the POPC instruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h POPC FLG ; Enable interrupts REJ09B0441-0010 Rev.0.10 Page 762 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.4 37.4.1 Notes on ID Code Areas Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.) 37.5 37.5.1 Notes on Option Function Select Area Setting Example of Option Function Select Area As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.) REJ09B0441-0010 Rev.0.10 Page 763 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.6 37.6.1 Notes on DTC DTC activation source • Do not generate any DTC activation sources before entering wait mode or during wait mode. • Do not generate any DTC activation sources before entering stop mode or during stop mode. 37.6.2 DTCENi (i = 0 to 6) Registers • Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated. • When the interrupt source flag in the status register for the peripheral function is 1, do not modify the corresponding activation source bit among bits DTCENi0 to DTCENi7. • Do not access the DTCENi register using a DTC transfer. 37.6.3 Peripheral Modules • Do not set the status register bit for the peripheral function to 0 using a DTC transfer. • When the DTC activation source is SSU/I2C bus receive data full, read the SSRDR register/the ICDRR register using a DTC transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by reading the SSRDR register/the ICDRR register. However, the RDRF bit is not set to 0 by reading the SSRDR register/the ICDRR register when the DTC data transfer setting is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCRj register value to change from 1 to 0 while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode. • When the DTC activation source is SSU/I2C bus transmit data empty, write to the SSTDR register/the ICDRT register using a DTC transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT register. REJ09B0441-0010 Rev.0.10 Page 764 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.7 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count • • starts. Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time in the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READMODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. The TCSTF bit remains 0 (count stops) for zero or one cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first active edge of the count source after The TCSTF bit is set to 1 (during count operation). The TCSTF bit remains 1 for zero or one cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Note: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA • • • • • When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. • When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. REJ09B0441-0010 Rev.0.10 Page 765 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.8 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time in the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR register to 1 (oneshot stops), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. • The TCSTF bit remains 0 (count stops) for one or two cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts counting at the first active edge of the count source after the TCSTF bit is set to 1 (during count operation). The TCSTF bit remains 1 for one or two cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Note: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR • When the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. • When 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. When 1 is written to the TOSSP bit during the period between when 1 is written to the TOSST bit and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, when 1 is written to the TOSST bit during the period between when 1 is written to the TOSSP bit and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1. 37.8.1 Timer Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. 37.8.2 Programmable Waveform Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. REJ09B0441-0010 Rev.0.10 Page 766 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.8.3 Programmable One-Shot Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously during count operation, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously during count operation, allow three or more cycles of the prescaler underflow for each write interval. 37.8.4 Programmable Wait One-shot Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. REJ09B0441-0010 Rev.0.10 Page 767 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.9 37.9.1 Notes on Timer RC TRC Register • The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (TRC register cleared by compare match with TRCGRA register). When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h. • Reading from the TRC register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV.W TRC,DATA ;Read 37.9.2 TRCSR Register Reading from the TRCSR register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV.B TRCSR,DATA ;Read 37.9.3 TRCCR1 Register To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency higher than the CPU clock frequency. 37.9.4 Count Source Switching • Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. • After switching the count source from fOCO40M to another clock, allow two or more cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for two or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off). 37.9.5 Input Capture Function • The pulse width of the input capture signal should be set to three cycles or more of the timer RC operation clock (refer to Table 20.1 Timer RC Operating Clocks). • The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used). 37.9.6 TRCMR Register in PWM2 Mode When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA. REJ09B0441-0010 Rev.0.10 Page 768 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.10 Notes on Timer RD 37.10.1 TRDSTR Register • Set the TRDSTR register using the MOV instruction. • When the CSELi (i = 0 or 1) is set to 0 (count stops at compare match between registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit. When the CSELi bit is set to 0, write 0 to the TSTARTi bit to change other bits without changing the TSTARTi bit. To stop counting by a program, write 0 to the TSTARTi bit after setting the CSELi bit to 1. If 1 is written to the CSELi bit and 0 is written to the TSTARTi bit is set to 0 at the same time (with one instruction), the count cannot be stopped. • Table 37.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops while the TRDIOji (j = A, B, C, or D) pin is used for the timer RD output. Table 37.1 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops TRDIOji Pin Output when Count Stops Holds the output level immediately before the count stops. Holds the output level after the output changes by the compare match. Stopping Count When the CSELi bit is set to 1, write 0 to the TSTARTi bit and the count stops. When the CSELi bit is set to 0, the count stops at compare match between registers TRDi and TRDGRAi. 37.10.2 TRDi Register (i = 0 or 1) • When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These notes apply when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register. - 001b (Clear by the TRDi register at compare match with the TRDGRAi register.) - 010b (Clear by the TRDi register at compare match with the TRDGRBi register.) - 011b (Synchronous clear) - 101b (Clear by the TRDi register at compare match with the TRDGRCi register.) - 110b (Clear by the TRDi register at compare match with the TRDGRDi register.) • When writing the value to the TRDi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.W #XXXXh, TRD0 ;Write JMP.B L1 ;JMP.B L1: MOV.W TRD0,DATA ;Read REJ09B0441-0010 Rev.0.10 Page 769 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.10.3 TRDSRi Register (i = 0 or 1) When writing the value to the TRDSRi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.B #XXh, TRDSR0 ;Write JMP.B L1 ;JMP.B L1: MOV.B TRDSR0,DATA ;Read 37.10.4 Count Source Switching • Switch the count source after the count stops. Switching procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. • When changing the count source from fOCO40M to another source and stopping fOCO40M, wait two or more cycles of f1 after setting the clock switch, and then stop fOCO40M. Switching procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. (3) Wait for two or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off). 37.10.5 Input Capture Function • The pulse width of the input capture signal should be set to three or more cycles of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks). • The value of the TRDi register is transferred to the TRDGRji register two or three cycles of the timer RD operating clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or D) (when the digital filter is not used). 37.10.6 Reset Synchronous PWM Mode • When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1. • Set to reset synchronous PWM mode by the following procedure: Switching procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode). (4) Set the other registers associated with timer RD again. REJ09B0441-0010 Rev.0.10 Page 770 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.10.7 Complementary PWM Mode • When complementary PWM mode is used for motor control, make sure OLS0 = OLS1. • Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure. Switching procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other timer RD again. Switching procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode). • Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation. When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed. • If the value set in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decrement operation. When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0 and TRDGRA0), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers such as the TRDGRA0 register. TRD0 register count value m+1 TRDGRA0 register setting value m Set to 0 by a program. IMFA bit in TRDSR0 register 1 0 Transfer from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register No transfer from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 11b (transfer from the buffer register to the general register at compare match between registers TRD0 and TRDGRA0). No change Figure 37.2 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 771 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes • The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment operation. The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in the TRD1 register), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains unchanged. TRD0 register count value 1 0 FFFFh Set to 0 by a program. UDF bit in TRDSR0 register OVF bit in TRDSR0 register 1 0 1 0 Transfer from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register No transfer from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 10b (transfer from the buffer register to the general register when the TRD1 register underflows). No change Figure 37.3 Operation when TRD1 Register Underflows in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 772 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes • Using bits CMD1 to CMD0, select the timing of data transfer from the buffer register to the general register. However, transfer takes place with the following timing in spite of the values of bits CMD1 to CMD0 in the following cases: Buffer register value ≥ TRDGRA0 register value: Transfer takes place at underflow of the TRD1 register. After this, when the buffer register is set to 0001h or above and a value smaller than the value of the TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0. n3 m+1 TRD0 register count value n2 n1 0000h TRD1 register count value TRDGRD0 register n2 Transfer n3 Transfer n2 n3 n2 Transfer n2 n1 Transfer n1 TRDGRB0 register n1 Transfer with timing set by bits CMD1 to CMD0 Transfer at TRD1 register underflow because of n3 > m Transfer at TRD1 register underflow because of first setting to n2 < m Transfer with timing set by bits CMD1 to CMD0 TRDIOB0 output TRDIOD0 output m: Value set in TRDGRA0 register The above applies under the following conditions: • Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match between registers TRD0 and TRDGRA0 in complementary PWM mode). • Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase). Figure 37.4 Operation when Buffer Register Value ≥ TRDGRA0 Register Value in Complementary PWM Mode REJ09B0441-0010 Rev.0.10 Page 773 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes When the value of the buffer register is set to 0000h: Transfer takes place at compare match between registers TRD0 and TRDGRA0. After this, when the buffer register is set to 0001h or above and a value than smaller the value of the TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD0 and CMD1. m+1 n2 n1 0000h TRD1 register count value TRD0 register count value TRDGRD0 register n1 Transfer 0000h Transfer n1 0000h n1 Transfer n1 Transfer TRDGRB0 register n2 Transfer with timing set by bits CMD1 to CMD0 Transfer at compare match between registers TRD0 and TRDGRA0 because content of TRDGRD0 register is set to 0000h. Transfer at compare match between registers TRD0 and TRDGRA0 because of first setting to 0001h ≤ n1 < m Transfer with timing set by bits CMD1 to CMD0 TRDIOB0 output TRDIOD0 output m: Value set in TRDGRA0 register The above applies under the following conditions: • Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at TRD1 register underflow in PWM mode). • Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase). Figure 37.5 Operation when Buffer Register Value Is Set to 0000h in Complementary PWM Mode 37.10.8 Count Source fOCO40M • The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V. For supply voltage other than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (fOCO40M selected as the count source). REJ09B0441-0010 Rev.0.10 Page 774 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.11 Notes on Timer RE 37.11.1 Reset A reset input does not reset the timer RE data registers that store data of seconds, minutes, hours, and days of the week. This requires the initial setting of all registers after power on. 37.11.2 Starting and Stopping Count Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. When the TSTART bit is set to 1 (count starts), timer RE starts counting and the TCSTF bit is set to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit. Similarly, when the TSTART bit is set to 0 (count stops), timer RE stops counting and the TCSTF bit is set to 0 (count stops). It takes the time for up to two cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. Note: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR 37.11.3 Register Setting Write to the following registers or bits while timer RE is stopped. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 • Bits H12_H24, PM, and INT in the TRECR1 register • Bits RCS0 to RCS3 in the TRECSR register Timer RE is stopped while bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 37.6 shows a Setting Example in Real-Time Clock Mode. REJ09B0441-0010 Rev.0.10 Page 775 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes TSTART in TRECR1 = 0 Stop timer RE operation TCSTF in TRECR1 = 0? TOENA in TRECR1 = 0 TREIC ← 00h (timer RE interrupt disabled) Disable the timer RE clock output (when necessary) TRERST in TRECR1 = 1 Reset the timer RE registers and the control circuit TRERST in TRECR1 = 0 Set registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in the TRECR1 register Select the clock output Select the clock source Seconds, minutes, hours, days of week, operating mode Set the a.m./p.m., interrupt timing Set TRECR2 Set TREIC (IR bit ← 0, select the interrupt priority level) Select the interrupt source TOENA in TRECR1 = 1 TSTART in TRECR1 = 1 Enable the timer RE clock output (when necessary) Start timer RE operation TCSTF in TRECR1 = 1? Figure 37.6 Setting Example in Real-Time Clock Mode REJ09B0441-0010 Rev.0.10 Page 776 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.11.4 Time Reading Procedure in Real-Time Clock Mode In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (data is not being updated). When reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below. • Using an interrupt Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine. • Monitoring with a program 1 Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated). • Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0. • Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible. REJ09B0441-0010 Rev.0.10 Page 777 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.12 Notes on Timer RG 37.12.1 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode The phase difference and overlap between the external input signals from pins TRGCLKA and TRGCLKB should be 1.5 f1 or more, respectively. The pulse width should be 2.5 f1 or more. Figure 37.7 shows the Phase Difference, Overlap, and Pulse Width in Phase Counting Mode. Phase difference Phase difference Pulse width Pulse width TRGCLKA input TRGCLKB input Phase difference and overlap: 1.5 f1 or more Pulse width: 2.5 f1 or more Overlap Overlap Figure 37.7 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 37.13 Notes on Serial Interface (UARTi (i = 0 or 1)) • When reading data from the UiRB (i = 0 or 1) register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Program example to read the receive buffer register: MOV.W 00A6H,R0 ; Read the U0RB register • When writing data to the UiTB register in clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first and then the low-order byte, in 8-bit units. Program example to write to the transmit buffer register: MOV.B #XXH,00A3H ; Write to the high-order byte of the U0TB register MOV.B #XXH,00A2H ; Write to the low-order byte of the U0TB register REJ09B0441-0010 Rev.0.10 Page 778 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.14 Notes on Serial Interface (UART2) 37.14.1 Clock Synchronous Serial I/O Mode 37.14.1.1 Transmission/Reception When the RTS function is used with an external clock, the RTS2 pin outputs a low-level signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high-level signal when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 37.14.1.2 Transmission If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock). • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). • If the CTS function is selected, input to the CTS2 pin is low. 37.14.1.3 Reception In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2associated registers for transmission even if the MCU is used for reception only. Dummy data is output from the TXD2 pin during reception. When an internal clock is selected, the shift clock is generated by setting the TE bit in the U2C1 register to 1 (transmission enabled) and setting dummy data in the U2TB register. When an external clock is selected, the shift clock is generated by setting the TE bit to 1 (transmission enabled), setting dummy data in the U2TB register, and inputting an external clock. If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an overrun error occurs, the IR bit in the S2RIC register remains unchanged. To receive data consecutively, set dummy data in the low-order byte in the U2TB register per each receive operation. If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1. • The RE bit in the U2C1 register is set to 1 (reception enabled). • The TE bit in the U2C1 register is set to 1 (transmission enabled). • The TI bit in the U2C1 register is set to 0 (data in the U2TB register). REJ09B0441-0010 Rev.0.10 Page 779 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.14.2 Clock Asynchronous Serial I/O (UART) Mode 37.14.2.1 Transmission/Reception When the RTS function is used with an external clock, the RTS2 pin outputs a low-level signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high-level signal when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 37.14.2.2 Transmission If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock). • The TE bit in the U2C1 register is set to 1 (transmission enabled) • The TI bit in the U2C1 register is set to 0 (data in the U2TB register) • If the CTS function is selected, input on the CTS2 pin is low. 37.14.3 Special Mode 1 (I2C Mode) To generate start, stop, and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before changing each condition generation bit (STAREQ, RSTAREQ, and STPREQ) from 0 to 1. REJ09B0441-0010 Rev.0.10 Page 780 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.15 Notes on Synchronous Serial Communication Unit To use the synchronous serial communication unit, set the IICSEL bit in the SSUIICSR register to 0 (SSU function selected). 37.16 Notes on I2C bus Interface To use the I2C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I2C bus interface function selected). 37.17 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point. 37.18 Notes on A/D Converter • Write to the ADMOD, ADINSEL, ADCON0 (other than the ADST bit), ADCON1, or OCVREFCR register must • be performed while A/D conversion is stopped (before a trigger occurs). To use the A/D converter in repeat mode 0, repeat mode 1, or repeat sweep mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select fOCO-F as φAD. Connect 0.1 µF capacitor between pins VREF and AVSS. Do not enter stop mode during A/D conversion. Do not enter wait mode during A/D conversion regardless of the state of the CM02 bit in the CM0 register (1: Peripheral function clock stops in wait mode or 0: Peripheral function clock does not stop in wait mode). Do not set the FMSTP bit in the FMR0 register to 1 (flash memory stops) during A/D conversion. • • • • REJ09B0441-0010 Rev.0.10 Page 781 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.19 Notes on LCD Drive Control Circuit 37.19.1 Voltage Multiplier The voltage multiplier boosts the VL1 pin voltage by charging/discharging the capacitor connected between pins CL1 and CL2. As a result, the expected level from the VL4 pin may not achieved when driving a large LCD panel. An external power source is recommended to obtain a stable power supply in these cases. 37.19.2 When Division Resistors are Connected Externally Set the resistor value between pins VL4 and VCC (the total of R1 to R4 as shown in Figure 34.4) to the highest value 100 kΩ or more. REJ09B0441-0010 Rev.0.10 Page 782 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.20 Notes on Flash Memory 37.20.1 CPU Rewrite Mode 37.20.1.1 Prohibited Instructions The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK. 37.20.1.2 Non-Maskable Interrupts Tables 37.2 and 37.3 list CPU Rewrite Mode Interrupts (1) and (2), respectively. Table 37.2 Mode EW0 Erase/ Write Target Data flash CPU Rewrite Mode Interrupts (1) Status During auto-erasure (suspend enabled) Maskable Interrupt • Address Match • Address Break (Note 1) EW1 During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming Program During auto-erasure ROM (suspend enabled) During auto-erasure (suspend disabled) During auto-programming Data During auto-erasure flash (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0 (erase restart). Interrupt handling is executed while auto-erasure or auto-programming is being performed. Usable by allocating a vector in RAM. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming Program During auto-erasure ROM (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0. Interrupt handling is executed while auto-erasure or auto-programming is being performed. Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Autoerasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes. While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. During auto-erasure Auto-erasure and auto-programming have priority and interrupt requests are put on (suspend disabled standby. Interrupt handling is executed after auto-erase and auto-program complete. or FMR22 = 0) During auto-programming FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. REJ09B0441-0010 Rev.0.10 Page 783 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes Table 37.3 Erase/ Write Target CPU Rewrite Mode Interrupts (2) • Watchdog Timer • Undefined Instruction • Oscillation Stop Detection • INTO Instruction • Voltage Monitor 2 • BRK Instruction • Voltage Monitor 1 • Single Step (Note 1) • NMI (Note 1) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0 (erase restart). Interrupt handling is executed while auto-erasure or auto-programming is being performed. Mode Status EW0 Data flash During auto-erasure (suspend enabled) Program ROM During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming During auto-erasure (suspend enabled) During auto-erasure (suspend disabled) During auto-programming EW1 Data flash During auto-erasure (suspend enabled) Program ROM During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming During auto-erasure (suspend enabled) When an interrupt request is acknowledged, Not usable during auto-erasure or auto-erasure or auto-programming is forcibly auto-programming. stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-programming after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0. Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming When an interrupt request is acknowledged, Not usable during auto-erasure or auto-erasure or auto-programming is forcibly auto-programming. stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. REJ09B0441-0010 Rev.0.10 Page 784 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.20.1.3 How to Access To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. • The FMR01 or FMR02 bit in the FMR0 register • The FMR13 bit in the FMR1 register • The FMR20, FMR22, or FMR 27 bit in the FMR2 register To set one of the following bits to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and writing 0. • The FMR14, FMR15, FMR16, or FMR17 bit in the FMR1 register 37.20.1.4 Rewriting User ROM Area In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode. 37.20.1.5 Programming Do not write additions to the already programmed address. 37.20.1.6 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend. When the FST7 in the FST register is set to 0 (busy (during programming or erasure execution), do not enter to stop mode or wait mode. 37.20.1.7 Programming and Erasure Voltage for Flash Memory To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. REJ09B0441-0010 Rev.0.10 Page 785 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 37. Usage Notes 37.21 Notes on Noise 37.21.1 Inserting Bypass Capacitor between Pins VCC and VSS as Countermeasure against Noise and Latch-up Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible. 37.21.2 Countermeasures against Noise Error of Port Control Registers During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the MCU internal noise control circuitry. In such cases the contents of the port related registers may be changed. As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up control registers be reset periodically. However, examine the control processing fully before introducing the reset routine as conflicts may be created between the reset routine and interrupt routines. REJ09B0441-0010 Rev.0.10 Page 786 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 38. Notes on On-Chip Debugger 38. Notes on On-Chip Debugger When using the on-chip debugger to develop and debug programs for the R8C/L35A Group, R8C/L35B Group, R8C/ L36A Group, R8C/L36B Group, R8C/L38A Group, R8C/L38B Group, R8C/L3AA Group, R8C/L3AB Group, take note of the following: (1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be accessed by the user. Refer to the on-chip debugger manual for which areas are used. (2) Do not set the address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1 and fixed vector tables) in a user system. (3) Do not use the BRK instruction in a user system. (4) Debugging is available under the condition of supply voltage VCC = 1.8 to 5.5 V. Set the supply voltage to 2.7 V or above for rewriting the flash memory. Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for details. REJ09B0441-0010 Rev.0.10 Page 787 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology web site. JEITA Package Code P-LQFP52-10x10-0.65 RENESAS Code PLQP0052JA-A Previous Code 52P6A-A MASS[Typ.] 0.3g HD *1 39 D 27 40 26 bp b1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 HE E c1 c Reference Symbol Dimension in Millimeters 14 1 ZD Index mark 13 ZE 52 Terminal cross section A2 A c F e y L *3 bp x Detail F L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom 10.0 10.0 1.4 11.8 12.0 11.8 12.0 0.05 0.27 0.09 0° Min 9.9 9.9 Max 10.1 10.1 0.35 12.2 12.2 1.7 0.1 0.15 0.32 0.37 0.30 0.145 0.20 0.125 8° 0.65 0.13 0.10 1.1 1.1 0.5 0.65 1.0 REJ09B0441-0010 Rev.0.10 Page 788 of 809 Jul 30, 2008 A1 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 49 32 HE E Reference Symbol *2 c1 Dimension in Millimeters c 64 1 Index mark ZD 16 ZE 17 Terminal cross section F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 e *3 A1 y bp x L L1 Detail F Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 A2 JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 48 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 49 32 bp b1 A c c1 HE E c Reference Symbol *2 Dimension in Millimeters Terminal cross section 64 17 1 ZD Index mark 16 F L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 bp x Detail F Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0° 8° 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 ZE A A2 REJ09B0441-0010 Rev.0.10 Page 789 of 809 Jul 30, 2008 A1 c Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 61 40 bp b1 c1 *2 HE E c Reference Symbol Dimension in Millimeters Terminal cross section 80 21 1 ZD Index mark 20 F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e bp A1 *3 x L L1 Detail F Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 10° 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 ZE A2 A JEITA Package Code P-LQFP80-14x14-0.65 RENESAS Code PLQP0080JA-A Previous Code FP-80W / FP-80WV MASS[Typ.] 0.6g HD *1 D 41 60 61 40 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 c c1 Reference Symbol c Dimension in Millimeters 80 21 1 ZD Index mark 20 ZE Terminal cross section A2 A F A1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 L y e *3 L1 bp Detail F x Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.27 0.32 0.37 0.30 0.09 0.145 0.20 0.125 8° 0° 0.65 0.13 0.10 0.825 0.825 0.35 0.5 0.65 1.0 REJ09B0441-0010 Rev.0.10 Page 790 of 809 Jul 30, 2008 c Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 76 50 bp b1 HE E Reference Symbol *2 Dimension in Millimeters c1 c Terminal cross section 1 Index mark ZD 25 F ZE 100 26 A2 A D E A2 HD HE A A1 bp b1 c c1 c A1 y e *3 bp L L1 Detail F x e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JD-B Previous Code 100P6F-A MASS[Typ.] 1.8g Under development HD *1 80 D 51 81 50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 HE E Reference Dimension in Millimeters Symbol ZE 100 31 1 ZD Index mark 30 F c A2 L e y *3 bp x Detail F D E A2 HD HE A A1 bp c e x y ZD ZE L Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0° 10° 0.65 0.13 0.10 0.575 0.825 0.4 0.6 0.8 A REJ09B0441-0010 Rev.0.10 Page 791 of 809 Jul 30, 2008 A1 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 2. Connection Examples with M16C Flash Starter Appendix 2. Connection Examples with M16C Flash Starter Appendix Figures 2.1 to 2.5 show connection examples with the M16C Flash Starter (M3A-0806). 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 R8C/L35A Group R8C/L35B Group MODE 5 6 7 RESET VSS VCC 8 Connect an oscillation circuit (1) 9 10 11 12 13 TXD 10 TXD 7 VSS RXD 4 1 VCC M16C Flash Starter (M3A-0806) RXD Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 2.1 Connection Example with M16C Flash Starter (1) REJ09B0441-0010 Rev.0.10 Page 792 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 2. Connection Examples with M16C Flash Starter 53 52 51 50 49 64 1 2 63 62 61 60 59 58 57 56 55 54 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MODE 3 4 5 R8C/L36A Group R8C/L36B Group RESET VSS VCC Connect an oscillation circuit (1) 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TXD 10 TXD 7 VSS RXD 4 1 VCC M16C Flash Starter (M3A-0806) RXD Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 2.2 Connection Example with M16C Flash Starter (2) REJ09B0441-0010 Rev.0.10 Page 793 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 2. Connection Examples with M16C Flash Starter 65 64 63 62 61 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 R8C/L38A Group R8C/L38B Group 5 MODE 6 7 8 RESET VSS VCC Connect an oscillation circuit (1) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TXD 10 TXD 7 VSS RXD 4 1 VCC M16C Flash Starter (M3A-0806) RXD Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 2.3 Connection Example with M16C Flash Starter (3) REJ09B0441-0010 Rev.0.10 Page 794 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 2. Connection Examples with M16C Flash Starter 100 1 2 3 4 5 6 80 79 78 77 76 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MODE 7 R8C/L3AA Group R8C/L3AB Group 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RESET VSS VCC Connect an oscillation circuit (1) TXD 10 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 26 27 28 29 30 TXD 7 VSS RXD 4 1 VCC M16C Flash Starter (M3A-0806) RXD Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 2.4 Connection Example with M16C Flash Starter (4) REJ09B0441-0010 Rev.0.10 Page 795 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 2. Connection Examples with M16C Flash Starter 100 1 2 3 4 5 6 7 8 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R8C/L3AA Group R8C/L3AB Group MODE 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 RESET VSS VCC Connect an oscillation circuit (1) TXD 10 TXD 7 VSS RXD 4 1 VCC 31 49 37 44 45 46 47 48 50 32 33 34 35 36 38 39 40 41 42 43 M16C Flash Starter (M3A-0806) RXD Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 2.5 Connection Example with M16C Flash Starter (5) REJ09B0441-0010 Rev.0.10 Page 796 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 3. Connection Examples with E8a Emulator Appendix 3. Connection Examples with E8a Emulator Appendix Figures 3.1 to 3.5 show connection examples with the E8a Emulator (R0E00008AKCE00). (2) 52 51 50 49 48 47 46 45 44 43 42 41 40 VCC Open collector buffer 4.7 kΩ or more User logic 1 2 3 4 5 6 7 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 R8C/L35A Group R8C/L35B Group Connect an oscillation circuit (1) 8 9 10 11 12 14 12 10 8 VCC 6 4 2 VSS 13 RESET 4.7 kΩ ± 10% MODE VSS 13 7 MODE VCC E8a emulator (R0E00008AKCE00) Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 3.1 Connection Example with E8a Emulator (1) REJ09B0441-0010 Rev.0.10 Page 797 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 3. Connection Examples with E8a Emulator (2) 53 52 51 50 49 64 63 62 61 60 59 58 57 56 55 54 VCC Open collector buffer 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 4.7 kΩ or more User logic 2 3 4 5 R8C/L36A Group R8C/L36B Group Connect an oscillation circuit (1) 6 7 14 12 10 8 VCC 6 4 2 VSS 13 RESET 4.7 kΩ ± 10% MODE VSS 8 9 10 11 12 13 14 15 16 7 MODE VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 E8a emulator (R0E00008AKCE00) Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 3.2 Connection Example with E8a Emulator (2) REJ09B0441-0010 Rev.0.10 Page 798 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 3. Connection Examples with E8a Emulator 65 64 63 62 61 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 (2) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 VCC Open collector buffer 4.7 kΩ or more User logic 2 3 4 5 R8C/L38A Group R8C/L38B Group 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connect an oscillation circuit (1) VSS 14 12 10 8 VCC 6 4 2 VSS 7 MODE 13 RESET 4.7 kΩ ±10% MODE VCC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 E8a emulator (R0E00008AKCE00) Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. Appendix Figure 3.3 Connection Example with E8a Emulator (3) REJ09B0441-0010 Rev.0.10 Page 799 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 3. Connection Examples with E8a Emulator 100 80 79 78 77 76 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (2) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 VCC Open collector buffer 4.7 kΩ or more User logic 3 4 5 6 7 R8C/L3AA Group R8C/L3AB Group 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Connect an oscillation circuit (1) VSS 14 12 VCC 10 8 6 4 2 VSS 7 MODE 13 RESET 4.7 kΩ ± 10% MODE VCC E8a emulator (R0E00008AKCE00) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. 26 27 28 29 30 Appendix Figure 3.4 Connection Example with E8a Emulator (4) REJ09B0441-0010 Rev.0.10 Page 800 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 3. Connection Examples with E8a Emulator 100 1 2 3 4 (2) 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC Open collector buffer 4.7 kΩ or more User logic 5 6 7 8 R8C/L3AA Group R8C/L3AB Group 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Connect an oscillation circuit (1) VSS 14 12 10 8 VCC 6 4 2 VSS 7 MODE 13 4.7 kΩ ± 10% MODE RESET VCC E8a emulator (R0E00008AKCE00) Notes: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. 2. Input the reference potential to the VREF pin as shown in 36. Electrical Characteristics: A/D Converter Characteristics or connect the pin to VCC. 31 49 37 44 45 46 47 48 50 32 33 34 35 36 38 39 40 41 42 43 Appendix Figure 3.5 Connection Example with E8a Emulator (5) REJ09B0441-0010 Rev.0.10 Page 801 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 4. Examples of Oscillation Evaluation Circuit Appendix 4. Examples of Oscillation Evaluation Circuit Appendix Figures 4.1 to 4.5 show examples of the oscillation evaluation circuit. 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 R8C/L35A Group R8C/L35B Group Connect an oscillation circuit 7 RESET Connect an oscillation circuit 8 9 VSS 10 11 12 13 VCC Note: 1. After a reset, the XIN clock is stopped. Write a program to oscillate the XIN clock. Appendix Figure 4.1 Example of Oscillation Evaluation Circuit (1) REJ09B0441-0010 Rev.0.10 Page 802 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 4. Examples of Oscillation Evaluation Circuit 53 52 51 50 49 64 1 2 3 4 63 62 61 60 59 58 57 56 55 54 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R8C/L36A Group R8C/L36B Group Connect an oscillation circuit 5 RESET Connect an oscillation circuit 6 7 VSS 8 9 10 11 12 13 14 15 16 VCC Note: 1. After a reset, the XIN clock is stopped. Write a program to oscillate the XIN clock. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Appendix Figure 4.2 Example of Oscillation Evaluation Circuit (2) REJ09B0441-0010 Rev.0.10 Page 803 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 4. Examples of Oscillation Evaluation Circuit 65 64 63 62 61 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 R8C/L38A Group R8C/L38B Group 6 7 Connect an oscillation circuit 8 RESET Connect an oscillation circuit 9 10 11 12 13 14 15 16 17 18 19 20 VSS VCC Note: 1. After a reset, the XIN clock is stopped. Write a program to oscillate the XIN clock. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Appendix Figure 4.3 Example of Oscillation Evaluation Circuit (3) REJ09B0441-0010 Rev.0.10 Page 804 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 4. Examples of Oscillation Evaluation Circuit 100 1 2 3 4 5 6 7 8 80 79 78 77 76 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R8C/L3AA Group R8C/L3AB Group Connect an oscillation circuit 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RESET Connect an oscillation circuit VSS VCC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: 1. After a reset, the XIN clock is stopped. Write a program to oscillate the XIN clock. 26 27 28 29 30 Appendix Figure 4.4 Example of Oscillation Evaluation Circuit (4) REJ09B0441-0010 Rev.0.10 Page 805 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Appendix 4. Examples of Oscillation Evaluation Circuit 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R8C/L3AA Group R8C/L3AB Group Connect an oscillation circuit RESET Connect an oscillation circuit VSS VCC Note: 1. After a reset, the XIN clock is stopped. Write a program to oscillate the XIN clock. 31 37 49 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 50 Appendix Figure 4.5 Example of Oscillation Evaluation Circuit (5) REJ09B0441-0010 Rev.0.10 Page 806 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Index Index [A] ADCON0 ............................................................................. 648 ADCON1 ............................................................................. 648 ADi (i = 0 to 7) ..................................................................... 645 ADIC .................................................................................... 174 ADINSEL ............................................................................. 647 ADMOD ............................................................................... 646 AIERi (i = 0 or 1) .................................................................. 196 [C] CM0 ............................................................................. 129, 146 CM1 ............................................................................. 130, 147 CM3 ............................................................................. 131, 148 CMPA ............................................................................ 64, 671 CSPR .................................................................................. 213 [D] DACON ............................................................................... 668 DAi (i = 0 or 1) ..................................................................... 668 DTBLSj (j = 0 to 23) ............................................................. 221 DTCCRj (j = 0 to 23) ............................................................ 221 DTCCTj (j = 0 to 23) ............................................................ 222 DTCENi (i = 0 to 6) .............................................................. 223 DTCTL ................................................................................. 224 DTDARj (j = 0 to 23) ............................................................ 222 DTRLDj (j = 0 to 23) ............................................................ 222 DTSARj (j = 0 to 23) ............................................................ 222 [F] FMR0 .................................................................................. 728 FMR1 .................................................................................. 730 FMR2 .................................................................................. 732 FMRDYIC ............................................................................ 175 FRA0 ........................................................................... 133, 150 FRA1 ................................................................................... 133 FRA2 ................................................................................... 134 FRA3 ................................................................................... 135 FRA4 ................................................................................... 135 FRA5 ................................................................................... 135 FRA6 ................................................................................... 135 FRA7 ................................................................................... 132 FST ..................................................................................... 726 [I] ICCR1 ................................................................................. 599 ICCR2 ................................................................................. 600 ICDRR ................................................................................. 598 ICDRS ................................................................................. 604 ICDRT ................................................................................. 598 ICIER ................................................................................... 602 ICMR ................................................................................... 601 ICSR .................................................................................... 603 INTCMP .............................................................................. 686 INTEN ......................................................................... 186, 686 INTEN1 ............................................................................... 187 INTF ............................................................................ 188, 687 INTF1 .................................................................................. 188 INTiIC (i = 0 to 7) ................................................................. 176 INTSR ........................................................................... 99, 185 [K] KIEN .................................................................................... 193 KIEN1 .................................................................................. 194 KISR .............................................................................. 98, 192 KUPIC .................................................................................. 174 [L] LCR0 ................................................................................... 694 LCR1 ................................................................................... 695 LCR2 ................................................................................... 696 LCR3 ................................................................................... 696 LINCR .................................................................................. 630 LINCR2 ................................................................................ 629 LINST .................................................................................. 630 LSE0 .................................................................................... 697 LSE1 .................................................................................... 697 LSE2 .................................................................................... 698 LSE3 .................................................................................... 698 LSE4 .................................................................................... 699 LSE5 .................................................................................... 699 LSE6 .................................................................................... 700 LSE7 .................................................................................... 700 [M] MSTCR ................ 280, 335, 351, 372, 389, 404, 421, 565, 597 [O] OCD ............................................................................. 132, 149 OCVREFCR ........................................................................ 644 OFS ......................................................... 52, 71, 207, 214, 724 OFS2 ..................................................................... 53, 208, 215 [P] P10DRR .............................................................................. 100 P11DRR ............................................................................... 101 PDi (i = 0 to 7, 10 to 13) ........................................................ 85 Pi (i = 0 to 7, 10 to 13) ........................................................... 86 PiPUR (i = 0 to 7) .................................................................. 99 PjPUR (j = 10 to 13) ............................................................ 100 PM0 ....................................................................................... 51 PM1 ..................................................................................... 212 POMCR0 ............................................................................. 152 PRCR .................................................................................. 168 [R] RMADi (i = 0 or 1) ................................................................ 196 RSTFR ................................................................................... 51 [S] S0RIC .................................................................................. 174 S0TIC .................................................................................. 174 S1RIC .................................................................................. 174 S1TIC ................................................................................... 174 S2RIC .................................................................................. 174 S2TIC .................................................................................. 174 SAR ..................................................................................... 604 SSBR ................................................................................... 567 SSCRH ................................................................................ 568 SSCRL ................................................................................. 569 SSER ................................................................................... 571 SSMR .................................................................................. 570 SSMR2 ................................................................................ 573 SSRDR ................................................................................ 568 SSSR ................................................................................... 572 REJ09B0441-0010 Rev.0.10 Page 807 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Index SSTDR ................................................................................ 567 SSUIC/IICIC ........................................................................ 175 SSUIICSR ............................................................. 97, 566, 597 [T] TRA ..................................................................................... 243 TRACR ................................................................................ 241 TRAIC ................................................................................. 174 TRAIOC ....................................... 241, 244, 247, 249, 251, 254 TRAMR ............................................................................... 242 TRAPRE .............................................................................. 242 TRASR .......................................................................... 87, 243 TRBCR ................................................................................ 258 TRBIC ................................................................................. 174 TRBIOC ............................................... 259, 262, 266, 269, 273 TRBMR ............................................................................... 259 TRBOCR ............................................................................. 258 TRBPR ................................................................................ 261 TRBPRE .............................................................................. 260 TRBRCSR ............................................................. 88, 261, 288 TRBSC ................................................................................ 260 TRC ..................................................................................... 285 TRCADCR ........................................................................... 287 TRCCR1 ...................................................... 282, 304, 312, 318 TRCCR2 .............................................................. 286, 313, 319 TRCDF ........................................................................ 286, 319 TRCGRA ............................................................................. 285 TRCGRB ............................................................................. 285 TRCGRC ............................................................................. 285 TRCGRD ............................................................................. 285 TRCIC ................................................................................. 175 TRCIER ............................................................................... 282 TRCIOR0 ............................................................ 284, 299, 305 TRCIOR1 ............................................................ 284, 300, 306 TRCMR ............................................................................... 281 TRCOER ............................................................................. 287 TRCPSR0 ..................................................................... 89, 289 TRCPSR1 ..................................................................... 90, 290 TRCSR ................................................................................ 283 TRD0 ................................................................... 396, 411, 429 TRD0IC ............................................................................... 175 TRD1 ................................................................................... 412 TRD1IC ............................................................................... 175 TRDADCR ........................................... 352, 373, 390, 405, 422 TRDCR0 ...................................................................... 394, 427 TRDCRi (i = 0 or 1) ..................................... 339, 358, 377, 409 TRDDFi (i = 0 or 1) .............................................................. 338 TRDECR ..................................... 335, 352, 373, 390, 404, 421 TRDFCR ..................................... 337, 355, 375, 392, 407, 424 TRDGRAi (i = 0 or 1) ................... 344, 363, 381, 397, 412, 430 TRDGRBi (i = 0 or 1) ................... 344, 363, 381, 397, 412, 430 TRDGRC1 ........................................................................... 412 TRDGRCi (i = 0 or 1) ........................... 344, 363, 381, 397, 430 TRDGRDi (i = 0 or 1) ................... 344, 363, 381, 397, 412, 430 TRDi (i = 0 or 1) ................................................... 343, 362, 380 TRDIERi (i = 0 or 1) ..................... 343, 362, 379, 396, 411, 429 TRDIORAi (i = 0 or 1) .................................................. 340, 359 TRDIORCi (i = 0 or 1) .................................................. 341, 360 TRDMR ....................................... 336, 354, 374, 391, 406, 423 TRDOCR ............................................................. 357, 377, 426 TRDOER1 ........................................... 356, 376, 393, 408, 425 TRDOER2 ........................................... 356, 376, 393, 408, 425 TRDPMR ............................................................. 337, 354, 375 TRDPOCRi (i = 0 or 1) ........................................................ 379 TRDPSR0 ............................. 91, 345, 364, 382, 398, 414, 432 TRDPSR1 ............................. 92, 346, 365, 383, 399, 415, 433 TRDSRi (i = 0 or 1) ...................... 342, 361, 378, 395, 410, 428 TRDSTR ...................................... 336, 353, 374, 391, 406, 423 TRECR1 ...................................................................... 449, 455 TRECR2 ...................................................................... 450, 455 TRECSR ...................................................................... 451, 456 TREHR ................................................................................ 448 TREIC .................................................................................. 174 TREMIN ....................................................................... 447, 454 TRESEC ...................................................................... 447, 454 TREWK ................................................................................ 448 TRG ..................................................................................... 469 TRGCNTC ........................................................................... 464 TRGCR ........................................................................ 465, 489 TRGGRA ............................................................................. 470 TRGGRB ............................................................................. 470 TRGGRC ............................................................................. 470 TRGGRD ............................................................................. 470 TRGIC ................................................................................. 175 TRGIER ............................................................................... 466 TRGIOR ............................................................... 468, 477, 481 TRGMR ............................................................................... 463 TRGPSR ........................................................................ 93, 471 TRGSR ................................................................................ 467 [U] U0SR ............................................................................. 93, 500 U1SR ............................................................................. 94, 501 U2BCNIC ............................................................................. 174 U2BRG ................................................................................ 517 U2C0 ................................................................................... 519 U2C1 ................................................................................... 520 U2MR .................................................................................. 517 U2RB ................................................................................... 521 U2SMR ................................................................................ 524 U2SMR2 .............................................................................. 524 U2SMR3 .............................................................................. 523 U2SMR4 .............................................................................. 523 U2SMR5 .............................................................................. 522 U2SR0 ........................................................................... 95, 525 U2SR1 ........................................................................... 96, 526 U2TB ................................................................................... 518 UiBRG (i = 0 or 1) ................................................................ 496 UiC0 (i = 0 or 1) ................................................................... 498 UiC1 (i = 0 or 1) ................................................................... 498 UiMR (i = 0 or 1) .................................................................. 496 UiRB (i = 0 or 1) ................................................................... 499 UiTB (i = 0 or 1) ................................................................... 497 URXDF ................................................................................ 522 [V] VCA1 ............................................................................. 65, 672 VCA2 ..................................................................... 66, 151, 673 VCAC ............................................................................. 65, 672 VCMP1IC ............................................................................. 174 VCMP2IC ............................................................................. 174 VD1LS ................................................................................... 67 VLT0 .................................................................................... 101 VLT1 .................................................................................... 102 VLT2 .................................................................................... 103 VW0C .................................................................................... 68 VW1C ............................................................................ 69, 674 VW2C ............................................................................ 70, 675 REJ09B0441-0010 Rev.0.10 Page 808 of 809 Jul 30, 2008 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Index [W] WDTC ................................................................................. 213 WDTR ................................................................................. 212 WDTS .................................................................................. 212 REJ09B0441-0010 Rev.0.10 Page 809 of 809 Jul 30, 2008 REVISION HISTORY REVISION HISTORY Rev. 0.02 0.10 Date Jun 24, 2008 Jul 30, 2008 R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Hardware Manual R8C/L35A Group, R8C/L35B Group, R8C/L36A Description Page First Edition issued Revised Edition issued Summary C-1 R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Hardware Manual Publication Date: Rev.0.02 Rev.0.10 Jun 24, 2008 Jul 30, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan