RMLV0816BGSD-4S2#HA1

RMLV0816BGSD - 4S2 8Mb Advanced LPSRAM (512k word × 16bit / 1024k word x 8bit) R10DS0253EJ0201 Rev.2.01 2020.02.20 Description The RMLV0816BGSD is a family of 8-Mbit static RAMs organized 524,288-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0816BGSD has realized higher density, higher performance and low power consumption. The RMLV0816BGSD offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 52pin TSOP (II). Features  Single 3V supply: 2.4V to 3.6V  Access time: ── Power supply voltage from 2.7V to 3.6V: 45ns (max.) ── Power supply voltage from 2.4V to 2.7V: 55ns (max.)  Current consumption: ── Standby: 0.45µA (typ.)  Equal access and cycle times  Common data input and output ── Three state output  Directly TTL compatible ── All inputs and outputs  Battery backup operation Part Name Information Part Name Power supply Access time 2.7V to 3.6V 45 ns 2.4V to 2.7V 55 ns RMLV0816BGSD-4S2 R10DS0253EJ0201 Rev.2.01 2020.02.20 Temperature Range Package -40 ~ +85°C 10.79mm × 10.49mm 52pin plastic µTSOP (II) Page 1 of 14 RMLV0816BGSD - 4S2 Pin Arrangement A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 Vss A11 5 48 LB# A10 6 47 DQ15/A-1 A9 7 46 DQ7 A8 8 45 DQ14 NC 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 NC 16 37 DQ3 NC 17 36 DQ10 A18 18 35 DQ2 A17 19 34 DQ9 A7 20 33 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 Vss A2 25 28 NC A1 26 27 A0 52pin TSOP (II) Pin Description Pin name VCC VSS A0 to A18 A-1 to A18 DQ0 to DQ15 CS1# CS2 Power supply Ground Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Function OE# WE# LB# UB# BYTE# NC Output enable Write enable Lower byte select Upper byte select Byte control mode enable No connection R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 2 of 14 RMLV0816BGSD - 4S2 Block Diagram A0 A1 MEMORY ARRAY ADDRESS ROW 512k-word x16-bit BUFFER DECODER or DQ0 1M-word x8-bit DQ1 A18 DQ BUFFER DQ7 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ8 COLUMN DECODER DQ9 DQ BUFFER CLOCK CS2 GENERATOR DQ15 / A -1 CS1# LB# UB# x8 / x16 CONTROL Vcc Vss BYTE# WE# OE# R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 3 of 14 RMLV0816BGSD - 4S2 Operation Table CS1# CS2 BYTE# UB# LB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation H X X X X X X High-Z High-Z High-Z Stand-by X L X X X X X High-Z High-Z High-Z Stand-by X X H H H X X High-Z High-Z High-Z Stand-by L H H H L L X Din High-Z High-Z Write in lower byte L H H H L H L Dout High-Z High-Z Read in lower byte L H H H L H H High-Z High-Z High-Z Output disable L H H L H L X High-Z Din Din Write in upper byte L H H L H H L High-Z Dout Dout Read in upper byte L H H L H H H High-Z High-Z High-Z Output disable L H H L L L X Din Din Din Word write L H H L L H L Dout Dout Dout Word read L H H L L H H High-Z High-Z High-Z Output disable L H L X X L X Din High-Z A-1 Byte write L H L X X H L Dout High-Z A-1 Byte read L H L X X H H High-Z High-Z A-1 Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Ratings Parameter Symbol Power supply voltage relative to VSS VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum) 3. Maximum voltage is +4.6V. Value -0.5 to +4.6 -0.5*2 to VCC+0.3*3 0.7 -40 to +85 -65 to +150 -40 to +85 unit V V W °C °C °C DC Operating Conditions Parameter Supply voltage Symbol VCC VSS ─ Max. 3.6 0 VCC+0.2 Unit V V V Vcc=2.4V to 2.7V ─ VCC+0.2 V Vcc=2.7V to 3.6V -0.2 ─ 0.4 V Vcc=2.4V to 2.7V 4 -0.2 ─ 0.6 V Vcc=2.7V to 3.6V 4 Ambient temperature range Ta -40 ─ Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum) +85 °C Input high voltage VIH Input low voltage VIL R10DS0253EJ0201 Rev.2.01 2020.02.20 Min. 2.4 0 Typ. 3.0 0 2.0 2.2 Test conditions Note Page 4 of 14 RMLV0816BGSD - 4S2 DC Characteristics Parameter Input leakage current Output leakage current Symbol | ILI | Min. ─ Typ. ─ Max. 1 Unit A Test conditions Vin = VSS to VCC BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# = VIH or CS2 = VIL or OE# = VIH A ─ ─ 1 | ILO | or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Cycle = 55ns, duty =100%, II/O = 0mA, Average operating current 25 mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ─ 20*5 CS1# = VIL, CS2 = VIH, Others = VIH/VIL ICC1 Cycle = 45ns, duty =100%, II/O = 0mA, ─ 25*5 30 mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# = VIL, CS2 = VIH, Others = VIH/VIL Cycle = 1s, duty =100%, II/O = 0mA, BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ICC2 ─ 1.5*5 3 mA CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V Standby current BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ISB ─ ─ 0.3 mA CS2 = VIL, Others = VSS to VCC Vin = VSS to VCC, Standby current A 2 ~+25°C ─ 0.45*5 BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V A ─ 0.6*6 4 ~+40°C (1) CS2 ≤ 0.2V or ISB1 (2) CS1# ≥ VCC-0.2V, A ─ ─ 7 ~+70°C CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, A ─ ─ 10 ~+85°C CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V Output high voltage 2.4 ─ ─ V IOH = -1mA VOH Vcc≥2.7V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V VOH2 2.0 ─ ─ V IOH = -0.1mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V Output low voltage ─ ─ 0.4 V IOL = 2mA VOL Vcc≥2.7V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V VOL2 ─ ─ 0.4 V IOL = 0.1mA Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. Note 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 7. This parameter is sampled and not 100% tested. R10DS0253EJ0201 Rev.2.01 2020.02.20 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 7 7 Page 5 of 14 RMLV0816BGSD - 4S2 AC Characteristics Test Conditions (Vcc = 2.4V ~ 3.6V, Ta = -40 ~ +85°C) 1.4V  Input pulse levels: VIL = 0.4V, VIH = 2.4V (Vcc=2.7V to 3.6V) VIL = 0.4V, VIH = 2.2V (Vcc=2.4V to 2.7V)  Input rise and fall time: 5ns  Input and output timing reference level: 1.4V  Output load: See figures (Including scope and jig) RL = 500 ohm DQ CL = 30 pF Read Cycle Vcc=2.4V to 2.7V Unit Note Min. Max. Min. Max. Read cycle time tRC 45 ─ 55 ─ ns Address access time tAA ─ 45 ─ 55 ns tACS1 ─ 45 ─ 55 ns Chip select access time tACS2 ─ 45 ─ 55 ns Output enable to output valid tOE ─ 22 ─ 30 ns Output hold from address change tOH 10 ─ 10 ─ ns LB#, UB# access time tBA ─ 45 ─ 55 ns tCLZ1 10 ─ 10 ─ ns 8,9 Chip select to output in low-Z tCLZ2 10 ─ 10 ─ ns 8,9 LB#, UB# enable to low-Z tBLZ 5 ─ 5 ─ ns 8,9 Output enable to output in low-Z tOLZ 5 ─ 5 ─ ns 8,9 tCHZ1 0 18 0 20 ns 8,9,10 Chip deselect to output in high-Z tCHZ2 0 18 0 20 ns 8,9,10 LB#, UB# disable to high-Z tBHZ 0 18 0 20 ns 8,9,10 Output disable to output in high-Z tOHZ 0 18 0 20 ns 8,9,10 Note 8. This parameter is sampled and not 100% tested. 9. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. 10. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. Parameter R10DS0253EJ0201 Rev.2.01 2020.02.20 Symbol Vcc=2.7V to 3.6V Page 6 of 14 RMLV0816BGSD - 4S2 Write Cycle Vcc=2.4V to 2.7V Unit Note Min. Max. Min. Max. Write cycle time tWC 45 ─ 55 ─ ns Address valid to write end tAW 35 ─ 50 ─ ns Chip select to write end tCW 35 ─ 50 ─ ns Write pulse width tWP 35 ─ 40 ─ ns 11 LB#,UB# valid to write end tBW 35 ─ 50 ─ ns Address setup time to write start tAS 0 ─ 0 ─ ns Write recovery time from write end tWR 0 ─ 0 ─ ns Data to write time overlap tDW 25 ─ 25 ─ ns Data hold from write end tDH 0 ─ 0 ─ ns Output enable from write end tOW 5 ─ 5 ─ ns 12 Output disable to output in high-Z tOHZ 0 18 0 20 ns 12,13 Write to output in high-Z tWHZ 0 18 0 20 ns 12,13 Note 11. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 12. This parameter is sampled and not 100% tested. 13. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. Parameter Symbol Vcc=2.7V to 3.6V BYTE# Timing Conditions Parameter Byte setup time Byte recovery time Symbol tBS tBR Vcc=2.7V to 3.6V Min. 5 5 Max. ─ ─ Vcc=2.4V to 2.7V Min. 5 5 Max. ─ ─ Unit Note ms ms BYTE# Timing Waveforms CS1# CS2 tBS tBR BYTE# R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 7 of 14 RMLV0816BGSD - 4S2 Timing Waveforms Read Cycle*14 tRC A0~18 Valid address (Word Mode) A -1~18 tAA (Byte Mode) tACS1 CS1# tCLZ1 *16,17 CS2 tCHZ1 *15,16,17 tACS2 tCLZ2 *16,17 tCHZ2 *15,16,17 tBA LB#,UB# tBLZ *16,17 WE# tBHZ *15,16,17 VIH WE# = “H” level tOHZ *15,16,17 tOE OE# tOLZ tOH *16,17 DQ0~15 (Word Mode) DQ0~7 High impedance Valid Data (Byte Mode) Note 14. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V 15. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 16. This parameter is sampled and not 100% tested 17. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 8 of 14 RMLV0816BGSD - 4S2 Write Cycle (1)*18 (WE# CLOCK, OE#=”H” while writing) tWC A0~18 Valid address (Word Mode) A -1~18 (Byte Mode) tCW CS1# CS2 tCW tBW LB#,UB# tWR tAW tWP *19 WE# tAS OE# DQ0~15 (Word Mode) DQ0~7 tWHZ *20,21 tOHZ *20,21 *22 tDW tDH Valid Data (Byte Mode) Note 18. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V 19. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 20. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 21. This parameter is sampled and not 100% tested 22. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins. R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 9 of 14 RMLV0816BGSD - 4S2 Write Cycle (2)*23 (WE# CLOCK, OE# Low Fixed) tWC A0~18 Valid address (Word Mode) A -1~18 (Byte Mode) tCW CS1# CS2 tCW tBW LB#,UB# tAW tWR tWP *24 WE# OE# OE# = “L” level tAS VIL tWHZ *25,26 DQ0~15 (Word Mode) DQ0~7 (Byte Mode) *27 tOW Valid Data tDW *27 tDH Note 23. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V 24. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 25. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 26. This parameter is sampled and not 100% tested. 27. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins. R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 10 of 14 RMLV0816BGSD - 4S2 Write Cycle (3)*28 (CS1#, CS2 CLOCK) tWC A0~18 (Word Mode) Valid address A -1~18 (Byte Mode) tAW tAS tCW tAS tCW tWR CS1# CS2 tBW LB#,UB# tWP *29 WE# OE# VIH OE# = “H” level DQ0~15 (Word Mode) DQ0~7 tDW tDH Valid Valid Data Data (Byte Mode) Note 28. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V 29. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 11 of 14 RMLV0816BGSD - 4S2 Write Cycle (4)*30 (LB#, UB# CLOCK, Word Mode) tWC A0~18 Valid address (Word Mode) tAW tCW CS1# tCW CS2 tAS tWR tBW LB#,UB# tWP *31 WE# OE# VIH OE# = “H” level tDW DQ0~15 (Word Mode) tDH Valid Data Note 30. BYTE# ≥ Vcc -0.2V 31. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 12 of 14 RMLV0816BGSD - 4S2 Low VCC Data Retention Characteristics Parameter VCC for data retention Data retention current Symbol VDR Min. Typ. Max. Test conditions*34 Unit 1.5 ─ 3.6 V Vin ≥ 0V, BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V ─ 0.45*32 2 A ~+25°C ─ 0.6*33 4 A ~+40°C ─ ─ 7 A ~+70°C ─ ─ 10 A ~+85°C ICCDR VCC = 3.0V, Vin ≥ 0V, BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 32. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 33. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. 34. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and DQ buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The other inputs levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high-impedance state. R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 13 of 14 RMLV0816BGSD - 4S2 Low Vcc Data Retention Timing Waveforms (CS1# controlled)*35 CS1# Controlled VCC tCDR 2.4V 2.4V tR VDR 2.0V 2.0V CS1# ≥ VCC - 0.2V CS1# Low Vcc Data Retention Timing Waveforms (CS2 controlled)*35 CS2 Controlled VCC tCDR CS2 2.4V 2.4V tR VDR 0.4V 0.4V CS2 ≤ 0.2V Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled, Word Mode)*36 LB#,UB# Controlled VCC tCDR 2.0V 2.4V 2.4V VDR tR 2.0V LB#,UB# ≥ VCC - 0.2V LB#,UB# Note 35. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V 36. BYTE# ≥ Vcc -0.2V R10DS0253EJ0201 Rev.2.01 2020.02.20 Page 14 of 14 Revision History Rev. 1.00 2.00 Date 2014.11.28 2015.06.26 2.01 2020.02.20 Page ─ P.1, 5 P.5 P.13 Last page RMLV0816BGSD Data Sheet Description Summary First Edition issued Standby current ISB1 : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.) Average operating current ICC2 : 25°C 2mA ->1.5mA (typ.) Data retention current ICCDR : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.) 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