XFP236156.250000I

XF Plastic Package Family of Low Phase Noise Quartz-based PLL Oscillators Description Features The XF devices are ultra-low phase noise quartz-based PLL oscillators supporting a large range of frequencies and output interface types. These devices are designed to operate at three different power supplies with several pinout configurations, as well as two operational temperature ranges. ▪ Output types: LVDS, LVPECL, CML XF Datasheet • Frequency range: 15MHz to 2100MHz ▪ Output type: HCSL • Frequency range: 15MHz to 725MHz ▪ Supply voltage options: 1.8V, 2.5V, or 3.3V ▪ Phase jitter (12kHz to 20MHz): 120fs typical ▪ Package options: The XF devices can be programmed to generate an output frequency from 15MHz to 2100MHz with a resolution as low as 1Hz accuracy. The configuration capability of this family of devices allows for fast delivery times for both sample and large production orders. • 5.0 × 3.2 mm • 3.2 × 2.5 mm • 2.5 × 2.0 mm Parts are for one time programming (OTP) at the factory for a fixed frequency application, or can be field programmable using I2C, based on system needs (see notes under Pin Descriptions). ▪ Operating temperatures and frequency stability: • -40°C to +85°C, ±25ppm • -40°C to +105°C, ±50ppm Typical Applications ▪ FOM Gear Box ▪ Data centers ▪ 10G / 40G / 100G / 400G Ethernet Pin Assignments Figure 1. 2.5 × 2.0 mm Package Figure 2. 5.0 × 3.2 mm and 3.2 × 2.5 mm Packages SDA 7 NC 1 12 Ground Core VDD Core Ground Output OE 1 6 VDD NC 2 5 OUT0b NC 2 11 Voltage Control SDA 3 10 4 9 Output 0b OE SCL 5 8 Output 0 6 7 VDD Output GND 3 4 OUT0 8 SCL ©2021 Renesas Electronics Corporation 1 R31DS0029EU0601 July 13, 2021 XF Datasheet Pin Descriptions Table 1. Pin Descriptions for 2.5 × 2.0 mm Package Pin Number 1 2 Pin Name Description 1 NC No connect. 2 NC No connect. 3 Voltage Control 2 Voltage control for VCXO option. 1 4 SDA Serial data. 5 OE Output enable. 6 SCL 1 Serial clock. 7 VDD Output Supply voltage. 8 Output 0 Output 0. 9 Output 0b Complementary output 0. 10 Ground Output Connect to ground. 11 VDD Core Supply voltage. 12 Ground Core Connect to ground. 13 EPAD (dotted area shown in Pin Assignments diagram) Connect to ground (required for heat dissipation). Pins 4 and 6 are no connect for non-I2C applications. Pin 3 is no connect for non-analog VCXO applications. See Ordering Information (VCXO) for more details. Table 2. Pin Descriptions for 5.0 × 3.2 mm and 3.2 × 2.5 mm Packages 1 Pin # Pin Name Description 1 2 3 4 5 6 7 8 OE NC GND OUT0 OUT0b VDD SDA 1 SCL 1 Output Enable (0 = output disabled, pulled high internally) No connect Connect to ground Output Complementary output Supply voltage Serial data Serial clock Pins 7 and 8 are no connect for non-I2C applications. See Ordering Information (VCXO) for more details. ©2021 Renesas Electronics Corporation 2 R31DS0029EU0601 July 13, 2021 XF Datasheet Ordering Information (XO) Custom Part Configuration Utility: https://www.renesas.com/customxo XF L 2 3 5 125.000000 I Family and ASIC Output Type Package Voltage Precision Frequency Temperature Range  I: Industrial range: ‐40 to +85°C  K: Extended industrial range: ‐40 to +105°C  1: 1.8 VDC ±5%  2: 2.5 VDC ±5%  3: 3.3 VDC ±5%  125.000000 Listed in MHz to 6 digits    015.000000MHz to 999.999999MHz  5: 5.0 x 3.2 mm  3: 3.2 x 2.5 mm  2: 2.5 x 2.0 mm  C: CML    L: LVDS  P:  LVPECL  N: HCSL F00.000000 to F99.999999 1500MHz to 1599.999MHz G00.000000 to G99.999999 1600MHz to 1699.999MHz H00.000000 to H99.999999 1700MHz to 1799.999MHz I00.000000 to I99.999999 1800MHz to 1899.999MHz J00.000000 to J99.999999 1900MHz to 1999.999MHz      K00.000000 to K99.999999 2000MHz to 2099.999MHz      5: ±50 ppm (K only)   6:  ±25 ppm (I only)  XF:  150fs jitter max. Ordering Information (VCXO) XF L 2 3 X 125.000000 I Family and ASIC Output Type Package Voltage Precision Frequency Temperature Range  1: 1.8 VDC ±5%  2: 2.5 VDC ±5%  3: 3.3 VDC ±5%   I: Industrial range  ‐40 to +85 °C  K: Extended industrial range  ‐40 to +105 °C  125.000000 Listed in MHz to 6 digits  2: 2.5 x 2.0 mm  C: CML    L: LVDS  P: LVPECL  N: HCSL    015.000000MHz to 999.999999MHz  F00.000000 to F99.999999 1500MHz to 1599.999MHz  G00.000000 to G99.999999 1600MHz to 1699.999MHz  H00.000000 to H99.999999 1700MHz to 1799.999MHz  I00.000000 to I99.999999 1800MHz to 1899.999MHz  J00.000000 to J99.999999 1900MHz to 1999.999MHz       K00.000000 to K99.999999 2000MHz to 2099.999MHz     XF: 150fs jitter max.   X: ±100ppm VCXO Pull Range; 20K VCXO Bandwidth   Y: ±150ppm VCXO Pull Range; 20K VCXO Bandwidth   Z: ±200ppm VCXO Pull Range; 20K VCXO Bandwidth ©2021 Renesas Electronics Corporation 3 R31DS0029EU0601 July 13, 2021 XF Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering Information (XO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information (VCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Termination for 3.3V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Termination for 2.5V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended Termination for HCSL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CML Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ©2021 Renesas Electronics Corporation 4 R31DS0029EU0601 July 13, 2021 XF Datasheet Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Thermal characteristics, in actual applications, should be assessed case by case to guarantee junction temperature does not exceed 125°C. Table 3. Absolute Maximum Ratings Item Rating VDD -0.5V to +3.8V E/D -0.5V to +3.8V Storage Temperature -55°C to 125°C Maximum Junction Temperature 125°C 97.0 °C/W 131.47 °C/W 138.43 °C/W Theta JA 1 2.5 × 2.0 mm (NJG12) 3.2 × 2.5 mm (LNG8) 5.0 × 3.2 mm (LXG8) 1 Theta JB 62.2 °C/W 92.89 °C/W 97.42 °C/W 1 Thermal characteristics are based on simulation in standard condition. ESD Compliance Table 4. ESD Compliance Human Body Model (HBM) 2000V Mechanical Testing Table 5. Mechanical Testing * Parameter Test Method Mechanical Shock Half-sine wave with 0.3ms 3000G. X, Y, Z each direction 1 time. Mechanical Vibration Frequency: 10 to 55MHz amplitude: 1.5mm. Frequency: 55–2000Hz peak value: 20G. Duration time: 4H for each X,Y,Z axis; total 12hours. High Temp Operating Life (HTOL) 1000 hours at 125°C (under power). Hermetic Seal Gross leak (air leak test). Fine leak (Helium leak test) He-pressure: 6kgf/cm² 2 hours. * MSL level does not apply. Solder Reflow Profile tP 10 seconds Max within 5°C of 260°C peak 260°C 225°C Ramp up 3°C/s Max 50 ±10 seconds above 225°C reflow area 180°C 160°C Ramp down not to exceed 6°C/s 120 ±20 seconds in pre-heating area 25°C 400 seconds Max from +25°C to 260°C peak ©2021 Renesas Electronics Corporation 5 R31DS0029EU0601 July 13, 2021 XF Datasheet DC Electrical Characteristics Note for all DC Electrical Characteristics tables: A pull-up resistor from VDD to OE enables output when pin 5 is left open. Table 6. 3.3V IDD DC Electrical Characteristics VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol Parameter Output Type Minimum Typical Maximum 15MHz to 400MHz. — 59 67 400MHz to 2.1GHz. — — 85 15MHz to 212.5MHz. — 84 94 212MHz to 400MHz. — — 110 400MHz to 2.1GHz. — — 110 HCSL 15MHz to 725MHz. — 74 83 CML 15MHz to 2.1GHz. — 45 61 Minimum Typical Maximum 15MHz to 400MHz. — 59 66 400MHz to 2.1GHz. — — 85 15MHz to 156.25MHz. — 84 94 156.25MHz to 400MHz. — — 110 400MHz to 2.1GHz. — — 110 15MHz to 400MHz. — — 95 400MHz to 725MHz. — 74 82 15MHz to 2.1GHz. — 54 61 Minimum Typical Maximum 15MHz to 400MHz. — 59 66 400MHz to 2.1GHz. — — 85 15MHz to 250MHz. — 84 93 250MHz to 2.1GHz. — — 110 15MHz to 400MHz. — — 95 400MHz to 725MHz. — 74 81 15MHz to 2.1GHz. — 54 61 LVDS IDD Current Consumption LVPECL Conditions Units mA Table 7. 2.5V IDD DC Electrical Characteristics VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol Parameter Output Type LVDS IDD Current Consumption LVPECL HCSL CML Conditions Units mA Table 8. 1.8V IDD DC Electrical Characteristics VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol Parameter Output Type LVDS IDD Current Consumption LVPECL HCSL CML ©2021 Renesas Electronics Corporation Conditions 6 Units mA R31DS0029EU0601 July 13, 2021 XF Datasheet Table 9. LVCMOS DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol Parameter Conditions Minimum Typical Maximum Units VIH Input High Voltage (OE pin only) VDD = 3.3V, 2.5V, 1.8V ±5% 0.7 × VDD — VDD + 0.3 V VIL Input Low Voltage (OE pin only) VDD = 3.3V, 2.5V, 1.8V ±5% GND - 0.3 — 0.3 × VDD V Table 10. LVDS DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol VOD VOS Parameter Differential Output Voltage Output Offset Voltage Conditions Minimum Typical Maximum VDD = 3.3V, 2.5V, 1.8V ±5% 0.30 0.44 0.60 VDD = 3.3V ±5% 1.11 1.26 1.41 VDD = 2.5V ±5% 1.08 1.25 1.41 VDD = 1.8V ±5% 0.75 0.88 1.01 Units V Table 11. LVPECL DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Conditions Minimum Typical Maximum VDD = 3.3V ±5%. 2.28 2.49 2.72 VDD = 2.5V ±5%. 1.52 1.69 1.87 VDD = 1.8V ±5%. 0.83 0.96 1.11 VDD = 3.3V ±5%. 1.68 1.84 2.01 VDD = 2.5V ±5%. 0.92 1.04 1.17 VDD = 1.8V ±5%. 0.19 0.30 0.42 Units V Table 12. HCSL DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol VOH VOL Parameter Output High Voltage Output Low Voltage ©2021 Renesas Electronics Corporation Conditions Minimum Typical Maximum VDD = 3.3V ±5%. 0.78 0.92 1.07 VDD = 2.5V ±5%. 0.74 0.88 1.03 VDD = 1.8V ±5%. 0.67 0.81 0.95 — -0.06 0.07 0.20 7 Units V R31DS0029EU0601 July 13, 2021 XF Datasheet Table 13. CML DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol VOH VOL Parameter Conditions Minimum Typical Maximum VDD = 3.3V ±5%. 3.09 3.26 3.43 VDD = 2.5V ±5%. 2.33 2.46 2.59 VDD = 1.8V ±5%. 1.66 1.76 1.85 VDD = 3.3V ±5%. 2.70 2.85 3.00 VDD = 2.5V ±5%. 1.95 2.06 2.17 VDD = 1.8V ±5%. 1.30 1.37 1.45 Minimum Typical Maximum -5 0.81 5 -5 1.36 5 SDATA -5 1.44 5 OE -20 -17.44 -14 -37 -33.49 -30 -20 -17.02 -14 Output High Voltage Output Low Voltage Units V V Table 14. DC Electrical Characteristics – Leakage Current VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. Symbol Parameter Input Conditions OE IIH IIL Input Leakage High Input Leakage Low SCLK SCLK VDD = 3.3V ±5%. VDD = 3.3V ±5%. SDATA Units µA µA AC Electrical Characteristics Notes for all AC Electrical Characteristics tables: 1. A pull-up resistor from VDD to OE enables output when pin 5 is left open. 2. Installation should include a 0.01μF bypass capacitor placed between VDD and GND to minimize power supply line noise. Table 15. 3.3V AC Electrical Characteristics VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Symbol F Parameter Minimum Typical Maximum LVDS, LVPECL, CML. 15 — 2100 HCSL. 15 — 725 Temperature = -40°C to +85°C. — — ±25 ppm Temperature = -40°C to +105°C. — — ±50 ppm Frequency Tolerance (25°C) Temperature = 25°C. — — ±15 ppm Aging (1st year) TA = 25°C. — — ±3 ppm Aging (10 years) TA = 25°C. — — ±10 ppm Output Frequency Range Frequency Stability ©2021 Renesas Electronics Corporation Test Condition 8 Units MHz R31DS0029EU0601 July 13, 2021 XF Datasheet Table 15. 3.3V AC Electrical Characteristics (Cont.) VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Symbol Parameter Output Load TST tR tF Start-up Time Output Rise Time Output Fall Time Test Condition TOE Output Clock Duty Cycle Output Enable/Disable Time ©2021 Renesas Electronics Corporation Typical Maximum LVDS. Differential. — 100 — LVPECL. VDD - 2.0V. — 50 — HCSL. To GND. — 50 — Output valid time after VDD meets minimum specified level. — 5 — LVDS. — 299 400 — 287 400 — 306 400 CML — 301 400 LVDS. — 279 400 — 274 400 — 284 400 — 279 400 LVPECL. 20% – 80%, 156.25MHz HCSL. LVPECL. 80% – 20%, 156.25MHz HCSL. CML ODC Minimum LVDS. 156.25MHz 45 — 55 LVPECL. 156.25MHz 45 — 55 HCSL. 156.25MHz 45 — 55 CML 156.25MHz 45 — 55 — 1 — — — 9 Units Ω ms ps ps % ms R31DS0029EU0601 July 13, 2021 XF Datasheet Table 16. 2.5V AC Electrical Characteristics VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Symbol F Parameter Minimum Typical Maximum LVDS, LVPECL, CML. 15 — 2100 HCSL. 15 — 725 Temperature = -40°C to +85°C. — — ±25 ppm Temperature = -40°C to +105°C. — — ±50 ppm Frequency Tolerance (25°C) Temperature = 25°C. — — ±15 ppm Aging (1st year) TA = 25°C. — — ±3 Aging (10 years) TA = 25°C. — — ±10 Output Frequency Range Frequency Stability Output Load TST tR tF Start-up Time Output Rise Time Output Fall Time Test Condition LVDS. Differential. — 100 — LVPECL. VDD - 2.0V. — 50 — HCSL. To GND. — 50 — Output valid time after VDD meets minimum specified level. — 5 — LVDS. — 303 400 — 292 400 — 310 400 CML — 304 400 LVDS. — 282 400 — 278 400 — 288 400 — 281 400 LVPECL. 20% – 80%, 156.25MHz HCSL. LVPECL. 80% – 20%, 156.25MHz HCSL. CML ODC TOE Output Clock Duty Cycle Output Enable/Disable Time ©2021 Renesas Electronics Corporation LVDS. 156.25MHz 45 — 55 LVPECL. 156.25MHz 45 — 55 HCSL. 156.25MHz 45 — 55 CML 156.25MHz 45 — 55 — 1 — — — 10 Units MHz Ω ms ps ps % ms R31DS0029EU0601 July 13, 2021 XF Datasheet Table 17. 1.8V AC Electrical Characteristics VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Symbol F Parameter Minimum Typical Maximum LVDS, LVPECL, CML. 15 — 2100 HCSL. 15 — 725 Temperature = -40°C to +85°C. — — ±25 ppm Temperature = -40°C to +105°C. — — ±50 ppm Frequency Tolerance (25°C) Temperature = 25°C. — — ±15 ppm Aging (1st year) TA = 25°C. — — ±3 ppm Aging (10 years) TA = 25°C. — — ±10 ppm Output Frequency Range Frequency Stability Output Load TST tR tF Start-up Time Output Rise Time Output Fall Time Test Condition LVDS. Differential. — 100 — LVPECL, HCSL. To GND. — 50 — Output valid time after VDD meets minimum specified level. — 5 — LVDS. — 311 450 — 312 450 — 316 450 CML — 313 450 LVDS. — 290 450 — 297 450 — 294 450 — 289 450 LVPECL. 20% – 80%, 156.25MHz HCSL. LVPECL. 80% – 20%, 156.25MHz HCSL. CML ODC TOE Output Clock Duty Cycle LVDS. 156.25MHz 45 — 55 LVPECL. 156.25MHz 45 — 55 HCSL. 156.25MHz 45 — 55 CML 156.25MHz 45 — 55 — 1 — Output Enable/Disable Time — — Units MHz Ω ms ps ps % ms Table 18. Phase Jitter Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Symbol fJITTER Parameter Phase Jitter (12kHz – 20MHz) ©2021 Renesas Electronics Corporation Conditions Minimum Typical Maximum Units 250.00MHz — 115 — fsec 312.50MHz — 125 — fsec 625.00MHz — 123 — fsec 644.53MHz — 120 — fsec 11 R31DS0029EU0601 July 13, 2021 XF Datasheet Output Waveforms Figure 3. LVDS/LVPECL/HCSL/CML Output Waveforms Output Levels /Rise Time/Fall Time Measurements TF TR OUT0b VOS 20% to 80% VOD OUT0 Oscillator Symmetry VOH OUT0b VOL OUT0 ½ Period Period ©2021 Renesas Electronics Corporation 12 R31DS0029EU0601 July 13, 2021 XF Datasheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 4 and Figure 5 show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4. 3.3V LVPECL Output Termination Figure 5. 3.3V LVPECL Output Termination ©2021 Renesas Electronics Corporation 13 R31DS0029EU0601 July 13, 2021 XF Datasheet Termination for 2.5V LVPECL Outputs Figure 6 and Figure 7 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 8 can be eliminated and the termination is shown in Figure 7. Figure 6. 2.5V LVPECL Driver Termination Example Figure 7. 2.5V LVPECL Driver Termination Example Figure 8. 2.5V LVPECL Driver Termination Example ©2021 Renesas Electronics Corporation 14 R31DS0029EU0601 July 13, 2021 XF Datasheet LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. Renesas offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 9 can be used with either type of output structure. Figure 10, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact Renesas and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. Figure 9. Standard LVDS Termination Figure 10. Optional LVDS Termination ©2021 Renesas Electronics Corporation 15 R31DS0029EU0601 July 13, 2021 XF Datasheet Recommended Termination for HCSL Outputs Figure 11 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω differential. Figure 12 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential. Figure 11. Recommended Source Termination (where the driver and receiver will be on separate PCBs) 0.5" Max Rs 22 to 33 +/-5% 0-0.2" 1-14" 0.5 - 3.5" L1 L2 L4 L5 L1 L2 L4 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 12. Recommended Termination (where a point-to-point connection can be used) Rs 0.5" Max 0 to 33 L1 0 to 33 L1 0-18" 0-0.2" L2 L3 L2 L3 PCI Expres s Rt Driver 49.9 +/- 5% CML Termination Figure 13 shows an example of the termination for a CML driver. In this example, the transmission line characteristic impedance is 50Ω. The R1 and R2 50Ω matched load terminations are pulled up to VDDO. The matched loads are located close to the receiver. Figure 13. CML Termination Example VDDO VDDO R1 50 R2 50 Zo = 50 Zo = 50 CML Driv er ©2021 Renesas Electronics Corporation 16 R31DS0029EU0601 July 13, 2021 XF Datasheet Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the links below. The package information is the most current data available and is subject to change without revision of this document. 2.5 × 2.0 mm package (NJG12) 3.2 × 2.5 mm package (LNG8) 5.0 × 3.2 mm package (LXG8) Marking Diagrams Marking Configuration for the 2.5 × 2.0 mm (NJG12) Package ▪ Line 1 indicates the following: ABC-YW $PF** • “ABC” denotes the truncated first three digits of the frequency code (e.g., 156). • “-YW” denotes the last digit of the year and week when the part was assembled. ▪ Line 2 indicates the following: • “$” denotes the mark location code. • “PF” denotes the package and frequency codes, where “P” = package code and “F” = frequency code. • “**” denotes the sequential lot number. Figure 14. Marking Configuration for the 3.2 × 2.5 mm (LNG8) Package (example based on XFL336156.250000I) ▪ Line 1 denotes the truncated part number as follows: • “F” = a combination of the 3rd digit (output type, e.g. “L”) and the 5th digit (voltage supply, e.g. “3”), in Fxxxxxx YWW**$ accordance with the mapping key as follows: • ▪ C1 = A, C2 = B, C3 = C, L1 = D, L2 = E, L3 = F, N1 = G, N2 = H, N3 = J, P1 = K, P2 = L, P3 = M “xxxxxx” = the first three digits to the left of the decimal point and the last three digits to the left of the decimal point as shown in the above example. This number will vary depending upon the frequency value selected in the orderable part number. (e.g. 156250)). ▪ Line 2 indicates the following: • “YWW” denotes the last digit of the year and week when the part was assembled. • “**” denotes the sequential lot number. • “$” denotes the mark location. Figure 15. Marking Configuration for the 5.0 × 3.2 mm (LXG8) Package (example based on XFL526125.000000I) XFL526 125000 YYWW** ▪ Line 1 indicates the following: • XF = family; “L” = output type; “526” = package, voltage, precision ▪ Line 2 indicates the following: • “125000” = the first three digits to the left of the decimal point and the last three digits to the left of the decimal point as shown in the above example. This number will vary depending upon the frequency value selected in the orderable part number. ▪ Line 3 indicates the following: • “YYWW” denotes the last digits of the year and week when the part was assembled. • “**” denotes the sequential lot number. ©2021 Renesas Electronics Corporation 17 R31DS0029EU0601 July 13, 2021 XF Datasheet Revision History Revision Date Description of Change July 13, 2021 ▪ Update Ordering Information (XO) key (precision specification). May 10, 2021 ▪ Updated Package and Precision codes in VCXO Ordering Information table. ▪ Moved XO and VCXO Ordering Information tables to follow Pin Descriptions. ▪ Updated VCXO Precision options from H, J, and K to X, Y, and Z, updated VCXO bandwidth values. March 31, 2021 ▪ Updated title of Ordering Information table to include (XO). ▪ Added a new Ordering Information table for (VCXO). ▪ Updated Frequency Tolerance values. February 11, 2021 Added new package options: 5.0 × 3.2 mm and 3.2 × 2.5 mm. January 6, 2020 Updated notes for pin descriptions. July 22, 2019 Updated LVDS Differential Output Voltage minimum value from 0.28V to 0.30V. May 22, 2019 Changed 3.3V, 2.5V, and 1.8V LVPECL current consumption conditions value from 670MHz to 2.1GHz. April 3, 2019 Initial release. ©2021 Renesas Electronics Corporation 18 R31DS0029EU0601 July 13, 2021 8-LGA, Package Outline Drawing 2.50 x 3.20 x 0.85 mm Body, 1.25mm Pitch LNG8D1, PSC-4837-01, Rev 01, Page 1 © Renesas Electronics Corporation 8-LGA, Package Outline Drawing 2.50 x 3.20 x 0.85 mm Body, 1.25mm Pitch LNG8D1, PSC-4837-01, Rev 01, Page 2 Package Revision History © Renesas Electronics Corporation Description Date Created Rev No. Nov. 12, 2019 00 Initial Release Jun. 21, 2021 01 Update to Renesas Logo 8-LGA, Package Outline Drawing 5.0 x 3.2 x 0.85 mm Body,1.27mm Pitch LXG8D1, PSC-4857-01, Rev 00, Page 1 © Renesas Electronics Corporation 8-LGA, Package Outline Drawing 5.0 x 3.2 x 0.85 mm Body,1.27mm Pitch LXG8D1, PSC-4857-01, Rev 00, Page 2 Package Revision History © Renesas Electronics Corporation Date Created Rev No. April 22, 2020 00 Description Initial Release IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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