YR8A77450S000BE

RZ/G1E Starter Kit Board Hardware Manual YR8A77450S000BE All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Rev.1.00 Oct 2015 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. “Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual Revision History Rev. 1.00 RZ/G1E Starter Kit Board Hardware Manual Date of Issue Page Oct 21, 2015 - YR8A77450S000BE October 24, 2015 Description Modification Newly created and released. Page I RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual Contents 1. Overview ........................................................................................................................................ 1 1.1. Features ..................................................................................................................................................................... 1 1.1.1. List of RZ/G1E Functions ................................................................................................................................... 1 1.1.2. List of YR8A77450S000BE Board Functions ........................................................................................................ 2 1.2. Usage Notes ............................................................................................................................................................... 4 1.2.1. YR8A77450S000BE Board Specifications ............................................................................................................ 4 1.3. Board Configuration.................................................................................................................................................... 5 1.3.1. Block Diagram of YR8A77450S000BE Board....................................................................................................... 5 1.3.2. Address Map of YR8A77450S000BE Board ......................................................................................................... 6 2. YR8A77450S000BE Interface Module Specifications .................................................................. 6 2.1. MODE Setting............................................................................................................................................................ 6 2.1.1. Specifications..................................................................................................................................................... 6 2.1.2. Initial Values of Mode Setting Pins on YR8A77450S000BE Board .......................................................................... 8 2.1.3. Multiplexing and Method of Setting for Mode Setting Pins ..................................................................................... 9 2.1.4. Block Diagram of Peripheral Circuit for Mode Pins ............................................................................................. 10 2.2. DDR3-SDRAM Interface .......................................................................................................................................... 11 2.2.1. Specifications................................................................................................................................................... 11 2.2.2. Signal Correlation............................................................................................................................................. 11 2.2.3. Block Diagram ................................................................................................................................................. 12 2.3. SPI-FLASH Interface (QSPI) ..................................................................................................................................... 13 2.3.1. Specifications................................................................................................................................................... 13 2.3.2. Block Diagram ................................................................................................................................................. 13 2.4. Video Input Interface (VIN0) ..................................................................................................................................... 14 2.4.1. Specifications................................................................................................................................................... 14 2.4.2. Block Diagram ................................................................................................................................................. 14 2.5. Video Output Interface .............................................................................................................................................. 15 2.5.1. Specifications................................................................................................................................................... 15 2.5.2. Block Diagram ................................................................................................................................................. 16 2.6. Debugger Interface.................................................................................................................................................... 17 2.6.1. Specifications................................................................................................................................................... 17 2.6.2. Block Diagram ................................................................................................................................................. 17 2.7. Debug Ether Interface (EtherMAC) ............................................................................................................................ 18 2.7.1. Specifications................................................................................................................................................... 18 2.7.2. Block Diagram ................................................................................................................................................. 18 2.8. Audio Codec Interfaces (SSI0, SSI1, SSI2, and SSI9) ................................................................................................... 19 2.8.1. Specifications................................................................................................................................................... 19 2.8.2. Block Diagram ................................................................................................................................................. 19 2.9. SD Card Host Interface (SDHI1) ................................................................................................................................ 20 2.9.1. Specifications................................................................................................................................................... 20 2.9.2. Block Diagram ................................................................................................................................................. 20 2.10. eMMC Memory Interface (MMC) ...............................................................................................................................21 Specifications................................................................................................................................................... 21 2.10.1. 2.10.2. Block Diagram ................................................................................................................................................. 21 2.11. USB2.0 Interface ...................................................................................................................................................... 22 2.11.1. Specifications....................................................................................................................................................22 2.11.2. Block Diagram ..................................................................................................................................................22 2.12. Debug Serial Interface (SCIF2) .................................................................................................................................. 23 2.12.1. Specifications................................................................................................................................................... 23 2.12.2. Block Diagram ..................................................................................................................................................23 2.13. Reset ....................................................................................................................................................................... 24 YR8A77450S000BE October 24, 2015 Page II RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.13.1. 2.13.2. Specifications................................................................................................................................................... 24 Block Diagram ..................................................................................................................................................24 2.14. I2C Interface .............................................................................................................................................................25 2.14.1. Specifications................................................................................................................................................... 25 2.14.2. List of Slave Addresses .....................................................................................................................................25 2.14.3. Block Diagram ................................................................................................................................................. 26 2.15. GPIO Interface (Software Switch, Tact Switch) ............................................................................................................ 27 2.15.1. Specifications...................................................................................................................................................27 2.15.2. Block Diagram .................................................................................................................................................27 2.16. External Interrupts ....................................................................................................................................................28 2.16.1. Specifications...................................................................................................................................................28 2.16.2. Block Diagram .................................................................................................................................................28 2.17. Clock ....................................................................................................................................................................... 29 2.17.1. Clocks Supplied to the RZ/G1E ......................................................................................................................... 29 2.17.2. Clocks Supplied to Devices Other than RZ/G1E .................................................................................................. 29 2.18. Power Supply ...........................................................................................................................................................30 2.18.1. Specifications...................................................................................................................................................30 2.18.2. Block Diagram .................................................................................................................................................31 2.18.3. Power Supply Sequencing ................................................................................................................................. 32 2.19. EXIO Connectors (JP1, JP2) .................................................................................................................................... .33 Specifications................................................................................................................................................... 3 2.19.1. 3. Outline Diagrams of YR8A77450S000BE Board ...................................................................... 34 3.1. External Dimensions and Hole Locations of YR8A77450S000BE Board ........................................................................ 34 3.2. Connector Locations on YR8A77450S000BE Board (Component Surface)................................................................... 35 3.3. Connector Locations on YR8A77450S000BE Board (Solder Surface) .......................................................................... 36 YR8A77450S000BE October 24, 2015 Page III RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual Tables Table 1.1.1 Functions of YR8A77450S000BE Board (1) .......................................................................................................... 2 Table 1.1.2 Functions of YR8A77450S000BE Board (2) .......................................................................................................... 3 Table 2.1.1 Initial Values of RZ/G1E Mode Setting Pins on YR8A77450S000BE Board .............................................................. 8 Table 2.1.2 Pin Multiplexing of Mode Setting Pins of RZ/G1E.................................................................................................. 9 Table 2.2.1 DDR3-SDRAM Specifications............................................................................................................................ 11 Table 2.2.2 DDR3-SDRAM Signal Correlation...................................................................................................................... 11 Table 2.3.1 SPI-FLASH Interface Specifications.................................................................................................................... 13 Table 2.5.1 Video Output Interface Specifications .................................................................................................................. 15 Table 2.6.1 Specifications of DBG and DBG2 ....................................................................................................................... 17 Table 2.7.1 Debug Ether Interface Specifications ................................................................................................................... 18 Table 2.8.1 SSI Codec Specifications.................................................................................................................................... 19 Table 2.8.2 SSI Connections on the YR8A77450S000BE board .............................................................................................. 19 Table 2.10.1 SD Card Host Interface (SDHI1) Specifications .................................................................................................. 20 Table 2.11.1 eMMC Memory (MMC) Interface Specifications ................................................................................................ 21 Table 2.12.1 USB2.0 Specifications...................................................................................................................................... 22 Table 2.13.1 Debug Serial Interface Specifications ................................................................................................................. 23 Table 2.14.1 RESET Specification........................................................................................................................................ 24 Table 2.15.1 I2C Interface Specifications............................................................................................................................... 25 Table 2.15.2 List of I2C Slave Addresses ............................................................................................................................... 25 Table 2.16.1 List of Software Switches (General-Purpose Switches) ........................................................................................ 27 Table 2.16.2 List of Tactile Switches (General-Purpose Switches) ........................................................................................... 27 Table 2.17.1 External Interrupt Specifications........................................................................................................................ 28 Table 2.18.1 List of Clocks and Crystals for RZ/G1E ............................................................................................................. 29 Table 2.18.2 List of Clocks and Crystals Other than for RZ/G1E ............................................................................................. 29 Table 2.19.1 List of Switching Controllers and Regulators on the YR8A77450S000BE Board .................................................... 30 Table 2.20.1 EXIO Connector Specification .......................................................................................................................... 33 Table 2.20.2 List of EXIO Connector (JP1) Pins .................................................................................................................... 33 Table 2.20.3 List of EXIO Connector (JP2) Pins .................................................................................................................... 33 YR8A77450S000BE October 24, 2015 Page IV RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual Figures Figure 1.3.1 Block Diagram of YR8A77450S000BE Board ...................................................................................................... 5 Figure 2.1.1 Peripheral Circuit for Mode Pins on YR8A77450S000BE Board........................................................................... 10 Figure 2.2.1 Block Diagram of DDR3-SDRAM Interface ....................................................................................................... 12 Figure 2.3.1 Block Diagram of SPI-Flash Interface ................................................................................................................ 13 Figure 2.4.1 Block Diagram of Video Input Interface (VIN0) .................................................................................................. 14 Figure 2.5.1 Block Diagram of Video Output Interface ........................................................................................................... 16 Figure 2.6.1 Block Diagram of JTAG Interface (DBG) ........................................................................................................... 17 Figure 2.7.1 Block Diagram of Debug Ether Interface ............................................................................................................ 18 Figure 2.8.1 Block Diagram of Audio Codec ......................................................................................................................... 19 Figure 2.9.1 Block Diagram of SD Card Host Interface (SDHI0) ...................... エラー! ブックマークが定義されていません。 Figure 2.10.1 Block Diagram of SD Card Host Interface (SDHI1) ........................................................................................... 20 Figure 2.11.1 Block Diagram of eMMC Memory Interface ..................................................................................................... 21 Figure 2.12.1 Block Diagram of USB2.0............................................................................................................................... 22 Figure 2.13.1 Block Diagram of Debug Serial Interface .......................................................................................................... 23 Figure 2.14.1 Block Diagram of Reset Circuit ....................................................................................................................... 24 Figure 2.15.1 Block Diagram of I2C Interface ........................................................................................................................ 26 Figure 2.16.1 Block Diagram of GPIO Interface (Software Switch, Tactile Switches) ................................................................ 27 Figure 2.17.1 Block Diagram of External Interrupts ............................................................................................................... 28 Figure 2.19.1 Block Diagram of Power Supply Circuit ........................................................................................................... 31 Figure 2.19.2 Power-On Sequence........................................................................................................................................ 32 Figure 3.1.1 External Dimensions and Hole Locations of the YR8A77450S000BE Board (Top View) ......................................... 34 Figure 3.2.1 Connector Locations of the YR8A77450S000BE Board (Component Surface) (Top View) ...................................... 35 Figure 3.3.1 Connector Locations of the YR8A77450S000BE Board (Solder Surface) (Top View) ............................................. 36 YR8A77450S000BE October 24, 2015 Page V RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 1. Overview The RZ/G1E is an SOC featuring the basic functionality required for the next generation of display audio systems. Its newly employed bus configuration maximizes the system performance, space saving, and cost efficiency. The YR8A77450S000BE board is RZ/G1E-specific evaluation board that can be used to evaluate systems using the RZ/G1E and to develop operating systems, device drivers, and applications. Using the YR8A77450S000BE board allows the developers to efficiently conduct required tasks such as evaluation of the RZ/G1E system performance and thus greatly to reduce the turn-around time in their product development. 1.1. Features 1.1.1.                List of RZ/G1E Functions Two 1.0-GHz ARM Cortex™-A7 MPCore™ cores (dual core: option) Memory controller for DDR3-SDRAM (DDR3-1333) with 32 bits × 1 channel Three-dimensional graphics engines Video processing unit Sound processing unit SD card host interface (3 channels), MMCIF (1 channel) USB2.0 host (1 channel), USB2.0 host/function (1 channel) DU (digtal RGB 2 channels), VIN (2 channels) VSP1, VCP3, FDP1, 2D-DMAC SCU, SSIU (10 channels), ADG CAN (2 channels), Ethernet MAC WDT, TPU, CMT1, TMU, CPG, INTC, DMAC, LBSC I2C (5 channels), IIC (2 channels), SCIF (6 channels), SCIFA (6 channels), SCIFB (3 channels), MSIOF (3 channels), QSPI, HSCIF (3 channels), PWM (7 channels) GPIO, etc Power supply voltages (typ.) 3.3 V, 1.8 V, 1.5 V/1.35 V, 1.0 V YR8A77450S000BE October 24, 2015 Page 1 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 1.1.2. List of YR8A77450S000BE Board Functions Table 1.1.1 Functions of YR8A77450S000BE Board (1) YR8A77450S000BE Board Function The SILK Board Function List. Page 1List. of 2Page 1 of 2 Board Function Module RAM DDR3 LBSC Description Single Channel DDR3-1333 1GByte, 32bit data width. 4Gbit(16bit data width) x2 devices.(MT41K256M16 , refer to M2 circuit) SDRAM Backup feature: Not supported. No device. ROM LBSC QSPI Not supported. SPI Flash: Spansion S25FL512SAGMFIG11 (512Mbit=64MB) x1 device. Spansion S25FL032P0XMFI011 (32Mbit=4MB) x1 device. Debug I/F DBG DBG2 GPIO SCIFA0 SCIFA1 SCIFA2 Connector: HTST-110-01-S-DV (20pin) through SD card slot for SDHI1 Mechanical switch x3 elements 'TactSW' for Android Purpose. Not supported. Not supported. Debug Serial x1 (TX, RX) USB to UART Bridge SILICON LABS CP2102-GM x1 (Bridge spec: max 1Mbps) Connector: USB Type microAB LAN EtherMAC USB2.0 I/F USB2.0 ch0 USB2.0 ch1 RTC I/F I2C1 SDHI SDHI0 Debug Ether(100Mbps) RMII PHY: MICREL KSZ8041RNLI Connector: RJ45: TDK TLA-6T718A (Refer to M1 circuit) Not supported. USB2.0 Host or Function Connector: Type A. USB2.0 Host Connector: Type A Not supported. WiFi module(LBEE6U4ZQC-TEMP) Interface voltage: Either 3.3V or 1.8V. SDHI1 SDHI2 Connector: microSD slot.(DM3AT-SF-PEJM5) Interface voltage: 3.3V or 1.8V Not supported. MMC I/F MMC1 eMMC: micron MTFC8GLWDQ-3M AIT Z x1 device. 8GByte MSIOF MSIOF EXIO connector HSCIF HSCIF0 HSCIF0 for WiFi Module YR8A77450S000BE October 24, 2015 Page 2 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual Table 1.1.2 Functions of YR8A77450S000BE Board (2) YR8A77450S000BE Board Function The SILK Board Function List. Page 2List. of 2Page 2 of 2 Video Output DU0 Either [A] or [B] [A] HDMI output HDMI Transmitter. Analog Devices ADV7511WBSWZ(U23) Connector: HDMI standard type A : Tyco 1747981-1 [B] LCD output. Connector: XF2M-4015-1A DU1 Analog RGB output DU output format: RGB666.(RGB888 is not supported by the ALT board) Video DAC: Analog Devices ADV7123 (DU1_DOTCLKOUT is connected) Connector: DSUB15pin Video Input VIN0 YCbCr 8bit. BT656 Video Decoder: Analog Devices ADV7180WBCP32Z, Connector: RCA Audio SSI0, SSI1, SSI2, SSI9 SSI3, SSI4 2 I C I/F I2C0 I2C1 I2C2 I2C3 I2C4 I2C5 I2C6 I2C7 WiFi Either [A] or [B] [A] Audio Output(SSI0) or Input(SSI1) Codec: AKM AK4643EN x1 Connector: mini jack x1 for stereo line output Connector: mini jack x1 for stereo line/MIC input [B] Audio Multi-Channel Output.(SSI0, SSI1, SSI2, SSI9) HDMI Transmitter ADV7511WBSWZ Connector: HDMI standard type A SSI　for Wi-Fi module Interface voltage: 3.3V Digital LCD panel Interface voltage: 3.3V This interface is connected to the following devices. HDMI Transmitter ADV7511, Video decoder ADV7180, Audio codes AK4643, I2C EEPROM Not supported. Not supported. Interface voltage: 3.3V Not supported. Not supported. Interface voltage: 1.8V PowerIC DA9063 SDHI0(SDR104) LBEE6U4ZQC-TEMP SSI3,4 HSCIF0 EXIO Connector various modules Power IC － Dialog Semiconductor DA9063 Power Supply － DC5.0V input Board size － 140mm x 120mm YR8A77450S000BE October 24, 2015 EXIO Connector 1: Box Wafer 10P 2.0mm EXIO Connector 2: Box Wafer 6P 2.0mm Page 3 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 1.2. Usage Notes 1.2.1. YR8A77450S000BE Board Specifications  Take particular care to ensure the correct configurations of the jumpers and switches mounted on the YR8A77450S000BE board. Incorrect configurations may damage on-board devices.  For the YR8A77450S000BE board, be sure to use the power supply that comes with it. Applying a voltage greater than 5 V may damage devices on the YR8A77450S000BE board.  There are sequences for turning on and off the power supply to the RZ/G1E. For the YR8A77450S000BE board, be sure to obey the notes below. (1) When power is turned on Press SW11 once to turn the YR8A77450S000BE board on (2) When power is shut off Long press SW11 to turn the YR8A77450S000BE board off. YR8A77450S000BE October 24, 2015 Page 4 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 1.3. Board Configuration The YR8A77450S000BE board is composed of a single board whose size is 140 mm × 120 mm. Figure 1.3.1 shows a block diagram of the YR8A77450S000BE board. 1.3.1. Block Diagram of YR8A77450S000BE Board RZ/G1E R-CarE2 DDR3(L)-SDRAM 1GB (2-devices) (MT41K256M16) 32bit DDR3-I/F LBSC ExA[20..25] / QSPI USB HOST Type-A Connector USB2.0 USB2.0-CH1 I/F (Host Only) USB HOST Type-A Connector USB2.0 USB2.0-CH0 I/F (Host / Function) QSPI SPI Flash Memoty 64MB,4MB SDHI0 (SDR104) SSI3,4 HSCIF0 WiFi Module LBEE6U4ZQC -TEMP RJ45 CN RMII PHY KSZ8041RNLI EtherMAC / VIN0 GP1_24(RESET) IRQ8 RGB888 SD Card Slot CN 3.3V SDHI1 (SDR50,CRPM) /DBG2 HDMI Transmitter ADV7511W DU0 HDMI OUT Type A I2C1(3.3V) GP2_31(IRQ) B G R 6 66 LDO DA9063(LDOx) CPx for MSIOF0 LCD Connector (for LCD-KIT-B01) GP4-29 MMC(3.3V only) /SDHI2(SDR50,CRPM) DU1 / MSIOF0 LDO DA9063(LDOx) IO S S GP4-31 DBG CN VIN0 JTAG RGB666 Video DAC ADV7123 0 1, ,2 ,9 1.8V/3.3V eMMC(8GB) MTFC8GLGQD-AIT Z DBG YCbCr[7:0] Video Decoder ADV7180W Analog RGB Out DSUB15 Composite IN RCA TX,RX USB to UART CP2102 USB microAB CN SCIF2(debug serial) /DU1 HSCIF0 (TX,RX,RTS,CTS) I2C1(3.3V) SSIO,1,2,8,9 /EtherMAC_B /MSIOF1_B SSI0,1 Audio DAC/ADC AK4643 I2C1(3.3V) I2C1(3.3V) I2C Buffer LTC4313 DA9063 Mini-Jack Line Out Mini-Jack Line/MIC in I2C1(3.3V-LVTTL) /DU1 I2C7(1.8V-I2C) EXIO Connector JP1 GPIO I2C3 MSIOF1 From AK4643-MCKO AUDIO_CLKC GPIO /TS GPIO /EtherMAC_B EXIO Connector JP2 GP5_12,GP5_11,GP5_10 Tac SW 3bit Figure 1.3.1 Block Diagram of YR8A77450S000BE Board YR8A77450S000BE October 24, 2015 Page 5 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 1.3.2. Address Map of YR8A77450S000BE Board For the DDR3L momory space, see the section DDR3-SDRAM Interface. For the other space, see the RZ/G Series User's Manual: Hardware. 2. YR8A77450S000BE Interface Module Specifications 2.1. MODE Setting 2.1.1. Specifications The operating mode of the RZ/G1E is set by a power-on reset. For details on the operating mode, see the documents related to the RZ/G1E operating mode specifications. 2.1.1.1. MD0 Pin  Selection of Free-Running Mode or Step-Up Mode This pin selects the free-running mode or step-up mode. MD0 Free-Running Mode or Step-Up Mode 0 Free-running mode 1 Step-up mode 2.1.1.2. MD[3:1] Pins  Selection of Boot Device These pins select the boot device. MD3 MD2 MD1 Selection of Boot Device 0 0 0 Boot from area 0 (boot from external mask ROM) 0 1 0 QSPI (48.75 MHz/16-Kbyte transfer) 0 0 1 Reserved 0 1 1 Reserved 1 0 0 QSPI (39 MHz/16-Kbyte transfer) 1 0 1 QSPI (78 MHz/16-Kbyte transfer) 1 1 0 QSPI (39 MHz/4-Kbyte transfer) 1 1 1 Reserved 2.1.1.3. MD4 Pin  Selection of CS0 Space Size This pin selects whether the area 0 space (CS0) is used as a normal space (64 Mbytes) or an expanded space (128 Mbytes). MD4 Area Division 0 Area 0: 64 Mbytes 1 Area 0: 128 Mbytes 2.1.1.4. MD5 Pin  Reserved Do not change the initial setting at shipment (MD5 = 1). 2.1.1.5. MD[7:6] Pins  Selection of Master Boot Processor These pins select the master boot processor. MD7 MD6 Selection of Master Boot Processor 0 0 Setting prohibited 0 1 CA7 boot 1 0 SH boot (32 bits) 1 1 Setting prohibited 2.1.1.6. MD8 Pin  Selection of Area 0 Space Data Bus Width This pin sets the data bus width of the area 0 space (CS0) to 8 bits or 16 bits. Select the data bus width of the boot device connected to the LBSC. MD8 EXBUS Area 0 Data Bus Width 0 8-bit bus 1 16-bit bus YR8A77450S000BE October 24, 2015 Page 6 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.1.1.7. MD9 Pin  Selection of Crystal Resonator or Crystal Oscillator This pin selects either a crystal resonator or a crystal oscillator to be connected to the EXTAL/XTAL pins. A crystal oscillator (X5: 20 MHz) is mounted on the YR8A77450S000BE board by default. MD9 EXTAL/XTAL Pin Setting 0 An external clock is input to the EXTAL pin. 1 A crystal resonator is connected to the EXTAL and XTAL pins. 2.1.1.8. MD12  Reserved Do not change the initial setting at shipment (MD12 = 0). 2.1.1.9. MD21, MD20, MD11, MD10, and MDT[1:0] Pins  Switching of JTAG, SDHI1, and SDHI2 These pins select the debugging function through the JTAG connector (CN1) or the SD card slot for the SDHI1 (CN4). The debugging through the SDHI1 or SDHI2 is possible by the combination of MD pin settings in the RZ/G1E specifications. MD10 MD[21:20] MD11 MDT[1:0] JTAG SDHI1 SDHI2 0 00 -Boundary SCAN Normal function Normal function 0 10 0 -Coresight* Normal function Normal function Coresight* 0 10 1 00 Audio DSP Normal function Coresight* 0 10 1 01 SH-X4 Normal function 0 10 1 10 Coresight* Normal function Audio DSP 0 10 1 11 Coresight* Normal function SH-X4 0 11 0 -SH-X4 Normal function Normal function 0 11 1 00 SH-X4 Coresight (*1) Normal function 1 01 0 -Coresight* Normal function Normal function 1 01 1 01 Coresight* SH-X4 Normal function Note: * “Coresight” is an abbreviation of “Coresight debug port”. 2.1.1.10. MD[14:13] Pins  Frequency Mode Setting These pins select the frequency mode. A crystal oscillator (X5: 20 MHz) is mounted on the YR8A77450S000BE board. Do not change the initial setting at shipment (MD14 = 0, MD13 = 1). EXTAL EXTAL PLL3 DDR3-1333 MD14 MD13 PLL1 (CPGM main) PLL0 (CPGMC) Frequency Divider MD19 = 1 × 208 × 88 x200 0 0 15 MHz × 1/1 VCO = 3120 MHz VCO = 3000MHz VCO = 1320 MHz × 156 × 66 x150 0 1 20 MHz × 1/1 VCO = 3120 MHz VCO = 3000MHz VCO = 1320 MHz × 240 x230 × 102 1 0 26 MHz × 1/2 VCO = 3120 MHz VCO = 2990MHz VCO = 1326 MHz × 208 x200 × 88 1 1 30 MHz × 1/2 VCO = 3120 MHz VCO = 3000MHz VCO = 1320 MHz 2.1.1.11. MD18 Pin  Reserved Do not change the initial setting at shipment (MD18 = 0). 2.1.1.12. MD19 Pin  Selection of DDR3-SDRAM Bus Clock This pin selects the frequency of the DDR3-SDRAM bus clock. Do not change the initial setting at shipment (MD19 = 1). MD19 0 1 Switching of DDR Clock Setting prohibited. DDR3-1333 mode YR8A77450S000BE October 24, 2015 Page 7 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.1.2. Initial Values of Mode Setting Pins on YR8A77450S000BE Board Table 2.1.1 Initial Values of RZ/G1E Mode Setting Pins on YR8A77450S000BE Board MD Pins MD0 MD[3:1] MD4 MD5 MD[7:6] MD8 MD9 MD12 MD10, MD[21:20], MD11, MDT[1:0] Initial Value 0 101 0 1 01 0 0 0 0,00,0,00 MD[14:13] MD18 MD19 01 0 1 YR8A77450S000BE October 24, 2015 Initial Function Free-running mode Boot from the QSPI (78 MHz/16-Kbyte transfer) Area 0 space size (64 Mbytes)  Cortex-A7 boot Area 0 space data bus width (16 bits) Crystal oscillator is used.  JTAG (CN1) = Boundary SCAN SDHI1 and SDHI2 = Normal function Input frequency = 20 MHz  DDR3-1333 mode Page 8 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.1.3. Multiplexing and Method of Setting for Mode Setting Pins The following table covers the pin functions that are multiplexed with the mode pins of the RZ/G1E, and how the individual mode pins are set. For the mode pins that are used with fixed values, resistors are used to set them to their fixed values according to the initial settings in Table 2.1.1, Initial Values of RZ/G1E Mode Setting Pins on YR8A77450S000BE Board. Such mode pins are described as "Fixed by a resistor" in the Setting Method column in the table below. Table 2.1.2 Pin Multiplexing of Mode Setting Pins of RZ/G1E Pin Name Pin Function MD0 A1 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD18 MD19 MD20 MD21 MDT0 MDT1 A4 A3 A0 A7 A9 A13 A15 BS# GP1_20 DU0_DSIP DU0_HSYNC DU0_VSYNC GP2_31 RD# A19 WE0# WE1# GP1_25 A18 A2 YR8A77450S000BE October 24, 2015 Strapping Options 0: Free-running mode 1: Step-up mode Selects boot device How to Set Default Setting Fixed by a resistor ON (0) Fixed by a resistor Selects area-0 size Selects boot processor Fixed by a resistor Fixed by a resistor Fixed by a resistor Selects EXBUS data bus width EXTAL or EXTAL/XTAL Debugging mode Fixed by a resistor Fixed by a resistor Fixed by a resistor Selects frequency mode Fixed by a resistor Fixed by a resistor OFF (1) ON (0) OFF (1) ON (0) OFF (1) OFF (1) ON (0) Pulled-down (0) Pulled-down (0) ON (0) ON (0) ON (0) Pulled-up (1) ON (0) ON (0) OFF (1) ON (0) OFF (1) ON (0) ON (0) DDR clock mode Debugging mode Debugging mode Set by SW7 Fixed by a resistor Set by SW7 Fixed by a resistor Page 9 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.1.4. Block Diagram of Peripheral Circuit for Mode Pins On the YR8A77450S000BE board, pull-up (100 kΩ) and pull-down (10 kΩ) resistors are used to implement the settings of the mode pins that are largely used with fixed values. When changes to the settings of mode pins are likely, this can be implemented by switches which, through resistive voltage division, select the low level when turned on and the high level when turned off. When the RZ/G1E is released from the power-on reset (when the PRESET# signal of the RZ/G1E is changed from low to high), the mode value set by the switch or resistive voltage division is input to the RZ/G1E. D3.3V Not mounted RZ/G1E R-CarE2 100k* 10k MD18/A19 D3.3V D3.3V 100k MD13/GP2_31 100k D3.3V MD6/A13 100k D3.3V MD5/A9 MDT1/A2 MDT0/A18 MD20/WE1# MD14/RD# MD12/DU0_VSYNC MD11/DU0_HSYNC MD10/DU0_DISP MD9/GP1_20 MD8/BS# MD7/A15 MD4/A7 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 100k MD3/A0 10k* D3.3V Not mounted D3.3V 100k* 10k 100k Not mounted 2 MD2/A3 MD21/GP1_25 MD19/WE0# 10k SW7 D3.3V 100k 10k* Not mounted MD1/A4 D3.3V Not mounted 100k* 10k MD0/A1 Figure 2.1.1 Peripheral Circuit for Mode Pins on YR8A77450S000BE Board YR8A77450S000BE October 24, 2015 Page 10 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual DDR3-SDRAM Interface 2.2.1. Specifications The YR8A77450S000BE board incorporates two 4-Gbit DDR3-SDRAMs (16-bit bus width) and operates at a maximum speed of DDR3-1333. The DDR3-SDRAMs are allocated to the address space from H'01_0000 0000 to H'01_FFFF FFFF in the RZ/G1E. The address ranges from H'00_4000 0000 to H'00_BFFF FFFF can be accessed by default as a mirror area of H'01_0000 0000 to H'01_7FFF FFFF. Table 2.2.1 DDR3-SDRAM Specifications Interface Product name Power supply voltage Capacity Bus width Memory bus frequency (RZ/G1E spec.) 2.2.2. DDR3-SDRAM MT41K256M16HA-125 AIT:E (DDR3-1600, ×16 bits, 4 Gbits) × 2 pcs 1.50 V Total: 1 Gbyte, H'01_0000 0000 to H'01_3FFF FFFF 32-bit data bus DDR3-1333 max. Signal Correlation Table 2.2.2 DDR3-SDRAM Signal Correlation RZ/G1E M0DQ[31:16] M0DQ[15:0] M0A[15:0] M0BA[2:0] M0CK1, M0CK1# M0CK0, M0CK0# M0CKE1 M0CKE0 M0CS1# M0CS0# M0WE# M0RAS# M0CAS# M0DQS3, M0DQS3# M0DQS2, M0DQS2# M0DQS1, M0DQS1# M0DQS0, M0DQS0# M0DM3, M0DM2 M0DM1, M0DM0 M0ODT1 M0ODT0 M0RESET# DDR3-SDRAM (M1) D[31:16] DQU[7:0], DQL[7:0]  A[15:0] BA[2:0]  CK, CK#  CKE  CS# WE# RAS# CAS# DQSU, DQSU# DQSL, DQSL#   DMU, DML   ODT RESET# DDR3-SDRAM (M2) D[15:0]  DQU[7:0], DQL[7:0] ← ← − ← − ← − ← ← ← ←   DQSU, DQSU# DQSL, DQSL#  DMU, DML  ← ← Notes Not connected Not connected Not connected Not connected Note: Half voltage of VDDQ_M0 is supplied to the M0VREFDQ[1:0] pins of the RZ/G1E. YR8A77450S000BE October 24, 2015 Page 11 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.2.3. Block Diagram The following figure shows a block diagram of the DDR3-SDRAM interface. RZ/G1E R-CarE2 :Differential termination D1.5V :Vtt termination M0DQ[31:0] M1 DDR3-SDRAM M0BA[2:0] M0A[15:0] BA[2:0] A[15:0] M0CS0# M0CKE0 M0ODT0 M0CK0 M0CK0# M0RAS# M0CAS# M0WE# M0RESET# CS# CKE ODT CK CK# RAS# BA[2:0] CAS# WE# A[15:0] RESET# CS# CKE ODT CK CK# DQS RAS# DQS# CAS# DMWE# ZQRESET# 10 M0DQS[3:2] M0DQS[3:2]# M0DM[3:2] 15 15 VDDQ D1.5V 240 M0CS1# M0CKE1 M0ODT1 M0CK1 M0CK1# Not Connected D1.5V 0.1uF M0DQ[31:24] DQU[7:0] VREFCA VREFDQ 0.1uF 20k VREFCA1 VREFDQ1 D1.5V M0DQ[15:8] M0DQ[7:0] VREFCA VREFDQ VREFCA0 0.1uF 20k VREFCA0 VREFDQ0 0.1uF 20k M2 DDR3-SDRAM D1.5V D1.5V 0.1uF 4.7k 20k VREFDQ0 0.1uF M0VREFDQ0 20k VREFDQ1 M0DQ[23:16] DQL[7:0] M0BKPRST# M0VREFDQ1 20k VSS DQL[7:0] DQS DQS# DM ZQ 0.1uF VDD DQU[7:0] M0DQS[1:0] M0DQS[1:0]# M0DM[1:0] 20k VREFCA1 240 15 15 0.1uF D1.5V M0VREFDQ1 D1.5V 20k D1.5V M0VREFDQ0 0.1uF M0VREFCA 20k M0VREFDQ1 0.1uF 20k M0VREFDQ0 M0ZQ 0.1uF 20k 0.1uF 20k 240 Figure 2.2.1 Block Diagram of DDR3-SDRAM Interface YR8A77450S000BE October 24, 2015 Page 12 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.3. SPI-FLASH Interface (QSPI) 2.3.1. Specifications The YR8A77450S000BE board incorporates 512-Mbit and 32-Mbit SPI flash memory devices manufactured by Spansion. These SPI flash memory devices are connected to the QSPI of the RZ/G1E via switches SW9. When the 512-Mbit SPI flash memory (U6) is to be accessed, set SW9 to pin 1 side, and when the 32-Mbit SPI flash memory (U7) is to be accessed, set SW9 to the pin 3 side. Since the loader and mini-monitor are stored in the lower-order address space of the SPI flash memory (U7, 32 Mbits), do not modify the contents of this area. The contents of the SPI flash memory (U6, 512 Mbits) can be modified as required. Table 2.3.1 SPI-FLASH Interface Specifications QSPI controller RZ/G1E’s on-chip QSPI module (1) U6: Spansion S25FL512SAGMFIG11 (512 Mbits) (2) U7: Spansion S25FL032P0XMFI011 (32 Mbits) 78-MHz operation (max.) SPI flash memory Clock rate of RZ/G1E’s QSPI 2.3.2. Block Diagram A block diagram of the SPI flash memory interface is shown below. R-CarE2 RZ/G1E SPI-FLASH S25FL032P0XMFI011 32Mbit QSPI_CLK A20 / SPCLK QSPI_SI/IO0 A21 / MOSI/IO0 QSPI_SO/IO1 A22 / MISO/IO1 QSPI_IO2 A23 / IO2 QSPI_IO3 A24/ IO3 SCK VCC SI/IO0 VSS D3.3V SO/IO1 W#/ACC/IO2 HOLD#/IO3 CS# 10k D3.3V SPI-FLASH QSPI1_CS# S25FL512SAGMFIG11 512Mbit QSPI_CLK QSPI_SI/IO0 QSPI_SO/IO1 QSPI_IO2 QSPI_IO3 SW9 A25 / SSL QSPI0_CS# CLK VCC SI/IO0 VSS D3.3V SO/IO1 WP#/IO2 HOLD#/IO3 CS# 10k D3.3V PRESET#(1.8V) Power On Reset Level Shift 3.3V to 1.8V Level Shift 1.8V to 3.3V PRESET#(3.3V) RESET# Figure 2.3.1 Block Diagram of SPI-Flash Interface YR8A77450S000BE October 24, 2015 Page 13 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.4. Video Input Interface (VIN0) 2.4.1. Specifications The RZ/G1E has two video input interfaces (VIN0 and VIN1). For details of these functions, see the section on video input in the RZ/G Series User’s Manual: Hardware. On the YR8A77450S000BE board, ADV7180WBCP32Z (U21) manufactured by Analog Devices is connected to VIN0 of the RZ/G1E and used as a composite video decoder. The ADV7180WBCP32Z (U21) handles inputs in the ITU-R BT.656 8-bit (YCbCr) format. The registers of ADV7180 can be set via an I2C interface (channel 1) of the RZ/G1E. The block diagram of the VIN0 is shown below. 2.4.2. Block Diagram R-CarE2 RZ/G1E Video Decoder ADV7180 AVB_RX_CLK / VIN0_CLK AVB_RXD6 / VIN0_DATA7 AVB_RXD5 / VIN0_DATA6 AVB_RXD4 / VIN0_DATA5 AVB_RXD3 / VIN0_DATA4 AVB_RXD2 / VIN0_DATA3 AVB_RXD1 / VIN0_DATA2 AVB_RXD0 / VIN0_DATA1 AVB_RX_DV / VIN0_DATA0 I2C(ch1) LLC AIN1 P[7:0] AIN2 CN10 RCA 8 AIN3 N.C. /INTRQ VS/FIELD HS X8 28.63636MHz XTAL I2C Buffer TCA4311ADGKR I2C ALSB PRESET# Power On Reset Level Shift 3.3V to 1.8V Level Shift 1.8V to 3.3V I2C address(ALSB=0) Write: 0x40 Read: 0x41 RESET# Figure 2.4.1 Block Diagram of Video Input Interface (VIN0) YR8A77450S000BE October 24, 2015 Page 14 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.5. Video Output Interface 2.5.1. Specifications The RZ/G1E incorporates two display units (DU0 and DU1) with the digital RGB interface. The YR8A77450S000BE board incorporates an HDMI transmitter (ADV7511), an Digital LCD connector, and a video D/A converter (ADV7123). The respective devices convert the digital RGB signals (RGB888) from DU0 to HDMI signals and digital RGB signals (RGB666) from DU1to analog RGB signals. The internal registers of the HDMI transmitter (ADV7511) are accessible via an I2C interface (channel 1) of the RZ/G1E. The INT output is connected to the GP2_31 pin of the RZ/G1E. On the YR8A77450S000BE board, the external dot clock inputs are connected as follows: DU0_DOTCLKIN is connected to X2 (148.50 MHz) and DU1_DOTCLKIN is connected to X3 (74.25 MHz, socket-mounted). Alternatively, a clock signal derived by frequency-dividing the RZ/G1E's internal clock can be selected. For details, see the display unit specifications in the RZ/G Series User’s Manual: Hardware. Table 2.5.1 Video Output Interface Specifications Display controller DU0 (digital RGB, RGB888) DU1 (digital RGB, RGB666) YR8A77450S000BE October 24, 2015 RZ/G1E’s on-chip display unit (DU) [HDMI Output] HDMI transmitter converts digital RGB signals to HDMI signals. U15: ADV7511WBSWZ by Analog Devices I2C slave address: 0x72 for write, 0x73 for read. Interrupt: GP5_23 Connector CN6: HMNF-195N-4BH90 (HDMI type A, standard, 19-pin) [LCD Output] Touch pannel connector, for panel with part name “LCD-KIT-B01” Connector CN8: FPC-VI-FPC-05L [Analog RGB Output] Video D/A converter converts digital RGB signals to analog RGB signals. U18: ADV7123KSTZ140 by Analog Devices Connector CN9: D02-M15SAG-23L9E by JAE Page 15 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.5.2. Block Diagram A block diagram of the video output interface on the YR8A77450S000BE board is shown below. RZ/G1E R-CarE2 HDMI Transmitter ADV7511 I2C Buffer LTC4313-1 I2C1 DU0 I2C RGB888 DU0_DR[7:0] DU0_DG[7:0] DU0_DB[7:0] 24 DU0_HSYNC DU0_VSYNC DU0_DISP 3 HSYNC VSYNC DE Interrupt X2 148.50MHz DU0_DOTCLKIN X3 74.25MHz DU1_DOTCLKIN CN6 HDMI out PD INT(OD) 18 HDMI signal I2C address Write: 0x72 Read: 0x73 CLK DU0_DOTCLKOUT0 GP2_31 D[23:0] TX0+, TX0TX1+, TX1TX2+, TX2TX3+, TX3TXC+, TXC- LCD Connector for LCD-KIT-B01 RGB666 R[7:2] G[7:2] B[7:2] I2C0 I2C HSYNC VSYNC DE LCDCLK RESET IRQ3 INT Video D/A Converter ADV7123 DU1 DU1_DR[7:2] DU1_DG[7:2] DU1_DB[7:2] RGB666 18 R[9:4] G[9:4] B[9:4] CLOCK DU1_DOTCLKOUT0 PSAVE# DU1_HSYNC DU1_VSYNC IOR IOG IOB BLANK# DU1_DISP 2 Analog R,G,B CN9 Analog RGB out R[3:0] G[3:0] 12 B[3:0] 3.3V to 5.5V 74LV1GT08A Level Shift HSYNC# VSYNC# 2 PRESETOUT# Figure 2.5.1 Block Diagram of Video Output Interface YR8A77450S000BE October 24, 2015 Page 16 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.6. Debugger Interface 2.6.1. Specifications The YR8A77450S000BE board incorporates two debugger interfaces; one is a 20-pin connector (DBG) for connection to the JTAG emulator. The RZ/G1E supports the DBG2 and DBG3 interface as a debugger interface, but the YR8A77450S000BE board does not include this function. For details on the debugger interface, see the RZ/G Series User’s Manual: Hardware. Table 2.6.1 Specifications of DBG and DBG2 DBG interface (20-pin) 2.6.2. CN1: HTST-110-01-S-V by Samtec Block Diagram D1.8V Not mounted R-CarE2 CN1 ARM JTAG Connector (20pin) TCK TRST# TDO TDI TMS Not mounted D1.8V Pin1 D1.8V Pin2 Pin19 ASEBRK PRESET# D1.8V SW2 Power On Reset Figure 2.6.1 Block Diagram of JTAG Interface (DBG) YR8A77450S000BE October 24, 2015 Page 17 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.7. Debug Ether Interface (EtherMAC) 2.7.1. Specifications The RZ/G1E incorporates one Ethernet MAC that supports 100 Mbps or 10 Mbps and is compliant with IEEE 802.3u. On the YR8A77450S000BE board, the signals for the MAC, EtherMAC or EtherMAC_B, are connected to the RMII PHY interface (KSZ8041RNLI) manufactured by Micrel. The pin functions for the EtherMAC and Ethernet AVB are multiplexed on the same pins due to the specifications of the RZ/G1E’s pin function controller. Accordingly, the EtherMAC and Ethernet AVB functions cannot be used at the same time. When the Ethernet AVB function and EtherMAC PHY function of the YR8A77450S000BE board are to be used at the same time, use the EtherMAC_B function, since the Ethernet AVB and EtherMAC_B functions can be used at the same time. Table 2.7.1 Debug Ether Interface Specifications MAC Layer Physical Layer Transceiver Reset method Interrupt request Modular Connector 2.7.2. RZ/G1E’s on-chip EtherMAC and EtherMAC_B U13: KSZ8041RNLI (RMII) by Micrel Assertion of RESET# (GP1_24 = ‘0’) Negation of RESET # (GP1_24 = ‘1’) IRQ8# CN5: CWKRJ-13BNL Block Diagram A block diagram of the debug Ether interface is shown below. R-CarE2 RZ/G1E KSZ8041RNLI EtherMAC 8 8 ETH_MDIO ETH_MDC ETH_RXD1 ETH_RXD0 ETH_RX_ER ETH_TX_EN ETH_TXD1 ETH_TXD0 ETH_CRS_DV ETH_REF_CLK ETH_LINK 3 3 MDIO MDC RXD1 RXD0 RX_ER TX_EN TXD1 TXD0 CN5 CWKRJ-13BNL TX+ TX- RJ45 Connector with P/T RX+ RX- 25MHz CRS_DV REF_CLK XI D3.3V XO YELLOW LED1/SPEED D3.3V GREEN LED0/NWAYEN D3.3V 4.7k IRQ8# GP1_24 INTRP RST# 1k LINK Figure 2.7.1 Block Diagram of Debug Ether Interface YR8A77450S000BE October 24, 2015 Page 18 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.8. Audio Codec Interfaces (SSI0, SSI1, SSI2, and SSI9) 2.8.1. Specifications On the YR8A77450S000BE board, the codec (AK4643) is connected to the SSI0 and SSI1 of the RZ/G1E. The reset signal PRESETIN# input to the RZ/G1E is level-shifted to 3.3 V and connected to the power-down (PDN) pin of the AK4643. The audio interface of AK4643 is in the slave mode after PRESETIN# is released from a reset and can be switched to the master mode by a register that is accessed via the I2C interface 1. Furthermore, the SSI on the RZ/G1E side can be set as the master or a slave. It is assumed that SSI_SDATA0 is set to transmit mode and SSI_SDATA1 is set to receive mode on the YR8A77450S000BE board. Among the signals of the audio interface, the signals of SSI0, SSI1, SSI2, and SSI9 are also connected to HDMI transmitter ADV7511 (U15) on the YR8A77450S000BE board. For the connections between the RZ/G1E and each device, see Table 2.8.2. The pin functions for the SSI_SDATA1, SSI_SDATA2 and EtherMAC_B are multiplexed on the same pin due to the specifications of the RZ/G1E’s pin function controller. Accordingly, the SSI_SDATA1, SSI_SDATA2 functions and EtherMAC_B function cannot be used at the same time. Table 2.8.1 SSI Codec Specifications Controller Codec RZ/G1E’s on-chip SSI0 and SSI1 U22: AK4643EN by Asahi Kasei RZ/G1E (SSI) = Master or slave selectable AK4643EN = Master or slave selectable (default: slave) LINE-OUT(CN11, 3.5-mm mini-jack) LINE-IN/MIC-IN (CN12, 3.5-mm mini-jack) Audio interface Audio connector 2.8.2. Block Diagram R-CarE2 RZ/G1E AK4643 GP5_1 / SSI_SCK0129 BICK GP5_2 / SSI_WS0129 LRCK GP5_3 / SSI_DATA0 GP5_13 / SSI_DATA1 / ETH_RXD0_B SDTI MPWR SW1 SDTO CN12 Line/MIC In LIN RIN GP5_22 / AUDIO_CLKC 0 GP4_0, GP4_1 / I2C(ch1) CN11 Line Out LOUT ROUT MCKO 0 I2C Buffer TCA4311ADGKR I2C address Write: 0x24 Read: 0x25 SCL, SDA CAD0 GP5_16 / SSI_DATA2 / ETH_REF_CLK_B GP5_19 / SSI_DATA9 MCKI from EtherMAC PHY KSZ8041 X9 12.2880MHz to HDMI Transmitter ADV7511 PRESET# Power On Reset Level Shift 3.3V to 1.8V Level Shift 1.8V to 3.3V PDN Figure 2.8.1 Block Diagram of Audio Codec Table 2.8.2 SSI Connections on the YR8A77450S000BE board GP5_22 RZ/G1E AUDIO_CLKC GP5_1 GP5_2 GP5_3 GP5_13 GP5_16 GP5_19 SSI_SCK0129 SSI_WS0129 SSI_SDATA0 SSI_SDATA1 SSI_SDATA2 SSI_SDATA9 YR8A77450S000BE October 24, 2015 AK4643 Connected (0-Ω resistors are mounted).    Connected (SW1).   ADV7511 Connected (0-Ω resistors are mounted).    Connected (SW1).   Page 19 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.9. SD Card Host Interface (SDHI1) 2.9.1. Specifications The YR8A77450S000BE board incorporates an SD card slot (CN4) for the on-chip SD card host interface (SDHI1) of the RZ/G1E. For details on the SDHI1, see the RZ/G Series User’s Manual: Hardware. On the YR8A77450S000BE board, the power (3.3 V) to be supplied to the VDD pin (pin 4 of CN4) of the SD card slot can be controlled by GP4_26. When GP4_26 is set to 1, power is supplied. When GP4_26 is set to 0, power is shut off. Table 2.9.1 SD Card Host Interface (SDHI1) Specifications SD card host interface Voltage control for VDD (pin 4 of CN4) Control of power supply voltage for the SDHI1 interface SD card slot 2.9.2. RZ/G1E’s on-chip SD card host interface 1 (SDHI1) VDD (pin 4 of CN4) = 3.3 V (GP4_26 = ‘1’) VDD (pin 4 of CN4) = 0.0 V (GP4_26 = ‘0’) VCCQ_SD2 = 3.3 V MSPN09-A0-1002 (CN4) Block Diagram VCCQ_SD1 R-CarE2 RZ/G1E 10k TDO2 / SD1_CLK SD Card Slot MSPN09-A0-1002 CLK 22 CMD TRST2_N / SD1_CMD DATA3 DATA2 DATA1 DATA0 ASEBRK2 / SD1_DATA3 TDI2 / SD1_DATA2 TMS2 / SD1_DATA1 TCK2 / SD1_DATA0 GP6_14 / SD1_CD GP6_15 / SD1_WP CD WP COM 1k SDIF_POWER Power Switch MIC94091 VDD GP4_26 VCCQ_SD1 VCCQ_SD1 D5.0V DA9063 LDO3 GP4_29 Figure 2.9.1 Block Diagram of SD Card Host Interface (SDHI1) YR8A77450S000BE October 24, 2015 Page 20 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.10. eMMC Memory Interface (MMC) 2.10.1. Specifications The YR8A77450S000BE board incorporates an eMMC memory MTFC8GLWDQ-3M AIT Z (8 GB, U5) manufactured by Micron that is connected to the on-chip MMC interface of the RZ/G1E. For details on the MMC, see the RZ/G Series User’s Manual: Hardware. Only 3.3 V can be supplied as the power supply voltage for the MMC interface (as VCCQ_SD2) due to the specifications of the RZ/G1E’s MMC. Accordingly, be sure to set the GP4_31 pin to 1 when the eMMC memory (U5) on the YR8A77450S000BE board is to be used. Table 2.10.1 eMMC Memory (MMC) Interface Specifications MMC controller Power supply voltage for the MMC interface eMMC memory RZ/G1E’s on-chip MMC interface (MMC) VCCQ_SD1 = 3.3 V U5: MTFC8GLWDQ-3M AIT Z (8 Gbytes) 2.10.2. Block Diagram A block diagram of the eMMC memory interface is shown below. D3.3V R-CarE2 RZ/G1E 100k eMMC MTFC8GLWDQ-3M AIT Z VCC CLK SD2_CLK / MMC_CLK D3.3V 22 CMD SD2_CMD / MMC_CMD GP6_25 / MMC_D7 GP6_24 / MMC_D6 SD2_WP / MMC_D5 SD2_CD / MMC_D4 DATA7 DATA6 DATA5 DATA4 SD2_DAT3 / MMC_D3 SD2_DAT2 / MMC_D2 SD2_DAT1 / MMC_D1 SD2_DAT0 / MMC_D0 DATA3 DATA2 DATA1 DATA0 VCCQ D5.0V VCCQ_SD1 DA9063 LDO3 PRESET# Power On Reset Level Shift 3.3V to 1.8V Level Shift 1.8V to 3.3V PRESET#(3.3V) RST_n Figure 2.10.1 Block Diagram of eMMC Memory Interface YR8A77450S000BE October 24, 2015 Page 21 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.11. USB2.0 Interface 2.11.1. Specifications The YR8A77450S000BE board has two USB2.0 ports that can be used as two USB2.0 host interface ports or one USB2.0 host interface port and one USB2.0 function interface port. The function interface is supported in channel 0. The YR8A77450S000BE board incorporates a a type A connector as CN2. For details on USB2.0, see the USB specifications in the RZ/G Series User’s Manual: Hardware and related datasheets. Table 2.11.1 USB2.0 Specifications USB controller RZ/G1E’s on-chip USB2.0 host and function controller BD82065FVJ by ROHM USB power supply Current limit 2.4 [A] RZ/G1E USB CH1 CN2 type A connector USB host CN USB-A x2 lower side RZ/G1E USB CH0 CN2 type A connector USB host/function CN USB-A x2 upper side ESD protection diode HZD6.2Z4 by Renesas Common mode filter DLM11SN900HY2 by Murata Chip beads BLM18PG330SN1D by Murata Note: The connector for channel 0 of the USB in the RZ/G1E is a type A connector shared by the USB host and function. 2.11.2. Block Diagram R-CarE2 RZ/G1E DIFFERENTIAL Impedance 90ohm DIFFERENTIAL Impedance 90ohm Common Mode Filter USB1_DP USB1_DM U8 Pull down 2k USB1_PWEN EN OUT (3.3V) 4.7k USB1_OVC 5.0V IN 1k Pull down /OC Pull up +5V GND USB Host(CN2) Type A D2+ D2- ESD Protection Chip Beads VBUS2 GND2 BD82065FVJ DIFFERENTIAL Impedance 90ohm DIFFERENTIAL Impedance 90ohm USB0_DP D1+ Common Mode Filter USB0_DM D1- U10 5.0V Pull down 2k USB0_PWEN SW10 EN IN (3.3V) 4.7k Pull up USB0_OVC/VBUS ESD Protection OUT /OC +5V Chip GND Beads VBUS1 GND1 BD82065FVJ USB_EXTAL 48MHz HD74LV1GT08A VCC=3.3V 1k Pull down USB_XTAL Figure 2.11.1 Block Diagram of USB2.0 YR8A77450S000BE October 24, 2015 Page 22 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.12. Debug Serial Interface (SCIF2) 2.12.1. Specifications On the YR8A77450S000BE board, the SCIF2 of the RZ/G1E is used as a debug serial interface. The SCIF2 of the RZ/G1E is connected to the USB micro-AB connector (CN4) via the USB to UART bridge CP2102. By connecting CN4 to the host PC through USB cable, this interface can be used as a debug serial interface. The SCIF_CLK pin of the RZ/G1E is connected to the 14.7456-MHz crystal oscillator (X4) on the YR8A77450S000BE board, which supplies a clock frequency of 14.7456 MHz. When 14.7456 MHz is the frequency of the source clock, since the UART supports 300 bps to 1 Mbps due to the CP2102 device specifications, the maximum transfer rate becomes 921.6 kbps, which is obtained by dividing the source clock by 16. The SCIF2 has the features shown below. For details, see the SCIF specifications in the RZ/G Series User’s Manual: Hardware. • • • Asynchronous serial communications Full-duplex communication supported Selectable bit rates by using the RZ/G1E's on-chip baud-rate generator The host PC connected to the YR8A77450S000BE board requires the CP2102 USB driver software. This driver software can be obtained from the following URL. http://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx Table 2.12.1 Debug Serial Interface Specifications Serial controller USB to UART bridge Connector RZ/G1E’s on-chip SCIF2 controller CP2102 (1 Mbps max.) by Silicon Laboratories CN13: KS-MCR-B02T3-L 2.12.2. Block Diagram RZ/G1E R-CarE2 CP2102 3.3V USB to UART Bridge TXD GP4_17 / SCIF2_TXD GP4_16 / SCIF2_RXD RXD RXD CN13 USB microAB(Func) VBUS VBUS DM DM DP DP TXD HD74LV1GT08A VCC=3.3V AVB_LINK / HSCIF0_HTX AVB_MDIO / HSCIF0_HRX D5.0V CTS GP3_27 / HSCIF0_HCTS# GP1_23 / SCIF_CLK RTS X4 14.7456MHz REGIN USB Self-Powered mode Figure 2.12.1 Block Diagram of Debug Serial Interface YR8A77450S000BE October 24, 2015 Page 23 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.13. Reset 2.13.1. Specifications In the YR8A77450S000BE board specifications, the power-on reset signal is cleared by the reset IC MAX708SCSA, 200 ms after the 3.3V power supply has settled. The power supplies for other voltage levels, 12.0 V, 5.0 V, 1.8 V, 1.5 V, and 1.0 V, are not monitored. A power-on reset signal can be generated by pushing the push switch (SW5). The reset signal is level-shifted from 3.3 V to 1.8 V by the HD74ALVC1G07 and is input to the PRESET# pin of the RZ/G1E. Table 2.13.1 RESET Specification Reset IC MAXIM MAX708SCSA - Threshold voltage: 2.93 V - Reset delay time: 200 ms 2.13.2. Block Diagram D3.3V Reset-IC MAX708SCSA D1.8V D1.8V SW5 RESET RESET# R-CarE2 PRESET# HD74ALVC1G07 Figure 2.13.1 Block Diagram of Reset Circuit YR8A77450S000BE October 24, 2015 Page 24 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.14. I2C Interface 2.14.1. Specifications The RZ/G1E has eight I2C interface channels. Channel 7 is a 1.8-V interface and channels 0 to 6 are 3.3 V interfaces. Since the RZ/G1E uses LVTTL-type I/O buffers on I2C interfaces 1, it cannot directly drive an I2C bus with a relatively high load capacitance (e.g. 100 pF). While the above restriction applies to interfaces 1 of the RZ/G1E, the design of the YR8A77450S000BE board calls for multiple I2C devices being connected to I2C interfaces 1. In order to compensate for the driving ability of the RZ/G1E, the YR8A77450S000BE board incorporates an TCA4311ADGKR I2C buffer manufactured by Texsa Instruments, via which each I2C device is connected to the I2C interface for the device. The following devices are connected to each I2C interface on the YR8A77450S000BE board. Table 2.14.1 I2C Interface Specifications I2C controller I2C devices through I2C (channel 7) RZ/G1E’s on-chip I2C controller [1.8 V] U30: Pins B4 (SK) and A5 (SI) of DA9063 by Dialog Semiconductor [3.3 V] U17: TestIC (not mounted) I2C devices through I2C (channel 4) [3.3 V] JP1: EXIO I2C devices through I2C (channel 3) [3.3 V] U15: ADV7511WBSWZ by Analog Devices U21: ADV7180WBCP32Z by Analog Devices U22: AK4643EN by AKM Semiconductor U30: Pins A8 (CLK) and A7 (DATA) of DA9063 by Dialog Semiconductor U14: R1EX24002ATAS0 by Renesas I2C devices through I2C (channel 1) [3.3 V] CN8: LCD-KIT-B01 I2C devices through I2C (channel 0) 2.14.2. List of Slave Addresses The table below lists the slave addresses of the I2C devices on the YR8A77450S000BE board. Table 2.14.2 List of I2C Slave Addresses I2C channel 7 4 3 1 0 Ux CNx U30 U17 JP1 U15 DA9063 TestIC EXIO ADV7511 U21 U22 U30 U14 CN8 YR8A77450S000BE October 24, 2015 Device SA7 SA6 SA5 SA4 SA3 SA2 SA1 R/W# PMIC Connector - - - - - - - - HDMI Tx 0 1 1 1 0 0 1 X ADV7180 AK4643 DA9063 R1EX24002 Video decoder SSI codec PMIC I2C EEPROM 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 X X X LCD-KIT-B01 Connector Note Not mounted Pin 22 (PD/AD) = GND Pin 26 (ALSB) = GND Pin 8 (CAD0) = GND Pins 3 to 1 (A[2:0]) = GND Page 25 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.14.3. Block Diagram D1.8V R-CarE2 RZ/G1E 2k U30 DA9063 SCL SDA SCL7 SDA7 Not mounted D3.3V U17 TestIC SCL 2k SDA SCL4 SDA4 D3.3V JP1 Header Pin SCL 2k SDA SCL3 SDA3 D3.3V D3.3V 2k 2k U15 ADV7511 SCL SDA U21 ADV7180 SCL SDA U22 AK4643 SCL SDA U30 DA9063 SCL SDA U14 R1EX24002 SCL SDA U52 LTC4313-1 SCL1 SDA1 D1.8V 2k CN8 For LCD-KIT-B01 SCL SDA SCL0 SDA0 Figure 2.14.1 Block Diagram of I2C Interface YR8A77450S000BE October 24, 2015 Page 26 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.15. GPIO Interface (Software Switch, Tact Switch) 2.15.1. Specifications The YR8A77450S000BE board incorporates a 4-bit software switch (SW12), three bits of tactile switches (SW3, SW4, SW6) They are connected to the GPIO pins of the RZ/G1E as follows. When the software switches are to be used, enable the internal pull-up resistors for GP3_12, GP3_11, GP3_10, and GP3_9. Table 2.15.1 List of Software Switches (General-Purpose Switches) Software Switch Bit 3 (Pin 4 of SW12) Bit 2 (Pin 3 of SW12) Bit 1 (Pin 2 of SW12) Bit 0 (Pin 1 of SW12) GPIO GP3_12 GP3_11 GP3_10 GP3_9 Multiplexed Function AVB_TX_EN AVB_COL AVB_RX_ER AVB_RXD7 Table 2.15.2 List of Tactile Switches (General-Purpose Switches) Tact Switch Bit 2 (SW6) Bit 1 (SW4) Bit 0 (SW3) GPIO GP5_12 GP5_11 GP5_10 Multiplexed Function ETH_RX_ER_B ETH_CRS_DV_B IRQ9 / ETH_MDIO_B 2.15.2. Block Diagram R-CarE2 RZ/G1E GP3_12( bit3 ) GP3_11( bit2 ) GP3_10( bit1 ) GP3_9( bit0 ) GP5_20( BT_HOST_WAKE ) GP5_18( BT_DEV_WAKE ) GP5_15( WL_HOST_WAKE ) GP5_14( BT_REG_ON ) GP2_26( WL_REG_ON ) Each bits are pulled up internally. 4 SW12 5 U28 LBEE6U4 SW6 GP5_12( bit2 ) SW4 GP5_11( bit1 ) SW3 GP5_10( bit0 ) Figure 2.15.1 Block Diagram of GPIO Interface (Software Switch, Tactile Switches) YR8A77450S000BE October 24, 2015 Page 27 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.16. External Interrupts 2.16.1. Specifications The RZ/G1E has external interrupt input pins NMI and IRQ[9:0]. The YR8A77450S000BE board uses NMI and IRQ8 as external interrupt input pins, and GP3_31, and GP5_23 as GPIO interrupts. These pins should be used as active-low signals in programs. For the interrupt functions of the RZ/G1E, see the RZ/G Series User’s Manual: Hardware. The devices and connectors of the interrupt request sources on the YR8A77450S000BE board are shown below. Table 2.16.1 External Interrupt Specifications Interrupt Pin Devices that Output Interrupt Request Connectors NMI Pull high RMII PHY U13: KSZ8041RNLI by Micrel PMIC U30: DA9063 by Dialog Semiconductor HDMI transmitter U15: ADV7511WBSWZ by Analog Devices - IRQ8 GP3_31 GP5_23 - 2.16.2. Block Diagram A block diagram of external interrupts is shown below. R-CarE2 RZ/G1E GP5_0 U13 KSZ8041 / IRQ8 GP3_31 U30 DA9063 GP5_23 D1.8V U15 ADV7511 NMI Figure 2.16.1 Block Diagram of External Interrupts YR8A77450S000BE October 24, 2015 Page 28 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.17. Clock The YR8A77450S000BE board uses the crystal oscillators and resonators shown below. 2.17.1. Clocks Supplied to the RZ/G1E Table 2.17.1 List of Clocks and Crystals for RZ/G1E No. 1 2 3 4 5 6 Xn X1 Frequency 48.0000 MHz X3 X2 X4 X5 X10 74.25 MHz 148.500 MHz 14.7456 MHz 20.0000 MHz 32.768 KHz Pin Name on RZ/G1E USB_XTAL, USB_EXTAL DU1_DOTCLKIN DU0_DOTCLKIN SCIF_CLK EXTAL LPO_IN Type Resonator Remarks - Oscillator Oscillator Oscillator Oscillator Oscillator - 2.17.2. Clocks Supplied to Devices Other than RZ/G1E Table 2.17.2 List of Clocks and Crystals Other than for RZ/G1E No. 1 2 3 4 5 6 Xn X6 X7 X8 X9 X11 X10 YR8A77450S000BE October 24, 2015 Frequency 25.0000 MHz 12.0000 MHz 28.63636 MHz 12.2880 MHz 32.768 kHz 32.768 kHz Device KSZ8041RNLI ADV7511WBSWZ ADV7180WBCP32Z AK4643 DA9063 LBEE6U4XQC-DTEMP Device Pin Name XI, XO CEC_CLK XTAL MCKI XTAL_IN, XTAL_OUT LPO_IN Type Resonator Oscillator Oscillator Oscillator Resonator Oscillator Page 29 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.18. Power Supply 2.18.1. Specifications The YR8A77450S000BE board operates on a single 5.0-VDC power supply. The power supplies used for the YR8A77450S000BE board are generated by the switching regulators and low-dropout regulators. Take care to ensure the following two points: (1) Specified sequences should be used to turn on and off the power supply to the RZ/G1E. Be sure to control the Power switch (SW11, press once to power on, long press to power down) to obey the power sequence on the YR8A77450S000BE board. See the table below for regulators used to generate power supplies on the YR8A77450S000BE board, their input voltage (Vin) and output voltage (Vout), and whether the Power switch can be used to enable or disable output of power supplies. Table 2.18.1 List of Switching Controllers and Regulators on the YR8A77450S000BE Board Vin Vout Power Supply DC5.0V through CN14 D5.0V D1.0V D1.5V D3.3V VTT D1.8V D5.0V VCCQ_SD1 (3.3/1.8 V) VIO33 (3.3 V) VLDO7_1.8V VCCQ_SD0 (3.3/1.8V) SDIF_POWER (3.3 V) YR8A77450S000BE October 24, 2015 Switching Controller/Regulator - - Power Switch Control Not supported Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Dialog Semiconductor DA9063 (U30) Analog Devices ADP3339AKCZ-3.3R7 (U12, not mounted) - Supported Power MOSFET Supported - Supported - Supported - Supported - Supported - Supported - Supported - Supported - Supported Page 30 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.18.2. Block Diagram DC5.0V D5.0V POWER Switch DA9063 VBUCKCORE1 D1.0V VDD_Buck VBUCKCORE2 D1.5V VDD_LDO VBUCKMEM D3.3V VBUCKPRO nONKEY VTT VBUCKPERI D1.8V D1.5V VTTQ_E_GP12 Power Switch MIC94091 D1.8V_PERI PWR_EN_GPIO9 VLDO3 VCCQ_SD1 VLDO4 VCCQ_SD2 VLDO8 VCCQ_SD0 Figure 2.18.1 Block Diagram of Power Supply Circuit YR8A77450S000BE October 24, 2015 Page 31 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.18.3. Power Supply Sequencing The diagram of the sequence for turning on the power (DA9063 OTP) to the YR8A77450S000BE board is shown below. D1.8V_PERI(for peripheral) D3.3V(for peripheral) D1.8V(for E2) D1.5V(for DDR) D1.0V(for E2-VDD) VTT(for DDR) 1.8V(for Power Circuit) 3.3V(for Power Circuit) D3.3V(for E2 & others) Notes:1. In the power-off sequence, turn off the power supplies in reverse order of the power-on sequence. Figure 2.18.2 Power-On Sequence YR8A77450S000BE October 24, 2015 Page 32 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 2.19. EXIO Connectors (JP1, JP2) 2.19.1. Specifications The YR8A77450S000BE board incorporates two connectors (JP1, JP2) that are connected to the peripheral I/O signals of the RZ/G1E. The arrangement of connectors and pins on the YR8A77450S000BE board is shown below. Table 2.19.1 EXIO Connector Specification EXIO Connector (JP1) EXIO Connector (JP2) Box Wafer 10-pin, 2.0-mm pitch. Box Wafer 6-pin, 2.0-mm pitch Table 2.19.2 List of EXIO Connector (JP1) Pins Pin 1 3 5 7 9 Net Name MSIOF1_SYNC MD5/MSIOF1_TXD I2C3_SDA_B GP3_22 GND Pin 2 4 6 8 10 Net Name MSIOF1_SCK MISOF1_RXD I2C3_SCL_B GP3_30 GND Table 2.19.3 List of EXIO Connector (JP2) Pins Pin 1 3 5 YR8A77450S000BE October 24, 2015 Net Name D3.3V GP1_16/TS_SDEN0_B GP1_15/TS_SCK0_B Pin 2 4 6 Net Name GP1_14/TS_SDATA0_B GP1_17/TS_SPSYNC0_B GND Page 33 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 3. Outline Diagrams of YR8A77450S000BE Board 3.1. External Dimensions and Hole Locations of YR8A77450S000BE Board The following shows the external dimensions and hole locations of the YR8A77450S000BE board. (Unit: mm) Figure 3.1.1 External Dimensions and Hole Locations of the YR8A77450S000BE Board (Top View) YR8A77450S000BE October 24, 2015 Page 34 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 3.2. Connector Locations on YR8A77450S000BE Board (Component Surface) The following shows the connector locations on the component surface. Figure 3.2.1 Connector Locations of the YR8A77450S000BE Board (Component Surface) (Top View) YR8A77450S000BE October 24, 2015 Page 35 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual 3.3. Connector Locations on YR8A77450S000BE Board (Solder Surface) The following shows the connector locations on the solder surface. Figure 3.3.1 Connector Locations of the YR8A77450S000BE Board (Solder Surface) (Top View) YR8A77450S000BE October 24, 2015 Page 36 of 37 RZ/G1E Starter Kit Board YR8A77450S000BE Hardware Manual RZ/G1E Starter Kit Board (YR8A77450S000BE) Hardware Manual Publication Date: Rev. 1.00 Oct 24, 2015 Published by: Renesas Electronics America Co., Ltd. YR8A77450S000BE October 24, 2015 Page 37 of 37