DATASHEET
ZL8801
FN8614
Rev.3.00
March 27, 2015
Dual Phase PMBus™ ChargeMode™ Control DC/DC Digital Controller
The ZL8801 is a dual phase digital DC/DC controller. Up to four
ZL8801s (8 phases) can be operated in parallel to provide
additional output current.
Features
The ZL8801 supports a wide range of output voltages
(0.54V to 5.5V) operating from input voltages as low as 4.5V
up to 14V.
• Output voltage range: 0.54V to 5.5V
With its fully digital ChargeMode™ Control loop the ZL8801
can respond to a transient load step within a single switching
cycle. This unique compensation-free modulation technique
allows designs to meet transient specifications with minimum
output capacitance, thus saving cost and board space.
• Charge mode control achieves fast transient response,
reduced output capacitance and provides output stability
without compensation
Intersil’s proprietary single wire DDC (Digital-DC™) serial bus
enables the ZL8801 to communicate between other Intersil
digital power ICs. By using the DDC, the ZL8801 achieves
complex functions such as inter-IC phase current balancing,
sequencing and fault spreading, eliminating complicated
power supply managers with numerous external discrete
components.
The ZL8801 features cycle-by-cycle overcurrent protection and
protection for overvoltage, undervoltage, over-temperature and
MOSFET driver under and overvoltage protection. A snapshot
parametric capture feature allows users to take a snapshot of
operating and fault data during normal or fault conditions.
Integrated Low Drop-Out (LDO) regulators allow the ZL8801 to
be operated from a single input supply eliminating the need
for additional linear regulators. A dedicated 5V VDRV LDO
output can be used to power external drivers or DrMOS
devices.
• Unique compensation-free design – always stable
• Input voltage range: 4.5V to 14V
• 1% output voltage accuracy over line, load and temperature
• Single 2-phase output, up to 8 phases with multiple devices
• Switching frequency range 200kHz to 1.33MHz
• Proprietary single wire DDC (Digital-DC) serial bus enables
voltage sequencing and fault spreading with all other Intersil
digital power ICs
• Tracking of an external power supply in the single 2-phase
configuration
• Cycle-by-cycle inductor peak current protection
• Digital fault protection for output voltage UV/OV, input
voltage UV/OV, temperature and MOSFET driver voltage
• 10-bit cycle-by-cycle average output current measurement
with adjustable gain settings for sensing with high current,
low DCR inductors
• 10-bit monitor ADC measures input voltage, input current,
output voltage, internal, external temperature, driver voltage
• Configurable to use standalone MOSFET drivers or
integrated driver-MOSFET (DrMOS) devices
With full PMBus™ compliance, the ZL8801 is capable of
measuring and reporting input voltage, input current, output
voltage, output current as well as the device’s internal
temperature, an external temperature and an auxiliary voltage
input.
• Nonvolatile memory (NVRAM) for storing operating
parameters and fault events.
Related Literature
• Servers/storage equipment
• AN1948, “ZL8801-4PH-DEMO1Z Demonstration Board User
Guide”
• Power supplies (memory, DSP, ASIC, FPGA)
• UG005, “ZL8801-2PH-DEMO1Z Demonstration Board User
Guide”
• AN1900, “USB to PMBus™ Adapter User Guide”
FN8614 Rev.3.00
March 27, 2015
• PMBus™ compliant
Applications
• Telecom/datacom equipment
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER DUAL OUTPUT DUAL PHASE DDC CURRENT SHARE
ZL8800
Yes
Yes
No
ZL8801
No
Yes
Yes
Page 1 of 87
ZL8801
Table of Contents
Simplified Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ZL8801 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configurable Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage and VOUT_MAX Selection (VSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency Setting (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Undervoltage Lockout Setting (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TON Delay and Rise Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
12
13
13
13
14
14
15
15
16
16
16
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Limit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Temperature Monitoring Using XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Nonvolatile Memory (NVRAM) and Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC/DC Converter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PMBus™ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus™ User Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus™ Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus™ Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
29
29
30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
FN8614 Rev.3.00
March 27, 2015
Page 2 of 87
ZL8801
Simplified Application
EN
PG
VIN
PWMH0
PWM
PWML0
EN
ZL8801
DrMOS
CONTROL
AND
STATUS
VIN
VDRV
VDD
VDD
VIN
4.5V TO 14V
BST
Vsw
GND
VO UT
0.6V TO 5V
ISENA0
ISENB0
VIN
VIN
VDRV
PMBus
PWMH1
PWM
PWML1
EN
SDA
SCL
SALRT
BST
DrMOS
DDC
VDD
INTER-DEVICE
COMMUNICATION
Vsw
GND
ISENA1
ISENB1
VSENP
VSENN
GND
FIGURE 1. SIMPLIFIED APPLICATION
FN8614 Rev.3.00
March 27, 2015
Page 3 of 87
ZL8801
ASCR
DIG ITAL PWM
MODULATOR
ADC
PWM+
DEAD
TIME
PWMH0
PWM+
DEAD
TIME
PWMH1
PWML0
DAC
VSE NP/N
PGA
Block Diagram
ASCR
DIG ITAL PWM
MODULATOR
ADC
PWML1
XTEMP0P/N
MUX
XTEMP1P/N
MONITOR
ADC
VTRKP/N
DIG ITAL LOGIC
+
OV/UV/OC/UC
COMPARATORS
VMON
VDD
MGN
EN
PG
OSC
PGA
PGA
ISENB1
IIN
ADC
LDO s
GAIN
IINN
VDD
UVLO
VSE T
SA
PIN-STRAP
RESISTOR
DETECTION
IINP
PMBUS
SERIAL
INTERFACE
VDRVEN
SALRT
ISENA1
IPEAK/
IAV G
ADC
VR6
SCL
MICROCONTROLLER
AND
NONVOLATILE
MEMORY
ISENB0
VDRV
SDA
DIG ITAL-DC
INTER-DEVICE
COMMUNICATIO NS
ISENA0
IPEAK/
IAV G
ADC
PLL
V25
DDC
CLK
GEN
VR5
SYNC
FIGURE 2. BLOCK DIAGRAM
FN8614 Rev.3.00
March 27, 2015
Page 4 of 87
ZL8801
FN8614 Rev.3.00
March 27, 2015
Schematic
VIN
10.8 TO 13.2V
RIN
IINN
VDD
VDRV
IINP
C3
10µF
R8
100kΩ
V25
C4
10µF
C7
10µF
VMON
V5
R9
6.65kΩ
V6
C5
10µF
CIN1
C6
1µF
1mΩ
(OPTIONAL)
PVCC VIN
L1
VCC
C8
1µF
ISL99140 SW
AGND
SYNC
PWM
EN
PWMH0
PWML0
SA
R3
UVLO
R5
64
BOOT
VOUT
ISENA0
ISENB0
COUT
VIN
U3
ZL8801
CONTROL
AND
STATUS
EN
PG
INTER-DEVICE
COORDINATION
(OPTIONAL)
DDC
PMBus
(OPTIONAL)
SDA
SYNC
SCL
L2
VCC
C10
1µF
V5
CIN2
PVCC VIN
IN REVIEW
R7
10kΩ
C1
R1
C9
0.1µF
THDN
PGND SMOD
VSET0
R4
PHASE
U1
ISL99140 SW
AGND
PWMH1
PWM
PWML1
EN
PHASE
U2
BOOT
THDN
PGND SMOD
ISENA1
ISENB1
VSENN
VSENP
DGND SGND
Page 5 of 87
FIGURE 3. ZL8801 SCHEMATIC
R2
C11
0.1µF
C2
ZL8801
Pin Configuration
34 IINN
35 IINP
36 V25
37 NC
39 NC
38 NC
40 XTEMP1N
41 XT EMP1P
43 NC
42 EN
44 SYNC
ZL8801
(44 LD QFN)
TOP VIEW
SCL
1
33
VDD
SDA
2
32
VR5
SALRT
3
31
VR6
SGND
4
30 VDRV
SA
5
29
VMON
6
EXPOSED PADDLE
CONNECT TO SGND
ISENA1
28 ISENB1
27
PWML1
DGND
7
MGN
8
26 PWMH1
NC
9
25 PWMH0
22
19
VSENP
ISENA0
18
VT RKN
21
17
VTRKP
VDRVEN
16
XT EMP0N
20
15
XT EMP0P
VSENN
14
DDC
ISENB0
13
23
UVLO
PWML0
NC 11
12
24
PG
VSET 10
Pin Description
PIN#
TYPE
PIN NAME (Note 1)
DESCRIPTION
1
SCL
I/O
Serial clock. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V
(recommend VR5, do not use V25) source.
2
SDA
I/O
Serial data. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V
(recommend VR5, do not use V25) source.
3
SALRT
O
4
SGND
PWR
Connect to low impedance ground plane. Internal connection to SGND. All pin-strap resistors should be connected
to SGND. SGND must be connected to DGND and PGND using a single point connection.
5
SA
M
Serial address select pin. Used to assign unique address for each individual device or to enable certain management
features. See Table 3 for SMBus address options. Connect resistor to SGND.
6
VMON
I
External voltage monitoring (can be used for external driver bias (VDRV) monitoring). Requires an external 16:1
resistor divider network. Connect bottom of resistor divider network to SGND. Connect divider network to VR5 if an
external voltage is not monitored.
7
DGND
PWR
8
MGN
I
Margin pin. High = margin high, low = margin low, float = no margin.
10
VSET
M
Output voltage selection pin. Used to set VOUT and VOUT max. See Table 4 for VOUT pin-strap options. Default VOUT
max is 115% of VOUT setting, but this can be overridden via the PMBus interface with VOUT_MAX command. Connect
resistor to SGND.
12
PG
O
Power-good output. Can be configured as open-drain or push-pull using the PMBus interface. Default setting is open
drain.
13
UVLO
M
Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT. See Table 6 for UVLO setting
options. Pin-strapped (configured) values can be overridden by the PMBus interface. Connect resistor to SGND.
14
DDC
I/O
Single wire DDC bus (Current sharing and interdevice communication). Requires a pull-up resistor to a 2.5 to 5.5V
(recommend VR5, do not use V25) source. Pull-up voltage must be present when the device is powered.
15
XTEMP0P
I
External temperature sensor input. Connect to external 2N3904 (Base Emitter junction) or equivalent embedded
thermal diode. If not used connect to SGND.
FN8614 Rev.3.00
March 27, 2015
Serial alert. Connect to external host if desired. Requires a pull-up resistor to a 2.5V to 5.5V (recommend VR5)
source. If not used this pin should be left floating.
Digital ground. Must connect to SGND and PGND using a single point connection.
Page 6 of 87
ZL8801
Pin Description
PIN#
(Continued)
TYPE
PIN NAME (Note 1)
DESCRIPTION
16
XTEMP0N
I
External temperature sensor input return. If not used connect to SGND.
17
VTRKP
I
Tracking sense positive input. Used to track an external voltage source. If not used, this pin can be left floating.
Tracking is only possible in 2-phase operation. Tracking is disabled in 4-, 6- and 8-phase operation.
18
VTRKN
I
Tracking sense negative input (return). If not used, this pin can be left floating.
19
VSENP
I
Differential voltage sense feedback. Connect to positive output regulation point.
20
VSENN
I
Differential voltage sense feedback. Connect to negative output regulation point.
21
VDRVEN
I
VDRV (MOSFET Driver Bias Supply) Enable. Leave unconnected (float) or pull-up to VR5 to enable, tie to ground to
disable.
22
ISENA0
I
Positive differential voltage input for phase 0 DCR current sensing. Should be routed as a pair with ISENB0. Should
connect to resistor located close to output inductor. See “Current Sensing Components” on page 17.
23
ISENB0
I
Negative differential voltage input for phase 0 DCR current sensing. Should be routed as a pair with ISENA0. Should
be connected to output inductor terminal. See “Current Sensing Components” on page 17.
24
PWML0
O
PWM0 Gate low signal/DrMOS enable. Configured using Bit 10 of USER_CONFIG command. Default is DrMOS
operation.
25
PWMH0
O
PWM0 Gate high signal.
26
PWMH1
O
PWM1 Gate high signal.
27
PWML1
O
PWM1 Gate low signal/DrMOS enable. Configure using Bit 10 of USER_CONFIG command. Default is DrMOS
operation.
28
ISENB1
I
Negative differential voltage input for phase 1 DCR current sensing. Should be routed as a pair with ISENA1. Should
be connected to output inductor terminal. See “Current Sensing Components” on page 17.
29
ISENA1
I
Positive differential voltage input for phase 1 DCR current sensing. Should be routed as a pair with ISENB1. Should
connect to resistor located close to output inductor. See “Current Sensing Components” on page 17.
30
VDRV
PWR
MOSFET driver bias supply regulator output. If disabled, this pin can be left floating. Decouple with a high quality
4.7µF X7R or better ceramic capacitor placed close to this pin.
31
VR6
PWR
Bypass for internal 6V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better
ceramic capacitor placed close to this pin. Keep this net as small as possible. Do not route near switching signals.
32
VR5
PWR
Bypass for internal 5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better
ceramic capacitor placed close to this pin.
33
VDD
PWR
Supply voltage. Decouple with a high quality 1µF X7R or better ceramic capacitor placed close to this pin.
34
IINN
I
Input current monitor negative input. If not used connect to VDD.
35
IINP
I
Input current monitor positive input. If not used connect to VDD
36
V25
PWR
9, 11, 37,
38, 39, 43
NC
40
XTEMP1N
I
External temperature sensor input for phase1. Connect to external 2N3904 (Base Emitter junction) or equivalent
embedded thermal diode. If not used connect to SGND.
Bypass for internal 2.5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better
ceramic capacitor placed close to this pin
Not Connected. Leave pin floating.
41
XTEMP1P
I
External temperature sensor input for phase 1 return. If not used connect to SGND.
42
EN
I
Enable input. Active signal enables PWM0 and PWM1 switching. Recommended to be tied low during device
configuration. Refer to “Enable” on page 16 for additional information.
44
SYNC
M/I/O
Clock synchronization input. Used to set the frequency of the internal clock to sync to an external clock or to output
internal clock. When configured as an output, this pin is push-pull and does not require a pull-up. See “Switching
Frequency Setting (SYNC)” on page 14 for additional information.
PAD
SGND
PWR
Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
NOTE:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pins.
FN8614 Rev.3.00
March 27, 2015
Page 7 of 87
ZL8801
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
ZL8801ALAFTK
PART
MARKING
TEMP. RANGE
(°C)
PACK
METHOD
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
8801
-40 to +85
Tape and Reel 1k
44 Ld QFN
L44.7x7B
ZL8801ALAFT7A
8801
-40 to +85
Tape and Reel 250pc
44 Ld QFN
L44.7x7B
ZL8801-2PH-DEMO1Z
2-phase Demonstration board.
ZL8801-4PH-DEMO1Z
4-phase Demonstration board.
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ZL8801. For more information on MSL, please see tech brief TB363
ZL8801
A L A F T
Product Designator
Shipping Option
TK = Tape and Reel - 1000 pcs
T7A = 7 inch Tape and Reel - 250 pcs
Lead Finish
F = Lead-free matte tin
Firmware Revision
Alpha character
Operating Temperature Range
L = -40°C to +85°C
Package Designator
A = QFN package
FN8614 Rev.3.00
March 27, 2015
Page 8 of 87
ZL8801
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage: VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic I/O Voltage: DDC, EN, MGN, PG,
SA, VDRVEN, SALRT, SCL, SDA, SYNC, UVLO,
VMON, VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Analog Input Voltages:
VSENP, VSENN, VTRKP, VTRKN, ISENA0, ISENA1,
ISENB0, ISENB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
XTEMP0P, XTEMP1P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
XTEMP0N, XTEMP1N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
IINN, IINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic Reference: V25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Bias Supplies: VR5, VR6, VDRV. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
PWM Logic Outputs, PWMH0, PWMH1, PWML0, PWML1 . . . .-0.3V to 6.5V
Ground Voltage Differential (VDGND, VSGND). . . . . . . . . . . . . . . .-0.3V to +0.3V
ESD Ratings
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C1010-D) . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
44 Ld QFN Package (Notes 6, 7) . . . . . . . .
25
1.5
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Input Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
5V (VR5) Supply Total Supplied Current (Note 8) . . . . . . . . . . . . . . . . . 5mA
5V LDO Supply (VDRV) (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 80mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Output current is limited by device thermal dissipation.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Total of current used by pull-ups to SDA, SCL, SALRT, DDC, EN, PG (including Push-pull configuration).
Electrical Specifications
range, TA -40°C to +85°C.
VDD = 12V. Typical values are at TA = +25°C. Boldface limits apply across the operating ambient temperature
MIN
(Note 14)
TYP
MAX
(Note 14)
UNITS
fSW = 200kHz
26
50
mA
fSW = 1.33MHz
50
80
mA
PARAMETER
TEST CONDITIONS
IC INPUT AND BIAS SUPPLY CHARACTERISTICS
IDD Supply Current
IDD Device Disabled Current
EN = 0V, SMBus inactive, VDD = 12V, fSW = 1.33MHz
20
30
mA
VR5 Reference Output Voltage
VDD > 6V, I < 5mA
4.5
5.0
5.5
V
V25 Reference Output Voltage
For reference only, VR > 3V
2.25
2.5
2.75
V
VR6 Reference Output Voltage
For reference only, VDD = 12V
5.5
6.1
6.6
V
VDRV 5V Output Voltage (Note 9)
VDD > 5.5V; 0 to 80mA
4.5
5.25
5.5
V
0.54
5.5
V
-1
1
% VOUT
OUTPUT CHARACTERISTICS
Output Voltage Adjustment Range
VIN > VOUT + 1.1V
Output Voltage Set-point Accuracy (Note 11)
Across line, load, temperature variation
Output Voltage Set-point Resolution (Note 10)
Set using PMBus™ command
Output Voltage Positive Sensing Bias Current
VSENP = 4V (negative = sinking)
Output Voltage Negative Sensing Bias Current
VSENN = 0V
±0.025
-100
20
% VOUT
100
20
µA
µA
Logic Input/Output Characteristics
Logic Input Leakage Current
Logic I/O - multi-mode pins
-100
Logic Input Low, VIL
Logic Input High, VIH
nA
0.8
V
2
Logic Output Low, VOL
2mA sinking
Logic Output High, VOH
2mA sourcing
FN8614 Rev.3.00
March 27, 2015
100
V
0.5
2.25
V
V
Page 9 of 87
ZL8801
Electrical Specifications
range, TA -40°C to +85°C. (Continued)
VDD = 12V. Typical values are at TA = +25°C. Boldface limits apply across the operating ambient temperature
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 14)
UNITS
0.5
V
PWM INPUT/OUTPUT CHARACTERISTICS
PWM Output Low
2mA sinking
PWM Output High
2mA sourcing
4.25
V
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
Switching Frequency Set-point Accuracy
200
1334
kHz
-5
5
%
Minimum SYNC Pulse Width
50% to 50%
150
Input Clock Frequency Drift Tolerance
Maximum allowed drift of external clock
-10
10
%
100
400
kHz
PMBus™ Clock Frequency (Note 12)
ns
POWER MANAGEMENT
SOFT-START/RAMP CHARACTERISTICS
tON Delay/tOFF Delay
Factory default
tON Delay/tOFF Delay Range
Set using PMBus™ command
tON Delay/TOFF Delay Accuracy
Turn on, Turn off delay
tON Ramp/tOFF Ramp Duration
Factory default (2-phase only)
tON Ramp/tOFF Ramp Duration Range
Set using PMBus™ command (2-phase only)
tON Ramp/tOFF Ramp Duration Accuracy
(2-phase only)
5
ms
4
5000
-0/+2
ms
ms
5
ms
5
100
±250
ms
µs
TRACKING
VTRK Input Bias Current
VTRK = 5V
VTRK Regulation Accuracy
100% Tracking, VOUT – VTRK (2-phase only)
70
-2
200
µA
2
% VOUT
POWER-GOOD
Power-good VOUT Threshold
Factory default
90
% VOUT
Power-good VOUT Hysteresis
Factory default
5
%
Power-good Delay
Applies to turn-on only (Low-to-high transition)
Factory default
1
ms
Set using PMBus™ command
0
5000
ms
MONITORING AND FAULT MANAGEMENT
INPUT VOLTAGE MONITOR AND FAULT DETECTION
VDD/VIN UVLO Threshold Range
2.85
16
V
VDD/VIN Monitor Accuracy
Full Scale (FS) = 14V
±2
% FS
VDD/VIN Monitor Resolution
Full Scale (FS) = 14V
±0.15
%
100
µs
VIN UV/OV Fault Response Delay
INPUT CURRENT
Input Current Sense Differential Input Voltage
VIINP to VIINN
Input Current Sense Input Offset Voltage
VIINP to VIINN
Input Current Sense Accuracy
% of Full Scale (20mV)
0
20
mV
±100
µV
±5
% FS
OUTPUT VOLTAGE MONITOR AND FAULT DETECTION
VOUT Monitor Accuracy
FS = VSET voltage (VOUT)
VOUT Monitor Resolution
FS = VSET voltage (VOUT)
VOUT UV/OV Fault Response Delay
-2
2
% FS
± 0.15
% FS
10
µs
OUTPUT CURRENT
OUTPUT CURRENT SENSE INPUT RESOLUTION
Low Range
±25mV Full Scale
37.5
µV
Medium Range
±35mV Full Scale
56.25
µV
High Range
±50mV Full Scale
75
µV
FN8614 Rev.3.00
March 27, 2015
Page 10 of 87
ZL8801
Electrical Specifications
range, TA -40°C to +85°C. (Continued)
VDD = 12V. Typical values are at TA = +25°C. Boldface limits apply across the operating ambient temperature
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 14)
UNITS
OUTPUT CURRENT SENSE INPUT BIAS CURRENT
VOUT Referenced
ISENA0 or ISENA1
-100
100
nA
ISENB0 or ISENB1
-25
25
µA
OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION
IOUT Monitor Temperature Compensation
Factory default
3900
ppm/°C
Configurable via PMBus™
100
12700
ppm/°C
Using VMON pin with 16:1 resistor divider
2.85
5
V
VMON BIAS MONITOR AND FAULT DETECTION
VMON UVLO Threshold Range
VMON Accuracy (Note 13)
Full Scale (FS) = 1.15V
VMON Resolution
Full Scale (FS) = 1.15V
-2
VMON UV/OV Fault Response Delay
2
% FS
±0.15
% FS
200
µs
TEMPERATURE SENSING
INTERNAL TEMPERATURE SENSOR
Internal Temperature Accuracy
Tested at +100°C
-5
Internal Temperature Resolution
Thermal Protection Threshold
(junction temperature)
5
1
Factory default
Configurable via PMBus™
°C
125
-40
Thermal Protection Hysteresis
°C
°C
125
°C
15
°C
±5
°C
EXTERNAL TEMPERATURE SENSOR: XTEMP0 and XTEMP1
External Temperature Accuracy
External Temperature Resolution
Thermal Protection Threshold
Factory default
Configurable via PMBus™
1
°C
125
°C
-40
Thermal Protection Hysteresis
125
15
°C
°C
NOTES:
9. Output current is limited by device thermal dissipation.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. VOUT measured at the termination of the VSENP and VSENN sense points.
12. For operation at 400kHz, see PMBus™ Power System Management Protocol Specification Part 1, Section 5.2.6.2 for timing parameter limits.
13. Does not include errors due to resistor divider tolerances.
14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN8614 Rev.3.00
March 27, 2015
Page 11 of 87
ZL8801
ZL8801 Overview
Digital-DC Architecture Overview
The ZL8801 is an innovative mixed-signal power conversion and
power management IC based on Intersil patented Digital-DC
technology that provides an integrated, high performance
step-down converter for a wide variety of power supply
applications.
The ZL8801 DC/DC controller is a dual phase controller based on
an architecture that does not require loop compensation. Adaptive
algorithms enable the power converter to automatically change
the operating state to increase efficiency and overall performance
with no user interaction needed.
The ZL8801 is a full digital loop that achieves precise control of
the entire power conversion process with no software required
resulting in a very flexible device that is also very easy to use. The
ChargeMode control algorithm is implemented that responds to
output current changes within a single PWM switching cycle,
achieving a smaller total output voltage variation with less output
capacitance than traditional PWM controllers. An extensive set of
power management functions are fully integrated and can be
configured using simple pin connections. The user configuration
can be saved in an internal nonvolatile memory (NVRAM).
Additionally, all functions can be configured and monitored via
the SMBus hardware interface using standard PMBus™
commands, allowing ultimate flexibility. The ZL8801 is compliant
with the PMBus™ Power System Management Protocol
Specification Part I and II version 1.2.
Once enabled, the ZL8801 is immediately ready to regulate
power and perform power management tasks with no
programming required. Advanced configuration options and
real-time configuration changes are available via PMBus™
commands if desired and continuous monitoring of multiple
operating parameters is possible with minimal interaction from a
host controller. Integrated subregulation circuitry enables single
supply operation from any supply between 4.5V and 14V with no
bias supplies needed.
The ZL8801 can be configured by simply connecting its pins
according to the tables provided in the following sections.
Additionally, a comprehensive set of online tools and application
notes are available to help simplify the design process. An
evaluation board is also available to help the user become
familiar with the device. This board can be evaluated as a
standalone platform using pin configuration settings. A
Windows™ based GUI is also provided to enable full configuration
and monitoring capability via the SMBus interface and the
included USB cable.
Power Management Overview
The ZL8801 incorporates a wide range of configurable power
management features that are simple to implement with no
external components. Additionally, the ZL8801 includes circuit
protection features that continuously safeguard the device and load
from damage due to unexpected system faults. The ZL8801 can
continuously monitor input voltage and current, output voltage and
current, internal temperature and the temperature of an external
thermal diode. A power-good output signal is also included to enable
power-on reset functionality for an external processor.
FN8614 Rev.3.00
March 27, 2015
All power management functions can be configured using either
pin configuration techniques described in this document or via
the SMBus interface using PMBus™ commands. Monitoring
parameters can also be preconfigured to provide alerts for
specific conditions. “PMBus™ Command Detail” starting on
page 30, contains a listing of all the PMBus™ commands
supported by the ZL8801 and a detailed description of the use of
each of these commands.
Multi-mode Pins
In order to simplify circuit design, the ZL8801 incorporates
patented multi-mode pins that allow the user to easily configure
many aspects of the device with no programming. Most power
management features can be configured using these pins. The
multi-mode pins can respond to four different connections as
shown in Table 2. These pins are sampled when power is applied.
Pin-strap Settings: This is the simplest implementation method,
as no external components are required. Using this method, each
pin can take on one of three possible states: LOW, OPEN, or
HIGH. These pins can be connected to the V25 pin for logic HIGH
settings (excluding VDRVEN which should be left floating or tied
to VR5). Using a single pin, one of three settings can be selected.
TABLE 2. MULTI-MODE PIN CONFIGURATION
PIN TIED TO
VALUE
LOW (Logic LOW)
2.0 VDC
Resistor to SGND
Set by resistor value
V25
LOGIC
HIGH
MULTI-MODE
PIN
OPEN
MULTI-MODE
PIN
LOGIC
LOW
PIN-STRAP
SETTINGS
RESISTOR
SETTINGS
FIGURE 4. PIN-STRAP AND RESISTOR SETTING
Resistor Settings: This method allows a greater range of
adjustability when connecting a finite value resistor
(in a specified range) between the multi-mode pin and SGND.
Standard 1% resistor values are used and only every fourth E96
resistor value is used so the device can reliably recognize the
value of resistance connected to the pin while eliminating the
error associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
Page 12 of 87
ZL8801
SMBus: Almost any ZL8801 function can be configured via the
SMBus interface using standard PMBus™ commands.
Additionally, any value that has been configured using the
pin-strap or resistor setting methods can also be reconfigured
and/or verified via the SMBus. The “PMBus™ Command Detail”
section, starting on page 30, explains the use of the PMBus™
commands in detail.
Configurable Pins
Four operating parameters can be set using the pin-strap or
resistor setting method: The SMBus address (pin 5, SA), output
voltage (pin 10, VSET), switching frequency (pin 44, SYNC) and
input voltage undervoltage lockout (pin 13, UVLO).
The SMBus device address and the output voltage are the only
parameters that must be set by external pins. All other device
parameters can be set via the SMBus. The device address is set
using the SA pin. The output voltage is set using the VSET pin.
SMBus Device Address Selection (SA)
Output Voltage and VOUT_MAX Selection
(VSET)
The output voltage may be set to any voltage between 0.54V and
5.5V provided that the input voltage is higher than the desired
output voltage by at least 1.1V. Using the pin-strap method, VOUT
can be set to any of the voltages shown in Table 4. The VOUT can
also be set using a PMBus™ command. VOUT_MAX is also
determined by this pin-strap setting and is 10% greater than the
VSET voltage setting. VOUT_MAX can be set higher than this
pin-strap setting using the VOUT_MAX PMBus command.
TABLE 4.
RVSET
(kΩ)
VOUT
(V)
RVSET
(kΩ)
VOUT
(V)
LOW (SGND)
1.00
38.3
1.30
OPEN
1.20
42.2
1.40
HIGH (>2.0V)
2.50
46.4
1.50
10
0.60
51.1
1.60
When communicating with multiple SMBus devices using the
SMBus interface, each device must have its own unique address
so the host can distinguish between the devices. The device
address can be set according to the pin-strap options listed in
Table 3. The SMBus address cannot be changed with a PMBus™
command.
11
0.65
56.2
1.70
12.1
0.70
61.9
1.80
13.3
0.75
68.1
1.90
14.7
0.80
75
2.00
TABLE 3. SMBus DEVICE ADDRESS SELECTION
16.2
0.85
82.5
2.10
17.8
0.90
90.9
2.20
19.6
0.95
100
2.30
21.5
1.00
110
2.50
23.7
1.05
121
2.80
26.1
1.10
133
3.00
28.7
1.15
147
3.30
31.6
1.20
162
4.00
34.8
1.25
178
5.00
RSA
(kΩ)
SMBus
ADDRESS
RSA
(kΩ)
SMBus
ADDRESS
LOW (SGND)
26h
42.2
28h
OPEN
28h
46.4
29h
10
19h
51.1
2Ah
11
1Ah
56.2
2Bh
12.1
1Bh
61.9
2Ch
13.3
1Ch
68.1
2Dh
14.7
1Dh
75
2Eh
16.2
1Eh
82.5
2Fh
17.8
1Fh
90.9
30h
19.6
20h
100
31h
21.5
21h
110
32h
23.7
22h
121
33h
26.1
23h
133
34h
28.7
24h
147
35h
31.6
25h
162
36h
34.8
26h
178
37h
38.3
27h
FN8614 Rev.3.00
March 27, 2015
Page 13 of 87
ZL8801
Switching Frequency Setting (SYNC)
The device’s switching frequency is set from 200kHz to 1333kHz
using the pin-strap method as shown in Table 5, or by using a
PMBus™ command. The ZL8801 generates the device switching
frequency by dividing an internal precision 16MHz clock by
integers from 12 to 80. 500kHz (n = 32) and 1000kHz (n = 16)
are not recommended operating frequencies; use 533kHz
(or 516kHz if setting the frequency with PMBus) and 1067kHz
instead.
TABLE 5.
RSYNC
(kΩ)
FREQ
(kHz)
RSYNC
kΩ
FREQ
(kHz)
LOW (SGND)
200
23.7
471
OPEN
400
26.1
533
HIGH (>2.0V)
1067
28.7
571
10
200
31.6
615
11
222
34.8
727
12.1
242
38.3
800
13.3
267
42.2
842
14.7
296
46.4
889
16.2
320
51.1
1067
17.8
364
56.2
1143
19.6
400
61.9
1231
21.5
421
68.1
1333
The ZL8801 incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source for
other Intersil digital power devices.
The SYNC pin can also be configured as an input. When
configured as an input, the device will automatically check for a
clock signal on the SYNC pin each time EN is asserted. The
ZL8801’s oscillator will then synchronize with the rising edge of
the external clock.
The incoming clock signal must be in the range of 200kHz to
1.33MHz, meet the limits given in the “Logic Input/Output
Characteristics” on page 9 and must be stable when the enable
pin (EN) is asserted. When using an external clock, the
frequencies are not limited to discrete values as when using the
internal clock. The external clock signal must not vary more than
10% from its initial value and should have a minimum pulse
width of 150ns. In the event of a loss of the external clock signal,
the output voltage may show transient overshoot or undershoot.
If loss of synchronization occurs, the ZL8801 will automatically
switch to its internal oscillator and switch at its configured
frequency. For this reason, it is important to configure the
ZL8801 to a frequency close to the expected external clock
frequency.
The SYNC pin can also be configured as an output. The device will
run from its internal oscillator and will drive the SYNC pin so other
devices can be synchronized to it. The output will conform to the
FN8614 Rev.3.00
March 27, 2015
limits given in the “Logic Input/Output Characteristics” on page 9.
The SYNC pin will not be checked for an incoming clock signal
while in this mode.
The switching frequency can be set to any value between 200kHz
and 1.33MHz using a PMBus™ command. The available
frequencies below 1.33MHz are defined by fSW = 16MHz/N,
where 12 ≤ N ≤ 80.
If a value other than fSW = 16MHz/N is entered using a PMBus™
command, the internal circuitry will select the switching
frequency value using N as a whole number to achieve a value
close to the entered value. For example, if 810kHz is entered, the
device will select 800kHz (N = 20).
Input Voltage Undervoltage Lockout Setting
(UVLO)
The input undervoltage lockout (UVLO) prevents the ZL8801 from
operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The input
voltage undervoltage lockout threshold can be set between
2.85V and 16V using the pin-strap method as shown in Table 6.
The UVLO can also be set or changed using the
VIN_UV_FAULT_LIMIT command.
TABLE 6.
RUVLO
(kΩ)
UVLO
(V)
RUVLO
(kΩ)
UVLO
(V)
LOW (SGND)
Not used
46.4
7.42
OPEN
4.5
51.1
8.18
HIGH (>2.0V)
10.8
56.2
8.99
26.1
4.18
61.9
9.90
28.7
4.59
68.1
10.90
31.6
5.06
75
12.00
34.8
5.57
82.5
13.20
38.3
6.13
90.9
14.54
42.2
6.75
100
16.00
Once an input undervoltage fault condition occurs, the user may
determine the desired response to the fault condition. The
following input undervoltage protection response options are
available:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an undervoltage fault is to shut down
and stay off until the fault has cleared and the device has been
disabled and reenabled (see option 1).
Refer to “PMBus™ Command Detail”, starting on page 30 of this
document, for details on how to select specific undervoltage fault
response options using the VIN_UV_FAULT_RESPONSE
command.
When controlling the ZL8801 exclusively through the PMBus™, a
high voltage setting for UVLO can be used to prevent the ZL8801
from being enabled until a lower voltage for UVLO is set using the
VIN_UV_FAULT_LIMIT command.
Page 14 of 87
ZL8801
Internal Bias Regulators and Input Supply
Connections
VDD
VDD
The ZL8801 employs internal low dropout (LDO) regulators to
supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
follows:
VR6
VR6
VR5
VR5
VR6: The VR6 LDO provides a regulated 6.1V bias supply for
internal circuitry. It is powered from the VDD pin. A 4.7µF
ceramic X7R filter capacitor to SGND is required at the VR6 pin.
Keep this net as small as possible and avoid routing this net near
any switching signals.
VR5: The VR5 LDO provides a regulated 5.1V bias supply for
internal circuitry. It is powered from the VDD pin. A 4.7µF
ceramic X7R filter capacitor to SGND is required at the VR5 pin.
This supply may be used for to provide a pull-up supply as long as
load current does not exceed 5mA.
V25: The V25 LDO provides a regulated 2.5V bias supply for the
main controller circuitry. It is powered from an internal 5V node.
A 4.7µF ceramic X7R filter capacitor to SGND is required at the
V25 pin. The V25 supply is used to power internal IC circuitry. It
should only be used externally to set pin-strap pins to the HIGH
state.
VDRV: The VDRV LDO provides a regulated 5.25V bias supply for
external MOSFET driver ICs or DrMOS integrated drivers/FETs. A
4.7µF ceramic X7R filter capacitor to PGND is required, however,
additional capacitance will be needed as specified by the
MOSFET driver or DrMOS device selected. The maximum rated
output current is 80mA, but device thermal limits must be
considered. The power dissipated by the VDRV supply, as shown
by Equation 1.
VIN – 5.25V x IDRV
(EQ. 1)
where IDRV is the current supplied by the VDRV bias supply. The
VDRV is enabled by leaving the VDRVEN unconnected (floating)
or connecting it to VR5 and is disabled by connecting VDRVEN to
ground.
NOTE: The internal bias regulators, VR6, VR5 and V25, are not
designed to be outputs for powering other circuitry. The
multi-mode pins may be connected to the V25 pin for logic HIGH
settings and the VR5 supply should be used to provide up to 5mA
of pull-up current for the SDA, SCL, SALRT, DDC and PG pins.
Operation with 5V VDD: When operating the ZL8801 at voltages
below 5.5V, the VR6 and VR5 supplies should be connected
directly to VDD for best performance. The VDRV supply should not
be used; the 5V VDD supply should be used instead for powering
DrMOS and MOSFET driver ICs.
VIN
VIN
4.5V < VIN < 5.5V
5.5V < VIN < 14V
FIGURE 5.
Start-up Procedure
The ZL8801 follows a specific internal start-up procedure after
power is applied to the VDD pin, as shown in Figure 6.
The device requires approximately 30ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded.
Once this process is completed, the device is ready to accept
commands via the serial interface and the device is ready to be
enabled. If the device is to be synchronized to an external clock
source, the clock frequency must be stable prior to asserting the
EN pin. Once enabled, the device requires approximately 2ms
before its output voltage may be allowed to start its ramp-up
process.
After the TON_DELAY period has expired, the output will begin to
ramp towards its target voltage according to the preconfigured
ton-rise time.
INPUT POWER APPLIED
PRE-RAMP DELAY
MINIMUM 2ms
DELAY BETWEEN ENABLE
SIGNAL AND START OF
OUTPUT RAMP.
ADDITIONAL DELAY MAY
BE ADDED WITH PMBUS
COMMAND
INTERNAL MEMORY
CHECK
20ms TO 30ms
DEVICE WILL IGNORE AN
ENABLE SIGNAL OR
PMBUS COMMANDS
DEVICE READY
FIGURE 6. ZL8801 INTERNAL START-UP PROCEDURE
The VIN should be above the ZL8801’s UVLO limit
(VIN_UV_FAULT_LIMIT) before the Enable pin is driven high.
Following this sequence will result in the most consistent turn-on
delays. When VIN is first applied to the ZL8801, for example
during initial PCB turn-on and test, the Enable pin must be held
low by some means until the ZL8801 configuration file can be
loaded. If the Enable pin is not held low, then the ZL8801 may
attempt to turn-on with incorrect configuration settings, possibly
causing circuit failure.
FN8614 Rev.3.00
March 27, 2015
Page 15 of 87
ZL8801
In those cases where the Enable pin cannot be held low during
the initial application of power, two options are available:
1. Limit VIN to 3.0V during initial testing. The ZL8801
configuration file can be loaded when VIN is as low as 3V.
Once the configuration file is loaded VIN can be increased to
the normal input voltage range.
2. Use a 100kΩ resistor to set UVLO to 16V. This will keep the
ZL8801 disabled while the configuration file is loaded. Ensure
that the VIN_UV_FAULT_LIMIT command is the last command
in the configuration file.
circuit. When the ZL8801 is used in a self-enabled mode, for
example, when EN is tied to VR5, or to a resistor divider to VIN,
the user must consider the ZL8801's default factory settings.
When a configuration file is used to configure the ZL8801, the
factory default settings are restored to both the user and default
stores in order to set the ZL8801 to an initialized state. Since the
default state of the ZL8801 is to be enabled when the enable pin
is high, it is possible for the ZL8801 to be enabled while the
PMBus™ commands are sent to the ZL8801 during the
configuration process. For this reason self-enabled mode is not
recommended for the ZL8801.
TON Delay and Rise Times
Power-good
In some applications, it may be necessary to set a delay from
when an enable signal is received until the output voltage starts
to ramp to its target value. In addition, the designer may wish to
precisely set the time required for VOUT to ramp to its target
value after the delay period has expired. The ZL8801 gives the
system designer the ability to independently control both the
delay and ramp time periods.
The ZL8801 provides a power-good (PG) signal that indicates the
output voltage is within a specified tolerance of its target level
and no fault condition exists. By default, the PG pin will assert if
the output is within 10% of the target voltage. These limits may
be changed using PMBus™ commands.
The TON_DELAY time begins when the EN pin is asserted. The
TON_DELAY time is set using the PMBus™ command TON_DELAY.
The TON-RISE time enables a precisely controlled ramp to the
nominal VOUT value that begins once the TON_DELAY time has
expired. The ramp-up is monotonic and its slope may be precisely
set using the PMBus™ command TON_RISE.
The TON_DELAY and TON_RAMP times can be set using
PMBus™ commands TON_DELAY and TON_RISE over the serial
bus interface. When the TON_DELAY time is set to 0ms, the
device will begin its ramp after the internal circuitry has
initialized.
The TON_DELAY and TON_RAMP times can be set using PMBus™
commands TON_DELAY and TON_RISE over the serial bus
interface. When the TON_DELAY time is set to 0ms, the device
will begin its ramp after the internal circuitry has initialized which
takes approximately 2ms to complete. The TON_RISE time may
be set to values less than 2ms, however the TON_RISE time
should be set to a value greater than 500µs to prevent
inadvertent fault conditions due to excessive inrush current. A
lower TON_RISE time limit can be estimated using the formula
as shown by Equation 2.
TON_RISE = C OUT *V OUT
(EQ. 2)
Where COUT is the total output capacitance, VOUT is the output
voltage and limit is the current limit setting for the ZL8801.
When interdevice current sharing is used (4-, 6- or 8- phases), the
output voltage rise time will vary by application. The rise time in
this case can be adjusted using the PMBus command
MULTI_PHASE_RAMP_GAIN. Higher gain values produce faster
turn-on ramps. Typical MULTI_PHASE_RAMP_GAIN values range
between 1 and 10; the default value is 3.
Enable
The enable pin (EN) is used to enable and disable the ZL8801.
The enable pin should be held low whenever a configuration file
or script is used to configure the ZL8801, or a PMBus™
command is sent that could potentially damage the application
FN8614 Rev.3.00
March 27, 2015
A PG delay period is defined as the time from when all conditions
within the ZL8801 for asserting PG are met to when the PG pin is
actually asserted. This feature is commonly used instead of using
an external reset controller to control external digital logic. By
default, the ZL8801 PG delay is set equal to 1ms. The PG delay
may be set using a PMBus™ command as described in the
“PMBus™ Command Summary” on page 25.
Power Management Functional
Description
Output Overvoltage Protection
The ZL8801 offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSEN pins) to a programmable threshold set
to 10% higher than the target output voltage (the default setting).
If the VSEN voltage exceeds this threshold, the PG pin will
deassert and the device can then respond to the following
options:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an overvoltage fault is to shut down
and stay off until the fault has cleared and the device has been
disabled and reenabled (see option 1).
Refer to the “PMBus™ Command Detail” section, starting on
page 30, for details on how to select specific overvoltage fault
response options using the VOUT_OV_FAULT_RESPONSE
command.
Output Prebias Protection
The ZL8801 provides prebiased start-up operation. An output
prebias condition exists when an externally applied voltage is
present on a power supply's output before the power supply's
control IC is enabled. Certain applications require that the
converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ZL8801 provides
Page 16 of 87
ZL8801
prebias protection by sampling the output voltage prior to
initiating an output ramp. If a prebias voltage lower than the
desired output voltage is present after the TON_DELAY time, the
ZL8801 starts switching with a duty cycle that matches the
prebias voltage. This ensures that the ramp-up from the prebias
voltage is monotonic. The output voltage is then ramped to the
desired output voltage at the ramp rate set by the TON_RISE
command. The resulting output voltage rise time will vary
depending on the prebias voltage, but the total time elapsed
from the end of the TON_DELAY time to when the TON-RISE time
is complete and the output is at the desired value will match the
preconfigured ramp time (see Figure 7).
VOUT
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an overcurrent voltage fault is to shut
down and stay off until the fault has cleared and the device has
been disabled and reenabled (see option 1).
Refer to the “PMBus™ Command Detail” section, starting on
page 30, for details on how to select specific overcurrent fault
response options using the IOUT_OC_FAULT_RESPONSE
command.
CURRENT SENSING COMPONENTS
The ZL8801 uses the inductor DCR current sensing technique.
Current sensing is achieved by selecting an R/C network as
shown in Figure 8.
DESIRED
OUTPUT
VOLTAGE
PREBIAS
VOLTAGE
VIN
VDRV
PWMH
tON
DELAY
tON
RISE
TIME
PWML
DRIVER
VDD
ZL8801
VPREBIAS < VTARGET
GH
VOUT
GL
R1
C1
ISENA
VOUT
ISENB
PREBIAS
VOLTAGE
FIGURE 8. DCR CURRENT SENSING (ONLY 1 PHASE SHOWN)
DESIRED
OUTPUT
VOLTAGE
For the voltage across C1 to reflect the voltage across the DCR of
the inductor, the time constant of the inductor must match the
time constant of the RC network, as shown in Equation 3:
RC L / DCR
tON
DELAY
tON
RISE
TIME
VPREBIAS > VTARGET
FIGURE 7. OUTPUT RESPONSES TO PREBIAS VOLTAGES
If a prebias voltage higher than the target voltage exists after the
preconfigured TON-DELAY time and TON-RISE time have
completed, the ZL8801 starts switching with a duty cycle that
matches the prebias voltage. This ensures that the ramp down
from the prebias voltage is monotonic. The output voltage is then
ramped down to the desired output voltage.
If a prebias voltage higher than the overvoltage limit exists, the
device will not initiate a turn on sequence and will stay off with
an output OV fault recorded.
Output Overcurrent Protection
The ZL8801 can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. Once the current limit threshold has been selected
(see “Current Limit Configuration” on page 18), the user may
determine the desired response to the fault condition. The
following overcurrent protection response options are available:
FN8614 Rev.3.00
March 27, 2015
L
BST
R1 C1
L
DCR
(EQ. 3)
For L, use the average of the nominal value and the minimum
value. Include the effects of tolerance, DC bias and switching
frequency on the inductance when determining the minimum
value of L. Use the typical room temperature value for DCR.
The value of R1 should be as small as feasible and no greater
than 5kΩ for best signal-to-noise ratio. The designer should make
sure the resistor package size is appropriate for the power
dissipated and include this loss in efficiency calculations. In
calculating the minimum value of R1, the average voltage across
C1 (which is the average IOUT, DCR product) is small and can be
neglected. Therefore, the minimum value of R1 may be
approximated by Equation 4:
V IN – V OUT V OUT
R1 min = -----------------------------------------------------------
P R1
(EQ. 4)
where PR1 is the maximum power dissipation specification for
the resistor. Once R1min has been calculated, solve for the
maximum value of C1 from Equation 5:
C1max
L
R1min DCR
(EQ. 5)
Page 17 of 87
ZL8801
Choose the next lowest readily available value (e.g., for
C1max = 1.86µF, C1 = 1.5µF is a good choice). Then substitute
the chosen value into the same equation and recalculate the
value of R1. Choose the 1% resistor standard value closest to this
recalculated value of R1.
Current Limit Configuration
The ZL8801 gives the power supply designer several choices for
the fault response during over or undercurrent condition. The
user can select the number of violations allowed before declaring
fault, a blanking time and the action taken when a fault is
detected. These parameters are configured using the
ISENSE_CONFIG command.
The blanking time represents the time when no current
measurement is taken. This is to avoid taking a reading just after
a switching transition (less accuracy due to potential ringing). It is
a configurable parameter from 0 to 832ns.
The ZL8801 provides an adjustable maximum full scale sensing
range. Three ranges are available: ±25mV, ±35mV and ±50mV
maximum input voltage.
By default, current sensing is enabled during the inductor current
down slope period of the switching period (D). In applications
where the steady state duty cycle is >0.5, for example a 5V to
3.3V converter, the ZL8801 can be configured to sense current
during the inductor up slope period of the switching cycle (D).
The user has the option of selecting how many consecutive
overcurrent readings must occur before an overcurrent fault and
subsequent shutdown are initiated. Either 1, 3, 5, 7, 9, 11, 13 or
15 consecutive faults can be selected.
Once the ISENSE_CONFIG parameters have been selected, the
user must select the desired current limit thresholds and the
resistance of the sensing element.
The current limit thresholds are set with 4 commands:
1. IOUT_OC_FAULT_LIMIT – this sets the overcurrent threshold
that must be exceeded by the number of consecutive times
chosen in ISENSE_CONFIG.
2. IOUT_UC_FAULT_LIMIT – this is the same as
IOUT_OC_FAULT_LIMIT, but represents the negative current
that flows in the lower FET during the D’ interval. Large
negative currents can flow during faults such as when a
higher voltage rail is shorted to a lower voltage rail.
3. IOUT_AVG_OC_FAULT_LIMIT – this limit is similar to
IOUT_OC_FAULT_LIMIT, but the limit represents an average
reading over several switching cycles. Since it is an average,
the response time is slower, but the limit can be set closer to
the maximum average expected output current.
4. IOUT_AVG_UC_FAULT_LIMIT – this limit is similar to
IOUT_AVG_OC_FAULT_LIMIT, but represents the negative
current that flows in the lower FET during the D’ interval.
Input Current Monitor
The input current can be monitored through the IINN and IINP
pins. The input current monitor input should be connected across
a current sensing resistor in series with the input supply. The IINP
pin is connected to the input supply side of the current sense
resistor, the IINN pin is connected to the ZL8801 VDD side of the
FN8614 Rev.3.00
March 27, 2015
current sense resistor. Using the IIN_SCALE command, set the
current sense resistor value. Select the current sense resistor
value such that the maximum expected input current times the
current sense resistor value does not exceed the maximum
current sensing input voltage of 20mV. If this feature is not used,
IINN and IINP should be tied to VDD.
Thermal Overload Protection
The ZL8801 includes an on-chip thermal sensor that continuously
measures the internal temperature of the die. This thermal
sensor is used to provide both over-temperature and
under-temperature protection. If the over-temperature limit is
exceeded, or the temperature falls below the under-temperature
limit, the ZL8801 is shut down. The over-temperature and
under-temperature limits are set by the OT_FAULT_LIMIT and
UT_FAULT_LIMIT respectively. The ZL8801 will not attempt to
restart until the temperature has fallen below the
OT_WARN_LIMIT for over-temperature faults or has risen above
the UT_WARN_LIMIT for under-temperature faults. The default
temperature limits are +125°C and -45°C, but the user may set
the limits to different values if desired. Note that setting a higher
over-temperature or under-temperature limit may result in
permanent damage to the device. Once the device has been
disabled due to an internal temperature fault, the user may
select one of the fault response options as follows:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an over-temperature or
under-temperature fault is to shut down and stay off until the
fault has cleared and the device has been disabled and
reenabled (see option 1).
Refer to the “PMBus™ Command Detail” section, starting on
page 30, for details on how to select specific over-temperature or
under-temperature fault response options using the
OT_FAULT_RESPONSE and UT_FAULT_ RESPONSE commands.
Voltage Tracking
Numerous high performance systems place stringent demands
on the order in which the power supply voltages are turned on.
This is particularly true when powering FPGAs, ASICs and other
advanced processor devices that require multiple supply voltages
to power a single die. In most cases, the I/O interface operates at
a higher voltage than the core and therefore the core supply
voltage must not exceed the I/O supply voltage according to the
manufacturers' specifications.
The ZL8801 integrates a tracking scheme that allows its output
to track a voltage that is applied to the VTRK pin with no external
components required. The VTRK pin is an analog input that,
when tracking mode is enabled, configures the voltage applied to
the VTRK pin to act as a reference for the device’s output
regulation. Tracking can only be used when operating as a
2-phase controller, i.e.; when the device is not part of a current
sharing group.
Page 18 of 87
ZL8801
Figure 9 illustrates the typical connection and the two tracking
modes:
Coincident: This mode configures the ZL8801 to ramp its output
voltage at the same rate as the voltage applied to the VTRK pin.
Ratiometric. This mode configures the ZL8801 to ramp its output
voltage at a rate that is a percentage of the voltage applied to the
VTRK pin. The default setting is 50%, but an external resistor
string may be used to configure a different tracking ratio. The
device that is tracking another output voltage (slave) must be set
to its desired steady-state output voltage.
The master ZL8801 device in a tracking group is defined as the
device that has the highest target output voltage within the
group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode.
The maximum tracking rise-time is 1V/ms. The slave device
must be enabled before the master.
Any device that is configured for tracking mode will ignore its
TON_DELAY and TON_RISE settings and its output will take on
the turn-on/turn-off characteristics of the reference voltage
present at the VTRK pin.
Tracking mode can be configured by using the TRACK_CONFIG
command.
VOUT
VTRACK
VOUT
TIME
COINCIDENT
VOUT
VTRACK
VOUT
TIME
RATIOMETRIC
FIGURE 9. TRACKING MODES
Voltage Margining
The ZL8801 offers a simple means to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. Margining is controlled through the
OPERATION command.
FN8614 Rev.3.00
March 27, 2015
Default margin limits of VOUT ±5% are preloaded in the factory,
but the margin limits can be modified through to be as high as
5.5V or as low as 0V.
Additionally, the transition rate between the nominal output
voltage and either margin limit can be configured using the
VOUT_TRANSITION_RATE command.
External Voltage Monitoring
The voltage monitoring (VMON) pin is available to monitor the
voltage supply for the external driver IC. The VMON input must be
scaled by a 16:1 ratio in order to read-back the VMON voltage
correctly. A 100kΩ and 6.65kΩ resistor divider is recommended.
Overvoltage and undervoltage fault thresholds can be set using
MFR_VMON_OV_FAULT_LIMIT and MFR_ VMON_UV_FAULT_LIMIT
commands. The response to these limits are set using the
VMON_OV_FAULT_RESPONSE and VMON_ UV_FAULT_RESPONSE
commands.
Once the device has been disabled due to VMON fault, the user
may select one of the following fault response option:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an overvoltage or undervoltage VMON
fault is to shut down and stay off until the fault has cleared and
the device has been disabled and reenabled (see option 1).
SMBus Communications
The ZL8801 provides a SMBus digital interface. The ZL8801 can
be used with any standard 2-wire SMBus host device. In addition,
the device is compatible with SMBus version 2.0 and includes an
SALRT line to help mitigate bandwidth limitations related to
continuous fault monitoring. Pull-up resistors are required on the
SMBus. The pull-up resistor may be tied to VR5 or to an external
3.3V or 5V supply as long as this voltage is present prior to or
during device power-up. The ideal design will use a central pull-up
resistor that is well-matched to the total load capacitance. The
minimum pull-up resistance should be limited to a value that
enables any device to assert the bus to a voltage that will ensure
a logic 0 (typically 0.8V at the device monitoring point) given the
pull-up voltage (5V if tied to VR5) and the pull-down current
capability of the ZL8801 (nominally 4mA). A pull-up resistor of
10kΩ is a good value for most applications.
The SMBus Data and Clock lines should be routed with a closely
coupled return or ground plane to minimize coupled interference
(noise). Excessive noise on the data and clock lines that cause
the voltage on these lines to cross the high and low logic
thresholds of 2.0V and 0.8V respectively, will cause command
transmissions to be interrupted and result in slow bus operation
or missed commands. For less than 10 devices on an SMBus, a
10kΩ resistor on each line provides good performance.
The ZL8801 accepts most standard PMBus™ commands. When
enabling the device with ON_OFF_CONFIG command, it is
recommended that the enable pin is tied to SGND.
In addition to bus noise considerations, it is important to ensure
that user connections to the SMBus are compliant to the
PMBus™ command standards. Any device that can malfunction
Page 19 of 87
ZL8801
in a way that permanently shorts SMBus lines will disable
PMBus™ communications. Incomplete PMBus™ commands can
also cause the ZL8801 to halt PMBus™ communications. This
can be corrected by disabling, then reenabling the device.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to communicate
between Intersil digital power Digital-DC devices. This dedicated bus
provides the communication channel between devices for features
such as sequencing, fault spreading and current sharing. The DDC
pin must be pulled up to an external 3.3V or 5.0V supply, even if the
ZL8801 is operating standalone. If the ZL8801 is used in a
standalone circuit and will not have its DDC pin connected to any
other devices, the ZL8801 DDC pin can be configured as a push-pull
output using the MFR_USER_CONFIG command and the pull-up
resistor can be eliminated. In addition, the DDC pin must be
pulled up (or configured as a push-pull output, with the limitations
listed previously) before the Enable pin is set high. The DDC pin on
all Digital-DC devices that utilize sequencing, fault spreading or
current sharing must be connected together. The DDC pin on all
Digital-DC devices in an application should be connected together. A
pull-up resistor is required on the DDC bus in order to guarantee the
rise time as shown by Equation 6:
Rise Time = R PU C LOAD 1s
(EQ. 6)
Where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to VR5 or to an
external 3.3V or 5V supply as long as this voltage is present prior
to or during device power-up. As a rule of thumb, each device
connected to the DDC bus presents approximately 12pF of
capacitive loading. The ideal design will use a central pull-up
resistor that is well matched to the total load capacitance. In
power module applications, the user should consider whether to
place the pull-up resistor on the module or on the PCB of the end
application. The minimum pull-up resistance should be limited to
a value that enables any device to assert the bus to a voltage that
will ensure a logic 0 (typically 0.8V at the device monitoring
point) given the pull-up voltage (5V if tied to VR5) and the
pull-down current capability of the ZL8801 (nominally 4mA). As
with SMBus data and clock lines, the DDC data line should be
routed with a closely coupled return or ground plane to minimize
coupled interference (noise). Excessive noise on the DDC signal
can cause the voltage on this line to cross the high and low logic
thresholds of 2.0V and 0.8V respectively and will cause
command transmissions to be interrupted and result in slow bus
operation or missed commands. For less than 10 devices on the
DDC bus, a 10kΩ resistor provides good performance.
Phase Spreading
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices have coincident rising
edges. Setting each converter to start its switching cycle at a
different point in time can dramatically reduce input capacitance
requirements. Since the peak current drawn from the input
supply is effectively spread out over a period of time, the peak
current drawn at any given moment is reduced and the power
losses proportional to IRMS2 are reduced.
FN8614 Rev.3.00
March 27, 2015
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. Configuring the SYNC
pin is described in the Configuration Pin on page 6 The ZL8801
will automatically offset the phase of parallel connected
ZL8801s in a current sharing group. Selecting the phase offset
for the device is accomplished by selecting a device address
according to Equation 7:
(EQ. 7)
Phase offset = device address 45
This behavior is illustrated in Table 7.
:
TABLE 7.
ADDRESS LSB
PHASE OFFSET
(°)
ADDRESS LSB
PHASE OFFSET
(°)
0
0
8
0
1
45
9
45
2
90
A
90
3
135
B
135
4
180
C
180
5
225
D
225
6
270
E
270
7
315
F
315
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments using the
INTERLEAVE PMBus™ command.
Output Sequencing
A group of Intersil digital power devices may be configured to
power-up in a predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs and ASICs
that require one supply to reach its operating voltage prior to
another supply reaching its operating voltage in order to avoid
latch-up from occurring. Multi-device sequencing can be
achieved by configuring each device using the SEQUENCE
PMBus™ command.
Multiple device sequencing is achieved by issuing PMBus™
commands to assign the preceding device in the sequencing
chain as well as the device that will follow in the sequencing
chain.
The enable (EN) pins of all devices in a sequencing group must be
tied together and driven high to initiate a sequenced turn on of
the group. Enable must be driven low to initiate a sequenced
turn off of the group. The DDC pins of all devices in a sequencing
group must be connected together to ensure accurate
sequencing.
Sequencing can also be accomplished by connecting the enable
pin of a sequel device to the power-good pin of a prequel device.
Sequencing is also achieved by using the TON_DELAY and
TON_RISE commands and choosing appropriate delay and rise
durations such that sequel devices start after their associated
prequel devices. The drawback to this method is that if a prequel
device fails to start properly, its sequel device will still start and
ramp on according to its delay and rise time settings. The best
sequencing performance is achieved by using the SEQUENCE
command and tying the Enable and DDC pins of the sequencing
Page 20 of 87
ZL8801
group devices together. If the DDC pins of the devices are not
connected together and the user depends on TON_DELAY and
TOFF_DELAY values alone to ensure device sequencing, timing
accuracy will suffer. This is due to the 0ms to 4ms delay
variability between ZL8801 devices.
VREFERENCE
VOUT
-R
Fault Spreading
Digital-DC devices can be configured to broadcast a fault event
over the DDC bus to the other devices in the group. When a fault
occurs and the device is configured to shut down on a fault, the
device will shut down and broadcast the fault event over the DDC
bus. The other devices on the DDC bus will shut down together if
configured to do so, and will attempt to restart in their prescribed
order if configured to do so.
Active Current Sharing
The PWM outputs of the ZL8801 are used in parallel to create a
dual phase power rail. The device outputs will share the current
equally within a few percent, assuming all external sensing
element variations and tolerances are negligible. Current sensing
element tolerances must be taken into account, or adjusted for
using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands in
any application.
Figure 10 shows a typical connection for a dual phase converter.
The ZL8801 will current share between phases without utilizing
output voltage droop.
Droop resistance is used in 4-, 6- and 8-phase current sharing to
add artificial resistance in the output voltage path to control the
slope of the load line curve, calibrating out the physical parasitic
mismatches due to power train components and PCB layout.
VMEMBER
-R
I MEMBER
IOUT
I REFERENCE
FIGURE 11. ACTIVE CURRENT SHARING
When current sharing up to 4 sets of ZL8801s (8 phases total),
the ZL8801 uses a low-bandwidth, first-order digital current
sharing technique to balance the unequal device output loading
by aligning the load lines of member devices to a reference
device.
Upon system start-up, the lowest numbered phase is defined as
the reference phase and all other phases are member phases.
The reference phase broadcasts its current over the DDC bus. The
member phases use the reference current information to trim
their reference voltages (VMEMBER) to balance the current
loading of each device in the system.
Figure 11 shows that, for load lines with identical slopes, the
member reference voltage is increased towards the reference
voltage, which closes the gap between the inductor currents.
The relation between reference and member current and voltage
is given by Equation 8:
VMEMBER VOUT R I REFERENCE I MEMBER
VIN
(EQ. 8)
Where R is the value of the droop resistance.
DRIVER
The ISHARE_CONFIG command is used to configure the device
for active current sharing. The default setting is a standalone non
current sharing, two-phase device. A current sharing rail can be
part of a system sequencing group.
VOUT
ZL8801
DRIVER
VI
N
FIGURE 10. DUAL PHASE SIMPLIFIED CIRCUIT
FN8614 Rev.3.00
March 27, 2015
A 4-, 6- or 8-phase current sharing group must have their DDC
and SYNC pins tied together in order to achieve current sensing
and accurate phase offsets between current sharing phases.
Temperature Monitoring Using XTEMP Pin
The ZL8801 supports measurement of an external device
temperature using either a thermal diode integrated in a
processor, FPGA or ASIC, or using a discrete diode-connected
2N3904 NPN transistor. Figure 12 illustrates the typical
connections required. A noise filtering capacitor, not exceeding
100pF, may be connected close to the ZL8801 XTEMP pins for
long or noisy trace runs. The external temperature sensors can
be used to provide the temperature reading for over-temperature
and under-temperature faults. The external sensors can also be
used to provide more accurate temperature compensation for
inductor DCR current sensing by being placed close to the
inductor. When routing the XTEMP signals between the inductor
and the ZL8801, these PCB traces should be kept away from the
switch node; (node connected the inductor to the MOSFET
switches).
Page 21 of 87
ZL8801
DUAL OUTPUT PWM PER PHASE
XTEMPxP
100pF
ZL
2N3904
The ZL8801 utilizes adaptive deadtime control to improve the
power conversion efficiency. The ZL8801 monitors the power
converter’s operating conditions and continuously adjusts the
turn-on and turn-off timing of the high-side and low-side driver
input signals to optimize the overall efficiency of the power supply.
XTEMPxN
DISCRETE NPN
XTEMPxP
µP
100pF
ZL
FPGA
DSP
ASIC
XTEMPxN
EMBEDDED THERMAL DIODE
FIGURE 12. EXTERNAL TEMPERATURE MONITORING
Nonvolatile Memory (NVRAM) and Security
Features
The ZL8801 has internal nonvolatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the device to a level that has been
made available to them. During the initialization process, the
ZL8801 checks for stored values contained in its internal
nonvolatile memory. The ZL8801 offers two internal memory
storage units that are accessible by the user as follows:
User Store: The User Store is the most commonly used store. It
provides the ability to modify certain power supply settings while
still protecting the equipment from modifying values that can
lead to a system level fault. The equipment manufacturer would
use the User Store to achieve this goal.
Default Store: The default store is less commonly used. It
provides a means to protect the circuit from damage by
preventing the user from modifying certain values that are
related to the physical construction of the circuit. In this case, the
Original Equipment Manufacturer (OEM) would use the “Default
Store” in a protected mode and allow the user to restore the
device to its default settings. In this case, the “User Store” would
be available to the end-user for making changes, but would
restrict the user from restoring the device to the factory settings
or modifying the default store.
The “User Store” takes priority over the “Default Store”. If there
are no values set in the “User or Default Store”, then the device
will use the pin-strap setting value.
For details regarding protection of the user and default stores,
see the PASSWORD PMBus command.
DC/DC Converter Design
The ZL8801 operates as a voltage-mode, synchronous buck
converter with a selectable constant frequency pulse width
modulator (PWM) control scheme that uses external driver,
MOSFETs, capacitors and an inductor to perform power
conversion.
FN8614 Rev.3.00
March 27, 2015
The ZL8801 has been designed to provide independent upper
and lower FET drive signals to a 2 input MOSFET driver such as
the ZL1505.
The ZL8801 can also be used with single-ended DrMOS
integrated driver and MOSFET devices. The DrMOS device or
single-ended MOSFET driver must have a fast-acting enable pin.
Power supplies using DrMOS devices can be made smaller than
discrete solutions utilizing separate drivers and MOSFETs, but at
a slightly lower efficiency. The option to use DrMOS or drivers and
discrete MOSFETs is set using the USER_CONFIG command.
Power Train Component Selection
The ZL8801 is a dual phase synchronous buck converter that
uses external Drivers, MOSFETs, inductors and capacitors to
perform the power conversion process. The proper selection of
the external components is critical for optimized performance.
To select the appropriate external components for the desired
performance goals, the power supply requirements listed in
Table 8 must be known.
TABLE 8. POWER SUPPLY REQUIREMENTS
PARAMETER
EXAMPLE VALUE
Input Voltage (VIN)
12V
Output Voltage (VOUT)
1.2V
Output Current (IOUT)
30A
Output Voltage Ripple (Vorip)
Output Load Step (Iostep)
Output Load Step Rate
Output Deviation Due to Load Step
Maximum PCB Temperature
Desired Efficiency
Other Considerations
1% of VOUT
50% of Io
10A/µs
±2%
+85°C
90%
Optimize for small size
DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency and cost. The inductor core
loss increases with frequency, so there is a trade-off between a
small output filter made possible by a higher switching frequency
and getting better power supply efficiency. Size can be decreased
by increasing the switching frequency at the expense of
efficiency. Cost can be minimized by using through-hole
inductors and capacitors; however these components are
physically large.
Page 22 of 87
ZL8801
To start the design, select a switching frequency based on
Table 9. This frequency is a starting point and may be adjusted as
the design progresses.
TABLE 9. CIRCUIT DESIGN CONSIDERATIONS
FREQUENCY RANGE
EFFICIENCY
CIRCUIT SIZE
200 to 400kHz
Highest
Larger
400 to 800kHz
Moderate
Smaller
800kHz to 1.33MHz
Lower
Smallest
INDUCTOR SELECTION
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
current (ΔIL), which will reduce output capacitance and produce a
low output ripple voltage, but may also compromise output
transient load performance. Therefore, a balance must be struck
between output ripple and optimal load transient performance. A
good starting point is to select the output inductor ripple equal to
30% to 50% of the maximum output current (IOUT).
ΔIL = 0.5*IOUT
OUTPUT CAPACITOR SELECTION
Several trade-offs must also be considered when selecting an
output capacitor. Low ESR values are needed to have a small
output deviation (Vstep) during transient load steps and low
output voltage ripple (ΔV). However, capacitors with low ESR,
such as X5R and X7R dielectric ceramic capacitors, also have
relatively low capacitance values. Many designs can use a
combination of high capacitance devices and low ESR devices in
parallel.
For high ripple currents, a low capacitance value can cause a
significant amount of output voltage ripple. Likewise, in high
transient load steps, a relatively large amount of capacitance is
needed to minimize the output voltage deviation while the
inductor current ramps up or down to the new steady state
output current value.
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to capacitance, as
shown in Equations 13 and 14:
8 f sw
Now the output inductance can be calculated using Equation 9,
where VIN is the input voltage:
V
VOUT 1 OUT
VIN
L
f sw I L
ESR
(EQ. 9)
The average inductor current is equal to the maximum output
current. The peak inductor current (ILpk) is calculated using
Equation 10, where IOUT is the maximum output current:
I Lpk I OUT
I
Select an inductor rated for the average DC current and with
saturation current rating above the peak current calculated.
Once an inductor is selected, the DCR and core losses in the
inductor are calculated. Use the DCR specified in the inductor
manufacturer’s datasheet, as shown in Equation 11:
PLDCR DCR I Lrms
2
(EQ. 11)
I L 2
(EQ. 12)
12
Where IOUT is the maximum output current. Next, calculate the
core loss of the selected inductor. Since this calculation is
specific to each inductor and manufacturer, refer to the chosen
inductor datasheet. Add the core loss and the ESR loss and
compare the total loss to the maximum power dissipation
recommendation in the inductor datasheet.
FN8614 Rev.3.00
March 27, 2015
(EQ. 13)
2
V
(EQ. 14)
2 I L
Use these values to make an initial capacitor selection, using a
single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output voltage
ripple can be calculated using Equation 15:
V I L ESR
I L
8 f sw COUT
(EQ. 15)
Because each part of this equation was made to be less than or
equal to half of the allowed output ripple voltage, the ΔV should
be less than the desired maximum output ripple.
ChargeMode control achieves a fast-acting, low deviation
transient response by detecting and reacting to very small
variations in the output voltage. ChargeMode control
performance is optimized when ΔV due to capacitor ripple is 1%
or less of the output voltage.
INPUT CAPACITOR
ILrms is given by Equation 12:
2
V
(EQ. 10)
2
I Lrms I OUT
I L
COUT
It is highly recommended that dedicated input capacitors be
used in any point-of-load design, even when the supply is
powered from a heavily filtered 5V or 12V “bulk” supply from an
off-line power supply. This is because of the high RMS ripple
current that is drawn by the buck converter topology. This ripple
(IinRMS) can be determined from Equation 16:
I inRMS I OUT D
(EQ. 16)
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated above the ripple current calculated above and
the maximum expected input voltage.
Page 23 of 87
ZL8801
QL SELECTION
MOSFET THERMAL CHECK
The bottom or lower MOSFET should be selected with the lowest
possible rDS(ON) while maintaining the desired circuit size and
cost.
Once the power dissipations for QH and QL have been calculated,
the MOSFET’s junction temperature can be estimated. Using the
junction to case thermal resistance (Rth) given in the MOSFET
manufacturer’s datasheet and the expected maximum printed
circuit board temperature, calculate the junction temperature
using Equation 25:
Calculate the RMS current in QL as shown by Equation 17:
I QLRMS I OUT 1 D
(EQ. 17)
Calculate the power dissipated due to rDS(ON) as shown in
Equation 18:
P QL = r DS ON I botrms 2
(EQ. 18)
NOTE: rDS(ON) given in the manufacturer’s datasheet is measured at
+25°C.
The actual rDS(ON) in the end-use application will be much higher.
Select a candidate MOSFET and calculate the required gate drive
current using Equation 19:
I g f SW Q g
(EQ. 19)
MOSFETs with lower rDS(ON) tend to have higher gate charge
requirements, which increases the current and resulting power
required to turn them on and off.
QH SELECTION
In addition to the rDS(ON) loss and gate charge loss, QH also has
switching loss. Select QH with a lower gate charge, keeping in
mind that QH’s rDS(ON) will be higher as a result. As was done
with QL, calculate the RMS current using Equations 20 and 21:
I QHRMS I OUT D
(EQ. 20)
P QH = r DS ON I QHRMS 2
(EQ. 21)
Next, calculate the switching time using Equation 22:
t SW
Qg
(EQ. 22)
I DR
where Qg is the gate charge of the selected QH and IDR is the
peak gate drive current available from the gate drive IC.
To calculate the switching time, use the ZL1505s minimum
guaranteed drive current of 3A for a conservative design. Using
the calculated switching time, calculate the switching power loss
in QH using Equation 23:
Pswtop V INM t sw I OUT f sw
(EQ. 23)
The total power dissipated by QH is given by Equation 24:
PQHtot PQH Pswtop
FN8614 Rev.3.00
March 27, 2015
T j max T pcb PQ Rth
(EQ. 25)
To calculate power losses and junction temperature rise in
DrMOS devices, consult the datasheet and application notes for
the DrMOS device selected.
EFFICIENCY OPTIMIZED DRIVER DEADTIME CONTROL
The ZL8801 utilizes a closed loop algorithm to optimize the
deadtime applied between the gate drive signals for the top and
bottom FETs. In a synchronous buck converter, the MOSFET drive
circuitry must be designed such that the top and bottom
MOSFETs are never in the conducting state at the same time.
Potentially damaging currents flow in the circuit if both top and
bottom MOSFETs are simultaneously on for periods of time
exceeding a few nanoseconds. Conversely, long periods of time in
which both MOSFETs are off, reduce overall circuit efficiency by
allowing current to flow in their parasitic body diodes.
It is therefore advantageous to minimize this deadtime to provide
optimum circuit efficiency. In the first order model of a buck
converter, the duty cycle is determined by Equation 26:
D
VOUT
VIN
(EQ. 26)
However, nonidealities exist that cause the real duty cycle to
extend beyond the ideal. Deadtime is one of those nonidealities
that can be manipulated to improve efficiency. The ZL8801 has
an internal algorithm that constantly adjusts deadtime
nonoverlap to minimize duty cycle, thus maximizing efficiency.
This circuit will null out deadtime differences due to component
variation, temperature and loading effects. This algorithm is
independent of application circuit parameters such as MOSFET
type, gate driver delays, rise and fall times and circuit layout. In
addition, it does not require drive or MOSFET voltage or current
waveform measurements. Adaptive deadtime is enabled using
the DEADTIME_CONFIG PMBus™ command. Adaptive deadtime
is only effective when a discrete driver (such as the ZL1505) and
MOSFETs are used. When DrMOS devices are selected using
USER_CONFIG, adaptive deadtime is automatically disabled.
Deadtime minimum and maximum limits can be set using the
DEADTIME PMBus™ command.
Monitoring via SMBus
(EQ. 24)
A system controller can monitor a wide variety of different
ZL8801 parameters through the SMBus interface. The device can
monitor for fault conditions by monitoring the SALRT pin, which
will be asserted when any number of preconfigured fault
conditions occur.
Page 24 of 87
ZL8801
The device can also be monitored continuously for any number of
power conversion parameters including but not limited to the
following:
• Input voltage
• Output voltage
The PMBus™ Host should respond to SALRT as follows:
1. ZL device pulls SALRT Low.
2. PMBus™ Host detects that SALRT is now low, performs
transmission with Alert Response Address to find which ZL
device is pulling SALRT low.
3. PMBus™ Host talks to the ZL device that has pulled SALRT
low. The actions that the host performs are up to the System
Designer.
• Input current
• Output current
• Internal junction temperature
If multiple devices are faulting, SALRT will still be low after doing
the above steps and will require transmission with the Alert
Response Address repeatedly until all faults are cleared.
• Temperature of an external device
• Switching frequency
Please refer to the “PMBus™ Command Detail” section, starting
on page 30, for details on how to monitor specific parameters via
the SMBus interface.
• Duty cycle
• Fault status information
PMBus™ Command Summary
CODE
COMMAND NAME
01h OPERATION
DESCRIPTION
Enable/disable, margin settings.
DATA
TYPE FORMAT
R/W
BIT
DEFAULT
VALUE
DEFAULT SETTING
00h
Immediate Off, Nominal Margin
02h ON_OFF_CONFIG
On/off configure settings.
R/W
BIT
17h
ENABLE Pin Control, Active High
03h CLEAR_FAULTS
Clears faults.
Write
N/A
N/A
N/A
11h STORE_DEFAULT_ALL
Stores values to default store.
Write
N/A
N/A
N/A
12h RESTORE_DEFAULT_ALL
Restores values from default store.
Write
N/A
N/A
N/A
15h STORE_USER_ALL
Stores values to user store.
Write
N/A
N/A
N/A
16h RESTORE_USER_ALL
Restores values from user store.
Write
N/A
N/A
N/A
BIT
13h
20h VOUT_MODE
Reports VOUT_COMMAND Mode value. Read
21h VOUT_COMMAND
Sets nominal VOUT setpoint.
R/W
L16u
13h, Fixed Value
Pin-strap Setting
23h VOUT_CAL_OFFSET
Applies offset voltage to VOUT setpoint. R/W
L16u
24h VOUT_MAX
Sets maximum VOUT setpoint.
R/W
L16u
1.10 X VOUT_COMMAND Pin-strap
Setting
25h VOUT_MARGIN_HIGH
Sets VOUT set point during margin high. R/W
L16u
1.05 x VOUT_COMMAND Pin-strap
Setting
26h VOUT_MARGIN_LOW
Sets VOUT setpoint during margin low.
R/W
L16u
0.95 x VOUT_COMMAND Pin-strap
Setting
27h VOUT_TRANSITION_RATE
Sets VOUT transition rate during margin R/W
commands.
L11
BA00h
1V/ms
28h VOUT_DROOP
Sets V/I slope for total rail output
current (all phases combined).
R/W
L11
0000h
0mV/A
33h FREQUENCY_SWITCH
Sets switching frequency.
R/W
L11
Pin-strap Setting
37h INTERLEAVE
Configures phase offset during group
operation.
R/W
BIT
Set by Pin-Strapped PMBus™
Address
40h VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault
threshold.
R/W
L16u
41h VOUT_OV_FAULT_RESPONSE
Sets the VOUT overvoltage fault
response.
R/W
BIT
44h VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault
threshold.
R/W
L16u
45h VOUT_UV_FAULT_RESPONSE
Sets the VOUT undervoltage fault
response.
R/W
BIT
80h
46h IOUT_OC_FAULT_LIMIT
Sets the IOUT peak overcurrent fault
threshold for each phase.
R/W
L11
DBC0h
FN8614 Rev.3.00
March 27, 2015
0000h
0V
1.15 x VOUT_COMMAND Pin-strap
Setting
80h
Disable, No Retry
0.85 x VOUT_COMMAND Pin-strap
Setting
Disable, No Retry
30A
Page 25 of 87
ZL8801
PMBus™ Command Summary
CODE
COMMAND NAME
(Continued)
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
4Bh IOUT_UC_FAULT_LIMIT
Sets the IOUT valley undercurrent fault
threshold for each phase.
R/W
L11
D440h
-15A
4Fh OT_FAULT_LIMIT
Sets the over-temperature fault limit.
R/W
L11
EBE8h
+125˚C
50h OT_FAULT_RESPONSE
Sets the over-temperature fault
response.
R/W
BIT
80h
51h OT_WARN_LIMIT
Sets the over-temperature warning
limit.
R/W
L11
EB70h
+110°C
52h UT_WARN_LIMIT
Sets the under-temperature warning
limit.
R/W
L11
DC40h
-30°C
53h UT_FAULT_LIMIT
Sets the under-temperature fault limit. R/W
L11
E530h
54h UT_FAULT_RESPONSE
Sets the under-temperature fault
response.
R/W
BIT
80h
55h VIN_OV_FAULT_LIMIT
Sets the VIN overvoltage fault threshold. R/W
L11
D380h
56h VIN_OV_FAULT_RESPONSE
Sets the VIN overvoltage fault response. R/W
BIT
80h
57h VIN_OV_WARN_LIMIT
Sets the VIN overvoltage warning
threshold.
R/W
L11
D360h
58h VIN_UV_WARN_LIMIT
Sets the VIN undervoltage warning
threshold.
R/W
L11
N/A
1.1 x VIN_UV_FAULT_LIMIT Pin-strap
Setting
59h VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault
threshold.
R/W
L11
N/A
Pin-strap Setting
5Ah VIN_UV_FAULT_RESPONSE
Sets the VIN undervoltage fault
response.
R/W
BIT
80h
Disable, No Retry
5Eh POWER_GOOD_ON
Sets the voltage threshold for
Power-good indication.
R/W
L16u
N/A
0.9 x VOUT_COMMAND Pin-strap
Setting
60h TON_DELAY
Sets the delay time from enable to VOUT R/W
rise.
L11
CA80h
5ms
61h TON_RISE
Sets the rise time of VOUT after ENABLE R/W
and TON_DELAY.
L11
CA80h
5ms
64h TOFF_DELAY
Sets the delay time from DISABLE to
start of VOUT fall.
R/W
L11
CA80h
5ms
65h TOFF_FALL
Sets the fall time for VOUT after
DISABLE and TOFF_DELAY.
R/W
L11
CA80h
5ms
78h STATUS_BYTE
First byte of STATUS_WORD.
Read
BIT
0000h
No Faults
Disable, No Retry
-45°C
Disable, No Retry
14V
Disable, No Retry
13.5V
79h STATUS_WORD
Summary of critical faults.
Read
BIT
0000h
No Faults
7Ah STATUS_VOUT
Reports VOUT warnings/faults.
Read
BIT
00h
No Faults
7Bh STATUS_IOUT
Reports IOUT warnings/faults.
Read
BIT
00h
No Faults
7Ch STATUS_INPUT
Reports input warnings/faults.
Read
BIT
00h
No Faults
7Dh STATUS_TEMPERATURE
Reports temperature warnings/faults.
Read
BIT
00h
No Faults
7Eh STATUS_CML
Reports Communication, memory,
logic errors.
Read
BIT
00h
No Errors
80h STATUS_MFR_SPECIFIC
Reports voltage monitoring/clock
synchronization faults.
Read
BIT
00h
No Faults
88h READ_VIN
Reports input voltage measurement.
Read
L11
N/A
N/A
89h READ_IIN
Reports input current measurement.
Read
L11
N/A
N/A
8Bh READ_VOUT
Reports output voltage measurement. Read
L16u
N/A
N/A
8Ch READ_IOUT
Reports output total current
measurement.
Read
L11
N/A
N/A
8Dh READ_TEMPERATURE_1
Reports internal temperature
measurement.
Read
L11
N/A
N/A
FN8614 Rev.3.00
March 27, 2015
Page 26 of 87
ZL8801
PMBus™ Command Summary
CODE
COMMAND NAME
(Continued)
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
8Eh READ_TEMPERATURE_2
Reports external temperature 0
measurement.
Read
L11
N/A
N/A
8Fh READ_TEMPERATURE_3
Reports external temperature 1
measurement.
Read
L11
N/A
N/A
94h READ_DUTY_CYCLE
Reports actual duty cycle.
Read
L11
N/A
N/A
95h READ_FREQUENCY
Reports actual switching frequency.
Read
L11
N/A
N/A
98h PMBUS_REVISION
Returns the revision of the PMBus
Specification to which the device is
compliant.
Read
BIT
11h
Part 1 Revision 1.2,
Part 2 Revision 1.2
99h MFR_ID
Sets a user defined identification.
R/W
ASC
N/A
9Ah MFR_MODEL
Sets a user defined model.
R/W
ASC
N/A
9Bh MFR_REVISION
Sets a user defined revision.
R/W
ASC
N/A
9Ch MFR_LOCATION
Sets a user defined location identifier.
R/W
ASC
N/A
9Dh MFR_DATE
Sets a user defined date.
R/W
ASC
N/A
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