RT7738GN/LN/HN
SmartJitterTM Multi-Mode Flyback Controller
General Description
Features
The RT7738GN/LN/HN series are enhanced high
efficient multi-mode PWM flyback controller with
proprietary SmartJitterTM technology. The innovative
SmartJitterTM technology can not only reduces the EMI
emissions of SMPS when the system enters green
mode, but also eliminates the output jittering ripple.
Also, the RT7738GN/LN/HN series feature multi-mode
control to optimize the product performance. To meet
the stringent trend toward performance in recent years,
the RT7738GN/LN/HN series are the best choice for
product designers.
The RT7738GN/LN/HN are available in SOT-23-6
package, and it is a current mode PWM controller.
Comprehensive protection and programmable functions
are built-in, including a programmable propagation delay
time compensation, a programmable output OverVoltage Protection (OVP), a programmable external
Over-Temperature Protection (OTP), and a programmable
bulk capacitor Brown-in/Brown-out protection. With the
above features, the RT7738GN/LN/HN are a costeffective and compact solution for AC/DC products.
Proprietary SmartJitterTM Technology
Reducing EMI Emissions of SMPS
Output Jittering Ripple Elimination
Ultra-low Start-up current ( VGM_ET
Maximum ON Time
TON_MAX
Minimum Green Mode
Frequency
fGM_MIN
PWM Frequency Jittering
Range
f
PWM Frequency Jittering
Period
TJIT
Frequency Variation Versus
VDD Deviation
f DV
VDD = 9V to 23V
--
--
2
%
Frequency Variation Versus
Temperature Deviation
f DT
TA = 30C to 105C
--
--
5
%
VCOMP_OP
COMP pin open
--
2.5
--
V
Short Circuit Current of COMP IZERO
VCOMP = 0V
--
0.135
--
mA
Delay Time of COMP
Open-loop Protection
TOLP
fOSC = 65kHz, RT7738GN/LN
--
64
--
fOSC = 100kHz, RT7738HN
--
41.6
--
Green Mode Entry Voltage
VGM_ET
--
1.75
--
Green Mode Ending Voltage
VGM_ED
RT7738GN/LN
--
1.6
--
RT7738HN
--
1.55
--
IDD Sinking Current
Oscillator Section
VCOMP < VGM_ED
kHz
s
kHz
%
ms
COMP Input Section
Open Loop Voltage
ms
V
V
Current Sense Section
Maximum Current Limit
VCS_MAX
0.38
0.40
0.42
V
Leading Edge Blanking Time
TLEB
350
475
600
ns
Threshold Voltage of
Secondary Rectifier Short
Protection
VSRSP_TH
--
1.1
--
V
--
0.7
--
V
fOSC = 65kHz, RT7738GN/LN
--
64
--
fOSC = 100kHz, RT7738HN
--
41.6
--
(Note 5)
Threshold Voltage for External
Over-temperature Protection
VOTP_TH
Application
Delay Time for External
Over-temperature Protection
TD_OTP
ms
GATE Section
Rising Time
TR
CL = 1nF
--
250
--
ns
Falling Time
TF
CL = 1nF
--
30
--
ns
VDD = 23V
10
13
--
V
Gate Output Clamping Voltage VCLAMP
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is a registered trademark of Richtek Technology Corporation.
DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
2.45
2.5
2.55
V
RT7738GN/LN
2.1
2.9
3.7
DMAG Section
Threshold Voltage of
Over-voltage Protection
VDMAG_OVP
Blanking Time Before
Over-voltage Protection of
DMAG Pin
TBK_OVP
RT7738HN
1.25
1.95
2.5
Threshold Voltage of
Under-voltage Protection
VDMAG_UVP After TD_OSP, COMP pin open
0.3
0.4
0.5
Delay Time of Under-voltage
Protection
TD_OSP
fOSC = 65kHz, RT7738GN/LN
--
16
--
fOSC = 100kHz, RT7738HN
--
10.4
--
On Threshold Current
IDMAG_BNI
141
160
179
A
Threshold Current of
Under-current Protection
IDMAG_BNO
128
145
162
A
--
--
1
mA
fOSC = 65kHz, RT7738GN/LN
--
64
--
ms
fOSC = 100kHz, RT7738HN
--
41.6
--
VCS = 0.36V
Maximum Sourcing Current of
IDMAG_MAX (Note 5)
DMAG Pin
Delay Time of Under-current
Protection
TD_BNO
s
V
ms
Over-Temperature Protection (OTP) Section
OTP Before Turn On
TOTP_INTH
Built-in OTP
(Note 5)
--
130
--
C
OTP After Turn On
TOTP_STTH
Built-in OTP
(Note 5)
--
140
--
C
Note1. Stresses beyond those listed ”Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured in natural convection (still air) at TA = 25°C with the component mounted on a low effective thermal
conductivity test board of JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7738GN/LN/HN-00
January 2015
is a registered trademark of Richtek Technology Corporation.
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7
RT7738GN/LN/HN
Typical Application Circuit
VO+
Mains
(90V to 265V)
VO-
(Optional)
5
6
3 DMAG VDD
GATE
2
COMP
RT7738GN/LN/HN
CS 4
CCOMP
GND
1
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8
(Optional)
(Optional)
(Optional)
is a registered trademark of Richtek Technology Corporation.
DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
Typical Operating Characteristics
VTH_OFF vs. Temperature
VTH_ON vs. Temperature
15.5
9.50
RT7738GN/LN
9.25
VTH_OFF (V)
VTH_ON (V)
15.0
14.5
9.00
14.0
8.75
13.5
8.50
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
100
125
Temperature (°C)
Temperature (°C)
VOVP vs. Temperature
VDD_ET vs. Temperature
28.0
10.5
10.3
VDD_ET (V)
VOVP (V)
27.5
27.0
10.1
9.9
26.5
9.7
26.0
9.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
VDD_ED vs. Temperature
IDD_ST vs. VDD
11.00
0.6
0.5
I DD_ST (μA)
VDD_ED (V)
10.75
10.50
0.4
0.3
0.2
10.25
0.1
10.00
0.0
-50
-25
0
25
50
75
100
Temperature (°C)
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DS7738GN/LN/HN-00
January 2015
125
0
2
4
6
8
10
12
14
16
VDD (V)
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RT7738GN/LN/HN
IDD_LH vs. Temperature
10
0.75
8
I DD_LH (μA)
I DD_ST (μA)
IDD_ST vs. Temperature
1.00
0.50
0.25
RT7738LN
6
4
2
0.00
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
100
125
100
125
Temperature (°C)
Temperature (°C)
IDD_ARP vs. Temperature
VDD_LH & VLH_OFF vs. Temperature
700
6.8
RT7738LN
650
6.0
I DD_ARP (μA)
VDD_LH & VLH_OFF (V)
6.4
VDD_LH
5.6
5.2
600
550
VLH_OFF
4.8
500
4.4
4.0
450
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
Temperature (°C)
IDD_OP1 vs. Temperature
IDD_OP2 vs. Temperature
2.2
2.0
1.8
I DD_OP2 (mA)
I DD_OP1 (mA)
2.0
1.8
1.6
1.4
1.6
1.2
1.4
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
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10
125
-50
-25
0
25
50
75
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
fOSC vs. VDD
fOSC vs. Temperature
66.0
70.0
RT7738GN/LN
RT7738GN/LN
67.5
65.0
f OSC (kHz)
f OSC (kHz)
65.5
65.0
62.5
60.0
64.5
57.5
64.0
55.0
9
12
15
18
21
24
27
-50
-25
0
VDD (V)
fOSC vs. VDD
75
100
125
100
125
100
125
110
RT7738HN
RT7738HN
105
f OSC (kHz)
100.5
f OSC (kHz)
50
fOSC vs. Temperature
101.0
100.0
99.5
100
95
99.0
90
9
12
15
18
21
24
27
-50
-25
0
VDD (V)
25
50
75
Temperature (°C)
TON_MAX vs. Temperature
TON_MAX vs. Temperature
14
8.5
RT7738GN/LN
13
RT7738HN
8.0
TON_MAX (μs)
TON_MAX (μs)
25
Temperature (°C)
12
7.5
7.0
11
6.5
10
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7738GN/LN/HN-00
January 2015
125
-50
-25
0
25
50
75
Temperature (°C)
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11
RT7738GN/LN/HN
fGM_MIN vs. Temperature
fGM_MIN vs. Temperature
26
30
RT7738GN/LN
RT7738HN
28
f GM_MIN (kHz)
f GM_MIN (kHz)
24
22
26
24
22
20
20
18
18
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
VCOMP_OP vs. Temperature
50
75
100
125
100
125
100
125
IZERO vs. Temperature
2.70
160
2.65
150
2.60
140
I ZERO (μA)
VCOMP_OP (V)
25
Temperature (°C)
2.55
2.50
2.45
130
120
110
2.40
100
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
Temperature (°C)
TOLP vs. Temperature
TOLP vs. Temperature
75
50
RT7738GN/LN
RT7738HN
TOLP (ms)
TOLP (ms)
70
65
45
40
60
55
35
-50
-25
0
25
50
75
100
Temperature (°C)
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12
125
-50
-25
0
25
50
75
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
TLEB vs. Temperature
600
0.43
550
TLEB (ns)
VCS_MAX (V)
VCS_MAX vs. Temperature
0.45
0.41
0.39
0.37
500
450
400
0.35
350
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
VCLAMP vs. Temperature
50
75
100
125
VSRSP_TH vs. Temperature
14
1.15
1.13
VSRSP_TH (V)
13
VCLAMP (V)
25
Temperature (°C)
12
1.11
1.09
11
1.07
10
1.05
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
50
75
100
125
100
125
TR vs. Temperature
VOTP_TH vs. Temperature
0.76
400
0.74
350
0.72
300
TR (ns)
VOTP_TH (V)
25
Temperature (°C)
0.70
250
200
0.68
150
0.66
-50
-25
0
25
50
75
100
Temperature (°C)
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DS7738GN/LN/HN-00
January 2015
125
-50
-25
0
25
50
75
Temperature (°C)
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13
RT7738GN/LN/HN
TF vs. Temperature
VDMAG_OVP vs. Temperature
100
2.60
80
VDMAG_OVP (V)
TF (ns)
2.55
60
40
2.50
2.45
20
0
2.40
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
100
125
100
125
Temperature (°C)
VDMAG_UVP vs. Temperature
TBK_OVP vs. Temperature
0.50
4.0
RT7738GN/LN
3.5
TBK_OVP (μs)
VDMAG_UVP (V)
0.45
0.40
0.35
3.0
2.5
2.0
0.30
-50
-25
0
25
50
75
100
-50
125
-25
0
75
20
RT7738GN/LN
RT7738HN
18
TD_OSP (ms)
2.5
TBK_OVP (μs)
50
TD_OSP vs. Temperature
TBK_OVP vs. Temperature
3.0
2.0
16
14
1.5
12
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
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14
25
Temperature (°C)
Temperature (°C)
125
-50
-25
0
25
50
75
Temperature (°C)
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DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
IDMAG_BNI vs. Temperature
TD_OSP vs. Temperature
180
14
RT7738HN
170
I DMAG_BNI (μA)
TD_OSP (ms)
12
10
160
150
8
140
6
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
100
125
Temperature (°C)
Temperature (°C)
IDMAG_BNO vs. Temperature
TD_BNO vs. Temperature
160
75
RT7738GN/LN
70
TD_BNO (ms)
I DMAG_BNO (μA)
150
140
130
65
60
120
55
-50
-25
0
25
50
75
100
125
Temperature (°C)
-50
-25
0
25
50
75
Temperature (°C)
TD_BNO vs. Temperature
50
TD_BNO (ms)
RT7738HN
45
40
35
-50
-25
0
25
50
75
100
125
Temperature (°C)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7738GN/LN/HN-00
January 2015
is a registered trademark of Richtek Technology Corporation.
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15
RT7738GN/LN/HN
Application Information
The RT7738GN/LN/HN are a multi-mode PWM flyback
controller. As load decreases, the controller enters
green mode, burst mode, and VDD holdup mode. The
automatic multi-mode switching optimizes the product
performance under different load conditions. To meet
the stringent trend toward performance, the
RT7738GN/LN/HN are the best choice for product
VAUX
RA
RB
DMAG
RT7738GN/LN/HN
provides
programmable
The RT7738GN/LN/HN outputs a propagation delay
time compensation current on the CS pin by gain.
Product designers can compensate the propagation
delay time differences caused by different input
voltages by adjusting the propagation delay time
compensation resistor (RPDC) to keep the same output
current under different input voltages and accurate
over-load protection.
beginning
of
propagation
delay
time
compensation function setting, designers could set
RPDC = 470, and CRC = 100pF. In Figure 2, the ideal
output current should be the same as curve (1). No
matter under high line or low line, the output current
keeps the same. However, the propagation delay time
varies OLP curve under different input voltages
according to different designs of transformer
inductance, parasitic capacitance of MOSFET, series
resistance on the GATE of MOSFET. If the OLP curve
is like curve (2), designers should increase the
resistance of RPDC; if the OLP curve is like curve (3),
designers should increase the capacitance of CRC.
Designers optimize the OLP curve through propagation
delay time compensation to keep the same output
current under different input voltages.
OLP Curve
Heavy
Load
(2) High Line Up
(1) Target
(3) High Line Down
Light
Load
Low Line
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Input Voltage
High Line
Figure 2. Curve Chart of OLP
External Over-Temperature Protection
The RT7738GN/LN/HN implements external arbitrary
over-temperature protection by CS pin. Designer can
design arbitrary OTP via constant voltage source
(VAUX_Clamp), fast diode and the divided resistors on
CS pin, as shown in Figure 3. The constant voltage
source is sensing by auxiliary voltage at GATE off, and
the divided resistors are NTC resistor (RNTC), setting
resistor (RSET), resistor of propagation delay
compensation (RPDC) and current sense resistor (RCS).
When temperature is higher, the resistance of NTC
resistor becomes small. The sampling voltage of
divided resistors on CS pin during GATE off exceeds
the VOTP_TH trip level, and then after delay time TD_OTP
the controller will be shut down and cease switching.
Until the OTP is released, the controller resumes
operation. The design equation is :
N
VOTP_TH VO VF A VF_OTP
NS
RPDC RCS
RNTC_OTP RSET RPDC RCS
Where RNTC_OTP
over-temperature.
16
RCS
Figure 1. Function Block Diagram of Propagation Delay
propagation delay time compensation function, as
shown in Figure 1.
the
CRC
Time Compensation
Programmable Propagation Delay Time Compensation
Function
In
RPDC
xK
RT7738GN/LN/HN
designers.
The
CS
Vin
Detection
is
the
NTC
resistance
at
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DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
VO+
+ VF -
+
+
Mains
(90V to 265V)
NP
VBulk
NS
VO
-
-
VO-
+
VF_OTP
-
+
VAUX
-
VAUX_Clamp
5
VDD
NA
RNTC
6
3 DMAG
GATE
2
COMP
RT7738GN/LN/HN
CS/OTP 4
GND
1
GATE
TON
(VO + VF )
VAUX_Clamp
0V
RSET
RPDC
VCS
0V
RCS
NA
VF_OTP
NS
T
VOTP_TH S
Sample
TBK
Blanking Time
Figure 3. Application Circuit of External Over-Temperature Protection
SmartJitterTM Technology
The RT7738GN/LN/HN series applies
proprietary SmartJitterTM technology.
RICHTEK
In order to reduce switching loss for lower power
consumption during light load or no load, general PWM
controllers have green mode function.
The output power equation is :
2
x V
PO_DCM(VCOMP ) 1 Lp ( 1 COMP ) fS (VCOMP ) η
2
RCS
Where LP is the magnetizing inductance of the
transformer, RCS is the current sense resistor, VCOMP
is the feedback voltage of the COMP pin. f S is the
switching frequency of the power switch, is the
conversion efficiency, and x 1 is a constant coefficient.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7738GN/LN/HN-00
January 2015
Output power is a function of feedback voltage VCOMP.
Frequency jittering technique is typically used to
improve EMI problems in general PWM controllers, and
the frequency jittering period is based on PWM
switching frequency.
When the system enters green mode, a output power
relationship is formed between the feedback voltage
VCOMP and the PWM switching frequency, and a new
stable equilibrium point is eventually reached after
back-and-forth adjustments. It is mutually-affected by
VCOMP and PWM switching frequency and limits the
frequency jittering. As a result, EMI improvement
function worsens, as show in Figure 4.
The innovative SmartJitterTM technology not only helps
reduce EMI emissions of SMPS when the system
enters green mode, but also eliminates output jittering
ripple.
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17
RT7738GN/LN/HN
General PWM Controller
Jittering Freq.
Normal Operating
RT7738GN/LN/HN
Jittering Freq.
Normal Operating
fs mean = 64.85kHz
Jittering Range =
General PWM Controller
Jittering Freq.
fs mean = 64.61kHz
Jittering Range =
6.3%
Green Mode
6.0%
RT7738GN/LN/HN
Jittering Freq.
Green Mode
fs mean = 42.99kHz
Jittering Range =
fs mean = 42.58kHz
Jittering Range =
3.3%
7.7%
Figure 4. Frequency Jittering Range During Green Mode : General PWM Controller vs. RT7738GN/LN/HN
DMAG Pin Resistance Setting
When the MOSFET turns on, the voltage of auxiliary
winding is negative, and the clamping circuit outputs a
clamp current to clamp the DMAG voltage at 0.1V.
The clamping current is proportional to the input
voltage. The RT7738GN/LN/HN features DMAG
threshold-on current (IDMAG_BNI), and DMAG
under-current protection threshold (IDMAG_BNO).
Designers can indirectly design bulk capacitor
Brown-in (VBulk_Brown-in) and Brown-out (VBulk_Brown-out)
by adjusting RA and RB on the DMAG pin, as shown
in Figure 5.
RA and RB, on the auxiliary winding as shown in
Figure 5. The RT7738GN/LN/HN provides DMAG
over-voltage protection, and designers can indirectly
design output OVP (VO_OVP) by DMAG OVP
(VDMAG_OVP) :
VBulk_Brown-in NA
NP
RA
0.1
VO_OVP VF NA
NS
RB
VDMAG_OVP
R A RB
VBulk
CBulk
When one of Brown-in and Brown-out is set, others
are set proportionally.
The bulk capacitor input voltage Brown-out (VBrown-out)
is :
VBulk_Brown-out
VBulk_Brown-in IDMAG_BNO
IDMAG_BNI
When the MOSFET turns off, the DMAG pin detects
the output voltage according to the ratio of auxiliary
and secondary-side turns, and the series resistors,
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18
0.1
IDMAG_BNI
RB
NP
NS
Vo
+ VF -
VDD
RA
NA
DMAG
RB
RT7738GN/LN/HN
GATE
Figure 5. Design DMAG Pin Resistance
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DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
Adaptive Blanking Time
Start-Up Circuit
When the MOSFET turns off, the leakage inductance
of the transformer and parasitic capacitance (COSS)
of MOSFET induce resonance waveform on the
DMAG pin, as shown in Figure 6. The resonance
waveform makes the controller false trigger the
DMAG OVP (VDMAG_OVP) which affects the accuracy
of output OVP (VO_OVP), and it may cause the
To minimize power loss, it's recommended to connect
the start-up circuit to the bleeding resistors. It's power
saving and also could reset latch mode protection
quickly. Figure 7 shows IDD_Avg vs. RBleeding curve.
Users can apply this curve to design the adequate
bleeding resistors.
controller operate in unstable condition. As load
increases, the resonance time also increases. It is
recommended to add 10pF to 47pF bypass capacitor
to avoid noise false triggering on DMAG pin. The
bypass capacitor should be as close to DMAG pin as
possible.
power loss and thermal rising during hiccup, the
controller is designed to have smaller sinking current
during entering auto-recovery protection, IDD_ARP.
Therefore, the start-up current at maximum AC line
input voltage must be smaller than IDD_ARP
(IDD_ARP(min) = 400A). Otherwise, when the controller
enters auto-recovery protection, the VDD capacitor
won't be dropped down to VTH_OFF by IC's sinking
current and then restart. The controller behaves like
latch protection or triggers the SCR of VDD.
The RT7738GN/LN/HN provides adaptive blanking
time to prevent DMAG OVP from being false triggered.
The blanking time (TBK_OVP) varies with maximum
current limit of the CS pin (VCS_PK), and the blanking
In order to prolong turn-off period and minimize the
time can be calculated by the following formula :
TBK_OVP 2μs VCS_PK 2.5 μs/V for RT7738GN/LN
TBK_OVP 1.5μs VCS_PK 1.25 μs/V for RT7738HN
VDMAG_OVP
VDMAG
TBK_OVP
VCS_PK
VCS
Figure 6. Resonance Waveform on the DMAG Pin
IDD_Avg vs. RBleeding Curve
IDD_Avg vs. RBleeding Curve
90
250
RBleeding
80
RBleeding
60
VDD
50
90Vac
85Vac
80Vac
40
175
VDD
150
265Vac
230Vac
125
30
100
20
75
10
IDD_Avg
RBleeding
200
I DD_Avg (μA)
I DD_Avg (μA)
70
RBleeding
225
IDD_Avg
50
0.6
1.0
1.4
1.8
2.2
2.6
3.0
0.6
RBleeding (M)
1.0
1.4
1.8
2.2
2.6
3.0
RBleeding (M)
Figure 7. IDD_Avg vs. RBleeding Curve
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7738GN/LN/HN-00
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
19
RT7738GN/LN/HN
VDD Discharge Time in Auto Recovery Mode
Output Short Protection
Figure 8 shows the VDD and VGATE waveforms during
an auto recovery protection (e.g., OLP). In this mode,
the start-up resistors, VDD sinking current and VDD
decoupling capacitor will affect the restart time. The
VDD voltage discharge time tD_Discharge can be
calculated by the following equation :
The RT7738GN/LN/HN implements output short
protection by detecting output signal of DMAG pin
after delay time (TD_OSP). It can minimize the power
loss and temperature during output short, especially
at high line input voltage.
tD_Discharge
CVDD (VDD_DIS VTH_OFF )
IDD_ARP IST
Where the CVDD is the VDD decoupling capacitor, the
VDD_DIS is the initial VDD voltage after entering the
auto recovery mode, the VTH_OFF (9V typ.) is the
falling UVLO voltage threshold of the controller, the
IDD_ARP (550A typ.) is the sinking current of the VDD
pin in the auto recovery mode, and IST is the start-up
current of the power system.
Please note that the start-up current at high input
voltage must be smaller than the IDD_ARP. Otherwise,
the VDD voltage can't reach the VTH_OFF to activate
the next start-up process after an auto recovery
protection. Therefore, the system behavior resembles
the behavior of latch mode.
VDD
Resistors on GATE Pin
In Figure 9, RG is applied to alleviate ringing spike of
gate drive loop in typical application circuits. The
value of RG must be considered carefully with respect
to EMI and efficiency for the system.
The built-in internal discharge resistor RID in parallel
with GATE pin prevents the MOSFET from any
uncertain condition. If the connection between the
GATE pin and the Gate of the MOSFET is
disconnected, the MOSFET will be false triggered by
the residual energy through the Gate-to-Drain
parasitic capacitor CGD of the MOSFET and the
system will be damaged. Therefore, it’s highly
recommended to add an external discharge-resistor
RED connected between the Gate of MOSFET and
GND terminals. The energy through the CGD is
discharged by the external discharge-resistor to avoid
MOSFET false triggering.
VDD_DIS
VTH_ON
VTH_OFF
t
VGATE
OLP Delay
Time
AC Mains
(90V to 265V)
tD_Discharge
t
Figure 8. Auto Recovery Mode (e.g., OLP)
The RT7738GN/LN/HN build in a internal discharge-resistor
to prevent the MOSFET at any uncertain conditions.
VDD Holdup Mode
The VDD holdup mode is only designed to prevent
VDD from decreasing to the turn-off threshold voltage,
VTH_OFF, under light load or load transient. Compare
to burst mode, the VDD holdup mode brings higher
switching. Hence, it is highly recommended that the
system should avoid operating at this mode during
light load or no load conditions.
CGD
Soft
Driver
GATE
RG
RID
RED
CS
GND
Recommend to add the external dischargeresistor to avoid MOSFET falsely triggering.
Figure 9. Resistors on Gate Pin
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
20
is a registered trademark of Richtek Technology Corporation.
DS7738GN/LN/HN-00
January 2015
RT7738GN/LN/HN
Feedback Resistor
Internal Over-Temperature Protection
In order to enhance light load efficiency, the loss of
the feedback resistor in parallel with photo-coupler is
reduced, as shown in Figure 10. Due to small
feedback resistor current, shunt regulator selection
(e.g. TL-431) and minimum regulation current design
must be considered carefully to make sure it's able to
regulate under low cathode current.
The RT7738GN/LN/HN provides OTP function to
prevent permanent damage. It is not recommended to
apply this function to accurate temperature control.
Vo+
+
+
Vo-
Feedback
Resistor
When the IC turns on, the controller detects around
temperature before it starts switching. If the
temperature is higher than TOTP_INTH (typ. 130C),
the controller triggers OTP, and there is no output
signal. If the temperature is lower than TOTP_INTH, the
controller starts operation and the OTP threshold is
automatically set to TOTP_STTH (typ.140C), which
means when the controller starts switching, the OTP
threshold is TOTP_STTH.
When the controller triggers OTP, the controller will
be shut down and cease switching. At the same time,
VDD drops below VDD off threshold VTH_OFF, the
controller enters hiccup mode.
Thermal Considerations
Figure 10. Feedback Resistor
Negative Voltage Spike on Each Pin
Negative voltage (
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