RT8801PQV

Preliminary RT8801 Multi-Phase PWM Controller for CPU Core Power Supply with Serial Programming Interface General Description The RT8801 is a multi-phase synchronous buck controller which is implemented with full control functions for Intel® VR10.0/10.1-compliant CPU. The RT8801 could be operated with 2, 3 or 4 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. RT8801 is one of RichTek CPU core power solutions which integrates a specific series programming interface for the controller operation configuration. There are several registers implemented for the specific parameters configuration including VID for core power, and signal for load current indication. User can program the configuration of the parameters easily via the specific programming interface. With the implementation of RT8801, the part provides more flexibility and feature for customers advanced segment product design. The RT8801 applies the DCR sensing technology newly as well; with such a topology, the RT8801 extracts the DCR of output inductor as sense component to deliver a more precise load line regulation and better thermal balance for next generation processor application. For current sense setting, droop tuning, VCORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT8801 supports VRD10.x with 6-bit VID input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. The RT8801 comes to the package of VQFN-32L 5x5. Features Multi-Phase Power Conversion with Automatic Phase Selection 6-bits VRD10.x DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by DCR Current Sense Hiccup Mode Over-Current Protection Adjustable Switching Frequency (50kHz to 400kHz per Phase) Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number 2-wires programming interface Software Programmable VID 32-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free Applications Intel® VR10.x-compliant Processors Voltage Regulator L ow Output Voltage, High power density DC-DC Converters Voltage Regulator Modules Ordering Information RT8801 Package Type QV : VQFN-32L 5x5 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 1 RT8801 Pin Configurations Preliminary (TOP VIEW) VID125 PWM4 25 24 23 22 21 20 19 33 18 17 9 10 11 12 13 14 15 16 VID0 VID2 VID3 28 VID4 27 VID1 32 31 30 29 S LOT_OCC DATA CLK RST AD_SEL GND IC_OUT FB VDD 26 1 2 3 4 5 6 7 8 GND PWM3 PWM2 PWM1 CSP1 CSP2 CSP3 CSP4 ADJ PGOOD VOSS DVD RT SS COMP Registers 0x00 Hi-I setting registers; Default 0x00 Bit4-0 : Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 200 212.5 225 237.5 250 262.5 275 287.5 300 312.5 325 337.5 350 362.5 375 400 All brandname or trademark belong to their owner respectively www.richtek.com 2 DS8801-04 August 2007 SGND VQFN-32L 5x5 CSN Preliminary RT8801 0x01 Core Current. Default 0x00 (read only). The core current full scale is over current trigger point. Bit6-0 : Show core voltage current. 0x03 MISC. Default 0x04. Bit2 : Slot_OCC Detection. This bit be written clear and only can be written 0. 0 : Normal 1 : Slot_OCC ever be pulled high Bit1 : The reset pin ever be pull low when bit0 = 1 and only can be written 0. 0 : Never issue reset 1 : Ever issue reset Bit0 : Reset control. When this bit be write 1, the Watching Dog timer (Reset pin) will repeat counter 1400ms then pull low 200ms.Reset pin be pull low, if this bit = 1 will reset all registers to default exception MISC(Index 0x03). 0 : Disable 1 : Enable Note : If SLOT_OCC pin = 1 reset all registers value to default. RST enable 0x03 bit 0 7 x Tdelay WD Timer Tdelay RST Product information registers (Read Only) 0x13 Revision_ID 0x00 All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 3 10 12V PVCC12V 1uF 5VSB 0.1uF PVCC IPD09N03 www.richtek.com 4 1uF 1uF 1500uF VCORE 0.6uH 680uF x 10 12 13 2 0 2.2 0.01uF IPD06N03 RT8801 14 VCC 5 UGATE1 PHASE1 PWM1 LGATE1 0 11 BOOT1 VID0 15 VID1 VID2 VID3 VID4 VID12.5 10uF x 18 32 31 30 29 28 27 26 25 VID2 VID1 VID3 VID4 PWM4 VDD VID0 VID125 VCC 3V 4 PGND UGATE2 PHASE2 LGATE2 6 BOOT2 10 1uF 0 IPD06N03 2.2 0.01uF 3 NC 16 PWM2 8 RT9607PQV 1 GND 9 7 IPD09N03 SLOT_OCC RT8801 0 1uF 1500uF Typical Application Circuit 0.6uH 4.7k GND DATA CLK 5VSB 4.7k NC NC 1 SLOT_OCC 2 DATA 3 CLK 4 RST 5 AD_SEL 6 GND 7 IC_OUT 8 FB RT PGOOD DVD VOSS CSN SS NC NTC NC 200 10 1uF 5 PVCC 14 VCC UGATE1 PHASE1 PWM1 LGATE1 NC 16 VCC 5V 27k VCC 12V NC 3k 27k 1 PWM2 RT9607PQV GND 4 PGND UGATE2 PHASE2 9 7 LGATE2 6 BOOT2 10 0 0 11 BOOT1 12V 0.1uF 4.7k IN4148 NC VCORE 15 NC 12k 330 1uF 1uF 12 13 2 3 8 0 IPD06N03 2.2 PWM3 24 PWM2 23 PWM1 22 21 CSP1 20 CSP2 19 CSP3 18 CSP4 17 ADJ SGND 15k 10nF Preliminary COMP 10nF 9 10 11 12 13 14 15 16 PVCC12V 1500uF 0 IPD09N03 33pF 100k 0.6uH 3k 0.01uF All brandname or trademark belong to their owner respectively 1uF IPD09N03 IPD06N03 2.2 0.01uF 1500uF 0.6uH 0 0 1uF DS8801-04 August 2007 Preliminary Functional Pin Description SLOT_OCC (Pin 1) CPU socket occupied; the signal is defined to indicate if the CPU has been changed/ removed and it will reset all chip. There is one register implemented for the status indication. The register will be reset when the VDD power removed or CPU changed/removed. The pin is implemented as an input, TTL level, and active-low signal. DATA (Pin 2), CLK (Pin 3) 2-wires programming interface. PGOOD (Pin 14) RST (Pin 4) This pin be pull low (the Watching Dog = Low), it will reset some register, when 0x03 bit 0 be setting. AD_SEL (Pin 5) The pin select series bus address. Pin =1,Address = 0x5E & Pin = 0, Address = 0x5C. GND (Pin 6, Bottom Pad) Chip power ground. IC_OUT (Pin 7) The pin is defined as a reference current output. A capacitor is attached to set the default Watching Dog low pluse time. Write the index 0x03 bit0 = 1 delay 7 times Tdelay time then issue Tdelay low pluse. COUT where Tdelay = x VC_OUT IC_OUT FB (Pin 8) The pin is defined as an inverting input of internal error amplifier. COMP (Pin 9) The pin is defined as an output of the error amplifier and an input of the PWM comparator. SGND (Pin 10) Difference ground sense of VCORE. VOSS (Pin 11) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. ADJ (Pin 17) DVD (Pin 12) RT8801 Hardware adjustable system power UVLO detection; input pin; the internal trip threshold = 0.9V at VDVD rising. SS (Pin 13) The pin is defined to set soft-start ramp rate; a capacitor is attached to set the start time interval. Pull this pin lower than 1.0V (ramp valley of saw-tooth wave in pulse width modulator) will shut the converter down. Power Good Indication. PGOOD is an open drain output. PGOOD will go high impedance when SS voltage greater than 3.7V and no fault occurs. RT (Pin 15) Default operation switching frequency setting. A resistor is attached to set the default operation frequency. CSN (Pin 16) The pin is defined to sense load current of CPU. The pin should be connected to the output node of choke. Pin for active droop adjustment. An external resistor is attached to GND for load droop setting. CSP1 (Pin 21), CSP2 (Pin 20), CSP3 (Pin 19), CSP4 (Pin 18) Current sense inputs from the individual converter channels. PWM1 (Pin 22), PWM2 (Pin 23), PWM3 (Pin 24), PWM4 (Pin 25) PWM outputs for each phase switching drive. VDD (Pin 26) Chip powers supply. Connect this pin to a 5VSB or VCC5 supply. All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 5 RT8801 Preliminary VID4 (Pin 27), VID3 (Pin 28), VID2 (Pin 29), VID1 (Pin 30), VID0 (Pin 31), VID125 (Pin 32) DAC voltage identification; Input; The VID0~4 is implemented for VRM9.0 (5-bits) DAC identification; The VID0~4, VID125 is implemented for VRM10.X (6-bits) DAC identification. The pins are internally pulled to 1.2V (pull high 50μA) if left open. GND [Exposed Pad (33)] The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Function Block Diagram PWM1 PWM2 PWM3 PWM4 CSP1 + CSP2 CSP3 CSP4 M u x PWM Logic PWM Logic PWM Logic PWM Logic GM PWMCP PWMCP PWMCP PWMCP Mux + Oscillator & Ramp Generator RT Current Correction OCP + + + + + + + OCP Detection + + SUM/M + + OVP Trip Point CSN OCP INH Soft Start & PGOOD EA Droop Tune Power On Reset Offset Current Source/Sink COMP FB VOSS DATA RST CLK SLOT_OCC PGOOD VID0 VID1 VID2 VID3 VID4 VID125 VDD SGND ADJ DVD SS Digital Logic DAC WD Timer All brandname or trademark belong to their owner respectively www.richtek.com 6 DS8801-04 August 2007 AD_SEL IC_OUT GND + - Preliminary Table 1. Output Voltage Program Pin Name VID4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 VID1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 VID0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 VID125 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 RT8801 Nominal Output Voltage DACOUT No CPU 0.8375V 0.850V 0.8625V 0.875V 0.8875V 0.900V 0.9125V 0.925V 0.9375V 0.950V 0.9625V 0.975V 0.9875V 1.000V 1.0125V 1.025V 1.0375V 1.050V 1.0625V 1.075V 1.0875V 1.100V 1.1125V 1.125V 1.1375V 1.150V 1.1625V 1.175V 1.1875V 1.200V 1.2125V To be continued www.richtek.com 7 All brandname or trademark belong to their owner respectively DS8801-04 August 2007 RT8801 Pin Name VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Preliminary Table 1. Output Voltage Program Nominal Output Voltage DACOUT VID0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID125 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.225V 1.2375V 1.250V 1.2625V 1.275V 1.2875V 1.300V 1.3125V 1.325V 1.3375V 1.350V 1.3625V 1.375V 1.3875V 1.400V 1.4125V 1.425V 1.4375V 1.450V 1.4625V 1.475V 1.4875V 1.500V 1.5125V 1.525V 1.5375V 1.550V 1.5625V 1.575V 1.5875V 1.600V Note: (1) 0 : Connected to GND (2) 1 : Open (3) X : Don't Care All brandname or trademark belong to their owner respectively www.richtek.com 8 DS8801-04 August 2007 Preliminary Absolute Maximum Ratings (Note 1) RT8801 7V GND - 0.3V to VDD + 0.3V 2.78W 36°C/W 150°C 260°C −65°C to 150°C 2kV 200V Supply Voltage, VDD ----------------------------------------------------------------------------------------Input, Output or I/O Voltage -------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C VQFN-32L 5x5 -----------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) VQFN-32L 5x5, θJA ------------------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) --------------------------------------------------------------------------------MM (Machine Mode) ----------------------------------------------------------------------------------------- Recommended Operating Conditions (Note 3) Supply Voltage, VDD ----------------------------------------------------------------------------------------- 5V ± 10% Ambient Temperature Range ------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range ------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VDD = 5V, TA = 25°C, unless otherwise specified) Parameter VDD Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis Trip (Low to High) VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID125) Input Low DAC (VID0-VID125) Input High Hysteresis Symbol Test Conditions Min Typ Max Units IDD PWM 1,2,3,4 Open -- 12 16 mA VDDRTH VDDHYS VDVDTP VDVDHYS VDD Rising Enable 4.0 0.2 0.8 -- 4.2 0.5 0.9 70 4.5 -1.0 -- V V V mV fOSC fOSC_ADJ ΔVOSC VRV RRT = 22.5kΩ RRT = 22.5kΩ 250 50 -0.7 62 300 -1.9 1.0 66 1.8 350 400 --75 1.9 kHz kHz V V % V VRT RRT = 22.5kΩ VDAC ≥ 1V VDAC < 1V 1.7 −1 −10 -0.8 ΔVDAC VILDAC VIHDAC ----- +1 +10 0.3 -- % mV V V To be continued All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 9 RT8801 Parameter Offset Voltage VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier CSN Full Scale Source Current CSN Current for OCP Protection SS Current VSEN Over-Voltage Trip VDACOUT + VOFFSET Preliminary Symbol Test Conditions RVOSS = 100kΩ Min −3 VVOSS 1.6 Typ -1.7 Max 3 1.8 Units % V -GBW SR COMP = 10pF --- 85 10 3 ---- dB MHz V/μs μA μA μA % IISPFSS 150 -- -150 --- ISS ΔOVT VSS = 1V 8 130 13 140 18 150 Delay Time WD Timer, TDL (CL = 100nF) WD Timer, TDH (CL = 100nF) Power Good Output Low Voltage VPGOODL IPGOOD = 4mA --0.2 V --200 1400 --ms ms Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. All brandname or trademark belong to their owner respectively www.richtek.com 10 DS8801-04 August 2007 Preliminary Typical Operating Characteristics Adjustable Frequency 450 400 350 RT8801 Linearity of each PWM 3 2.8 2.6 2.4 F OSC (kHz) 300 V COMP (V) 250 200 150 100 50 0 0 20 40 60 80 100 120 2.2 2 1.8 1.6 1.4 1.2 1 0 500 1000 1500 2000 2500 PWM2 PWM3 PWM1 PWM4 fOSC = 200k 3000 3500 RRT (kΩ)) (k Pulse Width (ns) Load Transient Response V CORE V CORE Load Transient Response Phase1 Phase Phase2 IOUT VADJ CH1: CH2: CH3: CH4: (500mV/Div) (10V/Div) (50A/Div) (100mV/Div) Phase3 CH1: (500mV/Div), CH2: (10V/Div) CH3: (10V/Div), CH4: (10V/Div) Time (5μs/Div) Time (5μs/Div) Power-Off @ IOUT = 60A Power-On @ IOUT = 60A CH1:(5V/Div) CH2:(5V/Div) PWM CH1:(5V/Div) CH2:(20V/Div) VSS PWM UGATE CH3:(10V/Div) CH4:(1V/Div) UGATE CH3:(20V/Div) CH4:(10V/Div) LGATE LGATE VCOMP Time (10μs/Div) Time (10ms/Div) All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 11 RT8801 Preliminary Relationship Between Inductor Current and VADJ CH1:(5V/Div) CH2:(5V/Div) PWM VSS VADJ IL CH3:(50mV/Div) CH4:(20A/Div) Time (25ms/Div) All brandname or trademark belong to their owner respectively www.richtek.com 12 DS8801-04 August 2007 Preliminary Application Information RT8801 is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT8801 and its companion MOSFET driver RT9607/ RT9607A provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT8801 senses the CPU VCORE by SGND pin to sense the return of CPU to minimize the voltage drop on PCB trace at heavy load. OVP is sensed at FB pin. The internal high accuracy VID DAC provides the reference voltage for VRD10.X compliance. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. As conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT8801 senses the inductor current via inductor's DCR for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. If the current of some power channel is larger than average, the balancing signal reduces that channels pulse width to keep current balance. The use of single GM amplifier via time sharing technique to sense all inductor currents can reduce the offset errors and linearity variation between GMs. Thus it can greatly improve signal processing especially when dealing with such small signal as voltage drop across DCR. Load Droop The sensed power channel current signals regulate the reference of DAC to form an output voltage droop proportional to the load current. The droop or so call “active RT8801 voltage positioning” can reduce the output voltage ripple at load transient and the LC filter size. Fault Detection The chip detects FB for over voltage. The “ hiccup mode” operation of over current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT8801 interfaces with companion MOSFET drivers (like RT9619, RT9607 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) senses its interface voltage when IC POR acts (both VDD and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VDD. Tie the PWM to VDD and the corresponding current sense pins to GND or left float if the channel is unused. For example, for 3-Channel application, connect PWM4 high. Current Sensing Setting RT8801 senses the current flowing through inductor via its DCR for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal circuit (see Figure 1). VC L = R × C VC = DCR × IL I X = DCR R CSN L DCR VC C R + GMx Ix RCSN Figure 1. Current Sense Circuit Figure 2 is the test circuit for GM. We apply test signal at GM inputs and observe its signal process output at ADJ pin. Figure 3 shows the variation of signal processing of all channels. We observe zero offsets and good linearity between phases. All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 13 - + RT8801 L DCR Preliminary Over Current Protection RT8801 uses an external resistor R CSN t o set a programmable over current trip point. OCP comparator compares each inductor current with this reference current. RT8801 uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground. OCP Comparator + - VCSP + VCSN GMx Ix ESR VX RCSN 1k Figure 2. The Test Circuit of GM 150uA IX GM 300 Figure 5. Over Current Comparator Over Current Protection 250 200 V ADJ (mV) PWM 150 100 50 0 0 20 40 60 80 100 120 140 CH1:(5V/Div) CH2:(2V/Div) CH3:(1V/Div) VSS V CORE VX (mV) Figure 3. The Linearity of GMx Figure 4 shows the time sharing technique of GM amplifier. We apply test signal at phase 4 and observe the waveforms at both pins of GM amplifier. The waveforms show time sharing mechanism and the perfomance of GM to hold both input pins equal when the shared time is on. Time (25ms/Div) Figure 6. Over Current Protection at steady state Current Ratio Setting Time Sharing of GM CH1:(2V/Div) CH2:(50mV/Div) CH3:(50mV/Div) PWM3 Figure 7. Application circuit for current ratio setting VCSP4 VCSP4 and V CSN V CSN Time (1μs/Div) Figure 4 www.richtek.com 14 For some case with preferable current ratio instead of current balance, the corresponding technique is provided. Due to different physical environment of each channel, it is necessary to slightly adjust current loading between channels. Figure 7 shows the application circuit of GM for current ratio requirement. Applying KVL along L+DCR branch and R1+C//R2 branch: All brandname or trademark belong to their owner respectively DS8801-04 August 2007 Preliminary dIL V dV + DCR × IL = R1( C + C C ) + VC dt R2 dt dV R + R2 VC = R1C C + 1 dt R2 R2 For VC = DCR × IL R1 + R 2 L 35 30 25 RT8801 Current Ratio Function IL4 Look for its corresponding conditions : dIL dI + DCR × IL = (R1//R2)× C × DCR × L + DCR × IL dt dt L Let = (R1//R2)× C DCR L I L (A) 20 15 10 5 0 0 15 30 45 60 75 IL3 IL2 IL1 Thus if L = (R1//R2) × C DCR 90 I OUT (A) Then VC = R2 × DCR × IL R1+ R2 25 Figure 10 Current Balance Function With internal current balance function, this phase would share (R 1+R 2)/R 2 t imes current than other phases. Figure 8 & 9 show different settings for the power stages. Figure 10 shows the performance of current ratio compared with conventional current balance function in Figure 11. I L (A) IL1 20 15 IL4 IL2 IL3 10 5 0 -5 0 20 40 60 80 100 I OUT (A) Figure 8. GM4 Setting for current ratio function Figure 11 L DCR ESR V + CSP VCSN GMx Ix C Figure 9. GM1~3 Setting for current ratio function RCSN1 RCSN2 Figure 12. Application circuit of GM All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 15 RT8801 Preliminary VID on the Fly With external pull up resistors tied to VID pins, RT8801 converters different VID codes from CPU into output voltage. Figure 14 and Figure 15 show the waveforms of VID on the fly function. For load line design, with application circuit in Figure 12, it can eliminate the dead zone of load line at light loads. VCSP = VOUT +IL x DCR if GM holds input voltages equal, then VCSP = VCSN IX = = = VCSN IL × DCR + R CSN2 R CSN1 VID on the Fly (Falling) VOUT + IL × DCR IL × DCR + R CSN2 R CSN1 VOUT IL × DCR IL × DCR + + R CSN2 R CSN2 R CSN1 PWM V CORE VFB CH3:(500mV/Div) CH4:(1V/Div) For the lack of sinking capability of GM, RCSN2 should be small enough to compensate the negative inductor valley current especially at light loads. VCSN I × DCR ≥L R CSN2 R CSN1 Assume the negative inductor valley current is −5A at no load, then for RCSN1 = 330Ω, RADJ = 160Ω, VOUT = 1.300V 1.3V - 5A × 1m Ω ≥ R CSN2 330 Ω CH1:(5V/Div) CH2:(500mV/Div) VID125 VDAC = 1.500, IOUT = 5A Time (25μs/Div) Figure 14 VID on the Fly (Rising) PWM V CORE VFB CH3:(500mV/Div) CH4:(1V/Div) CH1:(5V/Div) CH2:(500mV/Div) RCSN2 ≤ 85.8kΩ Choose RCSN2 = 82kΩ Load Line without dead zone at light loads 1.31 1.3 1.29 VID125 VDAC = 1.500, IOUT = 5A V CORE (V) 1.28 1.27 1.26 1.25 1.24 1.23 0 5 10 15 20 25 Time (25μs/Div) RCSN2 open Figure 15 1/4 IVOSS RB1 EA + VDAC-VADJ RCSN2 = 82k I OUT (A) Figure 13 Figure 16 All brandname or trademark belong to their owner respectively www.richtek.com 16 DS8801-04 August 2007 Preliminary Output Voltage Offset Function To meet Intel® requirement of initial offset of load line, RT8801 provides programmable initial offset function. External resistor RVOSS and voltage source at VOSS pin generate offset current IVOSS = VVOSS . R VOSS One quarter of IVOSS flows through RB1 as shown in Figure 16. Error amplifier would hold the inverting pin equal to VDAC − VADJ. Thus output voltage is subtracted from VDAC − VADJ for a constant offset voltage. VCORE = VDAC - VADJ RFB1 4 × R VOSS RT8801 EA Rising Slew Rate VFB VCOMP CH1:(1V/Div) CH2:(2V/Div) A positive output voltage offset is possible by connecting RVOSS to VDD instead of to GND. Please note that when RVOSS is connected to VDD, VVOSS is VDD − 2V typically and half of IVOSS flows through RFB1. VCORE is rewritten as: VCORE = VDAC - VADJ + RFB1 R VOSS Time (250ns/Div) Figure 18. EA Falling Transient with 10pF Loading; Slew Rate = 8V/us 4.7k B 4.7k EA + Error Amplifier Characteristic For fast response of converter to meet stringent output current transient response, RT8801 provides large slew rate capability and high gain-bandwidth performance. A VREF EA Falling Slew Rate Figure 19. Gain-Bandwidth Measurement by signal A divided by signal B PGOOD Function VFB To indicate the condition of multiphase converter, RT8801 provides PGOOD signal through an open drain connection. As shown in Figure 20. PGOOD pin is externally pulled high when SS pin voltage higher than 3.7V and no fault occurs. CH1:(1V/Div) CH4:(2V/Div) VDD RPGOOD VCOMP Time (250ns/Div) VPGOOD SS > 3.7V Figure 17. EA Rising Transient with 10pF Loading; Slew Rate = 10V/us Figure 20 All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 17 RT8801 Design Procedure Suggestion Preliminary where VRAMP : ramp amplitude of saw-tooth wave LC Filter Pole = 1.45kHz and ESR Zero = 3.98kHz b. EA Compensation Network : Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and use the Type 2 compensation scheme shown in Figure 21. By calculation, the FZ = 0.88kHz, FP = 322kHz and Middle Band Gain is 3.19 (i.e 10.07dB). C2 68pF RB2 RB1 4.7k C1 a.Output filter pole and zero (Inductor, output capacitor value & ESR). b.Error amplifier compensation & sawtooth wave amplitude (compensation network). c.Kelvin sense for VCORE. Current Loop Setting GM amplifier S/H current (current sense component DCR, CSN pin external resistor value). VRM Load Line Setting a.Droop amplitude (ADJ pin resistor). b.No load offset (RCSN2) c.DAC offset voltage setting (VOSS pin & compensation network resistor RB1). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a.Kelvin sense for current sense GM amplifier input. b.Refer to layout guide for other items. Voltage Loop Setting Design Example Given: Apply for four phase converter VIN = 12V VCORE = 1.5V ILOAD (MAX) = 100A VDROOP = 100mV at full load (1mΩ Load Line) OCP trip point set at 40A for each channel (S/H) DCR = 1mΩ of inductor at 25°C L = 1.5μH COUT = 8000μF with 5mΩ equivalent ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero : From the following formula: Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB) 15k 12nF EA + Figure 21. Type 2 compensation network of EA The bode plot of EA compensation is shown as Figure 23. The bode plot of power stage is shown as Figure 24. The total loop gain is in Figure 25. 2. Over-Current Protection Setting Consider the temperature coefficient of copper 3900ppm/°C, IL × DCR = 150 μA R CSN R CSN = 40A × 1.39m Ω 150 μA R CSN = 370Ω 3. Soft-Start Capacitor Selection For most application cases, 0.1μF is a good engineering value. All brandname or trademark belong to their owner respectively www.richtek.com 18 DS8801-04 August 2007 Preliminary RT8801 0dB 180 ° Figure 22. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at 10.86MHz 0dB -180 ° Figure 23. The Frequency Response of the Compensator Network All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 19 RT8801 Preliminary 0dB -180 ° Figure 24. The Frequency Response of Power Stage 0dB -180 ° Figure 25. The Loop Gain of Converter All brandname or trademark belong to their owner respectively www.richtek.com 20 DS8801-04 August 2007 Preliminary Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. RT8801 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate stable current sensing. Keep well Kelvin sense to ensure the stable operation! 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path. SW1 L1 VIN RIN VOUT COUT CIN RL V L2 SW2 Figure 26. Power Stage Ripple Current Path All brandname or trademark belong to their owner respectively DS8801-04 August 2007 www.richtek.com 21 RT8801 +12V 0.1uF VCC PVCC BOOT1 UGATE1 CBOOT Next to IC Preliminary +12V or +5V PWM RT VOSS LO1 SGND COMP CC RCSN RT8801 CSN FB RFB RC Locate next to FB Pin VDD CBP Next to IC +5VSB PWM1 PHASE1 RT9607 LGATE1 GND CIN Kelvin Sense VCORE COUT Locate near MOSFETs CSPx ADJ GND For Thermal Couple Figure 27. Layout Consideration Figure 28 Figure 30 Figure 29 Figure 31 All brandname or trademark belong to their owner respectively www.richtek.com 22 DS8801-04 August 2007 Preliminary Outline Dimension RT8801 D D2 SEE DETAIL A L 1 E E2 e b 1 2 1 2 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol A A1 A3 b D D2 E E2 e L Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 4.950 3.400 4.950 3.400 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 5.050 3.750 5.050 3.750 Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.195 0.134 0.195 0.134 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.199 0.148 0.199 0.148 V-Type 32L QFN 5x5 Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com DS8801-04 August 2007 www.richtek.com 23