RT9262PS

Preliminary RT9262/A High Efficiency, Low Supply Current, Step-up DC/DC Converter General Description The RT9262/A is a compact, high efficient, step-up DC/DC converter with an adaptive current mode PWM control loop, providing a stable and high efficient operation over a wide range of load currents. It operates in both continuous and discontinuous current modes in stable waveforms without external compensation. The low start-up input voltage below 1V makes RT9262/A suitable for 1 to 4 battery cell applications providing up to 400mA output current. The 550kHz high switching rate minimized the size of external components. Besides, the 17μA low quiescent current together with high efficiency maintains long battery lifetime. The 1.8V to 5V output voltage is set with 2 external resistors. Both internal 2A switch and driver for driving external power devices (NMOS or NPN) are provided. A 300mA LDO is included in RT9262 to provide a secondary low noise output as well as an output current stop in the shutdown mode. Similarly, a 1.8V to 5V LDO output voltage can be set with 2 external resistors. For RT9262A, a low battery detector with 0.86V detection voltage is included. RT9262/A are provided in SOP-8 packages. Features 1.0V Low Start-up Input Voltage High Supply Capability to Deliver 3.3V 100mA with 1V Input Voltage 17μA Quiescent (Switch-off) Supply Current 90% Efficiency 550kHz Fixed Switching Rate Providing Flexibility for Using Internal and External Power Switches Built-in 300mA LDO, also for the Zero-OutputCurrent Shutdown Mode (RT9262) Boost DC-DC Integrating LDO for Up-Down Regulation (RT9262) Built-in 0.86V Voltage Detector (RT9262A) 8-Pin SOP Package RoHS Compliant and 100% Lead (Pb)-Free Applications PDA Portable Instrument Wireless Equipment DSC LCD Back Bias Circuit RF-Tags Ordering Information RT9262/A Package Type S : SOP-8 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Include Low Battery Detector Include LDO Pin Configurations (TOP VIEW) GND EXT LFB LDO O 2 3 4 8 7 6 5 EN LX VDD FB RT9262CS Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating. GND EXT LBO LBI 2 3 4 8 7 6 5 EN LX VDD FB RT9262ACS SOP-8 DS9262/A-11 March 2007 www.richtek.com 1 RT9262/A Typical Application Circuit Preliminary VIN VDD EN 2.5V VOUT2 R4 1.3M C6 10uF R3 680K C5 1nF LDO O LFB GND + C3 100uF C4 100pF EXT LX FB R2 C2 980K 1uF + R1 1.6M RT9262 L1 4.7uF D1 3.3V VOUT1 C1 100uF Figure 1. RT9262 Typical Application for Portable Instruments below 400mA VIN VDD EN Low Battery Warning Output (Open Collector) LBO R4 LFB R3 GND FB R2 C2 980K 1uF + C3 100uF C4 100pF R1 1.6M L1 4.7uF D1 3.3V VOUT1 RT9262 EXT LX C1 100uF Figure 2. RT9262A Typical Application for Portable Instruments below 400mA VIN Chip Enable EN 3.3V VOUT LDO O + C3 100uF VDD RT9262 EXT LX GND FB R2 C2 980K 1uF + C4 100pF R1 1.6M L1 4.7uF D1 C5 10uF LFB C1 100uF Figure 3. Application Circuit with Zero-Output-Current Shutdown Mode Control www.richtek.com 2 DS9262/A-11 March 2007 Preliminary RT9262/A VIN VDD EN 2.5V VOUT2 R4 1.3M R3 680K C5 1nF LDO O LFB GND RT9262 LX EXT FB R2 980K C2 1uF Q1 D1 N MOS + C3 100uF C4 100pF R1 1.6M L1 4.7uF 3.3V VOUT1 + C6 10uF C1 100uF Figure 4. 0.4A ~ 2A Output Current Application 5V VIN L1 C4 100uF EN 10uF VDD RT9262 EXT LX GND FB Rm 0.05 ~ 0.1 Q1 N MOS C3 0.1uF LDO O LFB D1 2.5V VOUT2 C6 10uF R4 1.3M R3 680K C5 1nF R1 2.2M + 15V VOUT1 DS9262/A-11 March 2007 + C2 R2 200K 1uF C1 100uF Figure 5. High Voltage Application (Rm should be added when IL > 100mA) www.richtek.com 3 RT9262/A Functional Pin Description Pin No. RT9262 1 2 3 4 RT9262A 1 2 --GND EXT LFB LDOO Ground Pin Name Preliminary Pin Function Output Pin for Driving External NMOS or NPN When driving an NPN, a resistor should be added for limiting base current. Feedback Pin of the Built-in LDO (Internal Vref = 0.86V) Voltage Output Pin of the Built-in LDO Drain Output Pin of the NMOS of the Built-in Low Voltage Detector -- 3 LBO This pin will be internally pulled low when the voltage at LBI pin drops to below 0.86V. -- 4 LBI Input Pin of the Built-in Low Voltage Detector Trip point = 0.86V Feedback Input Pin Internal reference voltage for the error amplifier is 1.25V. Input Positive Power Pin of RT9262/A Pin for Switching Chip Enable Pin (Active High). 5 6 7 8 5 6 7 8 FB VDD LX EN Function Block Diagram VDD Q2 P MOS LDO O LFB FB 1.25V VDD R2 Shut Down EN Q3 N MOS Over Temp. Detector RT9262 + EXT LX + Loop Control Circuit Q1 N MOS R1 0.86V VDD GND www.richtek.com 4 DS9262/A-11 March 2007 Preliminary VDD LBI LBO Q2 N MOS + 0.86V EXT LX FB 1.25V VDD R2 Shut Down EN Q3 N MOS Over Temp. Detector RT9262/A RT9262A + Loop Control Circuit Q1 N MOS R1 GND Absolute Maximum Ratings Supply Voltage ----------------------------------------------------------------------------------------------------- −0.3V to 7V LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to 7V LDO Output Voltage ---------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V) Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V) LX Pin Switch Current -------------------------------------------------------------------------------------------- 2.5A EXT Pin Driver Current -------------------------------------------------------------------------------------------- 30mA LBO Current -------------------------------------------------------------------------------------------------------- 30mA Power Dissipation, PD @ TA = 25°C SOP-8 ---------------------------------------------------------------------------------------------------------------- 0.625W Package Thermal Resistance SOP-8, θJA ---------------------------------------------------------------------------------------------------------- 160°C/W Operating Junction Temperature ------------------------------------------------------------------------------- 150°C Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to +150°C DS9262/A-11 March 2007 www.richtek.com 5 RT9262/A Electrical Characteristics Preliminary (VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified) Parameter Start-UP Voltage Operating VDD Range No Load Current I (VIN) Switch-off Current I (VDD) Shutdown Current I (VIN) Feedback Reference Voltage Feedback Reference Voltage for LDO LBI Pin Trip Point Switching Rate Maximum Duty LX ON Resistance Current Limit Setting EXT ON Resistance to VDD EXT ON Resistance to GND Line Regulation Load Regulation LDO PMOS ON Resistance RT9262 LDO Drop Out Voltage LBO ON Resistance EN Pin Trip Level Temperature Stability for FB, LFB, LBI Thermal Shutdown Thermal Shutdown Hysterises RT9262 RT9262A RT9262 RT9262A Symbol VST VDD INO LOAD Test Conditions IL = 1mA Start-up to IDD1 > 250μA VIN = 1.5V, VOUT = 3.3V Min -0.8 ---1.225 0.843 0.843 ---------- Typ 0.98 -47 17 0.1 1.25 0.86 0.86 550 92 0.25 2 40 30 10 0.25 1 70 40 0.8 50 165 10 Max 1.05 6.5 --1 1.275 0.877 0.877 --------1.5 --1.4 ---* Units V V μA μA μA V V V kHz % Ω A Ω Ω mV/V mV/mA Ω mV Ω V ppm/°C °C °C ISWITCH OFF VIN = 6V IOFF VREF VREF EN Pin = 0V, VIN = 4.5V Close Loop, VDD = 3.3V Close Loop, VDD = 3.3V VDD = 3.3V FS DMAX VDD = 3.3V VDD = 3.3V VDD = 3.3V ILIM VDD = 3.3V VDD = 3.3V VDD = 3.3V ΔVLINE ΔVLOAD VIN = 1.5 to 2.5V, IL = 1mA VIN = 2.5V, IL = 1 to 100mA VDD = 3.3V VDROP VDD = 3.3V, VDD = 3.3V VDD = 3.3V TS TSD ΔTSD Guaranteed by Design Guaranteed by Design Guaranteed by Design IL = 100mA --0.2 ---- * Note: The EN pin shall be tied to VDD pin and inhibit to act the ON/OFF state whenever the VDD pin voltage may reach to 5.5V or above. www.richtek.com 6 DS9262/A-11 March 2007 Preliminary Typical Operating Characteristics Efficiency 100 RT9262/A Efficiency 100 Refet to Application Circuit Figure 1 and Figure 2 90 80 Refet to Application Circuit Figure 1 and Figure 2 90 80 Efficiency (%) Efficiency (%) 70 60 50 40 30 70 60 50 40 30 VIN = 3.0V 2.5V 2.0V 1.5V 1.2V VOUT = 3.3V; TA = 25°C 0.1 1 10 VIN = 4.0V 3.0V 2.0V 1.5V 1.2V 1.0V 100 1000 20 0.01 VOUT = 5.0V; TA = 25°C 20 0.01 0.1 1 1.0V 10 100 1000 I LOAD (mA) I LOAD (mA) No Load Current 90 80 70 No Load Current 140 VOUT = 3.3V; TA = 25°C 120 100 VOUT = 5.0V; TA = 25°C 60 I DD (uA) I DD (uA) Refet to Application Circuit Figure 1 and Figure 2 50 40 30 80 60 40 20 10 0 1 1.2 1.5 2 2.5 3 20 Refet to Application Circuit Figure 1 and Figure 2 0 1 1.2 1.5 2 2.5 3 4 Input Voltage (V) Input Voltage (V) Start Up Voltage 1.4 Start Up Voltage 1.25 1.20 VOUT = 3.3V; TA = 25°C 1.3 VOUT = 5.0V; TA = 25°C Input Voltage (V) 1.2 1.1 1.0 0.9 Input Voltage (V) Refet to Application Circuit Figure 1 and Figure 2 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 Refet to Application Circuit Figure 1 and Figure 2 0 25 50 75 100 0.8 0 20 40 60 80 100 I LOAD (mA) DS9262/A-11 March 2007 I LOAD (mA) www.richtek.com 7 RT9262/A Applications Information Output Voltage Setting Preliminary Referring to application circuits Figure 1 to Figuer 5 the output voltage of the switching regulator (VOUT1) can be set with Equation (1). The LDO output voltage (VOUT2 of RT9262) can be set with Equation (2). VOUT1 = (1 + R1 ) × 1.25 V R2 R4 ) × 0.86 V R3 PRECAUTION 1: Improper probing to FB or LFB pin will cause fluctuation at VOUT1 and VOUT2. It may damage RT9262/A and system chips because VOUT1 may drastically rise to an overrated level due to unexpected interference or parasitics being added to FB pin. PRECAUTION 2: Disconnecting R1 or short circuit across R2 may also cause similar IC damage as described in precaution 1. PRECAUTION 3: When large R values were used in feedback loops, any leakage in FB/LFB node may also cause V OUT1 and V OUT2 v oltage fluctuation, and IC damage. To be especially highlight here is when the air moisture frozen and re-melt on the circuit board may cause several mA leakage between IC or component pins. So, when large R values are used in feedback loops, post coating, or some other moisture-preventing processes are recommended. (1) VOUT 2 = (1 + (2) And trip point of the low battery detector is 0.86V at LBI pin of RT9262A. Feedback Loop Design Referring to application circuits Figure 1 to Figure 5. The selection of R1, R2, R3, and R4 based on the trade-off between quiescent current consumption and interference immunity is stated below: Follow Equation (1) and Equation (2). Higher R reduces the quiescent current (Path current = 1.25V/R2, and 0.86V/R3), however resistors beyond 5MW are not recommended. Lower R gives better noise immunity, and is less sensitive to interference, layout parasitics, FB/LFB node leakage, and improper probing to FB/LFB pins. A proper value of feed forward capacitor parallel with R1 (or R4) on Figure 1 to Figure 5 can improve the noise immunity of the feedback loops, especially in an improper layout. An empirical suggestion is around 100pF ~ 1nF for feedback resistors of MW, and 10nF~ 0.1μF for feedback resistors of tens to hundreds kΩ. For applications without standby or suspend modes, lower values of R1 to R4 are preferred. For applications concerning the current consumption in standby or suspend modes, the higher values of R1 to R4 are needed. Such "high impedance feedback loops" are sensitive to any interference, which require careful layout and avoid any interference, e.g. probing to FB/LFB pins. VOUT1 Prober Parasitics _ Q + R1 FB Pin R2 Layout Guide A full GND plane without gap break. VOUT1 to GND noise bypass−Short and wide connection for C2 to Pin1 and Pin6. VIN to GND noise bypass - Add a 100μF capacitor close to L1 inductor, when VIN is not an idea voltage source. Minimized FB/LFB node copper area and keep far away from noise sources. Minimized parasitic capacitance connecting to LX and EXT nodes, which may cause additional switching loss. The following diagram is an example of 2-layer board layout for application circuits Figure 1 to Figure 4. www.richtek.com 8 DS9262/A-11 March 2007 Preliminary RT9262/A First Layer RT9262/A Second Layer (Full GND Plane) DS9262/A-11 March 2007 www.richtek.com 9 RT9262/A Outline Dimension Preliminary A H M J B F C I D Dimensions In Millimeters Symbol Min A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.170 0.050 5.791 0.400 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.200 1.270 Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.002 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 10 DS9262/A-11 March 2007