BD3506F_08

TECHNICAL NOTE High-performance Regulator IC Series for PCs Ultra Low Dropout Linear Regulators for PC Chipsets BD3506F, BD3506EFV Description The BD3506F/EFV is an ultra-low dropout linear regulator for chipset that can achieve ultra-low voltage input to ultra-low voltage output. By using N-MOS FET for built-in power transistor, the regulator can be used at ultra-low I/O voltage difference up to voltage difference generated by ON resistor (Ron = 120 mΩ/100 mΩ). Because by reducing the I/O voltage difference, large current (Iomax = 2.5A) output is achieved and conversion loss can be reduced, switching power supply can be replaced. BD3506F/EFV does not need any choke coil, diode for rectification and power transistor which are required for switching power supply, total cost of the set can be reduced and compact size can be achieved for the set. Using external resistors, optional output from 0.65V to 2.5V can be set. In addition, since voltage output start-up time can be adjusted by using the NRCS terminal, it is possible to meet the power supply sequence of the set. Features 1) Built-in high-accuracy reference voltage circuit (0.65V±1%) 2) Built-in VCC low input maloperation prevention circuit (Vcc = 4.15V) 3) Reduced rush current by NRCS 4) Built-in ultra-low on-resistor (120/100 mΩ typ) Nch Power MOSFET (BD3506F/BD3506EFV) 5) Built-in current limiting circuit (2.5A min) 6) Built-in thermal shutdown circuit 7) Output variable type (0.65-2.5V) 8) Adoption of SOP8 package (BD3506F): 5.0 x 6.2 x 1.5 (mm) 9) Adoption of high power HTSSOP-B20 package (BD3506EFV): 5.0 x 6.4 x 1.0 (mm) Applications Mobile PC, desktop PC, LCD-TV, DVD, digital home appliances ●Line up Parameter Ron Output Current Package BD3506F 120mΩ 2.5A SOP8 BD3506EFV 100mΩ 2.5A HTSSOP-B20 Oct. 2008 ●ABSOLUTE MAXIMUM RATINGS ◎BD3506F ○ABSOLUTE MAXIMUM RATINGS(Ta=25℃) Parameter Input Voltage1 Input Voltage2 Enable Input Voltage Power Dissipation1 Power Dissipation2 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Symbol VCC VIN Ven Pd1 Pd2 Topr Tstg Tjmax BD3506F 7* 7* 7 560 * 690 * 2 3 1 1 BD3506EFV 7* 7* 7 1000 * 4 1 1 Unit V V V mW mW ℃ ℃ ℃ -10～+100 -55～+125 +150 -10～+100 -55～+125 +150 *1 However, not exceeding Pd. *2 In the case of Ta≥25°C (no heat radiation board), derated at 4.48 mW/°C. *3 In the case of Ta≥25°C (when mounting to 70mmx70mmx1.6mm glass epoxy substrate), derated at 5.52 mW/°C. *4 In the case of Ta≥25°C (when mounting to 70mmx70mmx1.6mm glass epoxy substrate), derated at 8.00 mW/°C. ●RECOMMENDED OPERATING CONDITIONS ◎BD3506F/EFV ○RECOMMENDED OPERATING CONDITIONS(Ta=25℃) Parameter Input Voltage1 Input Voltage2 Output Voltage Enable Input Voltage Capacitor in NRCS pin Symbol VCC VIN Vo Ven CNRCS MIN 4.3 1.2 VFB -0.3 0.001 MAX 5.5 VCC-1 * 2.5 5.5 1 5 Unit V V V V uF *5 However, irrespective of charging order of VCC and VIN. * No radiation-resistant design is adopted for the present product. 2/16 ●ELECTRICAL CHARACTERISTICS ◎BD3506F/BD3506EFV ○ELECTRICAL CHARACTERISTICS (unless otherwise noted, Ta=25℃ VCC=5V Ven=3V VIN=1.8V R1=3.9KΩ Standard Value Parameter Symbol MIN TYP MAX Bias Current ICC 0.7 1.4 Bias current IST 0 10 Shut-Down Mode Current VOUT 1.200 Output Voltage Io 2.5 Maximum Output Current Iost 2.0 Maximum Short Current Tcvo 0.01 Temperature coefficient of Output VFB1 0.643 0.650 0.657 Voltage Feed Back Voltage 1 VFB2 0.630 0.650 0.670 Feed Back Voltage 2 Reg.l1 0.1 0.5 Line Regulation 1 Reg.l2 0.1 0.5 Line Regulation 2 Reg.L 0.5 10 Dropout Voltage (BD3506F) dVo 120 200 Dropout Voltage (BD3506EFV) dVo 100 160 Standby Discharge Current Iden 150 [Enable] High level Enable Input Voltage Enhi 2 5.5 Low level Enable Input Voltage Enlow -0.3 0.8 Enable pin Input Current Ien 7 10 [Voltage Feed Back] Feed Back terminal Bias Current IFB -100 0 100 [NRCS] NRCS Charge Current Inrcs 14 20 26 NRCS Standby Voltage VSTB 0 50 [UVLO] VCC UVLO VCCUVLO 4.00 4.15 4.30 VCC UVLO Hysterisis Vcchys 100 160 220 *5 Design Guarantee R2=3.3KΩ) Unit mA uA Ven=0V V Io=50mA A A Vo=0V %/℃ V V %/V %/V mV mV mV mA V V uA nA uA mV V mV Vnrcs=0.5V Ven=0V Vcc:Sweep-up Vcc:Sweep-down Io=50mA Io=0 to 2A, Ta=-10 to 100℃ *5 VCC=4.3V to 5.5V VIN=1.2V to 3.3V Io=0 to 2A Io=1A,VIN=1.2V, Ta=-10 to 100℃ *5 Io=1A,VIN=1.2V, Ta=-10 to 100℃ *5 Ven=0V, Vo=1V Condition Ven=3V 3/16 ●Reference Data 10 ⊿Vout (50mV/div) EN 8 Vin IIN(uA) 6 4 2 0 0 2 4 VIN(V) 6 8 Vcc Iout (1A/div) Vo Fig.1 Transient Response Fig.2 Input Voltage SequenceFinal Input Voltage EN 656 655 654 Fig.3 VIN-IIN(Ta=25℃) EN Vin Vfb(mV) EN Vin 653 652 651 650 649 Vcc Vcc Vo 648 647 646 -10 10 30 50 Ta( ℃) 70 90 Vo Fig.4 Input Voltage SequenceFinal Input Voltage VIN Fig.5 Ta-Vfb Fig.6 Input Voltage SequenceFinal Input Voltage VCC 18 16 Vo 20mV/DIV Vo 20mV/DIV IEN(uA) 14 12 10 8 6 4 2 0 0 1 2 3 VEN(V) 4 5 Io 1A/DIV Io 1A/DIV Fig.7 Transient Response (rise) Cout=100uF Fig.8 Transient Response (fall) Cout=100uF Fig.9 VEN-IEN Vo 20mV/DIV EN 2V/DIV NRCS 0.5V/DIV EN 2V/DIV NRCS 0.5V/DIV Vo 0.5V/DIV Io 1A/DIV Vo 0.5V/DIV Fig.10 Transient Response (rise) Cout=220uF Fig.11 Start up Wave Form Fig.12 Shut down Wave Form 4/16 700 600 500 VFB(mV) 400 300 200 100 0 0 0.2 0.4 0.6 0.8 VNRCS(V) 1 1.2 Vo 20mV/DIV Vo 50mV/DIV Io 1A/DIV Io 1A/DIV Fig.13 VNRCS-VFB Fig.14 Transient Response (fall) Cout=220uF Fig.15 Transient Response (rise) 47u MLCC+30mΩ Vo 50mV/DIV Io 1A/DIV Fig.16 Transient Response (fall) 47u MLCC+30mΩ 5/16 ●BLOCK DIAGRAM ◎BD3506F VCC 4 VCC VCC Enable EN 1 Reference Block UVLO CL Current Limit VIN 2 VIN Vo1 7 CL UVLO TSD 8 EN 3 NRCS TSD 6 NRCS 5 GND R1 Vo2 VFB R2 Vo Thermal Shutdown ◎BD3506EFV VCC 17 VCC VCC VIN1 UVLO VCC 5 6 7 CL UVLO TSD NRCS 4 NRCS 2 GND 3 20 8 EN 9 10 16 CL Current Limit 14 15 VIN2 VIN EN 13 Reference Block Vo1 Vo2 Vo3 Vo4 Vo5 Vo6 FB R1 R2 Vo Thermal Shutdown TSD 6/16 ◎BD3506F ●PIN CONFIGRATION ●PIN FUNCTION PIN No. PIN NAME 8 VO2 7 VO1 6 NRCS 5 GND 1 2 3 4 5 6 EN VIN FB VCC GND NRCS VO1 VO2 PIN FUNCTION Enable Pin Input Voltage Pin Output Voltage Feedback Power Source Ground Pin NRCS(Non Rush Current on Start Up) time setup VO1 Pin VO2 Pin EN 1 VIN 2 FB 3 VCC 4 7 8 ◎BD3506EFV ●PIN CONFIGRATION ●PIN FUNCTION PIN No. 1 PIN NAME N.C. GND1 GND2 NRCS VO1 VO2 VO3 VO4 VO5 VO6 N.C. N.C. EN VIN1 VIN2 FB VCC N.C. N.C. GND3 PIN FUNCTION Non connection Ground1 Pin Ground2 Pin NRCS(Non Rush Current on Start Up) time setup VO1 Pin VO2 Pin VO3 Pin VO4 Pin VO5 Pin VO6 Pin Non connection Non connection Enable Pin Input Voltage1 Pin Input Voltage2 Pin Output Voltage Feedback Power Source Non connection Non connection Ground3 Pin N.C. 1 GND1 2 GND2 3 NRCS 4 20 GND3 19 N.C. 18 N.C. 17 VCC 16 FB 15 VIN2 14 VIN1 13 EN 12 N.C. 11 N.C. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VO1 5 VO2 6 VO3 7 VO4 8 VO5 9 VO6 10 7/16 ●Block Function AMP An error amplifier that compares reference voltage (VREF) to Vo and drives Nch FET (Ron = 120/100 mΩ) of output. The frequency characteristics are optimized so that low ESR functional polymer capacitor can be used for the output capacitor and high-speed transient response can be achieved. The input voltage range at the AMP section is GND-2.5V and the output voltage range of the AMP section is GND-VCC. At the time of EN OFF or UVLO, the output is brought to the LOW level and the output NchFET is turned OFF. EN By the logic input pin, regulator ON/OFF is controlled. At the time of OFF, the circuit current is controlled to be 0 μA to reduce the standby current consumption of the apparatus. In addition, EN turns ON FET that can discharge NRCS terminal Vo and removes excess electric charge to prevent maloperation of IC on the load side. Since there is no electrical connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence. UVLO UVLO turned OFF output to prevent output voltage from making maloperation at the time of Vcc reduced voltage. Same as EN, UVLO discharges NRCS Vo. When voltage exceeds the threshold voltage (TYP 4.15V), UVLO starts output. CURRENT LIMIT In the event the output current that exceeds the current (2.5A or more) set inside the IC flows when output is turned ON, output voltage is attenuated to protect the IC on the load side. When current reduces, output voltage returns to the set voltage. NRCS Connecting an external capacitor to the counter-GND of NRCS pin can achieve soft start. The output voltage startup time is determined by the time when the NRCS terminal reaches VFB (0.65V). During start-up, the NRCS terminal serves as a constant current source of 20 uA (Typ.) output, and charges the capacitor externally connected. TSD (Thermal Shut down) In order to prevent thermal breakdown and thermal runaway of the IC, the output is turned OFF when chip temperature becomes high. In addition, when temperature returns to the specified temperature, the output is recovered. However, since the temperature protection circuit is originally built in to protect the IC itself, thermal design within Tj(max) is requested. VIN This is a large-current supply line. The VIN terminal is connected to the rain of output NchFET. Since there is no electrical connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence. However, because there is body Di of output NchFET between VIN and Vo, there is electrical connection (Di-connection) between VIN and Vo. Consequently, when the output is turned ON/OFF by VIN, reverse current flows from Vo to VIN, to which care must be taken. 8/16 ●TIMING CHART EN ON/OFF VIN VCC EN NRCS Start up Time Vo t VCC ON/OFF VIN UVLO hysterisis VCC EN NRCS Start up Time Vo t 9/16 ●Evaluation Board ■ BD3506F Evaluation Board Circuit U1 EN 1 VIN Cin1 VCC Ccc ■ BD3506F Evaluation Board Application Components Part No U1 R1 R2 Value 3.3k 3.9k Company ROHM ROHM ROHM Parts Name BD3506F MCR03EZPF3301 MCR03EZPF3901 Part No Ccc Cin1 Co C6 Value 1uF 10uF 220uF 0.01uF Company ROHM ROHM SANYO,etc ROHM Parts Name MCH184CN105K MCH218CN106K 2R5TPE220MF 2 3 4 EN VIN FB VCC BD3506F VO2 VO1 NRCS GND 8 7 6 GND 5 CNRCS R1 Vo CO R2 ■ BD3506F Evaluation Board Layout Silk Screen TOP Layer Bottom Layer For Evaluation Board, BD3506EFV is available. 10/16 ●Recommended Circuits R2 VOUT(1.2V)/2.5A 1 Ven 2 C2 VIN 3 R1 C4 4 Vcc C1 5 6 7 8 C3 + Part No R1/R2 Value 6.5k/5.5k voltage setting resistors (R1, R2). VREF bias current (±100 nA). Notes for use The present IC can set output voltage by external reference voltage (VR) and value of output Output voltage can be set by VRxR2/(R1+R2) but it is recommended to use at the resistance value (total: about 10 kΩ) which is not susceptible to C3 100μF Connect the output capacitor between Vo1, Vo2 terminals and GND terminal without fail in order to stabilize output voltage. The output capacitor has a role to compensate for the phase When of loop gain and to reduce output voltage fluctuation when load is rapidly changed. there is an insufficient capacity value, there is a possibility to cause oscillation, and when the equivalent serial resistance (ESR) of the capacitors is large, output voltage fluctuation is increased when load is rapidly changed. conditions. About 100-µF high-performance electrolytic capacitors are recommended but output capacitor greatly depends on temperature and load In addition, when only ceramic capacitors with low ESR are used, or various Thoroughgoing confirmation at application temperature capacitors are connected in series, the total phase allowance of loop gain becomes not sufficient, and oscillation may result. C1 0.1μF and under load range conditions is requested. The input capacitor plays a part to lower output impedance of a power supply connected to input terminals (Vcc). When output impedance of this power supply increases, the input The use of capacitors of about 0.1 μF with low ESR, voltages (Vcc,) become unstable and there is a possibility of giving rise to oscillation and degraded ripple rejection characteristics. which provide less capacity value changes caused by temperature changes, is recommended, but since input capacitor greatly depends on characteristics of the power supply used for input, substrate wiring pattern, thoroughgoing confirmation under the application temperature and load range, is requested. C2 10μF The input capacitor plays a part to lower output impedance of a power supply connected to input terminals (VIN). When output impedance of this power supply increases, the input The use of capacitors of about 10 μF with low ESR, voltages (VIN) become unstable and there is a possibility of giving rise to oscillation and degraded ripple rejection characteristics. which provide less capacity value changes caused by temperature changes, is recommended, but since input capacitor greatly depends on characteristics of the power supply used for input, substrate wiring pattern, thoroughgoing confirmation under the application temperature and load range, is requested. C4 1μ F To the present IC, there mounted is a function (Non Rush Current on Start-up: NRCS) to prevent rush current from VIN to load and output capacitor via Vo at the output voltage start-up. When the EN terminal is reset from High or UVLO, constant current is allowed to flow from the NRCS terminal. By this current, voltage generated at the NRCS terminal becomes the In order to stabilize the NRCS set time, it is reference voltage and output voltage is started. temperature change. recommended to use a capacitor (B special) with less capacity value change caused by 11/16 ●About heat loss In designing heat, operate the apparatus within the following conditions. (Because the following temperatures are warranted temperature, be sure to take margin, etc. into account.) 1. Ambient temperature Ta shall be not more than 100°C. 2. Chip junction temperature Tj shall be not more than 150°C. Chip junction temperature Tj can be considered under the following two cases. ①Chip junction temperature Tj is found from ②Chip junction temperature Tj is found from ambient temperature Ta: IC surface temperature TC under actual Tj=Ta+θj-a×W application conditions: ＜Reference value＞ Tj=TC+θj-c×W ＜Reference value＞ θj-a:SOP8 222.0℃/W (IC only) θj-c:SOP8 41.0℃/W 181.0℃/W Single-layer substrate HTSSOP-B20 45.0℃/W (substrate surface copper foil area: less 3%) Substrate size:70×70×1.6mm θj-a:HTSSOP-B20 125.0℃/W Single-layer substrate (Substrate surface capper (substrate surface copper foil area: less 3%)) foil area:less3%) 86.2℃/W 2nd-layer 2 (substrate surface copper foil area:15×15mm ) θj-a:HTSSOP-B20 125.0℃/W 54.3℃/W 2nd-layer 86.2℃/W 2 (substrate surface copper foil area: 70×70mm ) 54.3℃/W 39.1℃/W 4th-layer 39.1℃/W 2 (substrate surface copper foil area: 70×70mm ) Substrate size 70×70×1.6mm3 (thermal vias in the board.) Most of heat loss in BD3506F/EFV occurs at the output Nch FET. The power lost is determined by multiplying the voltage between VIN and Vo by the output current. Confirm voltage and output current conditions of VIN and Vo used, and collate them with the thermal derating characteristics. Because BD3506EFV employs the power PKG, the thermal derating characteristics significantly vary in accord with the pc board conditions. When designing, care must be taken to the size of a pc board to be used. Power dissipation (W) = {Input voltage (VIN) – Output voltage (V0≒VREF)}×Io (averaged) Ex.) If VIN = 1.8 volts, V0=1.2 volts, and Io (averaged)=1.5 A, the power dissipation is given by the following: Power dissipation (W) =(1.8 volts – 1.2 volts) × 1.5 (A) = 0.9 W ●EQUIVALENT CIRCUIT Vcc Vcc 1kΩ 1kΩ NRCS 1kΩ 1kΩ VIN 1kΩ 10kΩ 1kΩ Vcc Vcc VFB 10kΩ 1kΩ 100kΩ 100kΩ 20pF 1kΩ Vo1 Vo2 50kΩ 1kΩ EN 350kΩ 10kΩ 12/16 ●NOTE FOR USE 1. Input terminals(VCC,VIN,EN) In the present IC, EN terminal, VIN terminal, and VCC terminal have an independent construction. In addition, in order to prevent malfunction at the time of low input, the UVLO function is equipped with the VCC terminal. They begin to start output voltage when all the terminals reach threshold voltage without depending on the input order of input terminals. 2. Operating range Within the operating range, the operation and function of the circuits are generally guaranteed at an ambient temperature within the range specified. The values specified for electrical characteristics may not be guaranteed, but drastic change may not occur to such characteristics within the operating range. 3. Permissible dissipation With respect to the permissible dissipation, the thermal derating characteristics are shown in the Exhibit, which we hope would be used as a good-rule-of-thumb. Should the IC be used in such a manner to exceed the permissible dissipation, reduction of current capacity due to chip temperature rise, and other degraded properties inherent to the IC would result. You are strongly urged to use the IC within the permissible dissipation. 4. Built-in thermal shutdown protection circuit The thermal shutdown circuit is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the IC. Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the activation of the circuit premised. 5. Inspection by set substrate In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic measures, provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore, when the set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig and be sure to turn OFF power supply to remove the jig. 6. For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute maximum rating, physical safety measures are requested to be taken, such as fuses, etc.. 7. The use in the strong electromagnetic field may sometimes cause malfunction, to which care must be taken. 8. In the event that load containing a large inductance component is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode. (Example) OUTPUT PIN 9. We are certain that examples of applied circuit diagrams are recommendable, but you are requested to thoroughly confirm the characteristics before using the IC. In addition, when the IC is used with the external circuit changed, decide the IC with sufficient margin provided while consideration is being given not only to static characteristics but also variations of external parts and our IC including transient characteristics. 13/16 10. The present IC is a monolithic IC and has P+ isolation between elements to separate elements and a P substrate. With this P layer and N layer of each element, PN junction is formed, and various parasitic elements are formed. For example, when resistors and transistors are connected to terminals as illustrated below, at the resistor, when GND>terminal A, and at transistor (NPN), when GND>terminal B, PN junction works as a parasitic diode. at the transistor (NPN), when GND>terminal B, the parasitic NPN transistor is operated by the N-layer of other element adjacent to the parasitic diode. The parasitic element is inevitably formed because of the IC construction. The operation of the parasitic element gives rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently, take utmost care not to use the IC to operate the parasitic element such as applying voltage lower than GND (P substrate) to the input terminal. Resistor （PIN A） （PIN B） C NPN Transistor Structure (NPN) B E Parasitic diode GND N P+ N N P substrate N Parasitic diode GND Parasitic diode N P substrate GND Nearby other device Parasitic diode P P+ P+ N N C B E GND P P+ （PIN A） GND （PIN B） ●POWER DISSIPATION SOP8 (1) Mounted on board 70mm×70mm×1.6mm Glass-epoxy PCB θj-a=181℃/W (2) Without heat sink θj-a=222℃/W (1) 690mW HTSSOPB-20 measure：TH-156（Kuwano-Denki） measure condition：Rohm Standard Board PCB size：70mm×70mm×1.6mmt (PCB with Thermal Via) PCB①：Single-layer substrate PCB②：Double-layer substrate [mW] 700 600 Power Dissipation [Pd] 500 [W] 5 4 Power Dissipation Pd （substrate surface copper foil area 15mm×15mm） PCB③：Double-layer substrate (2) 560mW ④3.20W （substrate surface copper foil area 70mm×70mm） PCB④：Fourth-layer substrate 400 300 200 100 0 0 25 50 75 100 125 150 [℃] 100℃ 3 ③2.30W （substrate surface copper foil area 70mm×70mm） PCB①：θja=125.0℃/W PCB②：θja=86.2℃/W 2 ②1.45W ①1.00W PCB③：θja=54.3℃/W PCB④：θja=39.1℃/W 1 0 25 50 75 100 125 Ambient Temperature [Ta] Ambient Temperature [Ta] 150 [℃] 14/16 ●Ordering part number B ・BD3506 D 3 5 0 6 F ― E 2 Part Number Package Type ・F : SOP8 ・EFV : HTSSOP-B20 E2 Embossed carrier tape ●Package specification SOP8 Tape Quantity 5.0±0.2 8 5 Embossed carrier tape 2500pcs E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 6.2±0.3 4.4±0.2 1 4 1.5±0.1 0.11 0.15±0.1 0.1 1.27 0.4±0.1 0.3Min. Direction of feed 1234 (Unit:mm) Reel 1234 ※When you order , please order in times the amount of package quantity. 1234 1Pin 1234 1234 Direction of feed 1234 1234 1234 HTSSOP-B20 6.5 ± 0.1 20 11 Tape Quantity 0.5 ± 0.15 1.0 ± 0.2 Embossed carrier tape 2500pcs E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 6.4 ± 0.2 4.4 ± 0.1 Direction of feed 0.325 1 10 1.0Max. 0.85 ± 0.05 0.08 ± 0.05 0.17 +0.05 −0.03 S 0.08 S 0.65 0.2 +0.05 −0.04 1234 （Unit:mm) Reel 1234 ※When you order , please order in times the amount of package quantity. 1234 1pin 1234 1234 Direction of feed 1234 1234 1234 15/16 16/16 Catalog No.08T437A '08.10 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. 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If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev3.0