BD9211F

1/4 STRUCTURE NAME OF PRODUCT Silicon Monolithic Integrated Circuit LED Driver control IC TYPE FEATURE ＢＤ９２１１Ｆ ・ Using 20V high-voltage-withstand process ・ 1Channel Push-Pull control ・ Current and voltage feedback is controlled by drive frequency modulation ・ Built-in soft start circuit ・ Built-in timer latch circuit ・ Built-in shut down protection ・ Built-in UVLO detection circuit ・ Output Over Voltage Protection ・ Built-in error signal output function ・ Switching to current consumption save mode through STB pin ・ Possible to control the burst by external PWM ○Absolute Maximum Ratings (Ta=25℃) Item Power supply voltage Driver Output Operating temperature Storage temperature range Maximum Junction Temperature Symbol VCC N1,N2 Topr Tstg Tjmax Pd Rated voltage 20 20 -40～+85 -55～+150 +150 687* Unit V V ℃ ℃ ℃ mW Power Dissipation * It reduces gradually by 5.5 mW/℃ if above Ta= 25℃ (when mounting the board of 70.0mm×70.0mm×1.6mm) 〇Recommended Operation Ranges Item Power Supply PWMIN input frequency range Symbol VCC F_PWMIN FOUT Range 8.0～18.0 60～500 25～200 Unit V Hz kHz Output frequency REV. A 2/4 ○Electrical Characteristics (VCC=12V, Ta=25℃) Parameter （ WHOLE DEVICE） （ ） Circuit current during operation Circuit current during stand by operation （ STAND BY CONTROL） （ ） Stand-by voltage H Stand-by voltage L （ VCC UVLO BLOCK） （ ） Operating voltage (VCC) Hesteresis width (VCC UVLO) （ OSC BLOCK） （ ） RT Output Voltage （ PWMIN BLOCK） （ ） PWMIN pin H level input voltage range PWMIN pin L level input voltage range （ SOFT START BLOCK） （ ） VPWMINH VPWMINL 2.0 －0.3 5.0 0.8 VRT 1.05 1.50 1.95 V RT=79 kΩ V_VCCUVP ⊿V_VCCUVP 6.17 0.37 6.50 0.50 6.83 0.63 V V VstbH VstbL 2.0 -0.3 － － VCC 0.8 V V System ＯＮ System ＯＦＦ Icc1 Icc2 － － 2.3 0 5.0 20 mA μA FOUT=60kHz, PWMCMP=GND VSTB=0V Symbol MIN. Limits TYP. MAX. Unit Conditions V V Set up current for soft start Soft start end voltage （ FEED BACK BLOCK） （ ） IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage （ OUTPUT BLOCK） （ ） N1 output sink resistance N1 output source resistance N2 output sink resistance N2 output source resistance MAX DUTY N1-N2, N2-N1 OFF period Drive output frequency （ TIMER LATCH BLOCK） （ CP timer latch detect voltage CP timer latch charge current SDON latch detect voltage SDON latch charge current （ COMP BLOCK） （ ） COMP over voltage detect voltage Hysteresis width （COMP） COMPSD over voltage detect voltage （ FAIL BLOCK） （ ） FAIL ON Resistor value ISS VSS_END 1.5 2.8 2.0 3.0 2.5 3.2 uA V VIS VVS IIS1 IIS2 IVS VISCOMP 1.225 1.212 － 40 － 0.606 1.250 1.250 － 50 － 0.625 1.275 1.288 0.9 60 0.9 0.644 V V μA μA μA V PWMIN=2.5V PWMIN=0V, IS=1.0V Rsink_N1 Rsource_N1 Rsink_N2 Rsource_N2 MAX DUTY TOFF FOUT 1.5 4.5 1.5 4.5 43.0 100 57.9 3.0 9.0 3.0 9.0 45.0 200 60.0 6.0 18.0 6.0 18.0 47.0 400 62.1 Ω Ω Ω Ω % ns kHz RT=79 kΩ FOUT=60kHz VCP ICP VSDON ISDON 1.90 0.85 1.90 0.85 2.00 1.00 2.00 1.00 2.10 1.15 2.10 1.15 V μA V μA VCOMP ⊿VCOMP VCOMPSD 3.88 0.15 3.88 4.00 0.20 4.00 4.12 0.25 4.12 V V V RFAILL - 100 200 Ω （This product is not designed to be radiation-resistant.） REV. A 3/4 〇 External Dimensions , Marking Dvice Mark BD9211F Lot No. 〇 Block Diagram SOP18 (Unit:mm) ○Pin Number, Pin Name, Pin Function Pin No Pin Functions name No name Pin Pin Functions 1 2 3 4 5 6 7 8 9 VCC STB GND RT FB IS VS PWMCMP CP Power supply pin for IC （built-in UVLO function） Power ON/OFF control pin for IC Signal/ground pin for internal IC Drive frequency set up terminal. Lamp current, lamp voltage, error amp outputs Error amp input pin for lamp current feedback Error amp input pin for lamp voltage feedback at the opening time. PWM comparator input pin which controls PWM operation during brightness adjustment. Timer latch-setting pin 10 11 12 13 14 15 16 17 18 PWMIN SDON SS FAIL COMPSD COMP PGND N2 N1 PWM signal input pin for burst bright adjustment control Enable pin of COMPSD inputs over voltage detection Soft-start set up pin Error Indication signal Output Normal : L, Error : OPEN Detection pin for over voltage shut down Detection pin for over voltage and shut-down delay Power Ground for external MOSFET drive Output pin for external FET drive circuit (Ch. N2) Output pin for external FET drive circuit (Ch. N1) REV. A 4/4 〇NOTE FOR USE １. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady state and transient characteristics. ２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. ３. Mounting failures, such as misdirection or miscounts, may harm the device. ４. A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin. ６. If the voltage between VCC and I/O pins or GND and I/O pins is in opposite from the normal potential difference, unusual current flow into pins may occur which can destroy the IC. To avoid such occurrence it is recommended to place protection diodes for prevention against backward current flow. ７. BD9211F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. ８. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. ９. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. １０. By STB voltage, BD9211F are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～2.0V). １１. The pin connected a connector need to connect to the resistor for electrical surge destruction. + １２．This IC is a monolithic IC which (as shown is Fig.4)has P substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin Resistance (PinA) (PinB) Transistor (NPN) Ｃ Ｂ Ｅ ＧＮＤ Ｐ Ｐ Ｎ ＧＮＤ Ｐ Ｎ Ｎ Ｐ P substrate Ｐ Ｎ Ｎ Ｐ Ｎ Ｎ P substrate Parasitic diode (PinB) ＧＮＤ Parasitic diode (PinA) Parasitic Ｂ Ｃ Ｅ ＧＮＤ Parasitic diode ＧＮＤ Other adjacent components Fig.4. Simplified structure of a Bipolar IC REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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