BH3856

BH3856S / BH3856FS Audio ICs 2-wire serial sound control IC BH3856S / BH3856FS The BH3856S and BH3856FS are signal processing ICs designed for volume and tone control in televisions, mini component stereo systems, and other audio products. Their two-line serial control (I2C BUS) enables them to control volume and tone on the basis of signals from a microcomputer, etc. !Applications Televisions, [Video equipped television], personal computer televisions, mini component stereo systems, car stereos. !Features 1) I2C BUS facilitates direct serial control from a microcomputer of volume (main volume), balance (left / right), and tone (bass, treble). DC control is also possible. 2) Volume is produced by a low-distortion, low-noise VCA. Designed to minimize step noise. 3) Stable standard voltage supply and built-in I/O buffer mean that few attachments are needed. SSOP-A32 package designed to save space. 4) Matrix surround yields powerful sound. !Absolute maximum ratings (Ta = 25°C) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature BH3856S BH3856FS Symbol Vcc Pd Topr Tstg Limits 10.0 1200 ∗1 850 ∗2 −40~+85 −55~+150 Unit V mW °C °C ∗1 Reduced by 12mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 6.8mW for each increase in Ta of 1°C over 25°C. !Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Symbol VCC Min. 6.0 Typ. 9 Max. 9.5 Unit V Note : I2C BUS is a registered trademark of Philips. BH3856S / BH3856FS Audio ICs !Block diagram BH3856S 30k 30k A_GND IN1 BVN1 BIN1 BVO1 TVN1 TIN1 TVO1 OUT1 VCC SC N.C. SDA SCL D_GND 1 −− VCC 30 29 28 FILTER IN2 BVN2 BIN2 BVO2 TVN2 TIN2 TVO2 OUT2 VC1 VC2 TC BC Vref 2 3 47k 47k 4 5.1k − + +− (Bass) 27 5.1k (Bass) 5 6 26 Tone Tone Volume Volume 25 (Treble) Matrix surround (Treble) 7 2.1k 24 2.1k 8 9 10 VCC 11 200k 23 22 30k 30k − − + Volume Control Volume + 21 20 30k 12 30k 19 18 17 13 14 Reference Voltage 15 SLAVE ADDRESS 16 SELECT SW BH3856FS A_GND IN1 BVN1 BIN1 N.C. BVO1 TVN1 TIN1 TVO1 OUT1 VCC SC SDA N.C. SCL D_GND 1 2 3 30k −− 30k VCC 32 31 30 FILTER IN2 BVN2 N.C. BIN2 BVO2 TVN2 TIN2 TVO2 OUT2 VC1 VC2 TC BC 47k 47k 4 5.1k − + +− 29 28 (Bass) (Bass) 5 6 Volume Volume 5.1k Tone (Treble) Tone 27 (Treble) Matrix surround 7 8 2.1k 26 25 2.1k 9 10 11 VCC 12 200k 30k Control 24 23 30k − − + Volume Volume + 22 21 13 14 15 16 30k 20 30k 19 Reference Voltage 18 Vref 17 SELECT SW SLAVE ADDRESS BH3856S / BH3856FS Audio ICs !Pin descriptions Pin No. BH3856S BH3856FS Pin name 1 2 3 4 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 A_GND IN1 BVN1 BIN1 BVO1 TVN1 TIN1 TVO1 OUT1 VCC SC SDA SCL D_GND SASS Analog ground Function 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 12 Channel 1 volume input Channel 1 bass filter Channel 1 bass filter Channel 1 bass filter Channel 1 treble filter Channel 1 treble filter Channel 1 treble filter Channel 1 volume output Power supply Time constant pin for prevention of switching shock SDA data input pin SCL data input pin Digital ground Slave address selection pin Reference voltage output Time constant pin for prevention of switching shock Time constant pin for prevention of switching shock Time constant pin for prevention of switching shock Time constant pin for prevention of switching shock Channel 2 volume output Channel 2 treble filter Channel 2 treble filter Channel 2 treble filter Channel 2 bass filter Channel 2 bass filter Channel 2 bass filter Channel 2 volulme input Filter Not connected internally. Vref BC TC VC2 VC1 OUT2 TVO2 TIN2 TVN2 BVO2 BIN2 BVN2 IN2 FILTER N.C. 5, 14, 29 BH3856S / BH3856FS Audio ICs !Input / output circuits Symbol Pin voltage VCC Equivalent circuit Description IN1 IN2 4.5V 4.5V 2pin 31pin 47kΩ Main volume input pin. Designed for input impedance of 47kΩTyp.). 2/1VCC A_GND VCC BVN1 BVN2 4.5V 4.5V A_GND VCC 3pin 30pin 50kΩ Pin for low band filter connection. BIN1 BIN2 4.5V 4.5V 4pin 28pin 5.1kΩ Pin for low band filter connection. 2/1VCC A_GND VCC BVO1 BVO1 4.5V 4.5V 6pin 27pin 50kΩ Pin for low band filter connection. A_GND VCC 30kΩ FILTER 5.2V 32pin A_GND VCC 30kΩ Filter input pin. Please install a capacitor of about 10µF to the filter pin. Has built-in precharge and discharge circuits. TVN1 TVN2 4.5V 4.5V A_GND VCC 7pin 26pin 25kΩ Pin for high band filter connection. TIN1 TIN2 4.5V 4.5V 8pin 25pin 2.1kΩ Pin for high band filter connection. 2/1VCC A_GND ∗The pin numbers are for the BH3856S. BH3856S / BH3856FS Audio ICs Symbol Pin voltage VCC Equivalent Circuit Description TVO1 TVO2 4.5V 4.5V 9pin 24pin 25kΩ Pin for high band filter connection. A_GND VCC OUT1 OUT2 4.5V 4.5V 10pin 24pin Main volume output pin. OUT1 is the volume output for Channel 1. OUT2 is the volume output for Channel 2. A_GND VCC Digital VREF SC BC TC VC1 VC2 − 12pin 19pin 20pin 22pin 21pin A_GND For prevention of shock noise during step switching. SC : Surround pin BC : Bass pin TC : Treble pin VC1 : Volume pin (Channel 1) VC2 : Volume pin (Channel 2) VCC Vref 3.8V 18pin A_GND VCC 3.8V regulator output pin. Output requires capacitor for stopping oscillation. Output pin has built-in precharge and discharge circuits, so there is no problem with start-up or shut-down even with a large capacitor. This pin is for connection to the high-band filter. SDA SCL SASS − 2kΩ 13pin 15pin 17pin · I2C bass input pin SDA : serial data line SCL : serial clock line · Slave address selection pin SASS: slave address selection switch A_GND VCC A_GND D_GND − − − Power supply voltage pin. Analog GND pin. Connected to IC board. Digital GND pin. Separate from Analog GND pin. ∗The pin numbers are for the BH3856S. BH3856S / BH3856FS Audio ICs !Electrical characteristics (unless otherwise noted, Ta = 25°C, VCC = 9V, f = 1kHz, BW = 20 ~ 20kHz, VOL = Max., TONE = ALL FLAT, Rg = 600Ω, RL = 10kΩ) Parameter Quiescent current Maximum input Maximum output Voltage gain Maximum attenuation Crosstalk Low range control width Symbol IQ Vim Vom Gv ATT VCT VB Max. VB Min. High range control width VT Max. VT Min. Matrix surround single-channel gain Total Harmonic distortion Output noise voltage Residual output noise voltage Reference power supply output voltage Reference power supply output current capacity Channel balance Input impedance Output impedance Ripple rejection ratio Input high level voltage Input low level voltage Not designed for radiation resistance. Signal input occurs in equiphase. Min. − 2.3 2.3 −1.5 90 70 +12 −18 +12 −18 4 − − − 3.5 3.0 −1.5 33 − 40 4 − Typ. 20 2.5 2.5 0 110 80 +15 −15 +15 −15 6 0.01 45 2 3.8 10 0 47 − − − − Max. 27 − − +1.5 − − +18 −12 +18 −12 8 0.1 65 10 4.1 − +1.5 61 10 − − 1 Unit mA No signal Conditions THD=1%, VOL=−20dB (ATT) THD=1% VIN=1Vrms Vo=1Vrms Vo=1Vrms 100Hz, VIN=100mVrms 100Hz, VIN=100mVrms 100kHz, VIN=100mVrms 100kHz, VIN=100mVrms Vo=1Vrms Vo=0.5Vrms, BPF=400Hz~30kHz Vrms Vrms dB dB dB dB dB dB dB dB % GSR THD VNO1 VMNO ∗ ∗ ∗ µVrms No signal, VOL=Max., Rg=0 µVrms No signal, VOL=−∞, Rg=0 V mA dB kΩ Ω dB V V Vref Iref GCB RIN ROUT RR VIH VIL Iref=3mA Vref > 3.7V channel 1 taken as the standard for measurements. f=1kHz f=1kHz f=100Hz, VRR=1Vrms SCL, SDA SCL, SDA ∗ Measurement performed using Matsushita Communication Industrial VP-9690A DIN AUDIO filter (average value wave detection, effective value display). BH3856S / BH3856FS Audio ICs !Measurement circuit 30k 30k 1000µF VCC 30 0.47µF 29 S4 S2 2 123 28 1 0.47µF 2 S1 321 S3 1 2 4.7k C2 10µF 0.1µF 5 3 C1 0.1µF 47k 47k +− (Bass) (Bass) 4 5.1k −+ +− 0.1µF 27 5.1k 1 4.7k 0.1µF 26 10µF V VAIN11 V Tone V VAIN22 10k VAIN1 VAIN2 Tone Volume Volume V 6 25 (Treble) (Treble) C3 C4 10µF 2200pF 7 2200pF 8 9 2.1k Matrix surround 24 2.1k 2200pF 2200pF 23 10µF − − Volume Control 22 VVC1 30k 30k + 10k VAOUT1 THD V V VCC 11 200k VAOUT2 VOUT1 VOUT2 10 Volume + 21 VVC2 20 VTC 19 VBC 18 V V THD T1 I VCC A S5 2 10µF 10µF VCC VCC 1 S6 1 2 13 14 12 30k 30k T2 S7 17 Reference voltage 15 16 10µF 1 1.2k 2 V1 V BH3856S Units : R [Ω] C [F] Fig.1 Note : Diagram depicts the BH3856S. BH3856S / BH3856FS Audio ICs !Performing data settings (1) I2C BUS timing Parameter SCL clock frequency SCL clock hold time, HIGH state SCL clock hold time, LOW state SDA and SDL signal start-up time SDA and SDL signal shut-down time Set-up time for re-send [start] conditions Hold time (re-send) [start] conditions (After hold time ends, initial clock pulse is generated.) Set time for [stop] conditions. Bus free time between [stop] condition and [start] condition Data set-up time Symbol fSCL tHIGH tLOW tr tf tSU;STA tHD;STA tSU;STO tBUF tSU;DAT Min. 0 4 4.7 − − 4.7 4 4.7 4.7 250 Typ. − − − − − − − − − − Max. 100 − − 1 0.3 − − − − − Unit kHz µs µs µs µs µs µs µs µs ns tr SLC tf tLOW tHIGH SDA start condition tSU ; STA tHD ; STA SDA stop condition tSU ; STO tBUF SDA tSU ; DAT tHD ; DAT tSU ; STA = start code set-up time. tHD ; STA = start code hold time. tSU ; STO = stop code set-up time. tBUF = bus free time. tSU ; DAT = data set-up time. tHD ; DAT = data hold time. I2C BUS timing rules BH3856S / BH3856FS Audio ICs (2) I2C BUS data format MSB LSB MSB LSB MSB LSB S 1bit Slave address 8bit A 1bit Select address 8bit A 1bit Data 8bit A 1bit P 1bit •S • Slave address •A • Select address • Data •P = start condition (start bit recognition) = IC recognition. Upper 7 bits are random. Bottom bit is “L” for the sake of overwrite. = acknowledge bit (recognition of acknowledgment) = selection between volume, bass, treble and matrix surround. = volume and tone data = stop condition (stop bit recognition) (3) BH3856S / BH3856FS slave address MSB A6 1 A5 0 A4 0 A3 0 A2 0 A1 0 A0 A LSB R/W 0 • Slave address selection 1) A = 1 (10000010) [SASS pin HIGH] 2) A = 0 (10000000) [SASS pin LOW] (4) Interface protocol 1) Basic protocol S Slave address MSB LSB A Select address MSB LSB A Data MSB LSB A P 2) Auto increment (Select address increases (+1) by the value of the data.) S Slave address MSB LSB A Select address MSB LSB A MSB Data 1, data 2,...data N LSB A P (Example 1) The address data specified by select address is taken as data 1. (Example 2) The address data specified by select address +1 is taken as data 2. (Example 3) The address data specified by select address +N−1 is taken as data N. 3) Structure with which transmission is not possible (In this case, only select address 1 is set.) S Slave address MSB LSB A Select address 1 MSB LSB A Data MSB LSB A Select address 2 MSB LSB A Data MSB LSB A P Note : Following transmission of data, data transmitted as select address 2 will not be recognized as select address 2, but as data. BH3856S / BH3856FS Audio ICs (5) Specification of select address and data Function MSB Select address LSB MSB D7 VL7 VR7 0 0 0 D6 VL6 VR6 0 0 0 D5 VL5 VR5 BA5 TR5 0 Data D4 D3 VL4 VR4 BA4 TR4 0 VL3 VR3 BA3 TR3 0 LSB D2 VL2 VR2 BA2 TR2 0 D1 VL1 VR1 BA1 TR1 0 D0 VL0 VR0 BA0 TR0 SR0 0 Volume ch1 (L) 1 Volume ch2 (R) 2 Bass 3 Treble 4 Surround 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 ∗The auto increment function cycles the select address in the manner shown in Figure A. (Fig. A) 0→1→2 ↑ ↓ 4 ← ← ←3 ∗The cycle commences from the initially specified select address. (6) Surround data Function Matrix surround OFF Matrix surround ON MSB D7 0 0 D6 0 0 D5 0 0 Data D4 D3 0 0 0 0 LSB D2 0 0 D1 0 0 D0 0 1 (7) Matrix surround Input L→ + + + + + + ×1 Output (2L−R) Input R→ + ×1 Output (2R−L) BH3856S / BH3856FS Audio ICs (8) Volume attenuation (reference values) ATT (dB) 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 −16 −17 −18 DATA (HEX) FF E4 D8 CF C8 C2 BD B8 B2 AD A9 A5 A0 9C 98 94 90 8C 89 ATT (dB) −19 −20 −22 −24 −26 −28 −30 −32 −34 −36 −38 −40 −42 −44 −46 −48 −50 −52 −54 DATA (HEX) 85 82 7C 78 74 70 6D 6A 68 65 61 5C 59 55 52 4E 4B 48 45 ATT (dB) −56 −58 −60 −62 −64 −66 −68 −70 −72 −74 −76 −78 −80 −82 −84 −86 −90 −100 −112 DATA (HEX) 42 3F 3C 39 36 34 32 2F 2D 2A 28 26 24 22 20 1E 1A 13 00 Note : All figures in this table are reference values. When using this IC, check this table carefully and perform the appropriate setting. (9) Bass / Treble gain settings (reference values) ATT (dB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA (HEX) 3F 38 35 33 31 2F 2E 2D 2C 2B 2A 29 27 26 25 1F ATT (dB) 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 DATA (HEX) 1F 1C 1B 19 18 17 16 15 13 12 11 0F 0D 0B 08 05 Notes : (1) The gain values in the treble and bass data setting tables above are based on the assumption that the filter constants have been set so that maximum and minimum gain are equal to the peak and bottom values listed in the frequency characteristics drawings. (2) All figures in this table are reference values. When using this IC, check this table carefully and perform the appropriate setting. BH3856S / BH3856FS Audio ICs !Application example 30k 30k 10µF VCC 30 AGND 29 28 0.47µF 1 0.47µF 2 3 C1 C2 0.1µF 47k 47k +− C1 4 0.1µF 5 5.1k −+ +− 0.1µF 0.1µF (Bass) (Bass) Tone 27 5.1k C2 26 Volume Matrix Volume surround Tone 6 C3 C4 10µF 9 VCC 33µF 11 200k 25 C3 2200pF 2200pF 10µF 2200pF (Treble) (Treble) 7 2200pF 8 2.1k 24 2.1k C4 23 22 0.22µF − − + 10 VCC Volume Volume + Control 30k 30k 21 0.22µF 20 0.033µF 19 3.3µF 18 10µF 17 DGND 12 13 14 30k 30k MICRO COMPUTER Reference voltage 15 16 AGND BH3856S DGND Fig.2 Note : Diagram depicts the BH3856S. BH3856S / BH3856FS Audio ICs !Operation notes (1) Operating power supply voltage range As long as the operating power supply voltage and ambient temperature are kept within the specified range, the basic circuits are guaranteed to function, but be sure to check the constants as well as the element settings, voltage settings, and temperature settings. (2) Bass filter C1 BVO −3dB 0.1µF BIN C2 BVN R2 50kΩ − R1 5.1kΩ IC internal BIAS IC internal BIAS ( 1 Vcc ) 2 ( 1 Vcc ) 2 + 0.1µF f0 ∆f Frequency f: (Hz) ∗B.P.F. composed of multiple feedback active f0 can be varied according to the value of C.BIN (theoretical equation) f0 = 1 × 2π 1 R1R2C1C2 −1 1 2 Q 1 R2C1C2 1 2 × (C1 + C2) −1 G= R2 C1 × 1+ 5kΩ C2 Note : Filter gain is calculated using the equation on the left. Total output gain is the sum of the gain for each of the internal circuits. (When R1 = 5.1kΩ, R2 = 50kΩ, C1 = C2 = C) f0 = 1.0 × 10−5 C Q 1.57 G = 5.0 BH3856S / BH3856FS Audio ICs (3) About the treble filter C3 TVO −3dB 2200pF TIN C4 TVN R2 25kΩ − R1 2.1kΩ IC internal BIAS IC internal BIAS ( 1 Vcc ) 2 ( 1 Vcc ) 2 + 2200pF f0 ∆f Frequency f: (Hz) ∗The band-pass filter is constructed using a multiple-feedback active filter. f0 can be varied by changing the value of the capacitors. (Theoretical formulas) f0 = 1 × 2π 1 R1R2C3C4 −1 1 2 1 Q R1 R2C3C4 2 × (C3 + C4) −1 G= R2 C3 × 1+ 5kΩ C4 Note : The filter gain is given by the formula on the left, but the total output gain is determined by the this in combination with the internal circuit. (When R1 = 2.1kΩ, R2 = 25kΩ, C3 = C4 = C) f0 = 2.2 × 10−5 C Q 1.73 G = 2.5 (4) I2C BUS control High-frequency digital signals are input on the SCL and SDA terminals, so ensure that the wiring and PCB pattern is designed in such a way as to ensure that these signals do not interfere with the analog signal system. If you are not using I2C BUS control (i.e. you are using DC control), connect the SCL, SDA and SASS terminals to GND (do not leave them disconnected). (5) Step switching noise The VC1, VC2, TC, BC and SC terminals have components connected to them the application example. The values of these components may need to be changed depending on the signal level setting and PCB pattern. Investigate carefully before deciding on the values of the various circuit constants. The equivalent circuit for these terminals is given below (an integrator circuit is set at the first stage to slow the variation). R Each Pin + − R value (kΩ) VC1, VC2, BC, TC SC 30 200 C (6) Volume and tone level settings This specification sheet gives reference values for the amount of attenuation and gain with respect to the serial control data. The internal D / A convertor is an R-2R circuit, and data exists for the places where continuous variation does not occur between data. Use this when fine setting is required. The setting limits are up to 8 bits for volume (256 steps) and 6 bits (64 steps) for tone. BH3856S / BH3856FS Audio ICs (7) Digital / analog separation The digital and analog power supplies and grounds for this IC (BH3856) are completely separate. The digital circuits are supplied from a stable reference source that is on the chip (Vref (3.8V)). For this reason, there is no need to worry about timing shifts, on interference due to digital noise. (8) Matrix surround Input L→ + + + + + + ×1 Output (2L-R) Input R→ + ×1 Output (2R-L) ∗The matrix surround circuit construction is as shown in the diagram above. The gain is obtained from the formulas in the diagram. Phase Gain Negative Phase Gain 0dB 6dB (However, reverse-phase gain is for input to one channel only) (9) DC control An internal impedance of 30kΩ is seen from the VC1, VC2, TC and BC terminals, are 200kΩ is seen from the SC (pin 11) terminal, so with regard to DC control, we recommend direct control with the voltage source. When using variable volume, take the impedance into consideration when making the setting. Note : The DC control voltage range is 0V to Vref. Do not apply voltages above Vref to the terminals. (10) GND • As shown in the application circuit example, connect the external component GND to the analog GND. • However, the GND for the capacitor connected to the Vref terminal should be connected to the digital GND. • If a capacitor with goof high-frequency characteristics is connected in parallel with the capacitor connected to Vref, the performances of the circuit with respect to static noise will improve (we recommend a ceramic capacitor of between 0.001µF and 0.1µF) • When using long digital and analog ground lines, take care to ensure that there is no potential difference between the two ground lines. BH3856S / BH3856FS Audio ICs !Electrical characteristic curves TOTAL HARMONIC DISTORTION : THD (%) 24 22 QUIESCENT CURRENT : IQ (mA) RL = 10kΩ 1 VCC = 9V f = 1kHz 25 20 VOLTAGE GAIN : GBT (dB) VCC = 9V RL = 10kΩ 20 18 16 14 12 10 8 6 4 2 0 5 6 7 8 9 10 POWER SUPPLY VOLTAGE : VCC (V) 0.4 15 10 5 0 −5 −10 −15 −20 −25 10 0.1 0.04 0.01 −40 −30 −20 −10 0 10 100 1k 10k 100k INPUT VOLTAGE : VIN (dBV) FREQUENCY : f (Hz) Fig. 3 Quiescent curve vs. Power supply voltage Fig.4 Total harmonic distortion vs. Input voltage Fig. 5 Output gain vs. Frequency !External dimensions (Units : mm) BH3856S BH3856FS 28.0±0.3 30 16 8.4±0.3 13.6±0.2 32 17 7.8±0.3 0.51Min. 1 15 10.16 5.4±0.2 4.7±0.3 1 16 1.8±0.1 0.11 3.2±0.2 0.3±0.1 1.778 0.5±0.1 0°~15° 0.8 0.36±0.1 0.3Min. 0.15 SDIP30 SSOP-A32 0.15±0.1