Datasheet
Low Duty LCD Segment Driver
BU9797AFUV
MAX 144 Segments (SEG36×COM4)
General Description
Key Specifications
BU9797AFUV is a 1/4 duty general-purpose LCD driver
that can be used for consumer / battery operated
products and can drive up to 144 LCD Segments.
It has integrated display RAM for reducing CPU load.
Also, it is designed with low power consumption and no
external component needed.
■
■
■
■
■
■
Features
Supply Voltage Range:
+2.5V to +5.5V
Operating Temperature Range:
-40°C to +85°C
Max Segments:
144Segments
Display Duty:
1/4
Bias:
1/3
Interface:
2wire Serial Interface
Package
W (Typ.) x D (Typ.) x H (Max.)
Integrated RAM for Display Data (DDRAM):
36 x 4 bit (Max 144 Segment)
LCD Drive Output:
4 Common Output, Max 36 Segment Output
Integrated Buffer AMP for LCD Driving
Integrated Oscillator Circuit
No External Components
Low Power Consumption Design
Applications
etc.
Metering
Home Automation Goods
White Goods, Small Appliances
Healthcare Products
Battery Operated Products
TSSOP-C48V
8.10mm x 12.5mm x 1.00mm
Typical Application Circuit
VDD
C > 0.1uF
VDD
VLCD
COM0
COM1
COM2
COM3
SDA
SCL
Controller
SEG0
SEG1
・・
・
・・
・
・
SEG35
OSCIN
TEST1
Insert Capacitors
between VDD and VSS
VSS
Segment
LCD
・・
・・
・
・
・
Internal Clock Mode
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
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Datasheet
MAX 144 segments (SEG36×COM4)
Block Diagram
COM0……COM3
SEG0……SEG35
Common
Driver
Segment
Driver
VDD
LCD Voltage Generator
＋
LCD
Bias
Selector
－
Common
Counter
＋
－
Blink Timing
Generator
DDRAM
VLCD
Command
Data Decoder
Command
Register
OSCIN
Oscillator
Power On Reset
Serial Interface
IF Filter
VSS
TEST1
SDA
SCL
Figure 2. Block Diagram
SEG7
SEG6
SEG12
SEG1
SEG8
SEG13
SEG0
SEG5
SEG14
NC
SEG9
SEG15
SDA
SEG4
SEG16
SCL
SEG10
SEG17
OSCIN
SEG3
SEG18
SEG11
SEG19
VSS
TEST1
SEG2
SEG20
VDD
SEG24
COM1
SEG21
SEG25
COM0
VLCD
SEG26
SEG35
SEG22
SEG27
SEG34
COM3
SEG28
SEG33
SEG23
SEG29
SEG32
COM2
SEG30
SEG31
Pin Configuration
Figure 3. Pin Configuration (TOP VIEW)
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Datasheet
MAX 144 segments (SEG36×COM4)
Pin Description
Table 1. Pin Description
Handling
when unused
Pin Name
Pin No.
I/O
Function
TEST1
13
I
Test input (ROHM use only)
Must be connected to VSS
NC
17
-
Unused terminal
OSCIN
14
I
External clock input
External clock and Internal clock can be selected by command
Must be connected to VSS when using internal oscillator
SDA
16
I/O
SCL
15
VSS
VSS
OPEN
VSS
Serial data in-out terminal
-
I
Serial clock terminal
-
12
I
GND
-
VDD
11
I
Power supply
-
VLCD
10
I
Power supply for LCD driving
-
SEG0 to 35
18-40,
1-5
O
SEGMENT output for LCD driving
OPEN
COM0 to 3
6-9
O
COMMON output for LCD driving
OPEN
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Datasheet
MAX 144 segments (SEG36×COM4)
Absolute Maximum Ratings (VSS=0V)
Parameter
Symbol
Ratings
Unit
Remarks
Maximum Voltage1
VDD
-0.5 to +7.0
V
Power Supply
Maximum Voltage2
VLCD
-0.5 to VDD
V
LCD Drive Voltage
0.64
(Note1)
Power Dissipation
Pd
W
Input Voltage Range
Operational Temperature
Range
Storage Temperature Range
VIN
-0.5 to VDD+0.5
V
Topr
-40 to +85
°C
Tstg
-55 to +125
°C
(Note1) Derate by 6.4mW/°C when operating above Ta=25°C (when mounted in ROHM’s standard board).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta=-40°C to +85°C, VSS=0V)
Parameter
Symbol
Ratings
Min
Typ
Max
Unit
Remarks
Power Supply Voltage1
VDD
2.5
-
5.5
V
Power Supply
Power Supply Voltage2
VLCD
0
-
VDD-2.4
V
LCD Drive Voltage, VDD-VLCD 2.4V
Electrical Characteristics
DC Characteristics (VDD=2.5V to 5.5V, VLCD=0V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
“H” Level Input Voltage
VIH
0.7VDD
-
VDD
“L” Level Input Voltage
VIL
VSS
-
“H” Level Input Current
IIH
-
-
“L” Level Input Current
V
SDA,SCL,OSCIN
0.3VDD
V
SDA,SCL,OSCIN
1
µA
SDA,SCL,OSCIN
(Note2)
IIL
-1
-
-
µA
SDA,SCL,OSCIN
VOL_SDA
0
-
0.4
V
Iload = 3mA
SEG
RON
-
3
-
kΩ
COM
RON
-
3
-
kΩ
VLCD Supply Voltage
VLCD
0
-
VDD-2.4
V
VDD-VLCD2.4V
Standby Current
IDD1
-
-
5
µA
Display off, Oscillation off
Power Consumption
IDD2
-
7.5
20
µA
VDD=3.3V, VLCD=0V, Ta=25°C
Power save mode1, FR=71Hz
1/3 bias, Frame inverse
SDA “L” Level Output Voltage
LCD Driver On
Resistance
Iload=±10µA
(Note2) For external clock mode only.
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Datasheet
MAX 144 segments (SEG36×COM4)
Electrical Characteristics – continued
Oscillation Characteristics (VDD=2.5V to 5.5V, VLCD=0V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
FR = 80Hz setting,
Frame Frequency1
fCLK1
56
80
104
Hz
VDD=2.5V to 5.5V, Ta=-40°C to +85°C
Frame Frequency2
fCLK2
70
80
90
Hz FR = 80Hz setting, VDD=3.3V, Ta=25°C
Frame Frequency3
fCLK3
77.5
87.5
97.5
Hz
Frame Frequency4
fCLK4
67.5
87.5
108
Hz
External Clock Rise Time
tr
-
-
0.3
µs
External Clock Fall Time
tf
-
-
0.3
µs
External Frequency
fEXCLK
15
-
300
KHz
External Clock Duty
tdty
30
50
70
%
(Note)
DISCTL 80HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 71HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 64HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 53HZ setting: Frame frequency [Hz] = external clock [Hz]
FR = 80Hz setting, VDD=5.0V, Ta=25°C
FR = 80Hz setting, VDD=5.0V,
Ta=-40°C to +85°C
External clock mode (OSCIN)
(Note)
/ 512
/ 576
/ 648
/ 768
【Reference Data】
110
Frame Frequency [Hz]
100
VDD = 5.5V
90
VDD = 5.0V
80
VDD = 3.3V
VDD = 2.5V
70
60
50
-40
-20
0
20
40
60
80
Temperature [°C]
Figure 4. Typical Temperature Characteristics
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Datasheet
MAX 144 segments (SEG36×COM4)
Electrical Characteristics - continued
MPU interface Characteristics (VDD=2.5V to 5.5V, VLCD=0V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
Input Rise Time
tr
-
-
0.3
µs
Input Fall Time
tf
-
-
0.3
µs
SCL Cycle Time
tSCYC
2.5
-
-
µs
“H” SCL Pulse Width
tSHW
0.6
-
-
µs
“L” SCL Pulse Width
tSLW
1.3
-
-
µs
SDA Setup Time
tSDS
100
-
-
ns
SDA Hold Time
tSDH
100
-
-
ns
Buss Free Time
tBUF
1.3
-
-
µs
tHD;STA
0.6
-
-
µs
START Condition Setup Time
tSU;STA
0.6
-
-
µs
STOP Condition Setup Time
tSU;STO
0.6
-
-
µs
START Condition Hold Time
SDA
tBUF
tf
tS LW
tSCYC
SCL
tHD; STA
tr
tSDH
tS HW
tSDS
SDA
tSU; STO
tSU; STA
Figure 5. Interface Timing
I/O Equivalence Circuit
VDD
VDD
VLCD
VSS
VSS
OSCIN
SDA
VSS
VSS
TEST1
SCL
VSS
VSS
VDD
SEG/COM
VSS
Figure 6. I/O Equivalence Circuit
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Datasheet
MAX 144 segments (SEG36×COM4)
Application Example
VDD
VDD
VLCD
COM
COM
COM
COM
0
1
2
3
SDA
SCL
Controller
SEG 0
SEG 1
・
・
・
・
・・
・
SEG 35
OSCIN
TEST 1
VSS
Segment
LCD
・
・
・
・
・
・
・
Internal Clock Mode
VDD
VDD
VLCD
Controller
COM 0
COM 1
COM 2
COM 3
SDA
SCL
SEG 0
SEG 1
・
・
・
・
・
・
・
SEG 35
OSCIN
TEST1
VSS
Segment
LCD
・
・
・
・
・
・
・
External Clock Mode
Figure 7. Example of Application Circuit
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Datasheet
MAX 144 segments (SEG36×COM4)
Functional Descriptions
Command /Data Transfer Method
BU9797AFUV is controlled by 2wire signal (SDA, SCL).
SDA
SCL
START condition
STOP condition
Figure 8. 2 wire Command/Data Transfer Format
It is necessary to generate START and STOP condition when sending command or display data through this 2 wire serial
interface.
Slave address
S
0 1 1 1 1 1
0 M A C
A
Command
Display Data
A P
0
Write or Read
Command or data judgement bit
START condition judgement bit
Acknowledge
STOP condition
Figure 9. Interface Protcol
Slave address = “01111100” : Write Mode
Slave address = “01111101” : Read Mode
The following procedure shows how to transfer command and display data.
(1) Generate “START condition”.
(2) Issue Slave address.
(3) Transfer command and display data.
(4) Generate “STOP condition”
Acknowledge (ACK)
Data format is comprised of 8 bits, Acknowledge bit is returned after sending 8-bit data.
After the transfer of 8-bit data (Slave Address, Command, Display Data), release the SDA line at the falling edge of the 8th
clock. The SDA line is then pulled “Low” until the falling edge of the 9th clock SCL.
(Output cannot be pulled “High” because of open drain NMOS).
If acknowledge function is not required, keep SDA line at “Low” level from 8th falling edge to 9th falling edge of SCL.
SDA
1-7
8
9
1-7
8
9
1-7
8
9
SCL
S
START
condition
P
SLAVE ADDRESS
ACK
DATA
ACK
DATA
ACK
STOP
condition
Figure 10. Acknowledge Timing
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Datasheet
MAX 144 segments (SEG36×COM4)
Command Transfer Method
Issue Slave Address (“01111100”) after generating “START condition”.
For Write Mode set M bit to ‘0’.
st
The 1 byte after Slave Address always becomes command input.
MSB (“command or data judge bit”) of command decide to next data is command or display data.
When set “command or data judge bit”=‘1’, next byte will be command.
When set “command or data judge bit”=‘0’, next byte data is display data.
S Slave address A 1 Command
A 1 Command
A 1 Command
A 0 Command
A Display Data
…
P
It cannot accept input command once it enters into display data transfer state.
In order to input command again it is necessary to generate “START condition”.
If “START condition” or “STOP condition” is sent in the middle of command transmission, command will be cancelled.
If Slave address is continuously sent following “START condition”, it remains in command input state.
“Slave address” must be sent right after the “START condition”.
When Slave Address cannot be recognized in the first data transmission, no Acknowledge bit is generated and next
transmission will be invalid. When data is invalid status, if “START condition” is transmitted again, it will return to valid
status.
Consider the MPU interface characteristic such as Input rise time and Setup/Hold time when transferring command and
data (Refer to MPU Interface).
Write Display and Transfer Method
BU9797AFUV has Display Data RAM (DDRAM) of 36×4=144bit.
The relationship between data input and display data, DDRAM data and address are as follows;
Slave address
S
0111110 0 A
0
Comman
d
0000000
A
a b c
d
e f
g h A i j k l m
n o p
A
… P
Display Data
M=0(Write Mode)
8-bit data is stored in DDRAM. ADSET command specifies the address to be written, and address is automatically
incremented in every 4-bit data.
Data can be continuously written in DDRAM by transmitting data continuously.
When RAM data is written successively, after writing RAM data to 23h (SEG35), the address is returned to 00h (SEG0) by
the auto-increment function
BIT
04
DDRAM address
05
06
07
00
01
02
03
0
a
e
i
m
COM0
1
b
f
j
n
COM1
2
c
g
k
o
COM2
3
d
h
l
p
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
・・・
21h
SEG33
22h
SEG34
23h
SEG35
Display data is written to DDRAM every 4-bit data.
No need to wait for ACK bit to complete data transfer.
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Datasheet
MAX 144 segments (SEG36×COM4)
Read Display and Transfer Method
Issue Slave Address (“01111101”) after generating “START condition”.
For Read Mode set M bit to ‘1’.
The display data and command register value can be read during Read Mode.
The Read Mode sequence is shown below.
Slave address
S
0111110
0 A 1
1101000
Slave address
Command
Command
A 1
0000000
A
S
0111110
M=0(Write Mode)
1 A
A
Data
…...
A P
Data
M=1(Read Mode)
During Read Mode, the display data can be read from the DDRAM through the SDA line.
The data will output synchronously to SCL clock input.
First set address by Write Mode ADSET command to read display data.
If DDRAM address is not specified before DDRAM read, the read address will start from the current DDRAM
address.
Address will increment automatically by +2 addresses after 8bit data output.
Master side should output ACK signal after each 8bit data output.
BU9797AFUV is kept at Read Mode and address increment after receiving ACK signal from master side.
If there is no ACK response, BU9797AFUV will not keep above read operation, transmit “STOP condition”.
Read Mode will be stopped by sending “STOP condition”.
Address will be set to 00h automatically after 23h. (It does not increment to 24h or 25h address)
Shown below is an example of the display data read sequence.
S
SDA
P
Slave Address (read)
A
D7
D6 D5 D4 D3 D2 D1 D0 A
D7
D6 D5 D4 D3 D2 D1 D0
A
SCL
Figure 11. Read Sequence
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Datasheet
MAX 144 segments (SEG36×COM4)
Read Command Register and Transfer Method
The command registers can be read during Read Mode. The sequence for the command register read is
shown below and is similar to the display data read sequence.
Command
Slave address
S
0111110
0 A 1
Slave address
Command
110 1100
A
ADSET
A
S
0111110
M=0
Set ICSET [P2]=1
(Write Mode)
1 A
NA
Data
P
M=1(Read Mode)
Regarding address setting, refer to ADSET command.
The following register settings can be read in this mode by setting address to 24h and 25h.
Address does not increment automatically after command register value read.
Register
D7
D6
D5
D4
D3
D2
D1
D0
Address
REG1
0
0
0
P4
P3
P2
P1
P0
24h
REG2
P7
P6
P5
P4
P3
P2
P1
P0
25h
REG1: P4 = Internal/External clock setting
P3 = Software Reset setting
P2 to P0 = Blink setting
REG2: P7 to P6 = Frame Frequency setting
P5 to P4 = Power Save Mode setting
P3 = Frame/Line inversion setting
P2 = Display ON/OFF setting
P1 = All Pixels ON setting
P0 = All Pixels OFF setting
The ADSET and ICSET setting address map is shown below.
Write Mode
ADSET
RAM Address
D7
D6
D5
0
0
0
0
0
0
0000 0000 to 0001 1111
0010 0000 to 0010 1011
Read Mode
RAM Address
D[4:0]
0 0000 to 1 1111
0 0000 to 0 1011
ICSET
P7
P6
P5
P4
P3
1
1
1
1
1
1
0
0
1
1
ADSET
D7
D6
D5
1
1
0
0
0
0
0000 0000 to 0001 1111
0010 0000 to 0010 0101
P2
(Note)
0
1
P1
P0
0
0
0
0
P1
P0
0
0
0
0
ICSET
D[4:0]
0 0000 to 1 1111
0 0000 to 0 0101
P7
P6
P5
P4
P3
1
1
1
1
1
1
0
0
1
1
P2
(Note)
0
1
(Note) Please take care of ICSET [P2] setting.
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Datasheet
MAX 144 segments (SEG36×COM4)
Oscillator
The clock signals for logic and analog circuit can be generated from internal oscillator or external clock.
If internal oscillator circuit is used, OSCIN must be connected to VSS level.
When using external clock mode, input external clock from OSCIN terminal after ICSET command setting.
OSCIN
OSCIN
BU9797A
Clock
BU9797A
VSS
VSS
Figure 12. Internal Clock Mode
Figure 13. External Clock Mode
LCD Driver Bias Circuit
BU9797AFUV generates LCD driving voltage with on-chip Buffer AMP.
And it can drive LCD at low power consumption.
Line or frame inversion can be set by DISCTL command.
Refer to the “LCD driving waveform” for each LCD bias setting.
Blink Timing Generator
BU9797AFUV has Blink function.
Blink mode is asserted by BLKCTL command.
The Blink frequency varies depending on fclk characteristics at internal clock mode.
Refer to Oscillation Characteristics for fCLK.
Reset Initialize Condition
Initial condition after executing Software Reset is as follows.
・Display is OFF.
・DDRAM address is initialized (DDRAM Data is not initialized).
Refer to Command Description for initial value of registers.
Command / Function List
Description List of Command / Function
No.
Command
Function
1
Set IC Operation (ICSET)
Software reset, internal/external clock setting
( P2 is MSB data of DDRAM address )
2
Display Control (DISCTL)
Frame frequency, power save mode setting
3
Address Set (ADSET)
DDRAM address setting (00h to 23h)
4
Mode Set (MODESET)
Display on/off setting
5
Blink Control (BLKCTL)
Blink off/0.2/0.3/0.5/1/2Hz blink setting
6
All Pixel Control (APCTL)
All pixels on/off during DISPON
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Datasheet
MAX 144 segments (SEG36×COM4)
Detailed Command Description
D7 (MSB) is a command or data judgment bit.
Refer to Command and data transfer method.
C:
0: Next byte is RAM write data.
1: Next byte is command.
Set IC Operation (ICSET)
MSB
D7
C
D6
1
D5
1
D4
0
D3
1
D2
P2
D1
P1
LSB
D0
P0
P2: MSB data of DDRAM address. Refer to “ADSET” command.
Set software reset execution.
Setup
P1
No operation
0
Software Reset Execute
1
When “Software Reset” is executed, BU9797AFUV is reset to initial condition.
(Refer to Reset initialize condition)
Don’t set Software Reset (P1) with P2, P0 at the same time.
Set oscillator mode
Setup
Internal clock
P0
Reset initialize condition
0
○
External clock
1
Internal clock mode: OSCIN must be connected to VSS level.
External clock mode: Input external clock from OSCIN terminal..
DISCTL 80Hz setting: Frame frequency [Hz] = external clock [Hz] / 512
DISCTL 71Hz setting: Frame frequency [Hz] = external clock [Hz] / 576
DISCTL 64Hz setting: Frame frequency [Hz] = external clock [Hz] / 648
DISCTL 53Hz setting: Frame frequency [Hz] = external clock [Hz] / 768
Command
OSCIN_EN
(Internal signal)
ICSET
Internal clock mode
External clock mode
Internal oscillation
(Internal signal)
External clock
(OSCIN)
Figure 14. OSC MODE Switch Timing
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Display Control (DISCTL)
MSB
D7
C
D6
0
D5
1
D4
P4
D3
P3
Set Power save mode FR.
Setup
D2
P2
D1
P1
LSB
D0
P0
P4
P3
Reset initialize condition
Normal mode (80Hz)
0
0
○
Power save mode 1 (71Hz)
0
1
Power save mode 2 (64Hz)
1
0
Power save mode 3 (53Hz)
1
1
Power consumption is reduced in the following order:
Normal mode > Power save mode1 > Power save mode 2 > Power save mode 3.
Set LCD drive waveform.
Setup
P2
Reset initialize condition
Line inversion
0
○
Frame inversion
1
Power consumption is reduced in the following order:
Line inversion > Frame inversion
Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.
Regarding driving waveform, refer to LCD driving waveform.
Set Power save mode SR.
Setup
P1
P0
Power save mode 1
0
0
Power save mode 2
0
1
Normal mode
1
0
Reset initialize condition
○
High power mode
1
1
Power consumption is increased in the following order:
Power save mode 1 < Power save mode 2 < Normal mode < High power mode
Use VDD- VLCD ≥ 3.0V in High power mode condition.
(Reference current consumption data)
Setup
Current consumption
Power save mode 1
×0.5
Power save mode 2
×0.67
Normal mode
×1.0
High power mode
×1.8
The data above is for reference only. Actual consumption depends on Panel load.
Address Set (ADSET)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
C
0
0
P4
P3
P2
P1
P0
The range of address can be set from 000000 to 100011(bin).
Internal register
Command
MSB
Address
[5]
ICSET
P2
Address
[4]
ADSET
P4
Address
[3]
ADSET
P3
Address
[2]
ADSET
P2
Address
[1]
ADSET
P1
LSB
Address
[0]
ADSET
P0
Address [5:0]: MSB bit is specified in ICSET P2 and [4:0] are specified as ADSET P4 - P0.
Don’t set out of range address, otherwise address will be set to 00000.
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Mode Set (MODESET)
MSB
D7
C
D6
1
D5
0
D4
*
D3
P3
D2
P2
LSB
D0
*
D1
*
(* : Don’t care)
Set display ON and OFF.
Setup
P3
Reset initialize condition
Display OFF (DISPOFF)
0
○
Display ON (DISPON)
1
Display OFF : Regardless of DDRAM data, all SEGMENT and COMMON output will be stopped after 1frame of
OFF data write. Display OFF mode will be disabled after Display ON command.
Display ON : SEGMENT and COMMON output will be active and start to read the display data from DDRAM.
Blink Control (BLKCTL)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
C
1
1
1
0
P2
P1
P0
( * : Don’t care)
Set blink mode.
Blink mode (Hz)
P2
P1
P0
Reset initialize condition
OFF
0
0
0
○
0.5
0
0
1
1
0
1
0
2
0
1
1
0.3
1
0
0
0.2
1
0
1
The Blink frequency varies depending on fclk characteristics at internal clock mode.
Refer to Oscillation Characteristics for fCLK.
All Pixel Control (APCTL)
MSB
D7
C
D6
1
D5
1
D4
1
LSB
D0
P0
D3
1
D2
1
D1
P1
P1
Reset initialize condition
Normal
0
○
All pixel ON (APON)
1
All display set ON, OFF
Setup
Setup
P0
Reset initialize condition
Normal
0
○
All pixel OFF (APOFF)
1
All pixels ON: All pixels are ON regardless of DDRAM data.
All pixels OFF: All pixels are OFF regardless of DDRAM data.
This command is valid in Display on status. The data of DDRAM is not changed by this command.
If set both P1 and P0 =”1”, APOFF will be selected.
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
LCD Driving Waveform
(1/3bias)
Line Inversion
Frame Inversion
SEGn SEG n+1 SEG n+2 SEG n+3
SEGn SEG n+1 SEG n+2 SEG n+3
COM0
stateA
COM0
stateA
COM1
stateB
COM1
stateB
COM2
COM2
COM3
COM3
1frame
VDD
1frame
VDD
COM0
COM0
VLCD
VLCD
VDD
VDD
COM1
COM1
VLCD
VLCD
VDD
VDD
COM2
COM2
VLCD
VLCD
VDD
VDD
COM3
COM3
VLCD
VLCD
VDD
VDD
SEGn
SEGn
VLCD
VLCD
VDD
VDD
SEGn+1
SEGn+1
VLCD
VLCD
VDD
VDD
SEGn+2
SEGn+2
VLCD
VLCD
VDD
VDD
SEGn+3
SEGn+3
VLCD
VLCD
stateA
(COM0-SEGn)
stateA
(COM0-SEGn)
(VDD-VLCD)
(VDD-VLCD)
2/3 (VDD-VLCD)
1/3 (VDD-VLCD)
0
-1/3 (VDD-VLCD)
-2/3 (VDD-VLCD)
- (VDD-VLCD)
2/3 (VDD-VLCD)
1/3 (VDD-VLCD)
0
-1/3 (VDD-VLCD)
-2/3 (VDD-VLCD)
- (VDD-VLCD)
stateB
(COM1-SEGn)
stateB
(COM1-SEGn)
(VDD-VLCD)
(VDD-VLCD)
2/3 (VDD-VLCD)
2/3 (VDD-VLCD)
1/3 (VDD-VLCD)
1/3 (VDD-VLCD)
0
0
-1/3 (VDD-VLCD)
-1/3 (VDD-VLCD)
-2/3 (VDD-VLCD)
-2/3 (VDD-VLCD)
- (VDD-VLCD)
-(VDD-VLCD)
Figure 15. LCD Waveform at Line Inversion (1/3bias)
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Figure 16. LCD Waveform at Frame Inversion (1/3bias)
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Example of Display Data
If LCD layout pattern is like Figure 17 and Figure 18, and display pattern is like Figure 19,
display data will be shown as below.
COM0
COM1
COM2
COM3
Figure 17. Example COM Line Pattern
SEG1 SEG3
SEG2
SEG5 SEG7
SEG4 SEG6 SEG8
SEG9
SEG10
Figure 18. Example SEG Line Pattern
Figure 19. Example Display Pattern
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
10
S
E
G
11
S
E
G
12
S
E
G
13
S
E
G
14
S
E
G
15
S
E
G
16
S
E
G
17
S
E
G
18
S
E
G
19
COM0
D0
0
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
COM1
D1
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
COM2
D2
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
COM3
D3
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Initialize Sequence
Follow the Power-on sequence below to initialize condition.
Power on
↓
STOP condition
↓
START condition
↓
Issue slave address
↓
Execute Software Reset by sending ICSET command.
After Power-on and before sending initialize sequence, each register value, DDRAM address and DDRAM data are
random.
Start Sequence
Start Sequence Example1
Input
1
Power on
2
3
4
5
6
7
8
9
10
D6
D5
D4
D3
D2
D1
D0
Descriptions
VDD=0→5V
(Tr: Min 1ms to Max 500ms)
Initialize BU9797AFUV
Stop condition
Start condition
0
1
1
1
1
1
0
0
Issue slave address
1
1
1
0
1
0
1
0
Software Reset
1
1
1
1
0
*
0
0
Blink OFF
1
0
1
0
0
1
0
0
80Hz, Frame inv., Power save mode1
1
1
1
0
1
*
0
1
External clock input
0
0
0
0
0
0
0
0
RAM address set
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
address
address
00h to 01h
02h to 03h
*
*
*
*
*
*
*
*
address
22h to 23h
…
11
↓
wait min100µs
↓
Stop
↓
Start
↓
Slave address
↓
ICSET
↓
BLKCTL
↓
DISCTL
↓
ICSET
↓
ADSET
↓
Display Data
Display Data
D7
…
No.
12
13
14
15
16
(*: don’t care)
Display Data
↓
Stop
↓
Start
↓
Slave address
↓
MODESET
↓
Stop
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Stop condition
Start condition
0
1
1
1
1
1
0
0
Issue slave address
1
1
0
*
1
0
*
*
Display ON
Stop condition
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BU9797AFUV
MAX 144 segments (SEG36×COM4)
Datasheet
Start Sequence Example2
Initialize
Initialize Sequence
DISPON
DISPON Sequence
RAM Write
RAM Write Sequence
DISPOFF
DISPOFF Sequence
BU9797AFUV is initialized with Start Sequence, starts to display with “DISPON Sequence”, updates display data with “RAM
Write Sequence” and stops the display with “DISPOFF Sequence”.
Execute “DISPON Sequence” in order to restart display.
Initialize Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
Power on
wait 100us
STOP
START
Slave address
ICSET
MODESET
ADSET
Display data
…
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
Execute Software Reset
Display OFF
RAM address set
Display data
STOP
DISPON Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
START
Slave address
ICSET
DISCTL
BLKCTL
APCTL
MODESET
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
Execute internal OSC mode
Set Display Control
Set BLKCTL
Set APCTL
Display ON
STOP
RAM Write Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
START
Slave address
ICSET
DISCTL
BLKCTL
APCTL
MODESET
ADSET
Display Data
…
STOP
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
Execute internal OSC mode
Set Display Control
Set BLKCTL
Set APCTL
Display ON
RAM address set
Display data
DISPOFF Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
START
Slave address
ICSET
MODESET
STOP
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
0
0
0
0
0
0
Execute internal OSC mode
Display OFF
Abnormal operation may occur in BU9797AFUV due to the effect of noise or other external factor.
To avoid this phenomenon, it is highly recommended to input command according to sequence described above
during initialization, display ON/OFF and refresh of RAM data.
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Datasheet
MAX 144 segments (SEG36×COM4)
Cautions in Power ON/OFF
BU9797AFUV has “P.O.R” (Power-On Reset) circuit and Software Reset function.
Keep the following recommended Power-On conditions in order to power up properly.
Set power up conditions to meet the recommended tR, tF, tOFF, and Vbot specification below in order to ensure P.O.R
operation.
VDD
tF
tR
tOFF
Vbot
Recommended condition of tR, tF, tOFF, Vbot (Ta=25°C)
(Note)
(Note)
(Note)
(Note)
tR
tF
tOFF
Vbot
Less than
Max 5ms
Max 5ms Min 20ms
0.3V
(Note) This function is guaranteed by design, not tested in production process.
Figure 20. Power ON/OFF Waveform
If it is difficult to keep above conditions, execute the following sequence as quickly as possible after Power-On.
Note however that it cannot accept command while supply is unstable or below the minimum supply range.
Note also that software reset is not a complete alternative to POR function.
1. Generate STOP Condition
VDD
SDA
SCL
STOP condition
Figure 21. Stop Condition
2. Generate START Condition.
VDD
SDA
SCL
START condition
Figure 22. Start Condition
3. Issue Slave Address
4. Execute Software Reset (ICSET) Command
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Datasheet
MAX 144 segments (SEG36×COM4)
Display OFF operation in external clock mode
After receiving MODESET(Display OFF), BU9797AFUV enters to DISPOFF sequence synchronized with frame then
Segment and Common ports output VSS level after 1frame of OFF data write.
Therefore, in external clock mode, it is necessary to input the external clock based on each frame frequency setting after
sending MODESET(Display OFF).
For the required number of clock, refer to Power save mode FR of DISCTL.
Please input the external clock as below.
DISCTL 80HZ setting(Frame frequency [Hz] = external clock [Hz] / 512), it needs over 1024clk
DISCTL 71HZ setting(Frame frequency [Hz] = external clock [Hz] / 576) , it needs over 1152clk
DISCTL 64HZ setting( Frame frequency [Hz] = external clock [Hz] / 648) , it needs over 1296clk
DISCTL 53HZ setting( Frame frequency [Hz] = external clock [Hz] / 768) , it needs over 1536clk
Please refer to the timing chart below.
Comma nd
MODESET
OSCIN
To input External clock at
least more than 2 frame
SEG
VSS
COM0
VSS
COM1
VSS
COM2
VSS
COM3
VSS
Display ON
Display OFF
Last Display frame of
MODESET receiving
1 frame of OFF
data write
Figure 23. External Clock Stop Timing
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Note on the multiple devices be connected to 2 wire interface.
Do not access the other device without power supply (VDD) to the BU9797AFUV.
BU9797A
Controller
Device1
Figure 24.
Example of BUS connection
To control the slope of the falling edge, a capacitor is connected between gate and drain of a NMOS transistor (Refer to
Figure25).
The gate is in a high-impedance state when the power supply (VDD) is not supplied.
In this condition, the gate voltage is pulled up by the current flow through the capacitance as a result of the SDA signal's
transition from LOW to HIGH.
The NMOS transistor turns on and draws some current (Ids) from the SDA port if the gate voltage (Vg) is higher than the
threshold voltage (Vth).
An external resistor (R) is connected between the power line and SDA line to keep the SDA line as logic HIGH.
But the line cannot be kept as logic HGH if the voltage drop (R*Ids) is large.
Apply power supply(VDD) to BU9797AFUV when the multiple devices are on the same bus.
Z=1/jω C
VDD
SDA
internal circuit
Figure 25.
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Vg
SDA output cell structure
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating,
increase the board size and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
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BU9797AFUV
MAX 144 segments (SEG36×COM4)
Datasheet
Operational Notes – continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation
of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage.
Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin
lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power
supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have
voltages within the values specified in the electrical characteristics of this IC.
13. Data transmission
To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent
from the occurrence of disturbances on transmission and reception.
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BU9797AFUV
Datasheet
MAX 144 segments (SEG36×COM4)
Ordering Information
B
U
9
7
9
7
A
Part Number
F
U
V
Package
FUV
: TSSOP-C48V
-
E2
Product Rank
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
TSSOP-C48V (TOP VIEW)
BU9797AFUV
Part Number Marking
Lot Number
1PIN MARK
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BU9797AFUV
MAX 144 segments (SEG36×COM4)
Datasheet
Physical Dimension, Tape and Reel Information
Package Name
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TSSOP-C48V
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BU9797AFUV
MAX 144 segments (SEG36×COM4)
Datasheet
Revision History
Date
Revision
27. Sep. 2016
001
Changes
New Release
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© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
27/27
TSZ02201-0P4P0D3P01620-1-2
27.Sep.2016 Rev.001
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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