Datasheet
Real-Time Clock (RTC) series
I2C BUS Serial Interface RTC
with High-precision Oscillation Adjustment
BU9873
Outline
Important Characteristics
■
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The BU9873 is a CMOS real-time clock, which has a
built-in interrupt generation function. This product is
connected to the CPU via I2C interface, and configured to
perform serial transmission of time and calendar data to
the CPU. A high-precision oscillation adjustment circuit is
also integrated, which is capable of adjusting time counts
with digital method, and correcting deviations in the
oscillation frequency of the crystal oscillator.
■
■
■
■
Features
■
■
■
■
■
■
■
■
■
■
■
Package
Connected to the CPU via I2C Interface
Time (Hour ･ Minute ･ Second, Selectable 12-Hour
and 24-Hour Mode Setting)
Calendar (Year･Month･Day･Week)
Periodic Interrupt Function
(Output from INTRB, Ranging from 1 Second to 1
Month)
Alarm Interrupt Function
(Day-of-Week ･ Hour ･ Minute in Setting Format,
Output from INTRB)
Oscillation Halt Sensing Function
32.768 kHz Clock Output
(Output from 32KOUT with Control Register)
±30 Second Adjustment Function
Automatic Leap Year Recognition up to the Year
2099
Built-in Oscillation Stabilizing Capacitors (CG, CD)
High-Precision Oscillation Adjustment Circuit
○Product structure: Silicon monolithic integrated circuit
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Time Keeping Voltage
Time Keeping Current 1
(VDD=3V, Ta=+25°C)
Time Keeping Current 2
(VDD=3V, Ta=-40°C to +85°C)
Power Supply Voltage
Access Frequency 1
(VDD=1.8V to 2.5V)
Access Frequency 2
(VDD=2.5V to 5.5V)
1.45V to 5.5V
0.4µA (Typ)
1.0µA (Max)
1.8V to 5.5V
100kHz (Max)
400kHz (Max)
W (Typ) x D (Typ) x H (Max)
SOP8
MSOP8
5.00mm x 6.20mm x 1.71mm
2.90mm x 4.00mm x 0.90mm
SOP- J8
VSON008X2030
4.90mm x 6.00mm x 1.65mm
2.00mm x 3.00mm x 0.60mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
○This product has no designed protection against radioactive rays
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Typical Application Circuit
RPU 10kΩ
32KOUT
CPU
VDD
SCL
OSCIN
SDA
OSCOUT
VSS
INTRB
RS 1kΩ
C1
Primary
Battery
C2
CGOUT
CDOUT
Quartz crystal: 32.768 kHz
(CL=6pF, R1=20kΩ)
CGOUT = CDOUT = 0 pF
Figure 1. Typical application circuit (with primary battery)
RPU 10kΩ
32KOUT
CPU
VDD
SCL
OSCIN
SDA
OSCOUT
VSS
INTRB
RS 1kΩ
C1
C2
Secondary
Battery
CGOUT
CDOUT
Quartz crystal: 32.768 kHz
(CL=6pF, R1=20kΩ)
CGOUT = CDOUT = 0 pF
Figure 2. Typical application circuit (with secondary battery)
The above circuits do not guarantee operation. Set the circuits and constants after performing sufficient evaluation using the
actual application. And please arrange the circuits to keep “Notes during Power On”. If it is necessary, please use the discharge
circuits of battery to keep it.
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Pin Configuration
(TOP VIEW)
VDD
OSCIN
8
OSCOUT
7
BU9873F
BU9873FJ
BU9873FVT
BU9873FVM
BU9873NUX
6
INTRB
5
:SOP8
:SOP-J8
:TSSOP-B8
:MSOP8
:VSON008X2030
1
2
32KOUT
SCL
3
4
SDA
VSS
Figure 3. Pin configuration
Pin Description
Pin No.
Symbol
Input/Output
Function
1
32KOUT
2
SCL
3
SDA
4
VSS
-
5
INTRB
Output
6
OSCOUT
-
7
OSCIN
-
The OSCIN and OSCOUT pins are used to connect the 32.768 kHz
crystal oscillator (Beside the crystal, all other oscillation circuit
components is already integrated in this IC).
8
VDD
-
The VDD pin is connected to the power supply.
The 32KOUT pin is used to output 32.768 kHz clock pulses, which is
controlled by an internal register. This pin is enabled during power-on
from 0V, and is CMOS push-pull output.
The SCL pin is used to input clock pulses synchronizing the input/output
Input
data from SDA pin.
The SDA pin is used to input and output data for writing and reading,
Input/Output which is synchronized with SCL pin. This pin is N-channel open drain
output.
Output
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TSZ22111・15・001
The VSS pin is grounded.
The INTRB pin is used to output periodic interrupt, or alarm interrupt
(Alarm_A, Alarm_B) to the CPU. This pin is disabled during power-on
from 0V, and is also N-channel open drain output.
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Block Diagram
32KOUT
32KOUT
1
CONTROL
TIME COUNTER
I/O
SCL
2
FILTER
OSC
VDD
7
OCSIN
6
OSCOUT
5
INTRB
OSC
DETECT
SEC
CONTROL
8
MIN
HOUR
WEEK
DAY
DIV
MONTH
YEAR
SDA
3
FILTER
SDA
CONTROL
VSS
4
ALARM_A
COMP_A
ALARM_B
COMP_B
INTRB
CONTROL
Figure 4. Block diagram
Absolute Maximum Ratings
Item
Supply Voltage
Symbol
Rating
Unit
VDD
－0.3 to ＋6.5
V
0.45 (SOP8)
When using above Ta=25, decreased by 4.5mW/°C.
0.45 (SOP-J8)
Power Dissipation
Storage
Temperature
Operating
Temperature
Terminal Voltage
Pd
Remark
When using above Ta=25, decreased by 4.5mW/°C.
0.33 (TSSOP-B8)
W
When using above Ta=25, decreased by 3.3mW/°C.
0.31 (MSOP8)
When using above Ta=25, decreased by 3.1mW/°C.
0.30 (VSON008X2030)
When using above Ta=25, decreased by 3.0mW/°C.
Tstg
－55 to +125
°C
Topt
－40 to +85
°C
―
-0.3 to VDD +0.3
V
The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not lower than -0.8V.
Caution: Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all destructive situations such as
short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit protection measures, like adding a fuse, in case the IC is operated in a
special mode exceeding the absolute maximum ratings
Operating Conditions
Item
Symbol
Rating
Unit
Supply Voltage
Timekeeping
Voltage(Note 1)
Input Voltage
VDD
1.8 to 5.5
V
VCLK
1.45 to 5.5
V
VIN
0 to VDD
V
(Note1) For minimum time keeping voltage, CGOUT = CDOUT = 0 pF; Quartz crystal unit: CL (load capacitor) = 6 pF to 12.5 pF, Maximum value of R1 (equivalent
series resistance) = 80 KΩ.
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DC Characteristics
Item
Symbol
Pin Name
“H” Input Voltage
VIH
“L” Input Voltage
Spec
Unit
Conditions
Min
Typ
Max
SCL, SDA
0.7VDD
－
VDD+0.3
V
VIL
SCL, SDA
-0.3
－
0.3VDD
V
“H” Output Current
IOH
32KOUT
－
－
-0.5
mA
VOH=VDD-0.5V
“L” Output Current1
IOL1
INTRB, 32KOUT
1
－
－
mA
VOL1=0.4V
“L” Output Current2
IOL2
SDA
6
－
－
mA
VOL2=0.4V
Input Leakage Current
IILK
SCL
-1
－
1
μA
VIN=5.5V or VSS, VDD=5.5V
Output Off State Leakage
Current
IOZ
SDA, INTRB,
32KOUT
-1
－
1
μA
IDD1
VDD
－
0.4
0.6
μA
IDD2
VDD
－
－
1.0
μA
IDD3
VDD
－
－
1.35
μA
VOUT=5.5V or VSS,
VDD=5.5V
VDD=3V,
Topt=25°C,
SCL, SDA=3V,
CGOUT=CDOUT=0pF,
Output=Open(Note1)
VDD=3V,
Topt=-40°C to +85°C,
SCL, SDA=3V,
CGOUT=CDOUT=0pF,
Output=Open(Note1)
VDD=5.5V,
Topt=-40°C to +85°C,
SCL, SDA=5.5V,
CGOUT=CDOUT=0pF,
Output=Open(Note1)
CG
OSCIN
－
10
－
pF
CD
OSCOUT
－
10
－
pF
Standby Current
(time keeping current)
Internal Oscillation
Capacitance 1
Internal Oscillation
Capacitance 2
Unless otherwise specified: Vss=0V, VDD=3V, Topt=−40°C to +85°C, Oscillation frequency=32.768 kHz
(load capacitance CL=6pF, equivalent series resistance R1=20kΩ)
(Note 1) In this mode, 32KOUT is disabled and no clock is output from this pin.
For time keeping current when outputting 32-kHz pulse from 32KOUT pin (this pin without loading), please refer to “P.7 Typical Performance Curves”.
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AC Characteristics
Item
Symbol
VDD ≥1.8V
VDD ≥2.5V
Min
Typ
Max
Min
Typ
Max
Unit
SCL Clock Frequency
fSCL
0
－
100
0
－
400
kHz
SCL Clock “L” Time
tLOW
4.7
－
－
1.3
－
－
μs
SCL Clock “H” Time
tHIGH
4.0
－
－
0.6
－
－
μs
Start Condition Hold Time
tHD:STA
4.0
－
－
0.6
－
－
μs
Stop Condition Setup Time
tSU:STO
4.0
－
－
0.6
－
－
μs
Start Condition Setup Time
tSU:STA
4.7
－
－
0.6
－
－
μs
Data Setup Time
tSU:DAT
250
－
－
100
－
－
ns
“H” Data Hold Time
tHDH:DAT
0
－
－
0
－
－
ns
“L” Data Hold Time
tHDL:DAT
35
－
－
35
－
－
ns
SDA “L” Stable Time After Falling of SCL
tPL:DAT
－
－
2.0
－
－
0.9
μs
SDA Off Stable Time After Falling of SCL
tPZ:DAT
－
－
2.0
－
－
0.9
μs
tR
－
－
1000
－
－
300
ns
tF
－
－
300
－
－
300
ns
tSP
－
－
50
－
－
50
ns
tF
tHIGH
Rising Time of SCL and SDA (Input)
(Note 1)
Falling Time of SCL and SDA (Input)
(Note 1)
Spike Width that can be Filtered
Unless additional specified: VSS=0V, Topt=－40°C to +85°C
(Note1) Not 100% TESTED
Condition Input data level: VIL=0.2×VDD VIH=0.8×VDD
Input data timing reference level: 0.3×VDD/0.7×VDD
Output data timing reference level: 0.3×VDD/0.7×VDD
Rise/Fall time: ≤20ns
tR
SCL
tHD:STA
tLOW
tSU:DAT
tHD:DAT
SDA
(INPUT)
tPL:DAT
tPZ:DAT
SDA
(OUTPUT)
Figure 5. Input and output timing
SCL
tSU:STA
tSU:STO
tHD:STA
SDA
A
START BIT
STOP BIT
Figure 6. Start and stop condition
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Typical Performance Curves
1.2
Timekeeping Current IDD [uA]
Timekeeping Current IDD [uA]
0.8
0.6
0.4
0.2
1
2
3
4
5
0.8
0.6
0.4
0.2
0
-60
0
0
1
6
Supply Voltage VDD [V]
0
30
60
90
120
Figure 8. Timekeeping Current vs. Operating Temperature
(with no 32-kHz clock output, output pins open)
(CGOUT=CDOUT=0pF, VDD=3V)
Figure 7. Timekeeping Current vs. Supply Voltage
(with no 32-kHz clock output, output pins open)
(CGOUT=CDOUT=0pF, Topt=25°C)
40
CPU Access Current IDD [uA]
4
Timekeeping Current IDD [uA]
-30
Operation Temperature Topt [Celsius]
3
2
1
VDD=1.5V
VDD=3.0V
VDD=5.8V
30
20
10
0
0
0
1
2
3
4
5
0
6
200
300
400
SCL Clock Frequency [kHz]
Supply Voltage VDD [V]
Figure 10. CPU Access Current vs. SCL Clock Frequency
(with no 32-kHz clock output, SDA=“H”)
(other pins open, CGOUT=CDOUT=0pF, Topt=25°C)
Figure 9. Timekeeping Current vs. Supply Voltage
(with 32-kHz clock output, output pins open)
(CGOUT=CDOUT=0pF, Topt=25°C)
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0
Oscillation Frequency Deviation [ppm]
Oscillation Frequency Deviation [ppm]
10
5
0
-5
-10
0
1
2
3
4
5
-20
-40
-60
-80
-100
-120
-140
-60 -40 -20
6
Supply Voltage VDD [V]
Figure 11. Oscillation Frequency Deviation vs. Supply
Voltage
(VDD=3V, Topt=25°C as standard)
20
40
60
80
100
Figure 12. Oscillation Frequency Deviation vs. Operating
Temperature
(VDD=3V, Topt=25°C as standard)
500
Oscillation Start Time [mS]
0
Oscillation Frequency Deviation [ppm]
0
Operation Temperature Topt [Celsius]
-20
-40
Fosc vs. CGout (CDout=0)
Fosc vs. CDout (CGout=0)
-60
400
300
200
100
0
0
5
10
15
20
0
External Capacitance [pF]
2
3
4
5
6
Supply Voltage VDD [V]
Figure 13. Oscillation Frequency Deviation vs. External CG
and CD
(VDD=3V, Topt=25°C as standard)
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1
Figure 14. Oscillation Start Time vs. Supply Voltage
(Topt=25°C)
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40
40
VDD=1.6V
VDD=3.0V
VDD=5.5V
30
IOL [mA]
IOL [mA]
30
20
20
10
10
0
0
0
0.1
VDD=1.6V
VDD=3.0V
VDD=5.5V
0.2
0.3
0.4
0.5
0
VOL [V]
0.2
0.3
0.4
0.5
VOL [V]
Figure 15. IOL vs. VOL INTRB pin
(Topt=25°C)
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0.1
Figure 16. IOL vs. VOL SDA pin
(Topt=25°C)
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Function Description
IC function will be explained as the following sequence.
1. Communication interface
2. Address mapping of internal register
3. Clock and calendar function
4. Oscillation adjustment function with digital method
5. Alarm interrupts function
6. Periodic interrupt function
7. Test bit
8. ±30 second adjust function
9. Oscillation halts sensing function
10. 32-kHz clock output function
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1. Communication Interface
This product can read/write data from I2C bus interface with 2-wires: SDA (data) and SCL (clock). Since the output of SDA
pin is open-drain, data transferring between CPU with different supply voltage is possible by adopting a pull-up resistor on
the circuit board.
1-1. I2C BUS Communication
I2C BUS data communication starts by a start condition input, and ends by a stop condition input. The data length is 8-bit,
and acknowledges signal is always required after each byte.
I2C BUS carries out data transmission between plural devices connected by 2-wires: serial data (SDA) and serial clock
(SCL). Among these devices, there is “master” that generates clock and control the start and end signal, and “slave” that is
controlled by unique device address. RTC is “slave”. And the device that outputs data to bus during data transferring is
called “transmitter”, and the device that receives data is called “receiver”.
SDA
SCL
1-7
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
DATA
9
1-7
ACK
DATA
8
9
ACK
P
STOP
condition
Figure 17. I2C BUS communication
1-2. Start Condition (start bit recognition)
Before executing any command, start condition (start bit) is necessary, where SDA goes from “H” down to “L” when
SCL is “H”.
This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, no command will be executed.
1-3. Stop Condition (stop bit recognition)
Every command can be ended by stop condition (stop bit), where SDA rising from “L” to “H” when SCL is “H”.
1-4. Acknowledge (ACK) Signal
・This acknowledge (ACK) signal is a software rule to judge whether data transfer has been executed successfully or not. For
master and slave, the device (µ-COM during inputting slave address of write command, read command, and this IC during
outputting data of read command) at the transmitter side releases the bus after outputting 8-bit data.
・The device (this IC during inputting slave address of write command, read command, and µ-COM during outputting data of
read command) at the receiver side sets SDA “L” during the ninth clock cycle, and outputs acknowledge signal (ACK)
showing that it has received the 8-bit data.
・This IC outputs acknowledge signal (ACK) “L” after recognizing start condition and 8-bit slave address.
・Every write action outputs acknowledge signal (ACK) “L” after receiving 8-bit data (word address and write data).
・Every read action outputs 8-bit data (read data), and detects acknowledge signal (ACK) “L”. When acknowledge signal
(ACK) is detected, and stop condition is not sent from the master (µ-COM) side, this IC will continue to output data. When
acknowledge signal (ACK) is not detected, this IC will stop data transfer, and end read action after recognizing stop
condition (stop bit). Then, this IC will get in off-status.
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1-5. Write Command
Write command is illustrated as following: Firstly, input start condition; then, enter the 7-bit slave address. Slave address of
――
this IC is (0110010). Thereafter, enter “L” for the R/W bit, which indicates the direction of data transmission.
In the next byte, input the internal address pointer (4-bit) and transmission format (4-bit) to the IC. For write operation, only
one transmission format (0000) is available. The 3rd byte transmits data that will be written to the address specified by the
internal address pointer. Internal address pointer settings will also be automatically incremented for 4byte and after. Note
that when the internal address pointer is Fh, it will change to 0h during transmitting the next byte.
Example of write command (when writing to internal address Eh to Fh)
S
T
A
R
T
SDA
LINE
Internal
Address Transmission
Pointer Format
Slave
Address
0 1 1 0 0 1 0 0
1 1 1 0 0 0 0 0
R A
/ C
K
W
DATA
S
T
O
P
DATA
D0
D7
A
C
K
D7
D0
A
C
K
A
C
K
Figure 18. Write command
1-6. Read Command
This IC allows the following three methods of reading data from an internal register.
1-6-1. Read from a Specified Internal Address
The first method uses data write command to specify the internal address pointer and transfer format, and then repeat the
start condition again. After the 7-bit slave address, enter “H” for the R/ W bit, which indicates the direction of data
transmission. In the next byte, data from the specified internal address will be output. If entering “L” during the timing of ACK,
the data from the next address will be output continuously. The read operation will not be ended until entering “H” during the
timing of ACK and following a stop condition.
The internal address pointer is reset to Fh when a stop condition is met. Therefore, this read method allows no insertion of
stop condition before the end of read.
Example 1 of data read (when data is read from 2h to 3h)
S
T
A
R
T
SDA
LINE
Internal
Address
Pointer
Slave
Address
0 1 1 0 0 1 0 0
Transmission
Format
Slave
Address
0 1 1 0 0 1 0
0 0 1 0 0 0 0 0
R A
/ C
K
W
S
T
A
R
T
D7
R A
/ C
K
W
A
C
K
DATA
DATA
1
S
T
O
P
D0
D7
A
C
K
D0
A
C
K
Figure 19. Read from a specified internal address
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1-6-2. Fast Read from a Specified Internal Address (with changing transmission format)
The second method uses data write command to specify the internal address pointer, but the transfer format is designated
to be (0100). In the next byte, data from the specified internal address will be output immediately. If entering “L” during the
timing of ACK, the data from the next address will be output continuously. The read operation will not be ended until entering
“H” during the timing of ACK and following a stop condition.
Example 2 of data read (when data is read from internal addresses Eh to 1h)
S
T
A
R
T
SDA
LINE
Internal
Address
Pointer
Slave
Address
Transmission
Format
D7
1 1 1 0 0 1 0 0
0 1 1 0 0 1 0 0
D0
A
C
K
R A
/ C
K
W
DATA
DATA
DATA
D7
D0
D7
S
T
O
P
A
C
K
D0
A
C
K
A
C
K
Figure 20. Fast read from a specified internal address
1-6-3. Read from Address Fh (without specifying the internal address)
The third method starts with a start condition, and then enters the 7-bit slave address and “H” for the R/ W bit, which
indicates the direction of data transmission.
In the next byte, data from address Fh will be output immediately. If entering “L” during the timing of ACK, the data from
the next address will be output continuously. The read operation will not be ended until entering “H” during the timing of ACK
and following a stop condition
Since the internal address pointer is set to Fh by a stop condition, this method is only effective when reading is started
from the internal address Fh.
Example 3 of data read (when data is read from internal addresses Fh to 3h)
S
T
A
R
T
SDA
LINE
Slave
Address
DATA
0 1 1 0 0 1 0 1
D7
R A
/ C
K
W
DATA
D7
D0
D7
D0
A
C
K
A
C
K
DATA
DATA
DATA
D0
D7
A
C
K
S
T
O
P
D7
D0
D0
A
C
K
Figure 21. Read from address Fh
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1-7. Notes during RTC Data Transmission
To avoid invalid read and write, two features should be noted when accessing the RTC.
Hold function of clock carry-up
While read and write operation is executed (at the same time, RTC clock is still counting-up), this IC temporarily holds the
clock carry-up from start condition to stop condition, to prevent invalid read and write. If clock carry-up happens during this
period (read or write from start condition to stop condition), it will be adjusted within approx. 61μs after stop condition.
Automatic release function of access
When 0.5 to 1.0 second elapses after start condition, any access to the RTC will be automatically terminated, to release
the temporarily holding of clock carry-up, set Fh to the address pointer, and access from the CPU is forced to be stopped (as
long as stop condition is received, the same action will be made: automatic release function from the I2C bus interface).
Therefore, one access must be completed within 0.5 seconds. The automatic release function prevents delay in SCL clock,
even if SCL is stopped because of system sudden failure during read operation.
In addition, a second start condition (after the first start condition and ahead of the stop condition) is regarded as the
“repeated start condition”. Therefore, when 0.5 to 1.0 seconds elapses after the first start condition, access to the RTC will
also be released automatically.
If access is tried after automatic release function is activated, no acknowledge signal will be output for writing while FFh
will be output for reading.
The following points should be noted during accessing the RTC.
(1) No stop condition shall be generated until clock and calendar data read/write is started and completed
Bad example of time read
(Start condition) → (Read of seconds) → (Read of minutes) → (Stop condition) → (Start condition) → (Read of hours) →
(Stop condition)
Assuming read is started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to 06:00:00 P.M.
During this time, second digit is hold so the read result is 05:59:59. Then the IC confirms stop condition and carries
second digit that is being hold and the time changes to 06:00:00 P.M. Thus, when the hour digit is read, it changes to be
6. The invalid results of 06:59:59 will be read.
(2) One cycle of read/write operation shall be completed within 0.5 seconds.
(3)
Do not send start condition within 61μs from stop condition, because the clock carry-up that is hold during I2C access
will be adjusted within approx.61μs from stop condition.
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2. Address Mapping of Internal Register
Internal address
A3 A2 A1 A0
Contents
D7
—
D6
D5
D4
Data
D3
D2
D1
D0
0
0
0
0
0
Second Counter
(Note1)
S40
S20
S10
S8
S4
S2
S1
1
0
0
0
1
Minute Counter
—
M40
M10
M8
M4
M2
M1
2
0
0
1
0
Hour Counter
—
—
M20
H20
P/AB
H10
H8
H4
H2
H1
3
0
0
1
1
Day-of-week Counter
—
—
—
—
—
W4
W2
W1
4
0
1
0
0
Day Counter
—
—
D20
D10
D8
D4
D2
D1
5
0
1
0
1
Month Counter
—
—
—
MO10
MO8
MO4
MO2
MO1
6
0
1
1
0
Year Counter
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
7
0
1
1
1
—
F6
F5
F4
F3
F2
F1
F0
8
1
0
0
0
—
AM40
AM20
AM10
AM8
AM4
AM2
AM1
9
1
0
0
1
—
—
AH20
AP/AB
AH10
AH8
AH4
AH2
AH1
A
1
0
1
0
—
AW 6
AW 5
AW 4
AW 3
AW 2
AW 1
AW 0
B
1
0
1
1
—
BM40
BM20
BM10
BM8
BM4
BM2
BM1
C
1
1
0
0
—
—
BH20
BP/AB
BH10
BH8
BH4
BH2
BH1
D
1
1
0
1
Time Trimming Register
Alarm_A
(Minute Register)
Alarm_A
(Hour Register)
Alarm_A
(Day-of-week Register)
Alarm_B
(Minute Register)
Alarm_B
(Hour Register)
Alarm_B
(Day-of-week Register)
—
BW 6
BW 5
BW4
BW 3
BW 2
BW 1
BW 0
E
1
1
1
0
Control Register 1
AALE
BALE
—
—
TEST
CT2
CT1
CT0
AAFG
BAFG
(Note4)
ADJ
F
1
1
1
1
Control Register 2
—
—
(Note2)
12B/24
XSTP
CLENB CTFG
(Note3)
(Note1) The “–” mark indicates data which can be read only and set to “0” when it is read.
(Note2) For the ADJ/XSTP bit of control register 2, ADJ will be set to “1” if writing “1”, while XSTP will be set to “0” if writing “0” during normal oscillation.
Conversely, setting ADJ=0 and XSTP=1 cause no event. The value of XSTP bit is output when it is read.
(Note3) When XSTP is set to “1”, the internal register F6 to F0, CT2 to CT0, AALE, BALE, CLENB will be reset to “0”.
(Note4) The TEST bit of control register 1 is for shipment testing. Please always set TEST = 0. If this bit is set to “1” accidentally, it will be reset to “0” after stop
condition is input.
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3. Clock and Calendar Function
The clock and calendar function is available in this IC, ranging from seconds to years (the last two digits of a year).
Every register is configured in BCD code, and assigned to the following address respectively.
Second counter (internal address 0h)
Minute counter (internal address 1h)
Hour counter (internal address 2h)
Day-of-week counter (internal address 3h)
Day counter (internal address 4h)
Month counter (internal address 5h)
Year counter (internal address 6h)
3-1. Clock Counter (second counter, minute counter and hour counter)
Time digit in BCD code is displayed as follows.
Second counter: be reset to “00” and carried to minute digits when incremented from 00 to 59.
Minute counter: be reset to “00” and carried to hour digits when incremented from 00 to 59.
Hour counter: be reset to “00” and carried to day and day-of-the-week digits when incremented from 00 to 23 (in 24-hour
mode).
If non-existent time has been written, any carry from lower digits may cause the time counters to malfunction. Therefore,
such incorrect writing should be replaced with the writing of existent time data.
Users can choose to display time in 12-hour mode or 24-hour mode by setting the 12B/24 bit (internal address Fh).
12B/24-hour mode selection bit
12B/24
Description
0
12- hour time display system (separate for morning and afternoon)
1
24- hour time display system
Time Display Table
24-hour mode
12-hour mode
24-hour mode
12-hour mode
00
01
02
03
04
05
06
07
08
09
10
11
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
12
13
14
15
16
17
18
19
20
21
22
23
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
Setting the 12-hour or 24-hour mode should precede writing time data.
3-2. Day-of-week Counter
Day-of-week digits are incremented by 1 corresponding to the 7 days of week, e.g. (W4, W2, W1) = (0, 0, 0) → (0, 0, 1) → …
→ (1, 1, 0) → (0, 0, 0)
The relation between the days of week and day-of-week digits is user definable. (e.g. Sunday=0, 0, 0)
(W4, W2, W1) should not be set to (1, 1, 1).
3-3. Calendar Counter (day counter, month counter and year counter)
The automatic calendar function provides the calendar digit displayed in BCD code.
Day digits: Range from 1 to 31 (for January, March, May, July, August, October, and December)
Range from 1 to 30 (for April, June, September, and November)
Range from 1 to 29 (for February in leap years)
Range from 1 to 28 (for February in ordinary years)
Carried to month digits when reset to 1
Month digits: Range from 1 to 12 and carried to year digits when reset to 1.
Year digits: Range from 00 to 99 and 00, 04, 08… 92 and 96 are counted as leap years.
If non-existent time has been written, any carry from lower digits may cause the time counters to malfunction. Therefore,
such incorrect writing should be replaced with the writing of existent time data.
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3-4. Automatic Judgment of Leap Year
Automatic judgment function of leap year is included in this IC. Leap year is defined as follows.
The year that can be divided by 4 is leap year.
The year that can be divided by 100 is ordinary year.
The year that can be divided by 400 is leap year.
For example, year 2000 is a leap year while year 2100 is ordinary year.
Because the year register of this IC only supports the last two digits, a year will be automatically recognized as a leap year if
it is a multiple of 4. Therefore, year 2100 or 2000 will be determined as leap year because the last two digits are “00”. This
result in automatic judgment of leap years only can be up to the year 2099 in this IC.
4. Oscillation Adjustment Function with Digital Method
This IC has built-in oscillation capacitance CG and CD, the oscillation circuit can be configured easily by connecting an
external crystal oscillator. However, due to some variations such as parasitic capacitance, it is hardly for RTC to oscillate at
32,768 Hz exactly.
Therefore, if you want to achieve high-precision clock, it is necessary to use the error correction method. By using this
feature, you can achieve high-precision clock with only ±1.5ppm mismatch at a specified temperature. Because the crystal
oscillator has temperature dependency, the clock mismatch will increase when the temperature changes.
The clock adjustment step is about 3ppm and the total range is ±189ppm.
As following, some application is possible:
(1) If the temperature sensor is integrated in system, by setting the clock adjustment function in accordance with the
variation of temperature, it is possible to realize high-precision clock that does not depend on the temperature.
(2) By storing seasonal temperature information to the system, and using the clock adjustment function with this
temperature information, the realization of high-precision clock is available throughout the year.
4-1. Function Description
In the IC, counting up to seconds is made once per 32,768 of clock pulse generated by the oscillator. If oscillation
frequency is not 32,768 Hz which does not match with the number of clock counts, the time error will happen. This function is
designated to compensate the clock mismatch.
The adjustment function adds 2 clock pulses every 20 seconds: 2/(32,768×20)=3.051ppm, which delays the clock by
approx. 3ppm. Likewise, decrementing 2 clock pulses advances the clock by 3ppm. Thus the clock may be adjusted to the
precision of ±1.5ppm. and the total range is ±189.2ppm (±124 steps) according to the internal 7-bit trim register. The time
trimming circuit adjusts one second count based on this register when second digit is 00, 20 or 40 seconds. Note that the
time trimming function only adjust clock timing and oscillation frequency and 32-kHz clock output is not adjusted.
Setting data to internal register (internal address 7h) activates the time trimming circuit. And bit F6 decides either
increasing or decreasing the clock pulse.
The clock counts will be increased as ((F5, F4, F3, F2, F1, F0)－1) ×2 when F6 is set to “0”.
The clock counts will be decreased as ((/F5, /F4, /F3, /F2, /F1, /F0)＋1) ×2 when F6 is set to “1”.
Counts will not change when (F6, F5, F4, F3, F2, F1, F0) are set to (*, 0, 0, 0, 0, 0, *)
For example, when 32.768 kHz crystal is used:
When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 1, 1, 1), counts will change as: 32,768＋(7－1) ×2=32,780 (clock will
be delayed) when second digit is 00, 20 or 40.
When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32,768 without changing when second
digit is 00, 20 or 40.
When (F6, F5, F4, F3, F2, F1, F0) are set to (1, 1, 1, 1, 1, 1, 0), counts will change as: 32,768＋(－2) ×2=32,764 (clock will
be advanced) when second digit is 00, 20 or 40.
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4-2. Configuration Method of Time Adjustment
Time adjustment amount can be calculated following the rules below.
Case 1:
When oscillation frequency (Note1) >target frequency (Note2) (clock gains)
Adjustment amount (Note3) =
(Oscillation frequency − Target frequency + 0.1)
-------------------------------------------------------------Oscillation frequency × 3.051 × 10−6
≈ (Oscillation frequency − Target frequency) × 10 + 1
(Note1) Oscillation frequency : Clock frequency output from the 32KOUT pin at room temperature.
(Note2) Target frequency :
A frequency to be adjusted to.
Since temperature characteristics of a 32.768 kHz crystal oscillator generally generates the highest frequency at a room temperature, we recommend to set
the target frequency to approx. 32768.00Hz to 32768.10Hz (+3.05ppm to 32768Hz).
Note that this value may differ based on the environment or place where the device will be used.
(Note3) Adjustment amount: A value to be set finally to F6 to F0 bits. This value is expressed in 7bit binary digits with sign bit.
Example of Calculations
When oscillation frequency=32768.85 Hz; target frequency=32768.05 Hz
Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10-6)
≈ (32768.85 - 32768.05) × 10 + 1
= 9.001 ≈ 9
In this instance, write the settings (F6, F5, F4, F3, F2, F1, F0) = (0, 0, 0, 1, 0, 0, 1) in the oscillation adjustment register.
Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h.
Case 2:
When oscillation frequency=target frequency (no clock gain or loss)
(F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *).
In this case, the correction is not performed.
Case 3:
When oscillation frequency
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