Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL620Q504H-02
Issue Date: May. 20, 2020
ML620Q503H/Q504H
Ultra Low Power 16-bit Microcontroller
GENERAL DESCRIPTION
This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as
synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation
type A/D converter, and successive approximation type A/D converter are incorporated around 16-bit CPU
nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe
line architecture parallel processing. The Flash ROM* that is installed as program memory achieves low-voltage
low-power consumption operation (read operation) is most suitable for battery-driven applications. And, this LSI
has a data flash-memory* fill area by a software which can be written in.
The on-chip debug function that is installed enables program debugging and programming.
*: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. SuperFlash®
is a registered trademark of Silicon Storage Technology, Inc.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division,
bit manipulations, bit logic operations, jump, conditional jump, call return stack
manipulations, arithmetic shift, and so on
− Build-in On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
62.5ns (@16 MHz system clock)
• Built-in coprocessor for multiplication, division, and multiply-accumulate operations
− Signed or unsigned operation setting
− Multiplication: 16bit × 16bit (operation time 4 cycles)
− Division: 32bit / 16bit (operation time 8 cycles)
− Division: 32bit / 32bit (operation time 16 cycles)
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
• Internal memory
− Supports ISP function (re-writing the program memory area by software)
− Number of segments
Product name
ML620Q503H
ML620Q504H
Flash memory
Program area**
Data area
32KB (16K × 16bit)
2KB (1K × 16bit)
64KB (32K × 16bit)
2KB (1K × 16bit)
**: including 1KB of unusable test area
SRAM
2KB (1K × 16bit)
6KB (3K × 16bit)
• Interrupt controller (INTC)
− 1 non-maskable interrupt sources (Internal source: 1)
− 37 maskable interrupt sources (Internal sources: 29, External sources: 8)
− Software interrupt (SWI): maximum 64 sources
− External interrupts and comparator allow edge selection and sampling selection
− Priority level (4-level) can be set for each interrupt
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FEDL620Q504H-02
ML620Q503H/Q504H
• Time base counter (TBC)
− Low-speed time base counter ×1 channel
• Timers (TMR)
− 8 bits × 8 channels
(Timer0-7: 16-bit × 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7)
− Selection of one shot timer mode is possible
− External clock can be selected as timer clock.
• Function Timers (FTM)
− 16-bit × 4 channels
− Equipped with the timer/capture/PWM functions using a 16-bit counter
− Timer start/stop function by software/event trriger(external pin or other timer)
− External pin can be selected as counter clock
− Capture function (the measurement such as the pulse width is possible using external trigger input)
− Two types of PWM with the same period and different duties and complementary PWM with the dead time
set can be output.
• Watchdog timer (WDT)
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)
• Synchronous serial port (SSIOF/SSIO)
− without FIFOs (SSIO) : 1 channel
− with 4-byte transmits and receives FIFOs (SSIOF) : 1 channel
− Master/slave are selectable
− LSB first/MSB first are selectable
− 8-bit length/16-bit length are selectable
− Phase/Polarity of clock are selectable
− supports slave-select signal (only SSIOF)
• UART (UARTF/UART)
− without FIFOs (UART) : 1ch
− with 4-byte transmits and receives FIFOs (UARTF) : 1ch
− Full duplex buffer system
− Communication speed: Settable within the range of 2400bps to 115200bps.
− Programmable interface (data length, parity, stop bits selectable)
• I2C bus interface (I2C)
− Master function × 2 channel
− Fast mode (400 kbps), standard mode (100 kbps)
• General-purpose ports (PORT)
− Input port × 2, Input/output port × 36 channels
• Melody driver (MELODY)
− Tempo: 15 types
− Scale: 29 types (Melody sound frequency: 508 Hz to 10.922 kHz)
− Tone length: 63 types
− Buzzer output mode (4 output modes, 8 buzzer frequencies, 7duty levels at 4.096kHz /15 duty levels at
other buzzer frequencies)
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FEDL620Q504H-02
ML620Q503H/Q504H
• RC oscillation type A/D converter (RC-ADC)
− Time division × 2 channels
− 24-bit counter
• Successive approximation type A/D converter (SA-ADC)
− Input × 12 channels
− 12-bit A/D converter
− Starting by trigger of Timer/FTM function.
− Capacitive touch sense function
• Analog Comparator (CMP)
− Input × 2ch
− Common mode input voltage: 0.2V to VDD－0.2V
− Input offset voltage: 30mV(max)
− Interrupt allow edge selection and sampling selection are selectable
• Voltage Level Supervisor (VLS)
− Threshold voltages: selectable from 13 levels
− interrupt or reset generate are selectable
• Low Level Detector(LLD)
− Judgement Voltage: 1.8V±0.2V
− Usable as low level detection reset
• Reset
− Reset by the RESET_N pin
− Reset by power-on detection
− Reset by overflow of watchdog timer (WDT)
− Reset by Voltage Leve Supervisor(VLS)
− Reset by Low Level Detector(LLD)
• Clock
− Low-speed clock: (This LSI can not guarantee the operation without low-speed clock)
− Crystal oscillation (32.768 kHz)
− External clock input (30kHz to 36kHz)
− Built-in RC oscillation (32.768kHz)
− High-speed clock:
− Crystal/Ceramic oscillation (16 MHz)
− External clock input (300kHz to 16 MHz)
− Built-in RC oscillation (16MHz)
3/35
FEDL620Q504H-02
ML620Q503H/Q504H
• Power management
− HALT mode: Instruction execution by CPU is suspended. All peripheral circuits can keep in operating
states.
− HALT-H mode: Instruction execution by CPU is suspended. Stop of high-speed oscillation automatically.
All peripheral circuits can keep in operating states.
− DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTB,
etc.) can keep in operating states.
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral
circuits are stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4,
1/8,1/16,1/32 of the oscillation clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused
peripherals.
• Shipment
− Die * Please contact our responsible sales person for the pad layout information.
− 48-pin plastic TQFP Tray/Tape and Reel
ML620Q503H-xxxTB
ML620Q504H-xxxTB
• Guaranteed operating range
− Operating temperature (ambient) : −40°C to +85°C
− Operating voltage: VDD = 1.8V to 5.5V
4/35
FEDL620Q504H-02
ML620Q503H/Q504H
BLOCK DIAGRAM
Block Diagram of ML620Q503H/Q504H
CPU (nX-U16/100)
EPSW1~3
GREG
0~15
PSW
Timing
Controller
ALU
ECSR1~3
LR
DSR/CSR
EA
PC
SP
Instruction
Decoder
On-Chip
ICE
ELR1~3
Instruction
Register
Data-bus
VSS
Power
Data Flash
Memory
2Kbyte
VDD
VDDL
VDDX
RESET_N
TEST0
TEST1_N
XT0
XT1
OSC0
OSC1
LSCLKO
OUTCLK
LSCLKI
CLKIN
IN0
CS0
RS0
RT0
RCT0
RCM
IN1
CS1
RS1
RT1
VREF
RESET &
TEST
INT
1
CMP1P
CMP1M
Interrupt
Controller
INT
1
OSC
INT
1
RC-ADC
INT
3
INT
8
INT
1
SA-ADC
Program
Memory
(Flash)
32K/64Kbyte
BUS
Controller
INT
2
SSIO x 1
SSIOF x 1
3
I2C x 2
INT
Timer
×8
VLS
4
INT
1
Figure 1.
SDA0
SCL0
SDA1
SCL1
TMOUT0-9
TMOUTA-F
TMCKI0-7
MELODY
MD0
P00 to P05
PXT0 to PXT1
1
P10 to P11
LLD
2
RXD0
TXD0
RXDF0
TXDF0
Function
Timer x 4
INT
8
INT
Analog
Comparator
x2
UART x 1
UARTF x 1
INT
WDT
TBC
SCK0
SIN0
SOUT0
SCKF0
SINF0
SOUTF0
SSF0
INT
2
INT
AIN0 to AIN11
CMP0P
CMP0M
RAM
2K/6Kbyte
co-processor
(muldiv)
GPIO
P20 to P23
P30 to P37
P40 to P47
P50 to P57
Block Diagram of ML620Q503H/Q504H
5/35
FEDL620Q504H-02
ML620Q503H/Q504H
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
P53 | LED | *3
P52 | LED | *2
P51 | *1
P50 | *0
P47 | *7
P46 | *6
P45 | *5
P44 | *4
P43 | *3
P42 | *2
P41 | LED | *1
P40 | LED | *0
Pin Layout of ML620Q503H/Q504H TQFP Package
*7 | P57
TEST0
TEST1_N
VDDL
24
23
22
21
20
19
18
17
16
15
14
13
P05 | RCM
P04 | RT0
P03 | AIN11 | RS0 | *3$
P02 | AIN10 | RCT0 | *2$
P01 | AIN9 | CS0 | *1$
P00 | AIN8 | IN0 | *0$
P23 | AIN7 | RT1 | *7$
P22 | AIN6 | RS1 | *6$
P21 | AIN5 | CS1 | *5$
P20 | AIN4 | IN1 | *4$
VSS
VDD
RESET_N
OSC0 | P10
CLKIN | OSC1 | P11
*0 | CMP0P | P30
*1 | CMP0M | P31
*2$ | CMP1P | P32
*3$ | CMP1M | P33
*4 | AIN0 | P34
*5 | AIN1 | P35
*6$ | AIN2 | P36
*7$ | AIN3 | P37
VREF
VDD
VSS
VDDX
LSCLKI | XT1 | PXT1
XT0 | PXT0
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
*4 | P54
*5 | P55
*6 | P56
External intteruput inputpin(EXI) can be assigned to P00-P05, PXT0-1, P20-P57.
*0 to *7 and *0$ to *7$ has following functions. But 0$-7$ has limited function. Please refer to the pin list.
*0 : SDA0, SOUT0, RXD0
*4 : SDA1, SOUTF0, RXDF0
*1 : SCL0, SIN0 , TXD0
*5 : SCL1, SINF0, TXDF0
*2 : SCK0, TMOUT ,TMCKI
*6 : LSCLKO,SCKF0, TMOUT, TMCKI
*3 : MD0, TMOUT , TMCKI
*7 : OUTCLK,SSF0, TMOUT, TMCKI
*0$ : SOUT0, RXD0
*4$ : SOUTF0, RXDF0
*1$ : SIN0 , TXD0
*5$ : SIN F0, TXDF0
*2$ : SCK0, TMOUT
*6$ : SCKF0, TMOUT
*3$ : MD0(P33 only), TMOUT
*7$ : SSF0, TMOUT
Figure 2.
Pin Layout of ML620Q503H/Q504H TQFP Package
6/35
FEDL620Q504H-02
ML620Q503H/Q504H
PIN LIST
PKG
Pin
No.
1st Function
2nd/3rd/4th Function
Pin name
I/O
Reset State
Function
pin name
I/O
function
pin name I/O
function
pin name
I/O
function
14,
45
VSS
－
－
Negative power supply
pin
－
－
－
－
－
－
－
－
－
13,
44
VDD
－
－
Positive power supply
pin
－
－
－
－
－
－
－
－
－
43
VDDL
－
－
Power supply pin for
internal circuit
(internally generated)
－
－
－
－
－
－
－
－
－
46
VDDX
－
－
－
－
－
－
－
－
－
－
－
Reference voltage
input pin of SA-ADC
－
－
－
－
－
－
－
－
－
Reset input pin
－
－
－
－
－
－
－
－
－
Input pin for testing
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Power supply pin for
internal circuit (internally
generated)
12
VREF
I
－
1
RESET_N
I
Pull-up
Input
42
TEST1_N
I
41
TEST0
I/O
48
PXT0/
EXII0/
XT0
I
Input
disable
47
PXT1/
EXI1/
XT1/
LSCLKI
I/O
Hi-Z
output
19
P00/
EXI00/
AIN8
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
IN0
I
RC-ADC oscillation
input
SOUT0
O
SSIO data output
RXD0
I
UART
data
input
20
P01/
EXI01/
AIN9
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
CS0
O
RC-ADC reference
capacitance
connection pin
SIN0
I
SSIO data input
TXD0
O
UART
data
output
21
P02/
EXI02/
AIN10
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
RCT0
O
RCADC
resistor/capacitor
sensor connection
pin
SCK0
I/O
TMOUT0
O
FTM
output
22
P03/
EXI03/
AIN11
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
RS0
O
RC-ADC reference
resistor connection
pin
－
－
－
TMOUT1
O
FTM
output
23
P04/
EXI04
I/O
Hi-Z
output
Input-Output port/
External interrupt
RT0
O
RC-ADC
measurement
resistor sensor
connection pin
－
－
－
－
－
－
24
P05/
EXI05
I/O
Hi-Z
output
Input-Output port/
External interrupt
RCM
O
RC-ADC oscillation
monitor
－
－
－
－
－
－
2
P10/
OSC0
I/O
Hi-Z
output
Input-Output port/
High-speed oscillation
port
－
－
－
－
－
－
－
－
－
3
P11/
OSC1/
CLKIN
I/O
Hi-Z
output
Input-Output port/
High-speed oscillation
port
High-speed external
clock input
－
－
－
－
－
－
－
－
－
15
P20/
EXI20/
AIN4
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
IN1
I
RC-ADC oscillation
input
SOUTF0
O
SSIOF data
output
RXDF0
I
UARTF
data
input
16
P21/
EXI21/
AIN5
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
CS1
O
RC-ADC reference
capacitance
connection pin
SINF0
I
SSIOF data input
TXDF0
O
UARTF
data
output
17
P22/
EXI22/
AIN6
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
RS1
O
RC-ADC reference
resistor connection
pin
SCKF0
I/O
TMOUT2
O
FTM
output
Pull-up
Input
Pull-down Input/output pin
Input
for testing
Input port/
External interrupt/
Low-speed oscillation
port
Input-Output port/
External interrupt/
Low-speed oscillation
port
Low-speed external
clock input
SSIO clock
input/output
SSIOF clock
input/output
7/35
FEDL620Q504H-02
ML620Q503H/Q504H
PKG
Pin
No.
1st Function
2nd/3rd/4th Function
Pin name
I/O
Reset State
Function
pin name
I/O
18
P23/
EXI23/
AIN7
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
4
P30/
EXI30/
CMP0P
I/O
Hi-Z
output
5
P31/
EXI31/
CMP0M
I/O
6
P32/
EXI32/
CMP1P
7
function
RT1
O
RC-ADC
measurement
resistor sensor
connection pin
Input-Output port/
External interrupt/
Comparator plus input
SDA0
I/O
I2C data
input/output
Hi-Z
output
Input-Output port/
External interrupt/
Comparator minus
input
SCL0
O
I2C clock output
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Comparator plus input
－
－
P33/
EXI33/
CMP1M
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Comparator minus
input
MD0
O
Melody/Buzzer
output
8
P34/
EXI34/
AIN0
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
SDA1
I/O
I2C data
input/output
9
P35/
EXI35/
AIN1
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
SCL1
O
I2C clock output
10
P36/
EXI36/
AIN2
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
－
－
11
P37/
EXI37/
AIN3
I/O
Hi-Z
output
Input-Output port/
External interrupt/
SA-ADC input
－
25
P40/
EXI40/
LED
I/O
Hi-Z
output
Input-Output port/
External interrupt/
LED output
26
P41/
EXI41/
LED
I/O
Hi-Z
output
27
P42/
EXI42/
TMCKI0
I/O
28
P43/
EXI43/
TMCKI1
29
pin name I/O
function
pin name
I/O
function
TMOUT3
O
FTM
output
SSF0
I/O
SSIOF select
input/output
SOUT0
O
SSIO data output
RXD0
I
UART
data
input
SIN0
I
SSIO data input
TXD0
O
UART
data
output
SCK0
I/O
TMOUT4
O
FTM
output
－
－
TMOUT5
O
FTM
output
SOUTF0
O
SSIOF data
output
RXDF0
I
UARTF
data
input
SINF0
I
SSIOF data input
TXDF0
O
UARTF
data
output
－
SCKF0
I/O
SSIOF clock
input/output
TMOUT6
O
FTM
output
－
－
SSF0
I/O
SSIOF select
input/output
TMOUT7
O
FTM
output
SDA0
I/O
I2C data
input/output
SOUT0
O
SSIO data output
RXD0
I
UART
data
input
Input-Output port/
External interrupt/
LED output
SCL0
O
I2C clock output
SIN0
I
SSIO data input
TXD0
O
UART
data
output
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input
－
－
SCK0
I/O
TMOUT8
O
FTM
output
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input
MD0
O
Melody/Buzzer
output
－
－
TMOUT9
O
FTM
output
P44/
EXI44
I/O
Hi-Z
output
Input-Output port/
External interrupt
SDA1
I/O
I2C data
input/output
SOUTF0
O
SSIOF data
output
RXDF0
I
UARTF
data
input
30
P45/
EXI45
I/O
Hi-Z
output
Input-Output port/
External interrupt
SCL1
O
I2C clock output
SINF0
I
SSIOF data input
TXDF0
O
UARTF
data
output
31
P46/
EXI46/
TMCKI2
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input
LSCLKO
O
Low-speed clock
output
SCKF0
I/O
SSIOF clock
input/output
TMOUTA
O
FTM
output
32
P47/
EXI47/
TMCKI3
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input
OUTCLK
O
High-speed clock
output
SSF0
I/O
SSIOF select
input/output
TMOUTB
O
FTM
output
33
P50/
EXI50
I/O
Hi-Z
output
Input-Output port/
External interrupt
SDA0
I/O
I2C data
input/output
SOUT0
O
SSIO data output
RXD0
I
UART
data
input
34
P51/
EXI51
I/O
Hi-Z
output
Input-Output port/
External interrupt
SCL0
O
I2C clock output
SIN0
I
SSIO data input
TXD0
O
UART
data
output
35
P52/
EXI52/
TMCKI4/
LED
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input/
LED output
－
－
SCK0
I/O
TMOUTC
O
FTM
output
36
P53/
EXI53/
TMCKI5/
LED
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input/
LED output
MD0
O
－
－
TMOUTD
O
FTM
output
－
－
－
Melody/Buzzer
output
SSIO clock
input/output
－
SSIO clock
input/output
－
SSIO clock
input/output
－
8/35
FEDL620Q504H-02
ML620Q503H/Q504H
PKG
Pin
No.
1st Function
Pin name
I/O
Reset State
37
P54/
EXI54
I/O
Hi-Z
output
38
P55/
EXI55
I/O
39
P56/
EXI56/
TMCKI6
40
P57/
EXI57/
TMCKI7
2nd/3rd/4th Function
Function
pin name
I/O
function
Input-Output port/
External interrupt
SDA1
I/O
I2C data
input/output
Hi-Z
output
Input-Output port/
External interrupt
SCL1
O
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input
LSCLKO
I/O
Hi-Z
output
Input-Output port/
External interrupt/
Timer clock input
OUTCLK
pin name I/O
function
pin name
I/O
function
SOUTF0
O
SSIOF data
output
RXDF0
I
UARTF
data
input
I2C clock output
SINF0
I
SSIOF data input
TXDF0
O
UARTF
data
output
O
Low-speed clock
output
SCKF0
I/O
SSIOF clock
input/output
TMOUTE
O
FTM
output
O
High-speed clock
output
SSF0
I/O
SSIOF select
input/output
TMOUTF
O
FTM
output
9/35
FEDL620Q504H-02
ML620Q503H/Q504H
PIN DESCRIPTION
The pin name represents the function pin name of the primary function of each terminal, The pin mode
represents the set of mode register of Port Control.
(1st:primary function, 2nd:secondary function, 3rd: tertiary function, 4th: quartic function)
Pin name
System
RESET_N
I/O
Description
Reset input pin. When this pin is set to a “L” level,
system reset mode is set and the internal section
is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up
resistor is internally connected.
Crystal connection pin for low-speed clock.
XT0
I
Capacitors CDL and CGL are connected across
XT1
O
this pin and VSS as required.
External clock input for Low-speed clock.
LSCLKI
I
Crystal/ceramic
connection pin for high-speed
OSC0
I
clock
OSC1
O
(16 MHz max.). Capacitors CDH and CGH are
connected across this pin and Vss.
CLKIN
I External clock input for High-speed clock.
LSCLKO
O Low-speed clock output pin.
OUTCLK
O High-speed clock output pin.
General-purpose input/output port
PXT0-PXT1
I General-purpose input port(without
pull-up/pull-down resister).
P00-P05
I/O General-purpose input/output port.
P10-P11
I/O General-purpose input/output port.
P20-P23
I/O General-purpose input/output port.
P30-P37
I/O General-purpose input/output port.
P40-P47
I/O General-purpose input/output port.
P50-P57
I/O General-purpose input/output port.
I
External interrupt
EXII0-EXII1
I External maskable interrupt input pins. It is
possible, for each bit, to specify
EXI00-05
whether the interrupt is enabled and select the
EXI20-23
interrupt edge by software.
EXI30-37
EXI40-47
EXI50-57
LED
LED
O N-channel open drain output pins to drive LED.
Melody/Buzzer
MD0
— Melody/buzzer signal output pin.
UART
TXD0
O UART0 data output pin.
RXD0
I UART0 data input pin.
TXDF0
O UART with FIFO data output pin.
RXDF0
I UART with FIFO data input pin.
LSI pin name
Pin mode
Logic
RESET_N
—
L
PXT0
PXT1
1st
1st
—
—
PXT1
P10
P11
1st
1st
1st
—
—
—
P11
P46,P56
P47,P57
1st
2nd
2nd
—
—
—
PXT0PXT1
P00-P05
P10-P11
P20-P23
P30-P37
P40-P47
P50-P57
1st
—
1st
1st
1st
1st
1st
1st
—
—
—
—
—
—
PXT0-PXT1
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
1st
H/L
P40,P41,P52,P53
1st
—
P33,P43,P53
2nd
H
P01,P31,P41,P51
P00,P30,P40,P50
P21,P35,P45,P55
P20,P34,P44,P54
4th
4th
4th
4th
—
—
—
—
10/35
FEDL620Q504H-02
ML620Q503H/Q504H
Description
Pin name
I/O
2
I C bus interface
2
SDA0
I/O I C0 data input/output pin. This pin has an NMOS
open drain output. When using this pin as a
2
function of the I C, externally connect a pull-up
resistor.
2
SCL0
O I C0 clock output pin.
This pin has an NMOS open drain output. When
2
using this pin as a function of the I C, externally
connect a pull-up resistor.
2
SDA1
I/O I C1 data input/output pin. This pin has an NMOS
open drain output. When using this pin as a
2
function of the I C, externally connect a pull-up
resistor.
2
SCL1
O I C1 clock output pin. This pin has an NMOS open
drain output. When using this pin as a function of
2
the I C, externally connect a pull-up resistor.
Synchronous serial
SCK0
I/O Synchronous serial(SSIO) clock input/output pin.
LSI pin name
Pin mode
Logic
P30,P40,P50
2nd
—
P31,P41,P51
2nd
—
P34,P44,P54
2nd
—
P35,P45,P55
2nd
—
P02,P32,P42,P52
3rd
—
SIN0
I
Synchronous serial(SSIO) data input pin.
P01,P31,P41,P51
3rd
—
SOUT0
O
Synchronous serial(SSIO) data output pin.
P00,P30,P40,P50
3rd
—
SCKF0
I/O Synchronous serial with FIFO(SSIOF) clock
input/output pin.
I Synchronous serial with FIFO(SSIOF) data input
pin.
O Synchronous serial with FIFO(SSIOF) data output
pin.
I/O Synchronous serial with FIFO(SSIOF) select
input/output pin.
P22,P36,P46,P56
3rd
—
P21,P35,P45,P55
3rd
—
P20,P34,P44,P54
3rd
—
P23,P37,P47,P57
3rd
L
P02,P03,P22,P23
P32,P33,P36,P37,
P42,P43,P46,P47
P52,P53,P56,P57
P42,P43,P46,P47,
P52,P53,P56,P57
4th
—
1st
—
SINF0
SOUTF0
SSF0
FTM
TMOUT0-9
TMOUTA-F
TMCKI0-7
O
FTM output pin.
I
External clock input pin for FTM
RC oscillation type A/D converter
IN0
I Channel 0 oscillation input pin.
P00
2nd
—
P01
CS0
O
Channel 0 reference capacitor connection pin.
2nd
—
RS0
O
Reference resistor connection pin of Channel 0.
P03
2nd
—
RT0
O
P04
2nd
RCT0
O
P02
2nd
RCM
O
Resistor sensor connection pin of Channel 0 for
measurement.
Resistor/capacitor sensor connection pin of
Channel 0 for measurement.
RC oscillation monitor pin.
P05
2nd
—
IN1
I
Oscillation input pin of Channel 1.
P20
2nd
—
CS1
O
Reference capacitor connection pin of Channel 1.
P21
2nd
—
RS1
O
Reference resistor connection pin of Channel 1.
P22
2nd
—
O
Resistor sensor connection pin for measurement
of Channel 1.
P23
2nd
RT1
—
—
—
11/35
FEDL620Q504H-02
ML620Q503H/Q504H
Pin name
I/O
Description
LSI pin name
Pin mode
Logic
VREF
—
—
P34,P35,P36,P37,
P20,P21,P22,P23,
P00,P01,P02,P03
1st
Comparator0 Non-inverted input pin.
P30
1st
—
P31
1st
—
Successive approximation type A/D converter
VREF
I Reference voltage input pin for successive
approximation type A/D converter.
Channel 0 analog input for successive
AIN0-11
I approximation type A/D converter.
Analog comparator
CMP0P
I
—
CMP0M
I
Comparator0 Inverted input pin.
CMP1P
I
Comparator1 Non-inverted input pin.
P32
1st
—
CMP1M
I
Comparator1 Inverted input pin.
P33
1st
—
TEST0
—
—
—
—
For testing
TEST0
TEST1_N
Power supply
VSS
I/O Input/output pin for testing. A pull-down resistor is
internally connected.
I Input pin for testing. A pull-up resistor is internally
connected.
TEST1_N
—
Negative power supply pin.
VSS
—
—
VDD
—
—
VDDL
—
—
VDDX
—
—
VDD
—
Positive power supply pin.
VDDL
—
VDDX
—
Positive power supply pin (internally generated)
for internal logic. Capacitors CL0 and CL1 are
connected between this pin and VSS.
Positive power supply pin (internally generated)
for low-speed oscillation. Capacitor CX1 is
connected between this pin and VSS.
12/35
FEDL620Q504H-02
ML620Q503H/Q504H
TERMINATION OF UNUSED PINS
Table 1 shows methods of terminating the unused pins.
Table 1
Pin
RESET_N
TEST0
TEST1_N
VREF
P00 to P05
PXT0 to PXT1
P10 to P11
P20 to P23
P30 to P37
P40 to P47
P50 to P57
Termination of Unused Pins
Recommended pin termination
Connect to VDD
open
Connect to VDD
Connect to VDD
open
open
open
open
open
open
open
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance
inputs and left open, the supply current may become excessively large. Therefore, it is recommended to
configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
13/35
FEDL620Q504H-02
ML620Q503H/Q504H
ELECTRIC CHARACTERISTICS
Absolute Maximum Ratings
(VSS=0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta=25°C
-0.3 to +6.0
V
Power supply voltage 2
VDDL
Ta=25°C
-0.3 to +2.0
V
Power supply voltage 3
VDDX
Ta=25°C
-0.3 to +2.0
V
Input voltage
VIN
Ta=25°C
-0.3 to VDD+0.3
V
Output voltage
VOUT
Ta=25°C
-0.3 to VDD+0.3
V
Output current 1
IOUT1
Port 0 to 2 Ta=25°C
-12 to +11
mA
Output current 2
IOUT2
Port 3 to 5 Ta=25°C
-12 to +20
mA
Power dissipation
PD
Ta=25°C
0.9
W
Storage temperature
TSTG
―
-55 to +150
°C
14/35
FEDL620Q504H-02
ML620Q503H/Q504H
Recommended Operating Conditions
(VSS=0V)
Parameter
Symbol
Condition
Range
Unit
Operating temperature
(Ambience)
TOP
―
-40 to +85
°C
Operating voltage
VDD
―
1.8 to 5.5
V
Reference voltage
VREF
―
1.8 to VDD
V
fOP
―
30k to 16.8M
Hz
fEXTL
―
30k to 36k
Hz
fEXTH
―
2M to 16M
Hz
fXTL
―
32.768k
Hz
Operating frequency
（CPU）
Low-speed
external clock input
High-speed
external clock input
Low speed crystal
oscillation frequency
Low speed crystal
oscillation external
capacitor 1
Low speed crystal
oscillation external
capacitor 2
*1
Low speed crystal
oscillation external
capacitor 3
High speed Crystal/
Ceramic oscillation
frequency
High speed crystal
oscillation external
capacitor
CDL
CGL
CDL
CGL
CDL
CGL
fXTH
CDH
CGH
CDH
Using VT-200-FL(from SII）
Using DT-26(from Daishinku)
Using VT-200-F(from SII）
6.8 to 12
6.8 to 12
12 to 16
12 to 16
12 to 22
12 to 22
pF
pF
pF
―
16M
Hz
Using NX8045GB
(from Nihon Denpa Kogyo)
12 to 20
12 to 20
pF
Using FCSTCE16M0V53
(from Murata manufacturing)
Build in CL type
0 to 5
0 to 5
pF
Ceramic oscillation
External capacitor
CGH
VDDL external capacitor
*2
CL
ESR ≦ 500mΩ
2.2 ± 30%
μF
VDDX external capacitor
CX
―
0.33 ± 30%
μF
*1：Please use this crystal except DEEPHALT mode because this LSI may not be functioning at DEEPHALT mode with the crystal.
Please evaluate the matching when other crystal oscillator/ ceramic oscillator is used.
*2：Please evaluate on user’s conditions, put on CL0( = 0.1uF) if necessary.
See the application note; “Precautions for MCU board design” for details, when designing MCU board.
15/35
FEDL620Q504H-02
ML620Q503H/Q504H
Operating Conditions of Flash Memory
Condition
Range
(VSS= 0V)
Unit
Data area : write/erase
-40 to +85
°C
Program area : write/erase
0 to +40
°C
VDD
Write/erase
1.8 to 5.5
V
CEPD
Data area (1,024B x 2)
10,000
times
CEPP
Program area
100
times
Parameter
Symbol
Operating temperature
(Ambience)
TOP
Operating voltage
Write time
Erase unit
―
Block erase
Program area
8
Data area
2
KB
Sector erase
1
KB
Erase time(Maximum)
―
Block erase/Sector erase
100
ms
Write unit
―
―
1 word (2 byte)
―
16/35
FEDL620Q504H-02
ML620Q503H/Q504H
AC characteristics (Oscillation)
Parameter
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C , unless otherwise specified)
Rating
Measuring
Symbol
Condition
Unit
circuit
Max.
Min.
Typ.
Low speed crystal
oscillation start time
TXTL
―
―
―
2
s
High speed crystal
oscillation start time
TXTH
―
―
―
20
ms
Ta=25°C
typ
-1.5%
32.768
typ
+1.5%
Ta=-40 ~
85°C
typ
-5%
32.768
typ
+5%
Ta=25°C
typ
-1%
16
typ
+1%
Ta=-40 to
85°C
typ
-5%
16
typ
+5%
Low speed built-in RC
*1*2
oscillation frequency
High speed build-in RC
*1*2
oscillation frequency
fLCR
fHCR
kHz
1
MHz
*1 : Mean value of 1024 cycle.
*2 : Guarantee value at the time of the shipment.
17/35
FEDL620Q504H-02
ML620Q503H/Q504H
DC Characteristics (IDD)
Parameter
Symbol
Power
consumption 1
IDD1
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
Typ. Max.
Max.
circuit
Min.
CPU is Stopped
Low/High-speed oscillation is
stopped
(5.5V)
Ta=25°C
–
0.25
0.8
1.3
Ta=-40 to 85°C
–
–
15
18
–
0.45
1.3
1.6
DEEP-HALT mode *2*4
Ta=25°C
(LBTC function)
Low-speed crystal oscillating
(32.768kHz)
Ta=-40 to 85°C
High-speed oscillation is stopped.
HALT mode *2*4
Ta=25°C
(LTBC function)
Low-speed crystal oscillating
(32.768kHz)
Ta=-40 to 85°C
High speed oscillation is stopped.
Power
consumption 2
IDD2
Power
consumption 3
IDD3
Power
consumption 4
IDD4
CPU Low-speed *1*4
Ta=25°C
Low-speed built-in CR oscillating
High speed oscillation is stopped. Ta=-40 to 85°C
Power
consumption 5
IDD5
CPU High-speed(16MHz) *1*4
High-speed Built-in CR oscillating
IDD6
CPU High-speed(16MHz) *1*3*4
High speed crystal oscillating
(16MHz)
Power
consumption 6
(3.0V) (3.6V)
μA
μA
–
–
15
18
–
2
2.7
3.0
–
–
18
19
–
10
12
13
–
–
25
28
Ta=25°C
–
4
5.5
5.5
Ta=-40 to 85°C
–
–
6
6
Ta=25°C
–
6
7.5
9.4
Ta=-40 to 85°C
–
–
8
9.9
μA
1
μA
mA
mA
1
* ：at CPU activity rate =100%（No HALT state）
2
* : using 32.768KHz crystal oscillator VT-200-FL (from SII)(CGL/CDL＝12pF)
using 32.768KHz crystal oscillator DT-26(from Daishinku)(CGL/CDL＝12pF）
3
* : using NX8045GB(from Nihon denpa kogyo) (CGH/CDH＝16pF)
4
* : BLKCON0~BLKCON5 valid bits are all “1”.
18/35
FEDL620Q504H-02
ML620Q503H/Q504H
DC Characteristics (VLS)
Parameter
Symbol
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
*1
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
vlscon = 3H
VLS judge
voltage
(VDD=fall)
VVLS Hysteresis
width
(VDD=rise)
VVLS
Parameter
Symbol
LLD judge
Voltage
VLLR
1.898
1.998
vlscon = 4H
1.900
2.000
2.100
vlscon = 5H
1.993
2.093
2.193
vlscon = 6H
2.096
2.196
2.296
vlscon = 7H
2.209
2.309
2.409
vlscon = 8H
2.309
2.409
2.509
vlscon = 9H
2.505
2.605
2.705
vlscon = AH
2.700
2.800
2.900
vlscon = BH
2.968
3.068
3.168
vlscon = CH
3.294
3.394
3.494
vlscon = DH
3.697
3.797
3.897
vlscon = EH
4.126
4.226
4.326
vlscon = FH
4.567
4.667
4.767
VVLS
VVLS
VVLS
X
X
–
HVLS
DC characteristics (LLD)
1.798
1.8%
3.8%
X
6.3%
V
1
V
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Max.
Min.
Typ.
―
1.60
1.80
2.00
V
1
DC characteristics (Analog comparator)
Parameter
Common input
voltage range
Input offset
voltage
Comparator
judge time
Symbol
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
VCMPIN
―
0.2
―
VDD
-0.2
V
VCMPOF
―
-30
―
30
mV
TCMP
CMPP- CMPM =40mV
―
―
2
μs
1
19/35
FEDL620Q504H-02
ML620Q503H/Q504H
DC characteristics (VOHL, IOHL)
Parameter
Output voltage 1
( P00-P05,
P10-P11
P20-P23,
P30-P37
P40-P47,
P50-P57)
Output voltage
2
(P40,P41,
P52, P53)
(LED mode
is selected)
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Symbol
Condition
Unit
circuit
Min.
Typ. Max.
VOH1
VOL1
VOL2
Output voltage 3
(P30,P31, P34, P35,
P40, P41, P44, P45,
P50, P51, P54, P55)
Output leak 2
(P10-P11)
1.8V ≤ VDD ≤ 3.6V
IOH=-1.0mA
VDD
-0.5
–
–
3.6V < VDD ≤ 5.5V
IOL=+5.0mA
–
–
0.6
1.8V ≤ VDD ≤ 3.6V
IOL=+0.5mA
–
–
0.4
–
–
0.4
–
–
0.6
–
–
0.4
–
–
0.4
3.6V < VDD ≤ 5.5V
IOL=+5.0mA
2.7V ≤ VDD ≤ 3.6V
IOL=+5.0mA
1.8V ≤ VDD < 2.7V
IOL=+2.0mA
2
IOL3= +2mA(I Cspec)
(VDD < 2V)
–
–
VDD
×0.2
IOOH1
VOH=VDD (at high
impedance)
–
–
+1
-1
–
–
–
–
+2
-2
–
–
2
P30-P37, P40-P47,
P50-P57)
–
VOL4
(P30, P31, P34, P35,
(P00-P05,P20-P23,
–
IOL3= +3mA (I Cspec)
(VDD ≥ 2V)
(I C mode is
selected)
Output voltage 4
(I C mode is
selected)
Output leak 1
VDD
-0.6
VOL3
2
P40, P41, P44, P45,
P50, P51, P54, P55)
3.6V < VDD ≤ 5.5V
IOH=-2.5mA
2
IOOL1 VOL=VSS (at high impedance)
IOOH2
VOH=VDD (at high
impedance)
IOOL2 VOL=VSS (at high impedance)
V
2
μA
3
20/35
FEDL620Q504H-02
ML620Q503H/Q504H
DC characteristics (IIHL)
Parameter
Input current 1
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
*1
Rating
Measuring
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
IIH1
VIH1=VDD
―
―
1
IIL1
VIL1=VSS
-900
-300
-20
Input current 2
IIH2
VIH2=VDD
20
300
900
(TEST0)
IIL2
VIL2=VSS
-1
―
―
Input current 3
(PXT0-PXT1,
IIH3
VIH3=VDD (at pull down)
1
15
200
IIL3
-200
-15
-1
―
―
1
-1
―
―
IIH4
VIL3=VSS (at pull up)
VIH3=VDD
(at high impedance)
VIL3=VSS
(at high impedance)
VIH4=VDD (at pull down)
1
15
200
IIL4
VIL4=VSS (at pull up)
-200
-15
-1
―
―
2
-2
―
―
(RESET_N,
TEST1_N)
P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57)
Input current 4
(P10-P11)
IIH3Z
IIL3Z
VIH4=VDD
(at high impedance)
VIL4=VSS
IIL4Z
(at high impedance)
1
* : typ.rating is Ta=25°C , VDD=3.0V
IIH4Z
μA
4
DC characteristics (VIHL)
Parameter
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Symbol
Condition
unit
circuit
Min.
Typ.
Max.
Input voltage 1
(RESET_N,
TEST0,
TEST1_N,
PXT0-PXT1,
P00-P05,
P10-P11,
P20-P23,
P30-P37,
P40-P47,
P50-P57)
VIH1
―
0.7
×VDD
―
VDD
VIL1
―
0
―
0.3
×VDD
CIN
f=10kHz
Vrms=50mV
Ta=25°C
―
―
10
V
5
pF
―
Input terminal
capacitance
(RESET_N,
TEST0,
TEST1_N,
PXT0-PXT1,,
P00-P05,
P10-P11,
P20-P23,
P30-P37,
P40-P47,
P50-P57)
21/35
FEDL620Q504H-02
ML620Q503H/Q504H
Measuring circuit
Measuring circuit 1
CGL
CDL
CGH
XT0
32.768kHz XT1
Crystal
Oscillator
OSC0
CDH
16MHz
Crystal
Oscillator
OSC1
VDD VREF
VDDL
VDDX
A
CV
CX
CL
32.768kHz crystal oscillator : DT-26 (from Daishinku)
16MHz crystal oscillator
: NX8045GB (from Nihon denpa kogyo)
VSS
CV
CL
CX
CGL
CDL
CGH
CDH
: 1.0μF
: 2.2μF
: 0.33μF
: 12pF
: 12pF
: 16pF
: 16pF
Measuring circuit 2
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD
VDDL
VREF
VDDX
V
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
22/35
FEDL620Q504H-02
ML620Q503H/Q504H
Measuring circuit 3
(*2)
Input pins
Output pins
VIH
(*1)
VIL
VDD
VDDL
VREF
VDDX
A
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
Measuring circuit 4
Input pins
A
Output pins
(*3)
VDD
VDDL
VREF
VDDX
VSS
(*3) Measured at the specified output pins.
23/35
FEDL620Q504H-02
ML620Q503H/Q504H
Measuring circuit 5
VDD
VDDL
VREF
VDDX
Waveform monitoring
VIL
Input pins
(*1)
Output pins
VIH
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
24/35
FEDL620Q504H-02
ML620Q503H/Q504H
AC characteristics (external interrupt)
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
External interrupt disable
period
tNUL
Condition
Interruput enable (MIE=1)
CPU : NOP operation
Rating
Min.
Typ.
Max.
2.5 x
sysclk
―
3.5 x
sysclk
unit
φ
EXI0-7
(Rising-edge interrupt)
tNUL
(Falling-edge interrupt)
tNUL
EXI0-7
EXI0-7
(Both-edge interrupt)
tNUL
25/35
FEDL620Q504H-02
ML620Q503H/Q504H
AC characteristics (synchronous serial port)
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
SCK input cycle
(slave mode)
tSCYC
SCK output cycle
(master mode)
tSCYC
Rating
Condition
unit
Min.
Typ.
Max.
High-speed oscillation
is not active
10
―
―
μs
High speed oscillation is
active
500
―
―
ns
―
―
SCK*
―
s
High-speed oscillation
is not active
4
―
―
μs
High speed oscillation is
active
200
―
―
ns
1
SCK input pulse width
(slave mode)
tSW
SCK output pulse
width
(master mode)
tSW
―
tSCYC
×0.4
tSCYC
×0.5
tSCYC
×0.6
s
SOUT output delay
time
(slave mode)
tSD
―
―
―
180
ns
SOUT output delay
time
(master mode)
tSD
―
―
―
80
ns
SIN input
Setup time
(slave mode)
tSS
―
50
―
―
ns
SINinput
Hold time
tSH
―
50
―
―
ns
*1：The clock period which is selected by the below registers(min:250ns@reguraly, min:500ns@P02,
P22 is used)
In case of SSIO : S0CK2-0 of serial port 0 mode register(SIO0MOD).
In case of SSIOF : SF0BR9-0 of SIOF0 port register(SF0BRR)
tSCYC
tSW
tSW
SCK0
SCKF0
tSD
tSD
SOUT0
SOUTF0
tSS
tSH
SIN0
SINF0
26/35
FEDL620Q504H-02
ML620Q503H/Q504H
AC characteristics（I2C Bus interface : Standard mode 100kHz）
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
Condition
SCL clock frequency
SCL hold time
(Start/restart condition)
SCL”L” level time
fSCL
SCL”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SCL setup time
(stop condition)
Bus-free time
Rating
unit
Min.
Typ.
Max.
―
0
―
100
kHz
tHD:STA
―
4.0
―
―
μs
tLOW
―
4.7
―
―
μs
tHIGH
―
4.0
―
―
μs
tSU:STA
―
4.7
―
―
μs
tHD:DAT
―
0
―
3.45
μs
tSU:DAT
―
0.25
―
―
μs
tSU:STO
―
4.0
―
―
μs
tBUF
―
4.7
―
―
μs
AC characteristics（I2C bus interface : fast mode 400kHz）
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
Condition
SCL clock frequency
fSCL
SCLhold time
(start/restart condition)
Rateing
unit
Min.
Typ.
Max.
―
0
―
400
kHz
tHD:STA
―
0.6
―
―
μs
SCL”L” level time
tLOW
―
1.3
―
―
μs
SCL”H” level time
tHIGH
―
0.6
―
―
μs
SCL setup time
(restart condition)
tSU:STA
―
0.6
―
―
μs
SDA hold time
tHD:DAT
―
0
―
0.9
μs
SDA setup time
tSU:DAT
―
0.1
―
―
μs
SCLsetup time
(stop condition)
tSU:STO
―
0.6
―
―
μs
Bus-free time
tBUF
―
1.3
―
―
μs
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
27/35
FEDL620Q504H-02
ML620Q503H/Q504H
AC characteristics（RC Oscillation A/D Converter）
(VDD=1.8~5.5V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Rating
Condition
unit
Min.
Typ.
Max.
Parameter
Symbol
Resister for oscillation
RS0,RS1,RT
0,RT0-1,RT1
–
1
–
400
kΩ
fOSC1_0
Resister for oscillation
=1kΩ
–
528
–
kHz
fOSC2_0
Resister for oscillation
=10kΩ
–
59
–
kHz
fOSC3_0
Resister for oscillation
=100kΩ
–
5.9
–
kHz
Kf1_0
RT0, RT0-1, RT1=1kΩ
8.225
8.94
9.655
–
Kf2_0
RT0, RT0-1, RT1=10kΩ
0.99
1
1.01
–
Kf3_0
RT0, RT0-1, RT1=100kΩ
0.093
0.101
0.109
–
fOSC1_0
Resister for oscillation
=1kΩ
–
528
–
kHz
fOSC2_0
Resister for oscillation
=10kΩ
–
59
–
kHz
fOSC3_0
Resister for oscillation
=100kΩ
–
5.9
–
kHz
Kf1_0
RT0, RT0-1, RT1=1kΩ
8.225
8.94
9.655
–
Kf2_0
RT0, RT0-1, RT1=10kΩ
0.99
1
1.01
–
Kf3_0
RT0, RT0-1, RT1=100kΩ
0.093
0.101
0.109
–
Oscillation frequency
VDD = 3.0V
CVR=820pF
CS=560pF
RAMD0=0
RS to RT oscillation
1
frequency ratio *
VDD = 3.0V
CVR=820pF
CS=560pF
RAMD0=0
Oscillation frequency
VDD = 5.0V
CVR=820pF
CS=560pF
RAMD0=1
RS to RT oscillation
1
frequency ratio *
VDD = 5.0V
CVR=820pF
CS=560pF
RAMD0=1
1
* ：Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
Kfx =
fOSCX(RT0-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
,
fOSCX(RT0-1-CS0
oscillation)
fOSCX(RS0-CS0 oscillation)
fOSCX(RT1-CS1 oscillation)
,
fOSCX(RS1-CS1 oscillation)
28/35
FEDL620Q504H-02
ML620Q503H/Q504H
Measuring circuit
IN0
VIH
CS0 RCT0
RS0 RT0
VIL
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ
RS0, RS1: 10kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN1 CS1 RS1 RT1
RCM
VDD
CV
RT1
RS1
CS1
RT0
RS0
RT0-1
CVR1
Input pins
(*1)
CT0
CS0
CVR0
VDDL
VDDX
VREF
Measure frequency
(fOSCX)
VSS
CL1 CL0 CX
(*1) Input logic circuit to determine the specified measuring conditions.
【Note】
・Please have the shortest layout for the common node (wiring patterns which are connected to the external
capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1
and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not
have signals which may be a source of noise around the node.
・When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please shield the
signal by VSS(GND) .
・Please make wiring to components (capacitor, resistor and etc.) necessary for objective measurement. Wiring to
reserved components may affect to the A/D conversion operation by noise the components itself may have.
29/35
FEDL620Q504H-02
ML620Q503H/Q504H
Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
Resolution
n
Integral non-linearity
error
INL
Differential
non-linearity error
DNL
Zero-scale error
VOFF
Rating
Condition
Min.
Typ.
Max.
―
―
12
―
2.7V ≦ VREF ≦ 5.5V
2.2V ≦ VREF < 2.7V
1.8V ≦ VREF < 2.2V
(using Low-speed clock)
2.7V ≦ VREF ≦ 5.5V
2.2V ≦ VREF < 2.7V
1.8V ≦ VREF < 2.2V
(using Low-speed clock)
-4
-6
―
―
+4
+6
-10
―
+10
-3
-5
―
―
+3
+5
-9
―
+9
2.2V ≦ VREF ≦ 5.5V
-6
―
+6
1.8V ≦ VREF < 2.2V
(using Low-speed clock)
-10
―
+10
2.2V ≦ VREF ≦ 5.5V
-6
―
+6
Unit
bit
LSB
Full-scale error
FSE
1.8V ≦ VREF < 2.2V
(using Low-speed clock)
-10
―
+10
Input impidance
RI
―
―
―
5k
Ω
Reference voltage
VREF
―
1.8
―
VDD
V
tCONV
Using High-speed clock(max.
4MHz)
―
170
―
Using Low-speed clock
―
16
―
Conversion time
clk
Measuring circuit
VDD
Reference
Voltage
VREF
1μF
A
10μF
-
RI≦5kΩ
AIN
+
0.47μF
VSS
30/35
FEDL620Q504H-02
ML620Q503H/Q504H
Reset characteristics
(VDD=1.8 to 5.5V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measurin
Symbol
Condition
Unit
g circuit
Max.
Min.
Typ.
Parameter
Reset pulse width
Reset noise
elimination
pulse width
Power-on reset
activation
power rise time
PRST
–
200
–
–
μs
PNRST
–
–
–
0.3
μs
TPOR
–
–
–
10
ms
1
0.9*VDD
VDD
0.3*VDD
RESET_N
0.3*VDD
PRST
0.3*VDD
PRST
External reset sequence
0.9*VDD
VDD
0.1*VDD
TPOR
Power on reset sequence
Power-on and shutdown Procedures
In case of power-on or shutdown of VDD, the procedures and constraints are shown as following.
0.9*VDD
VDD
0.1*VDD
30mV or less
(VSS = 0)
TPOR
VDDL
100mV or less
(VSS = 0)
【Note】
・If VDDL level is 100mV or more over, reset the IC by RESET_N pin after power-on.
・TPOR is the value when VDD slope is liner. If VDD slope is not liner in your system, use RESET_N or contact us.
31/35
FEDL620Q504H-02
ML620Q503H/Q504H
APPLICATION CIRCUIT EXAMPLE
3.3V
VDD
CV
TEST1_N
TEST0
P00/IN0
RESET_N
VDDX
CX1
CL1
RD
RT0
P02/RCT0
P05/RCM
P20/IN1
XH
16MHz
Xtal
P21/CS1
P11/OSC1
CS1
RS1
P22/RS1
CVR1
RT1
P23/RT1
CGL
CVR0
RS0
P04/RT0
P10/OSC0
CDH
CS0
P03/RS0
Q504H
Vss
CGH
CDL
ML620Q503H/
VDDL
CL0
P01/CS0
PXT0/XT0
XL
32.768KHz
Xtal
PXT1/XT1
VREF
CAV
P33
/MD0
P41 P32 P51 P50
/LED (Output) /SCL /SDA
P40
/LED
Buzzer
LED
WP SCL SDA
I C EEPROM
A0
CV
CL1
CX1
CGL
CGH
RD
CAV
CS0, CS1
RT0, RT1
XH
XL
Vcc
2
A1
A2
Vss
: 1uF*
: 2.2uF
CL0
: 0.33uF
: 12~16pF*
CDL
: 12~20pF*
CDH
: 0Ω*
: 1uF*
RS0, RS1
: 560 pF
CVR0, CVR1
: Thermistor (103AT/Semitec)
: NX8045GB/16.000MHz, Nihon Denpa Kogyo
: DT-26, Daishinku
: open*
: 12~16pF*
: 12~20pF*
: 10 KΩ
: 820 pF
*: Make a decision the parameters after evaluating on an user’s conditions when designing circuits for mass production.
32/35
FEDL620Q504H-02
ML620Q503H/Q504H
PACKAGE DIMENSIONS
ML620Q503H/Q504H
Package Dimensions
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package
name, pin number, package code and desired mounting conditions(reflow method, temperature and times).
33/35
FEDL620Q504H-02
ML620Q503H/Q504H
REVISION HISTORY
Document No.
FEDL620Q504H-01
FEDL620Q504H-02
Date
Aug.31.2015
May.20.2020
Page
Previous
Current
Edition
Edition
–
4
13,32
–
4
13,32
15
15
31
31
17,31
31
33
33
Description
Final Edition issued
Updated shipment
Updated about RESET_N and TEST1_N
pins
Added comment in recommended
operating conditions.
Corrected “Power-on and shutdown
Procedures”
Changed placement of reset
characteristics.
Added note.
Updated package dimensions
34/35
FEDL620Q504H-02
ML620Q503H/Q504H
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,
semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent
personal injury or fire arising from failure, please take safety measures such as complying with the
derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and
fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the
use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided
only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken
into account when designing circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and
examples of application circuits for the Products. No license, expressly or implied, is granted hereby under
any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the
information contained in this document; therefore LAPIS Semiconductor shall have no responsibility
whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such
technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication,
consumer systems, gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please
contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships,
trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical
systems, servers, solar cells, and power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment,
nuclear power control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance
with the recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS
Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the
RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office.
LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance
with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must
abide by the procedures and provisions stipulated in all applicable export laws and regulations, including
without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade
Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Semiconductor.
Copyright
2015-2020 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
35/35
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