74ALVCH16841DGGY

74ALVCH16841 20-bit bus interface D-type latch; 3-state Rev. 3 — 12 September 2018 Product data sheet 1. General description The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits • • • • • • • • • • • Wide supply voltage range of 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at VCC = 3.0 V MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimize noise and ground bounce All data inputs have bushold Output drive capability 50 Ω transmission lines at 85 °C 3-state non-inverting outputs for bus oriented applications Complies with JEDEC standards: • JESD8-5 (2.3 V to 2.7 V) • JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V • CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74ALVCH16841DGG −40 °C to +85 °C TSSOP56 Description Version plastic thin shrink small outline package; 56 leads; SOT364-1 body width 6.1 mm 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 4. Functional diagram 1OE 1 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 1OE 2OE 1LE 28 55 2 54 3 52 5 2OE 1Q0 1Q1 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 56 2LE 1Q2 1D0 1Q3 1D1 1Q4 1D2 1Q5 1D3 1Q6 1D4 1Q7 1D5 1Q8 1D6 1Q9 1D7 2Q0 1D8 2Q1 1D9 2Q2 2D0 2Q3 2D1 2Q4 2D2 2Q5 2D3 2Q6 2D4 2Q7 2D5 2Q8 2D6 2Q9 2D7 2D8 29 2D9 1LE Fig. 1. 2LE 29 55 54 C1 EN4 C3 1D 2 Q 2 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 41 3D 4 15 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 aaa-029041 Fig. 2. D 28 EN2 aaa-029040 Logic symbol 1D0 1 56 1Q0 2D0 IEC logic symbol D LATCH 1 LE Q 2Q0 LATCH 11 LE 1LE 2LE 1OE 2OE to 9 other channels to 9 other channels aaa-029042 Fig. 3. Logic diagram VCC data input to internal circuit mna004 Fig. 4. Bushold circuit 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 2 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 5. Pinning information 5.1. Pinning 74ALVCH16841 1OE 1 56 1LE 1Q0 2 55 1D0 1Q1 3 54 1D1 GND 4 53 GND 1Q2 5 52 1D2 1Q3 6 51 1D3 VCC 7 50 VCC 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q9 14 43 1D9 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2Q9 27 30 2D9 2OE 28 29 2LE aaa-029043 Fig. 5. Pin configuration SOT364-1 (TSSOP56) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8, 1D9 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8, 2D9 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8, 1Q9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 data output 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8, 2Q9 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output 1OE, 2OE 1, 28 output enable inputs (active-LOW) 1LE, 2LE 56, 29 latch enable inputs GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 3 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Outputs Inputs nOE nLE nDn nQn L H L L L H H H L L X Q0 H X X Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min Max Unit -0.5 +4.6 V For control pins [1] -0.5 +4.6 V For data inputs [1] -0.5 VCC + 0.5 V [1] -0.5 VCC + 0.5 V VO output voltage IIK input clamping current VI < 0 V -50 - mA IOK output clamping current VO > VCC or VO < 0 V - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 600 mW [1] [2] Tamb = -40 °C to +85 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage Min Max Unit for maximum speed performance; 30 pF output load 2.3 2.7 V for maximum speed performance; 50 pF output load 3.0 3.6 V VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature -40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V - 20 ns/V VCC = 3.0 V to 3.6 V - 10 ns/V 74ALVCH16841 Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 4 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 °C to +85 °C Symbol Parameter Conditions Min Typ[1] Max VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V VIL VOH VOL LOW-level output voltage Unit VI = VIH or VIL II input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 μA IOZ OFF-state output current VCC = 2.3 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V 45 - - μA VCC = 3.0 V; VI = 0.8 V 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V -500 - - μA CI input capacitance - 5.0 - pF IBHH [1] All typical values are measured at Tamb = 25 °C. 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 5 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10; Tamb = -40 °C to +85 °C Symbol Parameter Conditions tpd nDn to nQn; see Fig. 6 propagation delay Min Typ[1] Max Unit VCC = 2.3 V to 2.7 V 1.0 2.5 5.0 ns VCC = 2.7 V 1.0 2.6 4.7 ns VCC = 3.0 V to 3.6 V 1.0 2.4 3.9 ns VCC = 2.3 V to 2.7 V 1.0 2.5 5.6 ns VCC = 2.7 V 1.0 2.6 5.1 ns VCC = 3.0 V to 3.6 V 1.0 2.4 4.3 ns VCC = 2.3 V to 2.7 V 1.0 2.7 6.2 ns VCC = 2.7 V 1.0 3.1 6.0 ns 1.0 2.3 4.9 ns VCC = 2.3 V to 2.7 V 1.1 2.2 5.3 ns VCC = 2.7 V 1.3 3.1 4.3 ns VCC = 3.0 V to 3.6 V 1.3 2.9 4.1 ns VCC = 2.3 V to 2.7 V 1.3 0.1 - ns VCC = 2.7 V 1.1 0.1 - ns VCC = 3.0 V to 3.6 V 1.0 0.6 - ns VCC = 2.3 V to 2.7 V 1.4 0.3 - ns VCC = 2.7 V 1.7 0.2 - ns VCC = 3.0 V to 3.6 V 1.4 0.2 - ns 3.3 1.5 - ns outputs enabled - 19 - pF outputs disabled - 3 - pF [2] nLE to nQn; see Fig. 7 ten enable time nOE to nQn; see Fig. 9 [3] VCC = 3.0 V to 3.6 V tdis disable time tsu set-up time th hold time nOE to nQn; see Fig. 9 nDn to nLE; see Fig. 8 nDn to nLE; see Fig. 8 tW pulse width nLE HIGH; VCC = 2.3 V to 3.6 V; see Fig. 7 CPD power dissipation capacitance per latch; VI = GND to VCC [1] [2] [3] [4] [5] [4] [5] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V. Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑ (CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; 2 ∑(CL × VCC × fo) = sum of outputs. 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 6 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 10.1. Waveforms and test circuit VI VI VM nDn input nLE input VM GND GND tPHL tPLH nQn output VM tPLH VM VOL 001aam011 001aam012 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. VM VM VM VOL VM tW tPHL VOH VOH nQn output VM Fig. 7. Input (nDn) to output (nQn) propagation delays Latch enable input (nLE) to data output (nQn) propagation delays and pulse width (nLE) VI nDn input VM GND th th tsu VI nLE input tsu VM GND 001aam013 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 8. Data setup and hold times for input (nDn) to input (nLE) VI nOE input VM VM GND tPLZ nQn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPZH tPHZ nQn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aal795 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 9. 3-State enable and disable times 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 7 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state Table 8. Measurement points Input Output VCC VI VM VM Vx Vy < 2.3 V VCC 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V VCC 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V VI negative pulse tW 90 % VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Fig. 10. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VCC VI tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL < 2.3 V VCC ≤ 2.0 ns 500 Ω 30 pF GND 2 × VCC open 2.3 V to 2.7 V VCC ≤ 2.0 ns 500 Ω 30 pF GND 2 × VCC open 2.7 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 8 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 11. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 11. Package outline SOT364-1 (TSSOP56) 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 9 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16841 v.3 20180912 Product data sheet - 74ALVCH16841 v.2 Modifications: • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74ALVCH16841 v.2 19980727 Product specification - 74ALVCH16841 v.1 19980727 Product specification - 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 74ALVCH16841 v.1 © Nexperia B.V. 2018. All rights reserved 10 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 11 / 12 74ALVCH16841 Nexperia 20-bit bus interface D-type latch; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline.......................................................... 9 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 12 September 2018 74ALVCH16841 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2018 © Nexperia B.V. 2018. All rights reserved 12 / 12