74ALVT16373DGG,118

74ALVT16373 16-bit transparent D-type latch; 3-state Rev. 4 — 2 February 2018 1 Product data sheet General description The 74ALVT16373 is a high-performance BiCMOS product designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility up to 5 V. This device is a 16-bit transparent D-type latch with non-inverting 3-state bus compatible outputs. The device can be used as two 8-bit latches or one 16-bit latch. When latch enable (nLE) input is HIGH, the nQn outputs follow the date (nDn) inputs. When latch enable is taken LOW, the nQn outputs are latched at the levels of the D inputs one setup time prior to the HIGH-to-LOW transition. 2 Features and benefits • • • • • • • • • • • • • 3 16-bit transparent latch 5 V I/O compatible 3-state buffers Output capability: +64 mA/–32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power-up reset Power-up 3-State No bus current loading when output is tied to 5 V bus Latch-up protection: – JESD 17: exceeds 500 mA ESD protection: – MIL STD 883 method 3015: exceeds 2000 V – MM exceeds 200 V Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVT16373DL -40 °C to +85 °C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 74ALVT16373DGG -40 °C to +85 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 4 Functional diagram 1 1OE 24 1LE 1OE 2OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 1D4 1Q4 8 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 36 2D0 2Q0 13 35 2D1 2Q1 14 2LE 1D0 1D1 1D2 1D3 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 2D5 2Q5 20 27 2D6 2Q6 22 26 2D7 2Q7 23 1LE 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2LE 2D7 48 25 1EN C3 24 2EN 25 C4 47 2 1 3D 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 4D 35 13 2 14 33 16 32 17 30 19 29 20 27 22 26 23 mgu768 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 mgu770 Figure 1. Logic symbol 1D0 1 48 Figure 2. IEC logic symbol D 1Q0 Q 2D0 LATCH 1 LE D 2Q0 Q LATCH 9 LE LE 1LE 2LE 1OE 2OE to 7 other channels LE to 7 other channels mgu769 Figure 3. Logic diagram 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 5 Pinning information 5.1 Pinning 74ALVT16373 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 1Q4 8 42 VCC 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 2Q4 19 31 VCC 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE aaa-028126 Figure 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 5.2 Pin description Table 2. Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data outputs 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data outputs 1OE, 2OE 1, 24 output enable inputs (active LOW) 1LE, 2LE 48, 25 latch enable inputs (active HIGH) GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 6 Functional description Table 3. Function table [1] Operating mode Inputs nOE nLE nDn Internal latches L H L L L L H H H H L ↓ l L L L ↓ h H H Hold L L X NC NC Latch register and disable outputs H L X NC Z H H nDn nDn Z enable and read register (transparent mode) latch and read register Outputs nQn [1] H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH-to-LOW LE transition; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don’t care; NC = No change; Z = high-impedance OFF-state. 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit -0.5 +4.6 V input voltage [1] -0.5 +7.0 V VO output voltage output in OFF-state or HIGH-state [1] -0.5 +7.0 V IIK input clamping current VI < 0 V -50 - mA IOK output clamping current VO < 0 V -50 - mA IO output current output in LOW-state - 128 mA output in HIGH-state -64 - mA -65 +150 °C - +150 °C VI Tstg Tj storage temperature [2] junction temperature [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 4 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V Unit Min Max Min Max 2.3 2.7 3.0 3.6 V VCC supply voltage VI input voltage 0 5.5 0 5.5 V IOH HIGH-level output current - -8 - -32 mA IOL LOW-level output current none - 8 - 32 mA current duty cycle ≤ 50 %; fi ≥ 1 kHz - 24 - 64 mA - 10 - 10 ns/V -40 +85 -40 +85 °C Δt/ΔV input transition rise and fall rate outputs enabled Tamb ambient temperature free-air 9 Static characteristics Table 6. Static characteristics At recommended operating conditions; Tamb = -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions [1] Max Unit - -0.85 -1.2 V Min Typ VCC = 2.5 V ± 0.2 V VIK input clamping voltage VIH HIGH-level input voltage 1.7 - - V VIL LOW-level input voltage - - 0.7 V VOH HIGH-level output voltage VCC - 0.2 - - V VCC = 2.3 V; IO = -8 mA 1.8 - - V VCC = 2.3 V; IO = 100 μA - 0.07 0.2 V - 0.3 0.5 V - - 0.55 V - 0.1 10 μA - 0.1 ±1 μA VCC = 2.7 V; VI = VCC - 0.1 1 μA VCC = 2.7 V; VI = 0 V - 0.1 -5 μA VOL LOW-level output voltage VCC = 2.3 V; IIK = -18 mA VCC = 2.3 V to 2.7 V; IO = -100 μA VCC = 2.3 V; IO = 24 mA VOL(pu) power-up LOW-level output VCC = 2.7 V; IO = 1 mA; voltage VI = VCC or GND [2] II input leakage current [3] all input pins VCC = 0 V or 2.7 V; VI = 5.5 V control pins VCC = 2.7 V; VI = VCC or GND [3] data pins; IOFF IBHL power-off leakage current bus hold LOW current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 μA data inputs; VCC = 2.3 V; VI = 0.7 V [4] - 90 - μA [4] - -10 - μA - 10 125 μA IBHH bus hold HIGH current data inputs; VCC = 2.3 V; VI = 1.7 V IEX external current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 5 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state Symbol Parameter Conditions IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care IOZ OFF-state output current VCC = 2.7 V; VI = VIL or VIH ICC supply current Min [5] Typ [1] Max Unit - 1 100 μA output HIGH: VO = 2.3V - 0.5 5 μA output LOW: VO = 0.5 V - 0.5 -5 μA - 0.04 0.1 mA VCC = 2.7 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - 2.3 4.5 mA [6] - 0.04 0.1 mA [7] - 0.04 0.4 mA ΔICC additional supply current per input pin; VCC = 2.3 V to 2.7 V; one input at VCC - 0.6 V; other inputs at VCC or GND CI input capacitance VI = 0 V or VCC - 3 - pF CO output capacitance Outputs disabled; VO = 0 V or 3 V - 9 - pF VCC = 3.0 V; IIK = -18 mA - -0.85 -1.2 V VCC = 3.3 V ± 0.3 V VIK input clamping voltage VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage VCC - 0.2 VCC - V VCC = 3.0 V; IO = -32 mA 2.0 2.3 - V VCC = 3.0 V; IO = 100 μA - 0.07 0.2 V VCC = 3.0 V; IO = 16 mA - 0.25 0.4 V VCC = 3.0 V; IO = 32 mA - 0.3 0.5 V - 0.4 0.55 V - - 0.55 V - 0.1 10 μA - 0.1 ±1 μA VCC = 3.6 V; VI = VCC - 0.5 1 μA VCC = 3.6 V; VI = 0 V - 0.1 -5 μA VOL LOW-level output voltage VCC = 3.3 V ± 0.3 V; IO = -100 μA VCC = 3.0 V; IO = 64 mA VOL(pu) power-up LOW-level output VCC = 3.6 V; IO = 1 mA; voltage VI = VCC or GND [2] II input leakage current [3] all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND [3] data pins IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 μA IBHL bus hold LOW current data inputs; VCC = 3 V; VI = 0.8 V 75 130 - μA IBHH bus hold HIGH current data inputs; VCC = 3 V; VI = 2.0 V IBHLO bus hold LOW overdrive current data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V [8] IBHHO bus hold HIGH overdrive current data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V [8] 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 -75 -140 - μA 500 - - μA -500 - - μA © Nexperia B.V. 2018. All rights reserved. 6 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state Symbol Parameter Conditions IEX external current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care IOZ OFF-state output current VCC = 3.6 V; VI = VIL or VIH ICC supply current Min Typ [1] Max Unit - 10 125 μA - 1 ±100 μA output HIGH: VO = 3.0V - 0.5 5 μA output LOW: VO = 0.5 V - 0.5 -5 μA - 0.04 0.1 mA [9] VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - 3.5 5 mA [6] - 0.05 0.1 mA [7] - 0.04 0.4 mA ΔICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC - 0.6 V; other inputs at VCC or GND CI input capacitance VI = 0 V or VCC - 3 - pF CO output capacitance output disabled; VO = 0 V or 3 V - 9 - pF [1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C. All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the latches after applying power. [3] Unused pins at VCC or GND. [4] Not guaranteed. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. [6] ICC with outputs disabled is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. [8] This is the bus hold overdrive current required to force the input to the opposite logic state. [9] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 7 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 10 Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; Tamb = -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions Min Typ [1] Max Unit VCC = 2.5 V ± 0.2 V tPLH LOW to HIGH propagation delay nDn to nQn; see Figure 5 1.0 2.0 3.2 ns tPHL HIGH to LOW propagation delay nDn to nQn; see Figure 5 1.0 2.4 4.2 ns tPLH LOW to HIGH propagation delay nLE to nQn; see Figure 6 1.5 2.6 4.2 ns tPHL HIGH to LOW propagation delay nLE to nQn; see Figure 6 1.5 2.8 4.5 ns tPZH OFF-state to HIGH propagation delay nOE to nQn; see Figure 7 2.0 3.5 5.5 ns tPZL OFF-state to LOW propagation delay nOE to nQn; see Figure 7 1.5 2.6 4.7 ns tPHZ HIGH to OFF-state propagation delay nOE to nQn; see Figure 7 1.5 2.7 4.5 ns tPLZ LOW to OFF-state propagation delay nOE to nQn; see Figure 7 1.0 2.0 3.5 ns tsu(H) set-up time HIGH nDn to nLE; see Figure 8 0 -0.7 - ns tsu(L) set-up time LOW nDn to nLE; see Figure 8 1.5 0.2 - ns th(H) hold time HIGH nDn to nLE; see Figure 8 0.5 -0.2 - ns th(L) hold time LOW nDn to nLE; see Figure 8 1.5 0.7 - ns tWH pulse width HIGH nLE; see Figure 6 1.5 - - ns VCC = 3.3 V ± 0.3 V tPLH LOW to HIGH propagation delay nDn to nQn; see Figure 5 0.5 1.6 2.5 ns tPHL HIGH to LOW propagation delay nDn to nQn; see Figure 5 0.5 1.8 2.9 ns tPLH LOW to HIGH propagation delay nLE to nQn; see Figure 6 1.0 2.0 3.1 ns tPHL HIGH to LOW propagation delay nLE to nQn; see Figure 6 1.0 2.3 3.3 ns tPZH OFF-state to HIGH propagation delay nOE to nQn; see Figure 7 1.5 2.3 4.0 ns tPZL OFF-state to LOW propagation delay nOE to nQn; see Figure 7 1.0 1.9 3.1 ns tPHZ HIGH to OFF-state propagation delay nOE to nQn; see Figure 7 1.5 2.9 4.5 ns tPLZ LOW to OFF-state propagation delay nOE to nQn; see Figure 7 1.5 2.3 3.7 ns tsu(H) set-up time HIGH nDn to nLE; see Figure 8 0.5 -0.2 - ns tsu(L) set-up time LOW nDn to nLE; see Figure 8 0.8 0.2 - ns th(H) hold time HIGH nDn to nLE; see Figure 8 0.8 0 - ns th(L) hold time LOW nDn to nLE; see Figure 8 1.0 0.2 - ns tWH pulse width HIGH nLE; see Figure 6 1.5 - - ns [1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C. All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C. 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 8 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 10.1 Waveforms and test circuit VI VI VM nDn input nLE input VM GND GND tPHL tPLH nQn output VM VM VOL VM tW tPHL VOH VOH nQn output VM tPLH VM VOL 001aam011 VM VM 001aam012 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 5. Input (nDn) to output (nQn) propagation delays Figure 6. Latch enable input (nLE) to data output (nQn) propagation delays and pulse width VI nOE input VM VM GND tPLZ 3.0 V or VCC output LOW-to-OFF OFF-to-LOW VOL tPZL VM VX tPHZ output HIGH-to-OFF OFF-to-HIGH tPZH VOH VY VM GND outputs enabled outputs disabled outputs enabled aaa-028124 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 7. OFF-state to HIGH or LOW and HIGH or LOW to OFF-state propagation delays VI nDn input VM GND VI nLE input th tsu th tsu VM GND 001aam013 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 8. Input (nDn) to input (nLE) data set-up and hold times 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 9 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state Table 8. Measurement points VCC Input Output VI VM VM VX VY VCC ≤ 2.7 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V VCC ≥ 3.0 V 3.0 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V VI negative pulse tW 90 % 90 % VM 10 % 0V tf tr tr tf VI positive pulse 0V VM VEXT VCC G 90 % VM VI VM 10 % DUT RT 10 % tW RL VO CL RL mna616 001aac221 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Figure 9. Test circuit for measuring switching times Table 9. Test data Input VI Load fi 3.0 V or VCC ≤ 10 MHz whichever is less 74ALVT16373 Product data sheet VEXT tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6 V or VCC x 2 open All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 10 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 11 Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3 ) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Figure 10. Package outline SOT370-1 (SSOP48) 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 11 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit max nom min mm A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Figure 11. Package outline SOT362-1 (TSSOP48) 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 12 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 12 Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge MIL Military MM Machine Model TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVT16373 v.4 20180202 Product data sheet - 74ALVT16373 v.3 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74ALVT16373 v.3 19991018 Product specification - 74ALVT16373 v.2 74ALVT16373 v.2 19980213 Product specification - 74ALVT16373 v.1 74ALVT16373 v.1 19960529 Product specification - - 74ALVT16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 13 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74ALVT16373 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 14 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74ALVT16373 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 15 / 16 74ALVT16373 Nexperia 16-bit transparent D-type latch; 3-state Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 3 Functional description ........................................4 Limiting values .................................................... 4 Recommended operating conditions ................ 5 Static characteristics .......................................... 5 Dynamic characteristics .....................................8 Waveforms and test circuit ................................ 9 Package outline .................................................11 Abbreviations .................................................... 13 Revision history ................................................ 13 Legal information .............................................. 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 2 February 2018 Document identifier: 74ALVT16373