HEF4060BT-Q100J

HEF4060B-Q100 14-stage ripple-carry binary counter/divider and oscillator Rev. 2 — 9 September 2014 Product data sheet 1. General description The HEF4060B-Q100 is a 14-stage ripple-carry binary counter/divider and oscillator. It has three oscillator terminals (RS, REXT and CEXT) and ten buffered outputs (Q3 to Q9 and Q11 to Q13). It also has an overriding asynchronous master reset input (MR). The oscillator configuration allows the design of either RC or crystal oscillator circuits. An external clock signal at input RS can replace the oscillator. The Schmitt trigger action of the clock makes it highly tolerant to slower clock rise and fall times. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of other input conditions. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 3)  Specified from 40 C to +85 C  Tolerant of slow clock rise and fall times  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Inputs and outputs are protected against electrostatic effects  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number HEF4060BT-Q100 Package Name Description Version SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4060B-Q100 Nexperia 14-stage ripple-carry binary counter/divider and oscillator 4. Functional diagram 10 9 REXT 11 12 CEXT RS 14-STAGE BINARY COUNTER CP CD MR Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q11 Q12 Q13 7 5 4 6 14 13 15 1 2 3 001aae652 Fig 1. Functional diagram CEXT REXT FF1 FF4 FF10 FF12 FF14 CP CP CP RS CP CP Q CD Q Q CD MR Q CD Q3 Q CD Q9 CD Q11 Q13 001aae654 Fig 2. Logic diagram 5. Pinning information 5.1 Pinning +()%4 4   9'' 4   4 4   4 4   4 4   05 4   56 4   5(;7 966   &(;7 DDD Fig 3. Pin configuration HEF4060B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 September 2014 © Nexperia B.V. 2017. All rights reserved 2 of 14 HEF4060B-Q100 Nexperia 14-stage ripple-carry binary counter/divider and oscillator 5.2 Pin description Table 2. Pin description Symbol Pin Description Q11 to Q13 1, 2, 3 counter output Q3 to Q9 7, 5, 4, 6, 14, 13, 15 counter output VSS 8 ground supply voltage CEXT 9 external capacitor connection REXT 10 oscillator pin RS 11 clock input/oscillator pin MR 12 master reset VDD 16 supply voltage 6. Functional description Table 3. Function table[1] Input Output RS MR Q3 to Q9 and Q11 to Q13  L no change  L count X H L [1] H = HIGH voltage level; L = LOW voltage level;  = LOW-to-HIGH clock transition;  HIGH-to-LOW clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Conditions Min 0.5 VI < 0.5 V or VI > VDD + 0.5 V 0.5 VO < 0.5 V or VO > VDD + 0.5 V Max Unit +18 V 10 mA VDD + 0.5 V - 10 mA input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Ptot total power dissipation Tamb 40 C to +85 C P power dissipation per output [1] [1] - 500 mW - 100 mW For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. HEF4060B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 September 2014 © Nexperia B.V. 2017. All rights reserved 3 of 14 HEF4060B-Q100 Nexperia 14-stage ripple-carry binary counter/divider and oscillator 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD VI Conditions Min Typ Max Unit supply voltage 3 - 15 V input voltage 0 - VDD V 40 - +85 C VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V Tamb ambient temperature in free air t/V input transition rise and fall rate input MR 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage IO < 1 A LOW-level input voltage IO < 1 A HIGH-level output voltage IO < 1 A LOW-level output voltage HIGH-level output current LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4060B_Q100 Product data sheet IO < 1 A VDD 5V Tamb = 40 C Tamb = 25 C Tamb = 85 C Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - Unit V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - 0.3 - 0.3 - 1.0 A 5V - 20 - 20 - 150 A IO = 0 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A - - - - 7.5 - - pF All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 September 2014 © Nexperia B.V. 2017. All rights reserved 4 of 14 HEF4060B-Q100 Nexperia 14-stage ripple-carry binary counter/divider and oscillator 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; VSS = 0 V; CL = 50 pF; tr = tf  20 ns; unless otherwise specified. Symbol Parameter propagation delay tpd transition time tt pulse width tW recovery time trec Conditions Typ Max Unit 183 ns + (0.55 ns/pF) CL - 210 420 ns 5V see Figure 4 10 V 69 ns + (0.23 ns/pF) CL - 80 160 ns 15 V 42 ns + (0.16 ns/pF) CL - 50 100 ns Qn Qn + 1; 5V - - 25 50 ns see Figure 4 10 V - - 10 20 ns 15 V - - 6 12 ns MR Qn; 5V 73 ns + (0.55 ns/pF) CL - 100 200 ns HIGH to LOW 10 V 29 ns + (0.23 ns/pF) CL - 40 80 ns see Figure 4 15 V 22 ns + (0.16 ns/pF) CL - 30 60 ns see Figure 4 5V [3] 10 ns + (1.00 ns/pF) CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns 120 60 - ns minimum width; 5 V RS HIGH; 10 V 50 25 - ns see Figure 4 15 V 30 15 - ns minimum width; 5 V 50 25 - ns MR HIGH; 10 V 30 15 - ns see Figure 4 15 V 20 10 - ns input MR; 5V 160 80 - ns see Figure 4 10 V 80 40 - ns 15 V 60 30 - ns see Figure 4 [1] [2] Extrapolation formula[1] Min RS Q3; maximum frequency input RS; fmax VDD 5V 4 8 - MHz 10 V 10 20 - MHz 15 V 15 30 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] tpd is the same as tPHL and tPLH. [3] tt is the same as tTHL and tTLH. HEF4060B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 September 2014 © Nexperia B.V. 2017. All rights reserved 5 of 14 HEF4060B-Q100 Nexperia 14-stage ripple-carry binary counter/divider and oscillator Table 8. Power dissipation Dynamic power dissipation PD and total power dissipation Ptot can be calculated from the formulas shown. Tamb = 25 C. Symbol Parameter Conditions VDD Typical formula for PD and Ptot (W)[1] PD per device 5V PD = 700  fi + (fo  CL)  VDD2 dynamic power dissipation 10 V PD = 3300  fi + (fo  CL)  VDD2 15 V PD = 8900  fi + (fo  CL)  VDD2 Ptot [1] total power dissipation when using the on-chip oscillator 5V Ptot = 700  fosc + (fo  CL)  VDD2 + 2  Ct  VDD2  fosc + 690  VDD 10 V Ptot = 3300  fosc + (fo  CL)  VDD2 + 2  Ct  VDD2  fosc + 6900  VDD 15 V Ptot = 8900  fosc + (fo  CL)  VDD2 + 2  Ct  VDD2  fosc + 22000  VDD Where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; (fo  CL) = sum of the outputs; Ct = timing capacitance (pF); fosc = oscillator frequency (MHz). 11. Waveforms tr tf 90 % VM MR input 10 % tW 1/fmax trec VM RS input tPHL tPLH tW tPHL 90 % Qn output VM 10 % tt tt 001aaj472 Measurement points are given in Table 9. Fig 4. Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR, and CP pulse widths Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4060B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 September 2014 © Nexperia B.V. 2017. All rights reserved 6 of 14 HEF4060B-Q100 Nexperia 14-stage ripple-carry binary counter/divider and oscillator 9'' 9, * 92 '87 &/ 57 DDJ Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test; CL = load capacitance including jig and probe capacitance; RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Test circuit for measuring switching times Table 10. Measurement point and test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD  20 ns 50 pF 12. RC oscillator +()%4 05IURPORJLF  56 & 5 5(;7 &(;7   5W &W DDD 1 Typical formula for oscillator frequency: f osc = -----------------------------2.3  R t  C t Fig 6. External component connection for RC oscillator 12.1 Timing component limitations The oscillator frequency is mainly determined by Rt  Ct, provided Rt