HEF4082BT-Q100J

HEF4082B-Q100 Dual 4-input AND gate Rev. 1 — 29 May 2015 Product data sheet 1. General description The HEF4082B-Q100 is a dual 4-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Inputs and outputs are protected against electrostatic effects  Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number HEF4082BT-Q100 Package Name Description Version SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4082B-Q100 Nexperia Dual 4-input AND gate 4. Functional diagram         $ Q$ % < &  Q% ' $ Q< % < & Q&  ' Q' DDD Fig 1. Functional diagram Fig 2. DDD Logic diagram (one gate) 5. Pinning information 5.1 Pinning +()%4 <   9'' $   < %   ' &   & '   % QF   $ 966   QF DDD Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 1B, 1C, 1D 2, 3, 4, 5 input 2A, 2B, 2C, 2D 9, 10, 11, 12 input 1Y, 2Y 1, 13 output n.c. 6, 8 not connected VSS 7 ground (0 V) VDD 14 supply voltage HEF4082B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 May 2015 © Nexperia B.V. 2017. All rights reserved 2 of 11 HEF4082B-Q100 Nexperia Dual 4-input AND gate 6. Functional description Table 3. Function table[1] Input Output nA nB nC nD nY L X X X L X L X X L X X L X L X X X L L H H H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max 0.5 +18 V - 10 mA 0.5 VO < 0.5 V or VO > VDD + 0.5 V Unit VDD + 0.5 V IOK output clamping current - 10 mA II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature Tamb ambient temperature Ptot total power dissipation [1] +150 C 40 +125 C - 500 mW - 100 mW Tamb = 40 C to + 125 C SO14 P 65 power dissipation per output [1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage 3 15 V VI input voltage 0 VDD V Tamb ambient temperature in free air 40 +125 C t/V input transition rise and fall rate VDD = 5 V - 3.75 ns/V VDD = 10 V - 0.5 ns/V VDD = 15 V - 0.08 ns/V HEF4082B_Q100 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 May 2015 Min Max © Unit Nexperia B.V. 2017. All rights reserved 3 of 11 HEF4082B-Q100 Nexperia Dual 4-input AND gate 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage IO < 1 A IO < 1 A HIGH-level output voltage IO < 1 A LOW-level output voltage IO < 1 A HIGH-level output current LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4082B_Q100 Product data sheet VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min Max Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A all valid input 5 V combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 A - 0.5 - 0.5 - 15.0 - 15.0 A - 1.0 - 1.0 - 30.0 - 30.0 A - - - 7.5 - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 May 2015 © Nexperia B.V. 2017. All rights reserved 4 of 11 HEF4082B-Q100 Nexperia Dual 4-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; CL = 50 pF; tr = tf  20 ns; waveforms see Figure 4; test circuit see Figure 5; unless otherwise specified. [1] Symbol Parameter propagation delay tpd Conditions nA, nB, nC, nD to nY HIGH to LOW output nY transition time tTHL LOW to HIGH output nY transition time tTLH VDD Min Typ Max Unit 38 + 0.55  CL - 65 125 ns 10 V 19 + 0.23  CL - 30 60 ns 15 V 17 + 0.16  CL - 25 45 ns 5V 10 + 1.0  CL - 60 120 ns 10 V 9 + 0.42  CL - 30 60 ns 15 V 6 + 0.28  CL - 20 40 ns 5V 10 + 1.0  CL - 60 120 ns 10 V 9 + 0.42  CL - 30 60 ns 15 V 6 + 0.28  CL - 20 40 ns 5V Extrapolation formula [2] [1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). [2] tpd is the same as tPHL and tPLH. Table 8. Dynamic power dissipation VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula where: 5V PD = 1500  fi + (fo  CL)  VDD (W) fi = input frequency in MHz; 2 10 V PD = 6700  fi + (fo  CL)  VDD2 (W) fo = output frequency in MHz; 15 V PD = 16800  fi + (fo  CL)  VDD2 (W) CL = output load capacitance in pF; (fo  CL) = sum of the outputs; VDD = supply voltage in V. HEF4082B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 May 2015 © Nexperia B.V. 2017. All rights reserved 5 of 11 HEF4082B-Q100 Nexperia Dual 4-input AND gate 11. Waveforms WU 9,  Q$Q%Q&Q'LQSXW 9 WI 90  W3/+ 92+ W3+/  Q