K4B1G1646G-BCH9

厂商：
SAMSUNG(三星)
封装：
FBGA96_7.5X13.3MM
描述：
1Gb G模DDR3 SDRAMx16仅96FBGA，无铅和无卤（符合RoHS标准）

数据手册：

下载K4B1G1646G-BCH9.pdf

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数据手册
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K4B1G1646G-BCH9 数据手册

Rev. 1.11, Jun. 2011 K4B1G1646G 1Gb G-die DDR3 SDRAM x16 only 96FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved. -1Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First release Nov. 2010 - S.H.Kim 1.1 - Added IDD SPEC values (speed bin 2133Mbps) on page 35. Dec. 2010 - S.H.Kim 1.11 - Corrected Typo. Jun. 2011 - J.Y. Lee -2Downloaded from Arrow.com. K4B1G1646G datasheet Rev. 1.11 DDR3 SDRAM Table Of Contents 1Gb G-die DDR3 SDRAM x16 only 1. Ordering Information ..................................................................................................................................................... 5 2. Key Features................................................................................................................................................................. 5 3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6 3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 6 3.2 FBGA Package Dimension (x16)............................................................................................................................. 7 4. Input/Output Functional Description.............................................................................................................................. 8 5. DDR3 SDRAM Addressing ........................................................................................................................................... 9 6. Absolute Maximum Ratings .......................................................................................................................................... 10 6.1 Absolute Maximum DC Ratings............................................................................................................................... 10 6.2 DRAM Component Operating Temperature Range ................................................................................................ 10 7. AC & DC Operating Conditions..................................................................................................................................... 10 7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 10 8. AC & DC Input Measurement Levels ............................................................................................................................ 11 8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 11 8.2 VREF Tolerances...................................................................................................................................................... 12 8.3 AC & DC Logic Input Levels for Differential Signals............................................................................................... 13 8.3.1. Differential signals definition ............................................................................................................................ 13 8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 13 8.3.3. Single-ended requirements for differential signals ........................................................................................... 14 8.4 Differential Input Cross Point Voltage...................................................................................................................... 15 8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 15 8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 15 9. AC & DC Output Measurement Levels ......................................................................................................................... 16 9.1 Single-ended AC & DC Output Levels..................................................................................................................... 16 9.2 Differential AC & DC Output Levels......................................................................................................................... 16 9.3 Single-ended Output Slew Rate .............................................................................................................................. 16 9.4 Differential Output Slew Rate .................................................................................................................................. 17 9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 17 9.6 Overshoot/Undershoot Specification ....................................................................................................................... 18 9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 18 9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 18 9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 19 9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 20 9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 20 9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 21 9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 22 9.9 ODT Timing Definitions ........................................................................................................................................... 23 9.9.1. Test Load for ODT Timings .............................................................................................................................. 23 9.9.2. ODT Timing Definitions .................................................................................................................................... 23 10. IDD Current Measure Method ..................................................................................................................................... 26 10.1 IDD Measurement Conditions ............................................................................................................................... 26 11. 1Gb DDR3 SDRAM G-die IDD Specification Table .................................................................................................... 35 12. Input/Output Capacitance ........................................................................................................................................... 36 13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-2133 ...................................................................... 37 13.1 Clock Specification ................................................................................................................................................ 37 13.1.1. Definition for tCK(avg).................................................................................................................................... 37 13.1.2. Definition for tCK(abs).................................................................................................................................... 37 13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 37 13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 37 13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 37 13.1.6. Definition for tERR(nper)................................................................................................................................ 37 13.2 Refresh Parameters by Device Density................................................................................................................. 38 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 38 13.3.1. Speed Bin Table Notes .................................................................................................................................. 43 -3Downloaded from Arrow.com. K4B1G1646G datasheet Rev. 1.11 DDR3 SDRAM 14. Timing Parameters by Speed Grade .......................................................................................................................... 44 14.1 Jitter Notes ............................................................................................................................................................ 50 14.2 Timing Parameter Notes........................................................................................................................................ 51 14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 52 14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 59 -4Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 1. Ordering Information [ Table 1 ] Samsung 1Gb DDR3 G-die ordering information table Organization DDR3-1066 (7-7-7) DDR3-1333 (9-9-9)6 DDR3-1600 (11-11-11)5 64Mx16 K4B1G1646G-BCF8 K4B1G1646G-BCH9 K4B1G1646G-BCK0 DDR3-1866 (13-13-13)4 DDR3-2133 (14-14-14)3 K4B1G1646G-BCMA K4B1G1646G-BCNB Package 96FBGA NOTE : 1. Speed bin is in order of CL-tRCD-tRP. 2. 12digit, "B" stands for flip chip FBGA PKG. 3. Backward compatible to DDR3-1866(13-13-13), DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7) 4. Backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7) 5. Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) 6. Backward compatible to DDR3-1066(7-7-7) 2. Key Features [ Table 2 ] 1Gb DDR3 G-die Speed bins Speed DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 Unit tCK(min) 1.875 1.5 1.25 1.07 0.935 ns CAS Latency 7 9 11 13 14 nCK tRCD(min) 13.125 13.5 13.75 13.91 13.09 ns tRP(min) 13.125 13.5 13.75 13.91 13.09 ns tRAS(min) 37.5 36 35 34 33 ns tRC(min) 50.625 49.5 48.75 47.91 46.09 ns • JEDEC standard 1.5V ± 0.075V Power Supply The 1Gb DDR3 SDRAM G-die is organized as a 8Mbit x 16 I/Os x 8banks • VDDQ = 1.5V ± 0.075V device. This synchronous device achieves high speed double-data-rate • 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 933 MHz fCK for 1866Mb/sec/pin, 1066 MHz fCK for 2133Mb/sec/pin transfer rates of up to 2133Mb/sec/pin(DDR3-2133)for general applications. • 8 Banks • Programmable CAS Latency(posted CAS): 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 • Programmable Additive Latency: 0, CL-2 or CL-1 clock • Programmable CAS Write Latency (CWL) = 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600), 9 (DDR3-1866), 10 (DDR3-2133) • 8-bit pre-fetch • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 G-die device is available in 96ball FBGA(x16). • Bi-directional Differential Data-Strobe • Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) • On Die Termination using ODT pin • Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C • Asynchronous Reset • Package : 96 balls FBGA - x16 • All of Lead-Free products are compliant for RoHS • All of products are Halogen-free NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing Diagram”. 2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. -5Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 3. Package pinout/Mechanical Dimension & Addressing 3.1 x16 Package Pinout (Top view) : 96ball FBGA Package 1 2 3 A VDDQ DQU5 B VSSQ C 4 5 6 7 8 9 DQU7 DQU4 VDDQ VSS A VDD VSS DQSU DQU6 VSSQ B VDDQ DQU3 DQU1 DQSU DQU2 VDDQ C D VSSQ VDDQ DMU DQU0 VSSQ VDD D E VSS VSSQ DQL0 DML VSSQ VDDQ E F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F G VSSQ DQL6 DQSL VDD VSS VSSQ G H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H J NC VSS RAS CK VSS NC J K ODT VDD CAS CK VDD CKE K L NC CS WE A10/AP ZQ NC L M VSS BA0 BA2 NC VREFCA VSS M N VDD A3 A0 A12/BC BA1 VDD N P VSS A5 A2 A1 A4 VSS P R VDD A7 A9 A11 A6 VDD R T VSS RESET NC NC A8 VSS T 1 A B Ball Locations (x16) C D E Populated ball Ball not populated F G H J K Top view (See the balls through the package) L M N P R T -6Downloaded from Arrow.com. 2 3 4 5 6 7 8 9 Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 3.2 FBGA Package Dimension (x16) Units : Millimeters 7.50 ± 0.10 A 0.80 x 8 = 6.40 #A1 INDEX MARK 0.80 1.60 3.20 B 9 8 7 6 5 4 3 2 1 96 - ∅0.48 Solder ball (Post Reflow ∅0.50 ± 0.05) 0.2 M A B 13.30 ± 0.10 0.80 x 15 = 12.00 0.40 0.80 (Datum B) 6.00 A B C D E F G H J K L M N P R T (Datum A) (0.30) MOLDING AREA (0.60) 0.10MAX BOTTOM VIEW 7.50 ± 0.10 13.30 ± 0.10 #A1 0.37 ± 0.05 1.10 ± 0.10 TOP VIEW -7Downloaded from Arrow.com. datasheet K4B1G1646G Rev. 1.11 DDR3 SDRAM 4. Input/Output Functional Description [ Table 3 ] Input/Output function description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM (DMU), (DML) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. A0 - A12 Input Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details RESET Input Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. DQ Input/Output Data Input/ Output: Bi-directional data bus. Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Output Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/ x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. DQS, (DQS) TDQS, (TDQS) NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.5V +/- 0.075V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.5V +/- 0.075V VSS Supply Ground VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration NOTE : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination. -8Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 5. DDR3 SDRAM Addressing 1Gb Configuration 256Mb x 4 128Mb x 8 64Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A13 A0 - A13 A0 - A12 Column Address A0 - A9,A11 A 0 - A9 A0 - A 9 BC switch on the fly A12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB Configuration 512Mb x 4 256Mb x 8 128Mb x 16 2Gb # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A14 A0 - A14 A0 - A13 Column Address A0 - A9,A11 A 0 - A9 A0 - A 9 BC switch on the fly A12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB Configuration 1Gb x 4 512Mb x 8 256Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP 4Gb Row Address A0 - A15 A0 - A15 A0 - A14 Column Address A0 - A9,A11 A 0 - A9 A0 - A 9 BC switch on the fly A12/BC A12/BC A12/BC 1 KB 1 KB 2 KB Configuration 2Gb x 4 1Gb x 8 512Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Page size *1 8Gb Row Address A0 - A15 A0 - A15 A0 - A15 Column Address A0 - A9,A11,A13 A0 - A9,A11 A0 - A 9 BC switch on the fly A12/BC A12/BC A12/BC 2 KB 2 KB 2 KB Page size *1 NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG÷8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits -9Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 6. Absolute Maximum Ratings 6.1 Absolute Maximum DC Ratings [ Table 4 ] Absolute Maximum DC Ratings Symbol Parameter Rating Units NOTE VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +100 °C 1, 2 NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 6.2 DRAM Component Operating Temperature Range [ Table 5 ] Temperature Range Symbol Parameter rating Unit NOTE TOPER Operating Temperature Range 0 to 95 °C 1, 2, 3 NOTE : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range. 7. AC & DC Operating Conditions 7.1 Recommended DC operating Conditions (SSTL_1.5) [ Table 6 ] Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Units NOTE 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.5 Supply Voltage for Output 1.425 1.5 NOTE : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. - 10 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 8. AC & DC Input Measurement Levels 8.1 AC & DC Logic input levels for single-ended signals [ Table 7 ] Single-ended AC & DC input levels for Command and Address Symbol DDR3-800/1066/1333/1600 Parameter DDR3-1866/2133 Unit NOTE VDD mV 1,5 VSS VREF - 100 mV 1,6 Note 2 - - mV 1,2,7 Note 2 VREF - 175 - - mV 1,2,8 VREF+150 Note 2 - - mV 1,2,7 Note 2 VREF-150 - - mV 1,2,8 VIH.CA(AC135) AC input logic high - - VREF + 135 Note 2 mV 1,2,7 VIL.CA(AC135) - - Note 2 VREF - 135 mV 1,2,8 Min. Max. Min. Max. VIH.CA(DC100) DC input logic high VREF + 100 VDD VREF + 100 VIL.CA(DC100) DC input logic low VSS VREF - 100 VIH.CA(AC175) AC input logic high VREF + 175 VIL.CA(AC175) AC input logic low VIH.CA(AC150) AC input logic high VIL.CA(AC150) AC input logic low AC input logic low VIH.CA(AC125) AC input logic high - - VREF+125 Note 2 mV 1,2,7 VIL.CA(AC125) - - Note 2 VREF-125 mV 1,2,8 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 3,4 VREFCA(DC) AC input logic low Reference Voltage for ADD, CMD inputs NOTE : 1. For input only pins except RESET, VREF = VREFCA(DC) 2. See ’Overshoot/Undershoot Specification’ on page 18. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135) and VIH.CA(AC125); VIH.CA(AC175) value is used when VREF + 175mV is referenced , VIH.CA(AC150) value is used when VREF + 150mV is referenced, VIH.CA(AC135) value is used when VREF + 135mV is referenced and VIH.CA(AC125) value is used when VREF + 125mV is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when VREF - 175mV is referenced, VIL.CA(AC150) value is used when VREF - 150mV is referenced, VIL.CA(AC135) value is used when VREF - 135mV is referenced and VIL.CA(AC125) value is used when VREF - 125mV is referenced. [ Table 8 ] Single-ended AC & DC input levels for DQ and DM Symbol Parameter DDR3-800/1066 DDR3-1333/1600 DDR3-1866/2133 Unit NOTE VDD mV 1,5 VSS VREF - 100 mV 1,6 Min. Max. Min. Max. Min. Max. VIH.DQ(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD VREF + 100 VIL.DQ(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 VIH.DQ(AC175) AC input logic high VREF + 175 NOTE 2 - - - - mV 1,2,7 VIL.DQ(AC175) AC input logic low NOTE 2 VREF - 175 - - - - mV 1,2,8 VIH.DQ(AC150) AC input logic high VREF + 150 NOTE 2 VREF + 150 NOTE 2 - - mV 1,2,7 VIL.DQ(AC150) AC input logic low NOTE 2 VREF - 150 NOTE 2 VREF - 150 - - mV 1,2,8 VIH.DQ(AC135) AC input logic high - - - - VREF + 135 NOTE 2 mV 1,2,7 VIL.DQ(AC135) AC input logic low - - - - NOTE 2 VREF - 135 mV 1,2,8 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 3,4 VREFDQ(DC) Reference Voltage for DQ, DM inputs NOTE : 1. For input only pins except RESET, VREF = VREFDQ(DC) 2. See ’Overshoot/Undershoot Specification’ on page 18. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) and VIH.DQ(AC135) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used when VREF + 150mV is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when VREF - 150mV is referenced. - 11 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 8.2 VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on page 11. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. voltage VDD VSS time Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1 . This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. - 12 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 8.3 AC & DC Logic Input Levels for Differential Signals 8.3.1 Differential signals definition tDVAC Differential Input Voltage (i.e. DQS-DQS, CK-CK) VIH.DIFF.AC.MIN VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC 8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) [ Table 9 ] Differential AC & DC Input Levels Symbol Parameter VIHdiff DDR3-800/1066/1333/1600/1866/2133 unit NOTE NOTE 3 V 1 NOTE 3 -0.2 V 1 differential input high ac 2 x (VIH(AC) - VREF) NOTE 3 V 2 differential input low ac NOTE 3 2 x (VIL(AC) - VREF) V 2 min max differential input high +0.2 VILdiff differential input low VIHdiff(AC) VILdiff(AC) NOTE : 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification" [ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS Slew Rate [V/ns] tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 270mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 250mV min max min max min max min max > 4.0 75 - 175 - TBD - TBD - 4.0 57 - 170 - TBD - TBD - 3.0 50 - 167 - TBD - TBD - 2.0 38 - 163 - TBD - TBD - 1.8 34 - 162 - TBD - TBD - 1.6 29 - 161 - TBD - TBD - 1.4 22 - 159 - TBD - TBD - 1.2 13 - 155 - TBD - TBD - 1.0 0 - 150 - TBD - TBD - < 1.0 0 - 150 - TBD - TBD - - 13 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 8.3.3 Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH(AC) / VIL(AC)} for ADD/CMD signals] in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax [approximately the ac-levels { VIH(AC) / VIL(AC)} for DQ signals] in every half-cycle proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK . VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSEL VSS or VSSQ time Figure 3. Single-ended requirement for differential signals Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. [ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU Symbol VSEH VSEL Parameter DDR3-800/1066/1333/1600/1866/2133 Unit NOTE NOTE3 V 1, 2 NOTE3 V 1, 2 Min Max Single-ended high-level for strobes (VDD/2)+0.175 Single-ended high-level for CK, CK (VDD/2)+0.175 Single-ended low-level for strobes NOTE3 (VDD/2)-0.175 V 1, 2 Single-ended low-level for CK, CK NOTE3 (VDD/2)-0.175 V 1, 2 NOTE : 1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification" - 14 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 8.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSEH VSEL VSS Figure 4. VIX Definition [ Table 12 ] Cross point voltage for differential input signals (CK, DQS) Symbol DDR3-800/1066/1333/1600/1866/2133 Parameter VIX Differential Input Cross Point Voltage relative to VDD/2 for CK,CK VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS Unit NOTE 150 mV 2 175 mV 1 150 mV 2 Min Max -150 -175 -150 NOTE : 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 ±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to Table 11 on page 14 for VSEL and VSEH standard values. 2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following. (VDD/2) + VIX(Min) - VSEL ≥ 25mV VSEH - ((VDD/2) + VIX(Max)) ≥ 25mV 8.5 Slew rate definition for Differential Input Signals See 14.3 “Address/Command Setup, Hold and Derating :” on page 48 for single-ended slew rate definitions for address and command signals. See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 54 for single-ended slew rate definitions for data signals. 8.6 Slew rate definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5. [ Table 13 ] Differential input slew rate definition Measured Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Defined by From To VILdiffmax VIHdiffmin VIHdiffmin VILdiffmax NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds. VIHdiffmin 0 VILdiffmax delta TRdiff delta TFdiff Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK - 15 Downloaded from Arrow.com. VIHdiffmin - VILdiffmax Delta TRdiff VIHdiffmin - VILdiffmax Delta TFdiff Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9. AC & DC Output Measurement Levels 9.1 Single-ended AC & DC Output Levels [ Table 14 ] Single-ended AC & DC output levels Symbol Parameter DDR3-800/1066/1333/1600/1866/2133 Units VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V NOTE VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V 1 VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V 1 NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2. 9.2 Differential AC & DC Output Levels [ Table 15 ] Differential AC & DC output levels Symbol Parameter DDR3-800/1066/1333/1600/1866/2133 Units NOTE VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V 1 VOLdiff(AC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V 1 NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs. 9.3 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and Figure 6. [ Table 16 ] Single-ended output slew rate definition Measured Description From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) Single ended output slew rate for falling edge VOH(AC) VOL(AC) Defined by VOH(AC)-VOL(AC) Delta TRse VOH(AC)-VOL(AC) Delta TFse NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test. [ Table 17 ] Single-ended output slew rate Parameter Single ended output slew rate Symbol SRQse DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Min DDR3-800 Max Min Max Min Max Min Max Min Max Min Max 2.5 5 2.5 5 2.5 5 2.5 5 2.5 51) 2.5 51) Units V/ns Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) se : Single-ended Signals For Ron = RZQ/7 setting NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. - Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low). - Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies. VOH(AC) VTT VOL(AC) delta TFse delta TRse Figure 6. Single-ended Output Slew Rate Definition - 16 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 18 and Figure 7. [ Table 18 ] Differential output slew rate definition Measured Description From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) Defined by VOHdiff(AC)-VOLdiff(AC) Delta TRdiff VOHdiff(AC)-VOLdiff(AC) Delta TFdiff NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test. [ Table 19 ] Differential output slew rate Parameter Symbol Differential output slew rate SRQdiff DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Min DDR3-800 Max Min Max Min Max Min Max Min Max Min Max 5 10 5 10 5 10 5 10 5 12 5 12 Units V/ns Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Differential Signals For Ron = RZQ/7 setting VOHdiff(AC) VTT VOLdiff(AC) delta TFdiff delta TRdiff Figure 7. Differential Output Slew Rate Definition 9.5 Reference Load for AC Timing and Output Slew Rate Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK/CK DUT DQ DQS DQS VTT = VDDQ/2 25Ω Reference Point Figure 8. Reference Load for AC Timing and Output Slew Rate - 17 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9.6 Overshoot/Undershoot Specification 9.6.1 Address and Control Overshoot and Undershoot specifications [ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT) Specification Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit Maximum peak amplitude allowed for overshoot area (See Figure 9) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V Maximum peak amplitude allowed for undershoot area (See Figure 9) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V Maximum overshoot area above VDD (See Figure 9) 0.67V-ns 0.5V-ns 0.4V-ns 0.33V-ns 0.28V-ns 0.25V-ns V-ns Maximum undershoot area below VSS (See Figure 9) 0.67V-ns 0.5V-ns 0.4V-ns 0.33V-ns 0.28V-ns 0.25V-ns V-ns Maximum Amplitude Volts (V) Overshoot Area VDD VSS Maximum Amplitude Undershoot Area Time (ns) Figure 9. Address and Control Overshoot and Undershoot Definition 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications [ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK) Specification Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit Maximum peak amplitude allowed for overshoot area (See Figure 10) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V Maximum peak amplitude allowed for undershoot area (See Figure 10) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V Maximum overshoot area above VDDQ (See Figure 10) 0.25V-ns 0.19V-ns 0.15V-ns 0.13V-ns 0.11V-ns 0.10V-ns V-ns Maximum undershoot area below VSSQ (See Figure 10) 0.25V-ns 0.19V-ns 0.15V-ns 0.13V-ns 0.11V-ns 0.10V-ns V-ns Maximum Amplitude Volts (V) Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition - 18 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9.7 34ohm Output Driver DC Electrical Characteristics A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows: RON34 = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm) The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows VDDQ-VOUT RONpu = under the condition that RONpd is turned off l Iout l VOUT RONpd = under the condition that RONpu is turned off l Iout l Output Driver VDDQ Ipu To other circuity RON Pu DQ Iout RON Pd Vout Ipd VSSQ Figure 11. Output Driver : Definition of Voltages and Currents [ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ; entire operating temperature range ; after proper ZQ calibration RONnom Resistor Vout Min Nom Max VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 1,2,3 RON34pd VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 1,2,3 VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 1,2,3 VOMdc = 0.5 x VDDQ -10 34Ohms RON34pu RON40pd 40Ohms RON40pu Mismatch between Pull-up and Pull-down, MMpupd 10 Units RZQ/7 RZQ/6 % NOTE 1,2,3 1,2,3 1,2,3 1,2,3 1,2,4 NOTE : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ 4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ: MMpupd = RONpu - RONpd RONnom x 100 - 19 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9.7.1 Output Drive Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 23 and Table 24. ΔT = T - T(@calibration); ΔV = VDDQ - VDDQ (@calibration); VDD = VDDQ *dRONdT and dRONdV are not subject to production test but are verified by design and characterization [ Table 23 ] Output Driver Sensitivity Definition Min Max Units RONPU@VOHDC 0.6 - dRONdTH * |ΔT| - dRONdVH * |ΔV| 1.1 + dRONdTH * |ΔT| + dRONdVH * |ΔV| RZQ/7 RON@VOMDC 0.9 - dRONdTM * |ΔT| - dRONdVM * |ΔV| 1.1 + dRONdTM * |ΔT| + dRONdVM * |ΔV| RZQ/7 RONPD@VOLDC 0.6 - dRONdTL * |ΔT| - dRONdVL * |ΔV| 1.1 + dRONdTL * |ΔT| + dRONdVL * |ΔV| RZQ/7 [ Table 24 ] Output Driver Voltage and Temperature Sensitivity Speed Bin DDR3-800/1066/1333 DDR3-1600/1866/2133 Units Min Max Min Max dRONdTM 0 1.5 0 1.5 %/°C dRONdVM 0 0.15 0 0.13 %/mV dRONdTL 0 1.5 0 1.5 %/°C dRONdVL 0 0.15 0 0.13 %/mV dRONdTH 0 1.5 0 1.5 %/°C dRONdVH 0 0.15 0 0.13 %/mV 9.8 On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register. ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as follows : RTTpu = RTTpd = VDDQ-VOUT under the condition that RTTpd is turned off l Iout l VOUT under the condition that RTTpu is turned off l Iout l Chip in Termination Mode ODT VDDQ Ipu To other circuitry like RCV, ... Iout=Ipd-Ipu RTTPu DQ Iout RTTPd VOUT Ipd VSSQ Figure 12. On-Die Termination : Definition of Voltages and Currents - 20 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9.8.1 ODT DC Electrical Characteristics Table 25 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80, RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines: [ Table 25 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration MR1 (A9,A6,A2) RTT RESISTOR RTT120pd240 (0,1,0) 120 ohm RTT120pu240 RTT120 RTT60pd240 (0,0,1) 60 ohm RTT60pu240 RTT60 RTT40pd240 (0,1,1) 40 ohm RTT40pu240 RTT40 RTT60pd240 (1,0,1) 30 ohm RTT60pu240 RTT60 Vout Min Nom Max Unit NOTE VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4 1,2,5 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4 1.6 RZQ/4 1,2,5 1,2,3,4 VIL(AC) to VIH(AC) (1,0,0) 20 ohm RTT60pu240 RTT60 0.6 1.0 1.1 0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 1,2,5 1,2,3,4 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/4 0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 1,2,5 1.1 RZQ/6 1,2,3,4 1,2,3,4 0.6 1.0 0.5XVDDQ 0.9 1.0 1.1 RZQ/6 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 1,2,5 5 % 1,2,5,6 Deviation of VM w.r.t VDDQ/2, ΔVM -5 - 21 Downloaded from Arrow.com. 1.0 RZQ/3 VOL(DC) 0.2XVDDQ RTT60pd240 0.9 VOL(DC) 0.2XVDDQ Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM NOTE : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2XVDDQ and 0.8XVDDQ. 4. Not a specification requirement, but a design guide line 5. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively RTT = VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC)) 6. Measurement definition for VM and ΔVM : Measure voltage (VM) at test pin (midpoint) with no load Δ VM = 2 x VM VDDQ -1 x 100 9.8.2 ODT Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to table below ΔT = T - T(@calibration); ΔV = VDDQ - VDDQ (@calibration); VDD = VDDQ [ Table 26 ] ODT Sensitivity Definition Min Max Units 0.9 - dRTTdT * |ΔT| - dRTTdV * |ΔV| 1.6 + dRTTdT * |ΔT| + dRTTdV * |ΔV| RZQ/2,4,6,8,12 Min Max Units dRTTdT 0 1.5 %/°C dRTTdV 0 0.15 %/mV RTT [ Table 27 ] ODT Voltage and Temperature Sensitivity NOTE : These parameters may not be subject to production test. They are verified by design and characterization. - 22 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 9.9 ODT Timing Definitions 9.9.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in Figure 13. VDDQ CK,CK DUT DQ, DM VTT= VSSQ RTT =25 ohm DQS , DQS TDQS , TDQS VSSQ Timing Reference Points Figure 13. ODT Timing Reference Load 9.9.2 ODT Timing Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided in Table 29. [ Table 28 ] ODT Timing Definitions Symbol Begin Point Definition End Point Definition Figure tAON Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ Figure 14 tAONPD Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ Figure 15 tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom Figure 16 tAOFPD Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at VRTT_Nom Figure 17 tADC Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4 of ODTLcwn8 End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively Figure 18 [ Table 29 ] Reference Settings for ODT Timing Measurements Measured Parameter tAON tAONPD tAOF tAOFPD tADC RTT_Nom Setting RTT_Wr Setting VSW1[V] VSW2[V] RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/12 RZQ/2 0.20 0.30 - 23 Downloaded from Arrow.com. NOTE Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM Begin point : Rising edge of CK - CK defined by the end point of ODTLon CK VTT CK tAON TSW2 DQ, DM DQS , DQS TDQS , TDQS TSW1 VSW2 VSW1 VSSQ VSSQ End point Extrapolated point at VSSQ Figure 14. Definition of tAON Begin point : Rising edge of CK - CK with ODT being first registered high CK VTT CK tAONPD TSW2 DQ, DM DQS , DQS TDQS , TDQS TSW1 VSW2 VSW1 VSSQ VSSQ End point Extrapolated point at VSSQ Figure 15. Definition of tAONPD Begin point : Rising edge of CK - CK defined by the end point of ODTLoff CK VTT CK tAOF End point Extrapolated point at VRTT_Nom VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS TSW2 TSW1 VSW2 VSW1 VSSQ TD_TAON_DEF Figure 16. Definition of tAOF - 24 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM Begin point : Rising edge of CK - CK with ODT being first registered low CK VTT CK tAOFPD End point Extrapolated point at VRTT_Nom VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS TSW2 TSW1 VSW2 VSW1 VSSQ Figure 17. Definition of tAOFPD Begin point : Rising edge of CK - CK defined by the end point of ODTLcnw Begin point : Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8 CK VTT CK tADC VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS tADC End point Extrapolated point at VRTT_Nom TSW21 End point Extrapolated point TSW11 at VRTT_Nom TSW22 VSW2 VRTT_Nom TSW12 VSW1 VRTT_Wr End point Extrapolated point at VRTT_Wr VSSQ Figure 18. Definition of tADC - 25 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 10. IDD Current Measure Method 10.1 IDD Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and IDDQ measurements. - IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. - IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply : - "0" and "LOW" is defined as VIN = VIHAC(min). - "FLOATING" is defined as inputs are VREF = VDD / 2. - "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 30 - "Basic IDD and IDDQ Measurement Conditions" are described in Table 31 - Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39. - IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 - Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. - Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW} - Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH} - RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms; During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC [ Table 30 ] Timing used for IDD and IDDQ Measured - Loop Patterns Parameter Bin tCKmin(IDD) CL(IDD) DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 6-6-6 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 2.5 1.875 1.5 1.25 1.07 0.935 ns 6 7 9 11 13 14 nCK Unit tRCDmin(IDD) 6 7 9 11 13 14 nCK tRCmin(IDD) 21 27 33 39 45 50 nCK tRASmin(IDD) 15 20 24 28 32 36 nCK tRPmin(IDD) 6 7 9 11 13 14 nCK tFAW(IDD) tRRD(IDD) x4/x8 16 20 20 24 26 27 nCK x16 20 27 30 32 33 38 nCK x4/x8 4 4 4 5 5 6 nCK x16 4 6 5 6 6 7 nCK tRFC(IDD) - 512Mb 36 48 60 72 85 97 nCK tRFC(IDD) - 1Gb 44 59 74 88 103 118 nCK tRFC(IDD) - 2Gb 64 86 107 128 150 172 nCK tRFC(IDD) - 4Gb 120 160 200 240 281 321 nCK tRFC(IDD) - 8Gb 140 187 234 280 328 375 nCK - 26 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G IDD VDD DDR3 SDRAM IDDQ VDDQ RESET CK/CK CKE DQS, DQS CS DQ, DM, RAS, CAS, WE TDQS, TDQS RTT = 25 Ohm VDDQ/2 A, BA ODT ZQ VSS VSSQ [NOTE : DIMM level Output test load condition may be different from above] Figure 19. Measurement Setup and Test Load for IDD and IDDQ Measurements Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Measurement Correlation Correction Channel IO Power Number Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement. - 27 Downloaded from Arrow.com. K4B1G1646G datasheet Rev. 1.11 DDR3 SDRAM [ Table 31 ] Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 32 Operating One Bank Active-Read-Precharge Current IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 33 Precharge Standby Current IDD2N CKE: High; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34 Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35 IDDQ2NT Precharge Standby ODT IDDQ Current Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge Power-Down Current Slow Exit IDD2P0 CKE: Low; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exi3) Precharge Power-Down Current Fast Exit IDD2P1 CKE: Low; External clock: On; tCK, CL: see Table 30 on page 26; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0 Active Standby Current IDD3N CKE: High; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34 Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0 Operating Burst Read Current IDD4R CKE: High; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 11); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 36 IDDQ4R Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Operating Burst Write Current IDD4W CKE: High; External clock: On; tCK, CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: see Table 37 Burst Refresh Current IDD5B CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 on page 26 ; BL: 81); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 38 Self Refresh Current: Normal Temperature Range IDD6 TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: SelfRefresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING - 28 Downloaded from Arrow.com. K4B1G1646G datasheet Rev. 1.11 DDR3 SDRAM [ Table 31 ] Basic IDD and IDDQ Measurement Conditions Symbol Description Operating Bank Interleave Read Current IDD7 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 on page 26 ; BL: 81); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 39 IDD8 RESET Low Current RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal : FLOATING NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B 2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range 6) Read Burst type : Nibble Sequential, set MR0 A[3]=0B - 29 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM ODT A[2:0] Data2) 1 1 0 0 00 0 0 0 0 - 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 00 0 0 0 0 - 3,4 ... nRAS Static High toggling ... A[6:3] WE 0 1 A[9:7] CAS 0 D, D A[10] RAS ACT A[15:11] CS 0 1,2 BA[2:0] Command 0 Cycle Number Sub-Loop CKE CK/CK [ Table 32 ] IDD0 Measurement - Loop Pattern1) repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC + 0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC + 1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - 0 0 F 0 1*nRC + 3, 4 ... 1*nRC + nRAS ... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 repeat 1...4 until 2*nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead NOTE : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. - 30 Downloaded from Arrow.com. 0 00 Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) 0 Cycle Number Sub-Loop CKE CK/CK [ Table 33 ] IDD1 Measurement - Loop Pattern1) 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 00 0 0 0 0 00000000 00 0 0 0 0 - 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD- 1, truncate if necessary RD 0 1 0 1 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC + 1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - 0 F 0 00110011 0 F 0 - 1*nRC + 3, 4 ... 1*nRC + nRCD ... 1*nRC + nRAS ... repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. RAS CAS WE ODT BA[2:0] A[15:11] A[10] 1 0 0 0 0 0 00 0 1 D 1 0 0 0 0 0 00 0 2 D 1 1 1 1 0 0 00 0 D 1 1 1 1 0 0 00 0 Static High toggling 3 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-27 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead NOTE : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. - 31 Downloaded from Arrow.com. Data2) CS D A[2:0] Command 0 A[6:3] Cycle Number 0 A[9:7] Sub-Loop CKE CK/CK [ Table 34 ] IDD2 and IDD3N Measurement - Loop Pattern1) 0 0 0 - 0 0 0 - 0 F 0 - 0 F 0 - Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) CKE Static High toggling CK/CK [ Table 35 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern1) 0 0 D 1 0 0 0 0 0 00 0 0 0 0 - 1 D 1 0 0 0 0 0 00 0 0 0 0 2 D 1 1 1 1 0 0 00 0 0 F 0 3 D 1 1 1 1 0 0 00 0 0 F 0 1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-27 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 NOTE : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) CKE Static High toggling CK/CK [ Table 36 ] IDD4R and IDDQ4R Measurement - Loop Pattern1) 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - 6,7 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. - 32 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) CKE Static High toggling CK/CK [ Table 37 ] IDD4W Measurement - Loop Pattern1) 0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 - 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 5 D 1 0 0 0 1 0 00 0 0 F 0 - 6,7 D,D 1 1 1 1 1 0 00 0 0 F 0 - 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) 0 0 1 0 0 00 0 0 0 0 - 1 0 0 0 0 0 00 0 0 0 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Static High toggling 3,4 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...4, but BA[2:0] = 4 21...24 repeat cycles 1...4, but BA[2:0] = 5 25...28 repeat cycles 1...4, but BA[2:0] = 6 29...32 repeat cycles 1...4, but BA[2:0] = 7 33...nRFC - 1 WE 0 D CAS REF 1,2 RAS Command 0 1 CS Cycle Number 0 Sub-Loop CKE CK/CK [ Table 38 ] IDD5B Measurement - Loop Pattern1) repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. NOTE : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. - 33 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM A[15:11] A[10] A[9:7] A[6:3] A[2:0] 1 0 0 00 0 0 0 0 - 0 1 0 0 00 1 0 0 0 00000000 D 1 0 0 0 0 0 00 0 0 0 0 - 2 ... 1 Static High toggling repeat above D Command until nRRD - 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 - nRRD + 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 D 1 0 0 0 0 1 00 0 0 F 0 - 0 3 00 0 0 F 0 - 0 F 0 - nRRD + 2 ... repeat above D Command until 2*nRRD-1 2 2 * nRRD repeat Sub-Loop 0, but BA[2:0] = 2 3 3 * nRRD repeat Sub-Loop 1, but BA[2:0] = 3 4 4 * nRRD D 1 0 0 nFAW repeat Sub-Loop 0, but BA[2:0] = 4 6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5 7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6 8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7 9 nFAW+4*nRRD D 1 0 0 0 0 7 00 0 Assert and repeat above D Command until 2*nFAW - 1, if necessary 2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 - 2*nFAW+2 11 0 Assert and repeat above D Command until nFAW - 1, if necessary 5 10 Data2) BA[2:0] 1 1 WE 0 0 CAS 0 RDA RAS ACT 1 CS ODT 0 Command 0 Cycle Number Sub-Loop CKE CK/CK [ Table 39 ] IDD7 Measurement - Loop Pattern1) Repeat above D Command until 2*nFAW + nRRD - 1 2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 - 2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 - 0 0 0 0 - 0 0 - 2*nFAW+nRRD+2 Repeat above D Command until 2*nFAW + 2*nRRD - 1 12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2 13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3 14 2*nFAW+4*nRRD D 1 0 0 0 0 3 00 Assert and repeat above D Command until 3*nFAW - 1, if necessary 15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4 16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5 17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6 18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7 19 3*nFAW+4*nRRD D 1 0 0 0 0 7 00 0 NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL. - 34 Downloaded from Arrow.com. 0 Assert and repeat above D Command until 4*nFAW - 1, if necessary Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 11. 1Gb DDR3 SDRAM G-die IDD Specification Table [ Table 40 ] IDD Specification for 1Gb DDR3 G-die 64Mx16 (K4B1G1646G) Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 Unit IDD0 45 45 45 50 55 IDD1 60 60 65 70 75 mA IDD2P0(slow exit) 10 10 10 10 10 mA IDD2P1(fast exit) 10 12 12 12 12 mA mA mA IDD2N 15 15 15 20 20 IDD2NT 20 25 25 25 27 mA IDDQ2NT 145 145 145 145 145 mA IDD2Q 15 15 15 20 20 mA IDD3P 20 20 20 20 20 mA IDD3N 25 25 25 30 30 mA IDD4R 95 120 135 150 170 mA IDDQ4R 105 105 105 105 105 mA IDD4W 90 110 120 140 155 mA IDD5B 90 90 95 105 120 mA IDD6 10 10 10 10 10 mA IDD7 140 170 195 195 210 mA IDD8 10 10 10 10 10 mA - 35 Downloaded from Arrow.com. NOTE Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 12. Input/Output Capacitance [ Table 41 ] Input/Output Capacitance Parameter Symbol Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance delta (CK and CK) Input capacitance (All other input-only pins) Input capacitance delta (DQS and DQS) Input capacitance delta (All control input-only pins) Input capacitance delta (all ADD and CMD input-only pins) DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Units NOTE 2.1 pF 1,2,3 0.8 1.3 pF 2,3 0.15 0 0.15 pF 2,3,4 0.75 1.2 0.75 1.2 pF 2,3,5 0.15 0 0.15 0 0.15 pF 2,3,6 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10 Min Max Min Max Min Max Min Max Min Max Min Max CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.4 2.2 1.4 CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 CI 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 CDDQS 0 0.2 0 0.2 0 0.15 0 CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS) CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11 Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12 NOTE : 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK 5. Absolute value of CIO(DQS)-CIO(DQS) 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTRL applies to ODT, CS and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance on ZQ pin: 5pF - 36 Downloaded from Arrow.com. datasheet K4B1G1646G Rev. 1.11 DDR3 SDRAM 13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-2133 13.1 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device. 13.1.1 Definition for tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. N ∑ tCKj N N=200 j=1 13.1.2 Definition for tCK(abs) tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. 13.1.3 Definition for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: N ∑ N tCHj N x tCK(avg) ∑ N=200 j=1 tCLj N x tCK(avg) N=200 j=1 13.1.4 Definition for note for tJIT(per), tJIT(per, Ick) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test. 13.1.5 Definition for tJIT(cc), tJIT(cc, Ick) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi} tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not subject to production test. 13.1.6 Definition for tERR(nper) tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test. - 37 Downloaded from Arrow.com. Rev. 1.11 datasheet K4B1G1646G DDR3 SDRAM 13.2 Refresh Parameters by Device Density [ Table 42 ] Refresh parameters by device density Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units tRFC 110 160 300 350 ns 0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 μs 85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 μs All Bank Refresh to active/refresh cmd time Average periodic refresh interval tREFI NOTE 1 NOTE : 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. [ Table 43 ] DDR3-800 Speed Bins Speed DDR3-800 CL-nRCD-nRP 6-6-6 Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period Units Symbol min max tAA 15 20 ns tRCD 15 - ns tRP 15 - ns tRC 52.5 - ns tRAS 37.5 9*tREFI ns NOTE CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,11,12 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3 Supported CL Settings Supported CWL Settings 5,6 nCK 5 nCK [ Table 44 ] DR3-1066 Speed Bins Speed DDR3-1066 CL-nRCD-nRP 7-7-7 Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period CL = 6 CL = 7 CL = 8 Symbol min max tAA 13.125 20 ns tRCD 13.125 - ns tRP 13.125 - ns tRC 50.625 - ns tRAS 37.5 9*tREFI ns CWL = 5 tCK(AVG) 3.0 3.3 ns CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) ACT to PRE command period CL = 5 Reserved 4 1,2,3,5 Reserved ns 1,2,3,4 Reserved ns 4 ns 1,2,3,4,10 ns 4 ns 1,2,3

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