K4D553238F-JC40

K4D553238F-JC 256M GDDR SDRAM 256Mbit GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 1.0 March 2004 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev 1.0 (Mar. 2004) K4D553238F-JC Revision History Revision 1.0 (March 8, 2004) • DC Specification finalized 256M GDDR SDRAM Revision 0.1 (March 2 , 2004) - Target Spec Revision 0.0 (October 28, 2003) - Target Spec • Defined Target Specification -2- Rev 1.0 (Mar. 2004) K4D553238F-JC 256M GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 2.5V + 5% power supply for device operation • 2.5V + 5% power supply for I/O interface • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs -. Read latency 3, 4 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock • Differential clock input • No Wrtie-Interrupted by Read Function • 4 DQS’s ( 1DQS / Byte ) • Data I/O transactions on both edges of Data strobe • DLL aligns DQ and DQS transitions with Clock transition • Edge aligned data & data strobe output • Center aligned data & data strobe input • DM for write masking only • Auto & Self refresh • 32ms refresh period (4K cycle) • 144-Ball FBGA • Maximum clock frequency up to 350MHz • Maximum data rate up to 700Mbps/pin ORDERING INFORMATION Part NO. K4D553238F-JC2A K4D553238F-JC33 K4D553238F-JC36 K4D553238F-JC40 K4D553238F-JC50 Max Freq. 350MHz 300MHz 275MHz 250MHz 200MHz Max Data Rate 700Mbps/pin 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin SSTL_2 144-Ball FBGA Interface Package 1. K4D553238F-EC is the Lead Free package part number 2. For the K4D553238F-JC2A, VDD & VDDQ =2.8V + 0.1V GENERAL DESCRIPTION FOR 2M x 32Bit x 4 Bank GDDR SDRAM The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. -3- Rev 1.0 (Mar. 2004) K4D553238F-JC PIN CONFIGURATION (Top View) 2 B C D E F G H J K L M N DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS 256M GDDR SDRAM 3 DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC 4 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0 5 DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0 6 DQ2 DQ1 VSSQ VSSQ 7 DQ0 VDDQ VDD VSS 8 DQ31 VDDQ VDD VSS 9 DQ29 DQ30 VSSQ VSSQ 10 DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS RFU2 A7 11 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CK A8/AP 12 DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CK CKE 13 DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC MCL VREF VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS A10 A2 A1 VSS VDD A11 A3 VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VDD A9 A4 VSS RFU1 A5 A6 NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional PIN DESCRIPTION CK,CK CKE CS RAS CAS WE DQS DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~A11 DQ0 ~ DQ31 VDD VSS VDDQ VSSQ NC MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQ’s Ground for DQ’s No Connection Must Connect Low -4- Rev 1.0 (Mar. 2004) K4D553238F-JC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input Type 256M GDDR SDRAM Function The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, DQS3 for DQ24 ~ DQ31. Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7,CA9 Column address CA8 is used for auto precharge. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommended to be left "No connection" on the device Must connect low CKE Input CS Input RAS CAS WE Input Input Input DQS0 ~ DQS3 Input/Output DM0 ~ DM3 DQ0 ~ DQ31 BA0, BA1 A0 ~ A11 VDD/VSS VDDQ/VSSQ VREF NC/RFU MCL Input Input/Output Input Input Power Supply Power Supply Power Supply No connection/ Reserved for future use Must Connect Low *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. -5- Rev 1.0 (Mar. 2004) K4D553238F-JC BLOCK DIAGRAM (2Mbit x 32I/O x 4 Bank) 256M GDDR SDRAM 32 Intput Buffer I/O Control LWE LDMi CK, CK Bank Select Data Input Register Serial to parallel 64 2Mx32 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 2Mx32 2Mx32 2Mx32 64 32 x32 DQi Address Register CK,CK ADDR Column Decoder LCBR LRAS Col. Buffer Latency & Burst Length Strobe Gen. Data Strobe (DQS0~DQS3) Programming Register LCKE LRAS LCBR LWE LCAS LWCBR DLL CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE DMi -6- Rev 1.0 (Mar. 2004) K4D553238F-JC FUNCTIONAL DESCRIPTION • Power-Up Sequence 256M GDDR SDRAM GDDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 0 CK,CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ ~ ~~ ~ Command precharge ALL Banks EMRS MRS DLL Reset precharge ALL Banks 1st Auto Refresh 2nd Auto Refresh ~~ ~ tRP 2 Clock min. 2 Clock min. tRP tRFC tRFC ~ 2 Clock min. Mode Register Set Any Command ~ Inputs must be stable for 200us * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. ~ ~ 200 Clock min. -7- Rev 1.0 (Mar. 2004) K4D553238F-JC MODE REGISTER SET(MRS) 256M GDDR SDRAM The mode register stores the data for controlling the various operating modes of GDDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make GDDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The GDDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus RFU 0 RFU DLL TM CAS Latency BT Burst Length Mode Register DLL A8 0 1 DLL Reset No Yes Test Mode A7 0 1 mode Normal Test Burst Type A3 0 1 Type Sequential Interleave Burst Length CAS Latency BA0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle 0 CK, CK Command NOP Precharge All Banks NOP NOP MRS A2 Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 NOP Any Command NOP NOP tRP tMRD=2 tCK *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. -8- Rev 1.0 (Mar. 2004) K4D553238F-JC EXTENDED MODE REGISTER SET(EMRS) 256M GDDR SDRAM The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Extended Mode Register RFU 1 RFU D.I.C RFU D.I.C DLL BA0 0 1 An ~ A0 MRS EMRS A6 0 1 A1 1 1 Output Driver Impedence Control Weak Matched A0 0 1 DLL Enable Enable Disable *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. Figure 7. Extended Mode Register set -9- Rev 1.0 (Mar. 2004) K4D553238F-JC ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS 256M GDDR SDRAM Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 2.0 50 Unit V V V °C W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD VDDQ VREF Vtt VIH(DC) VIL(DC) VOH VOL IIL IOL Min 2.375 2.375 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5 Typ 2.5 2.5 VREF - Max 2.625 2.625 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76 5 5 Unit V V V V V V V V uA uA Note 1, 7 1, 7 2 3 4 5 IOH=-15.2mA IOL=+15.2mA 6 6 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. For the K4D553238F-JC2A, VDD & VDDQ = 2.8V + 0.1V - 10 - Rev 1.0 (Mar. 2004) K4D553238F-JC Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) 256M GDDR SDRAM DC CHARACTERISTICS Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank interleaving) Symbol Version Test Condition -2A ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 ICC7 Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), 400 120 190 170 250 650 470 8 840 680 630 150 130 220 550 415 140 120 210 520 395 6 590 550 -33 340 -36 320 90 130 110 200 460 365 120 100 190 430 335 -40 300 -50 280 mA mA mA mA mA mA mA mA mA 2 1 Unit Note tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. tRC ≥ tRFC(min) CKE ≤ 0.2V Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) Note : 1. Measured with outputs open. 2. Refresh period is 32ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C) Parameter Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK Symbol VIH VIL VID VIX Min VREF+0.35 0.7 0.5*VDDQ-0.2 Typ - Max VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2 Unit V V V V Note 1 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev 1.0 (Mar. 2004) K4D553238F-JC AC OPERATING TEST CONDITIONS (VDD=2.5V±5%, TA= 0 to 65°C) Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF Vtt See Fig.1 Vtt=0.5*VDDQ 256M GDDR SDRAM Unit V V V/ns V V V Note RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ (Fig. 1) Output Load Circuit CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz) Parameter Input capacitance( CK, CK ) Input capacitance(A0~A11, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ31) Input capacitance(DM0 ~ DM3) Symbol CIN1 CIN2 CIN3 COUT CIN4 Min 5.0 5.0 5.0 4.0 4.0 Max 10.0 9.0 9.0 8.0 8.0 Unit pF pF pF pF pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. - 12 - Rev 1.0 (Mar. 2004) K4D553238F-JC AC CHARACTERISTICS Parameter CK cycle time CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period CL=3 CL=4 256M GDDR SDRAM Symbol -2A Min 2.86 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.35 0.35 tCLmin or tCHmin tHP -0.35 Max 10 0.55 0.55 0.6 0.6 0.35 1.1 0.6 1.15 0.6 0.6 0.6 Min 3.3 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.35 -33 Max 10 0.55 0.55 0.6 0.6 0.35 1.1 0.6 1.15 0.6 0.6 0.6 Min 3.6 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.40 -36 Max 10 0.55 0.55 0.6 0.6 0.40 1.1 0.6 1.15 0.6 0.6 0.6 Min 4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.40 -40 Max 10 0.55 0.55 0.6 0.6 0.40 1.1 0.6 1.15 0.6 0.6 0.6 Min 5.0 0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 -50 Max 10 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.2 0.6 0.6 0.6 - Unit ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns Note tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP 1 Data output hold time from DQS tQH 0.35 tCLmin or tCHmin tHP -0.35 0.40 tCLmin or tCHmin tHP -0.4 0.40 tCLmin or tCHmin tHP -0.4 0.45 tCLmin or tCHmin tHP0.45 1 1 Simplified Timing @ BL=2, CL=4 tCH tCK tCL 0 CK, CK 1 2 3 4 5 6 7 8 CS tDQSCK tIS tIH tDQSS tDQSH tDQSL DQS tRPRE tRPST tWPREH tWPRES tDS tDH tDQSQ tAC DQ Qa1 Qa2 Db0 Db1 DM COMMAND READA WRITEB - 13 - Rev 1.0 (Mar. 2004) K4D553238F-JC 256M GDDR SDRAM Note 1 : - The JEDEC GDDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL4, BL2) tHP 0 CK, CK 1 2 3 4 5 CS DQS tDQSQ(max) tQH tDQSQ(max) DQ Qa0 Qa1 COMMAND READA - 14 - Rev 1.0 (Mar. 2004) K4D553238F-JC AC CHARACTERISTICS (I) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read command Power down exit time Refresh interval time 256M GDDR SDRAM Symbol -2A Min 16 17 11 5 3 5 3 4 4 3 1 2 9 200 3tCK +tIS -33 Max 100K - -36 Max 100K - -40 Max 100K - Min 16 17 11 5 3 5 3 4 4 3 1 2 9 200 3tCK +tIS Min 16 17 11 4 2 5 3 4 4 2 1 2 9 200 3tCK +tIS Min 13 15 9 4 2 4 3 3 3 2 1 2 7 200 3tCK +tIS Max 100K - -50 Unit Note Min Max 12 14 8 4 2 4 3 3 3 2 1 2 7 200 3tCK +tIS tRC tRFC tRAS tRCDRD tRCDW tRP tRRD tWR tWR_A tCDLR tCCD tMRD 100K - tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us 1 1 1 tDAL tXSR tPDEX tREF 7.8 - 7.8 - 7.8 - 7.8 - 7.8 - Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM (Unit : Number of Clock) AC CHARACTERISTICS (II) K4D553238F-JC2A Frequency Cas Latency 350MHz ( 2.86ns ) 4 300MHz ( 3.3ns ) 4 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 tRC 16 16 16 13 12 tRFC 17 17 17 15 14 tRAS 11 11 11 9 8 tRCDRD tRCDWR 5 3 5 3 4 2 4 2 4 2 tRP 5 5 5 4 4 tRRD 3 3 3 3 3 (Unit : Number of Clock) tDAL 9 9 9 7 7 Unit tCK tCK tCK tCK tCK K4D553238F-JC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 tRC 16 16 13 12 tRFC 17 17 15 14 tRAS 11 11 9 8 tRCDRD tRCDWR 5 3 4 2 4 2 4 2 tRP 5 5 4 4 tRRD 3 3 3 3 tDAL 9 9 7 7 Unit tCK tCK tCK tCK - 15 - Rev 1.0 (Mar. 2004) K4D553238F-JC K4D553238F-JC36 Frequency Cas Latency 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 256M GDDR SDRAM tRC 16 13 12 tRFC 17 15 14 tRAS 11 9 8 tRCDRD tRCDWR 4 2 4 2 4 2 tRP 5 4 4 tRRD 3 3 3 tDAL 9 7 7 Unit tCK tCK tCK K4D553238F-JC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 tRC 13 12 tRFC 15 14 tRAS 9 8 tRCDRD tRCDWR 4 2 4 2 tRP 4 4 tRRD 3 3 tDAL 7 7 Unit tCK tCK K4D553238F-JC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 tRC 12 tRFC 14 tRAS 8 tRCDRD tRCDWR 4 2 tRP 4 tRRD 3 tDAL 7 Unit tCK Simplified Timing(2) @ BL=4 0 CK, CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 BA[1:0] BAa BAa BAa BAa BAb BAa BAb A8/AP Ra Ra Ca Ra Rb ADDR (A0~A7, Ra A9,A10) Ra Rb Ca Cb WE DQS DQ Da0 Da1 Da2 Da3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM COMMAND ACTIVEA WRITEA PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRC tRP tRRD Normal Write Burst (@ BL=4) Multi Bank Interleaving Write Burst (@ BL=4) - 16 - Rev 1.0 (Mar. 2004) K4D553238F-JC PACKAGE DIMENSIONS (144-Ball FBGA) A1 INDEX MARK 256M GDDR SDRAM 12.0 12.0 0.8x11=8.8 0.10 Max A1 INDEX MARK 0.8 B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2 0.8 0.8x11=8.8 0.45 ± 0.05 0.40 0.35 ± 0.05 1.40 Max 0.40 Unit : mm - 17 - Rev 1.0 (Mar. 2004)