Industrial Temperature K4E660412E,K4E640412E CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification - K4E660412E-JI/P(3.3V, 8K Ref., SOJ) - K4E640412E-JI/P(3.3V, 4K Ref., SOJ) - K4E660412E-TI/P(3.3V, 8K Ref., TSOP) - K4E640412E-TI/P(3.3V, 4K Ref., TSOP) • Extended Data Out Mode operation • CAS-before-RAS refresh capability • R AS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • LVTTL(3.3V) compatible inputs and outputs • Active Power Dissipation Unit : mW S peed -45 -50 -60 • Refresh Cycles Part NO. K4E660412E* K4E640412E Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS CAS W Control Clocks VBB Generator Vcc Vss
• Early Write or output enable controlled write • JEDEC Standard pinout • Available in Plastic SOJ and TSOP(II) packages • + 3.3V±0.3V power supply • Industrial Temperature operating ( -40~85°C ) 4K 432 396 360
8K 324 288 252
FUNCTIONAL BLOCK DIAGRAM
Refresh Control Refresh Counter Memory Array 16,777,216 x 4 Cells
S e n s e A m p s & I /O
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS -before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) • Performance Range Speed -45 -50 -60
Refresh Timer
Row Decoder Data in Buffer DQ0 to DQ3 Data out Buffer
t RAC
45ns 50ns 60ns
t CAC
12ns 13ns 15ns
t RC
74ns 84ns 104ns
t HPC
17ns 20ns 25ns
A0~A12 (A0~A11)*1 A0~A10 (A0~A11)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Industrial Temperature K4E660412E,K4E640412E
PIN CONFIGURATION (Top Views)
• K4E660412E-J • K4E640412E-J V CC DQ0 DQ1 N.C N.C N.C N.C W RAS A0 A1 A2 A3 A4 A5 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS V CC DQ0 DQ1 N.C N.C N.C N.C W RAS A0 A1 A2 A3 A4 A5 V CC • K4E660412E-T • K4E640412E-T
CMOS DRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(J : 400mil SOJ)
(T : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name A0 - A12 A0 - A11 DQ0 - 3 VSS RAS CAS W OE VCC N.C
Pin Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
Industrial Temperature K4E660412E,K4E640412E
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to V SS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VO U T V CC Tstg PD IOS Address Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Units V V °C W mA
CMOS DRAM
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VC C VSS VI H V IL Min 3.0 0 2.0 -0.3 *2
(Voltage referenced to Vss, TA= -40 to 85°C)
Typ 3.3 0 Max 3.6 0 Vcc+0.3 0.8
*1
Units V V V V
*1 : Vcc+1.3V at pulse width ≤ 15ns which is measured at VC C *2 : -1.3 at pulse width ≤15ns which is measured at V SS
DC AND OPERATING CHARACTERISTICS
Parameter Input Leakage Current (Any input 0≤V I N≤V CC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0V≤V OUT ≤ VCC ) Output High Voltage Level(IO H=-2mA) Output Low Voltage Level(IOL=2mA)
(Recommended operating conditions unless otherwise noted.)
Symbol II(L) Min -5 Max 5 Units uA
IO(L) VO H VOL
-5 2.4 -
5 0.4
uA V V
Industrial Temperature K4E660412E,K4E640412E
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed K4E660412E ICC1 Don ′t care Normal L Don ′t care -45 -50 -60 Don ′t care -45 -50 -60 -45 -50 -60 Don′t care -45 -50 -60 Don′t care Don′t care 90 80 70 1 1 90 80 70 100 90 80 0.5 200 120 110 100 350 350 Max K4E640412E 120 110 100 1 1 120 110 100 100 90 80 0.5 200 120 110 100 350 350 mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA Units
CMOS DRAM
ICC2
ICC3
ICC4
Don ′t care Normal L Don ′t care L L
ICC5
ICC6
ICC7 IC C S
ICC1 * : Operating Current (RAS and CAS, Address cycling @tRC =min.) ICC2 : Standby Current (RAS =CAS=W=V IH) ICC3 * : RAS-only Refresh Current (CAS=V IH , RAS, Address cycling @ t RC=min.) ICC4 * : Extended Data Out Mode Current (RAS=VIL , CAS, Address cycling @ t HPC =min.) ICC5 : Standby Current (RAS =CAS=W=V CC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and CAS cycling @ tRC =min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VI H)=VC C-0.2V, Input low voltage(VIL)=0.2V, CAS =CAS-before-RAS cycling or 0.2V W, OE =VI H, Address=Don′t care, DQ=Open, TR C=31.25us ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=V CC -0.2V or 0.2V, DQ0 ~ DQ3=V CC-0.2V, 0.2V or Open
*Note :
ICC1 , I CC3 , IC C 4 a nd I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , IC C 3 a nd I CC6, address can be changed maximum once while RAS=V IL . In I CC4 , address can be changed maximum once within one EDO mode cycle time, t HPC .
Industrial Temperature K4E660412E,K4E640412E
CAPACITANCE (TA=25°C,
Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS , CAS, W, OE ] Output capacitance [DQ0 - DQ3]
CMOS DRAM
Symbol CIN1 CIN2 CDQ Min Max 5 7 7 Units pF pF pF
VCC=3.3V, f=1MHz)
Test condition : VC C=3.3V ±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Symbol
AC CHARACTERISTICS (-40 °C≤TA≤85°C, See note 2)
-45 Min Max Min 84 113 45 12 23 3 3 3 1 25 45 8 35 7 11 9 5 0 7 0 7 23 0 0 0 7 6 8 7 0 5K 33 22 10K 50 13 3 3 3 1 30 50 8 38 8 11 9 5 0 7 0 7 25 0 0 0 7 7 8 7 0 10K 37 25 10K 50 13 50 13 25 3 3 3 1 40 60 10 40 10 14 12 5 0 10 0 10 30 0 0 0 10 10 10 10 0 10K 45 30 10K 50 13 -50 Max Min 104 138 60 15 30 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 8 8 16 4 10 3,4,10,12 3,4,5,12 3,10,12 3 6,13 3 2 Units Note
tR C tR W C t RAC t CAC t AA t CLZ t CEZ t OLZ tT tR P t RAS t RSH t CSH t CAS t RCD t RAD t CRP t ASR t RAH t ASC t CAH t RAL t RCS t RCH t RRH t WCH tW P tR W L t CWL tD S
74 101
Industrial Temperature K4E660412E,K4E640412E
AC CHARACTERISTICS
Parameter Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay CAS precharge to W delay time Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh)
CMOS DRAM
-45 Min Max Min 7 64 128 0 24 57 35 5 10 5 24 17 47 6.5 45 24 12 8 36 3 5 10 10 10 10 4 3 3 8 5 5 5 5 100 74 -50 13 13 11 10 41 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 90 -50 13 13 13 200K 20 47 7 50 30 13 13 52 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 110 -50 13 13 13 200K 0 27 64 39 5 10 5 28 25 56 10 60 35 15 200K 64 128 0 32 77 47 5 10 5 35 -50 Max Min 10 64 128 -60 Max ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns 15,16,17 15,16,17 15,16,17 6,13 6 11 11 6 3 3 14 14 7 7 7 7 9
(Continued)
Symbol Units Note
tD H tR E F tR E F t WCS t CWD tR W D t AWD t CSR t CHR t RPC t CPA t HPC t HPRWC tC P t RASP t RHCP t OEA t OED t CPWD tOEZ t OEH t WTS t WTH t WRP t WRH t DOH tR E Z t WEZ t WED t OCH t CHO t OEP t WPE t RASS tRPS t CHS
7
Industrial Temperature K4E660412E,K4E640412E
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Hyper Page cycle time Hyper Page read-modify-write cycle time RAS pulse width (Hyper page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 89 121 50 17 28 50 12 18 39 28 29 62 40 22 52 50 200K 29 17 13 13 18 18 10K 10K 55 13 18 43 30 35 72 47 25 53 55 200K 33 18 20 20 55 18 30 10K 10K 65 15 20 50 35 39 84 54 30 61 65 200K 40 20 -50 Max Min 109 145 65 20 35 10K 10K -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 7 7 7 14 14 3,4,10,12 3,4,5,12 3,10,12 Units
CMOS DRAM
( Note 11 )
Note
tR C tR W C t RAC t CAC t AA tRAS tCAS t RSH t CSH tRAL t CWD tR W D t AWD t HPC t HPRWC t RASP t CPA t OEA t OED t OEH
79 110
Industrial Temperature K4E660412E,K4E640412E
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS -before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH (min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL (max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the t RCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that t R C D≥t R C D(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol . 7. t W C S, tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If t WCS ≥tW C S(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If t C W D≥t C W D(min), tRWD ≥ tRWD (min) and t AWD ≥t AWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH o r t RRH must be satisfied for a read cycle. 9. This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the t RAD (max) limit insures that t RAC (max) can be met. t RAD (max) is specified as a reference point only. If t RAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA . 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC , t AA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 14. t ASC ≥6ns, Assume tT = 2.0ns, if t ASC ≤6ns, then tHPC (min) and tCAS (min) must be increased by the value of "6ns-tASC ". 15. If t R A S S≥100us, then RAS precharge time must use t RPS instead of t R P. 16. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 17. For distributed CAS -before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
CMOS DRAM
Industrial Temperature K4E660412E,K4E640412E
READ CYCLE
CMOS DRAM
tR C t RAS
RAS VIH VIL -
tR P
tC R P
CAS VIH VIL -
t CSH tR C D t RSH t CAS t RAD
tCRP
t ASR
A V IH V IL -
t RAH
t ASC
tR A L t CAH
COLUMN ADDRESS
ROW ADDRESS
tR C S
W V IH V IL -
tR C H tRRH
t WEZ tAA
OE VIH VIL -
tC E Z tO E Z tOEA
tOLZ tCAC
DQ0 ~ DQ3(7) VO H V OL -
tRAC OPEN
tCLZ
t REZ
DATA-OUT
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = O PEN
CMOS DRAM
tRC tR A S
RAS VIH VIL -
tR P
tCSH t CRP
CAS V IH V IL -
tRCD
t RSH tCAS
tC R P
tRAD tASR tRAH t ASC t RAL t CAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tC W L t RWL tWCS
W VIH VIL -
t WCH tW P
OE
V IH V IL -
DQ0 ~ DQ3(7) VIH VIL -
t DS
tD H
DATA-IN
Don ′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = O PEN
CMOS DRAM
tR C t RAS
RAS V IH V IL -
tRP
tCRP
CAS V IH V IL -
tCSH tRCD tRSH tCAS tCRP
tRAD tR A L t ASR
A V IH V IL -
t RAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL t RWL
W V IH V IL -
t WP
OE
VIH VIL -
t OED tDS
t OEH tDH
DATA-IN
DQ0 ~ DQ3(7) V IH V IL -
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
READ - MODIFY - WRITE CYCLE
CMOS DRAM
tR W C tRAS
RAS V IH V IL -
tRP
t CRP
CAS V IH V IL -
tRCD t RAD
tRSH tC A S
t ASR
V IH V IL -
tRAH
t ASC
tCAH tCSH
A
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL -
t RWL tC W L tW P
tRWD
OE V IH V IL -
t OEA tOLZ tCLZ tCAC tAA t RAC
VALID DATA-OUT
tOED tOEZ tD S tDH
DQ0 ~ DQ3(7) V I/OH V I/OL -
VALID DATA-IN
Don ′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
HYPER PAGE READ CYCLE
CMOS DRAM
t RASP
RAS VIH VIL ¡ó
t RP
tCSH tC R P
CAS VIH VIL -
t RHCP tHPC tC P t HPC tCAS tC P t HPC tCAS tC P tCAS
tR C D tCAS t RAD
t ASR
A VIH VIL -
t RAH tASC
t CAH
tASC
tCAH
t ASC
tCAH
COLUMN ADDR
tASC
tCAH
t REZ
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL t RCS
W V IH V IL -
tRRH t RCH
tCAC t AA tCPA tAA tOCH tOEA tCAC tOEA t OEP
t CAC t AA t CPA
tCPA tCAC tAA t CHO t OEP
OE
VIH VIL -
t OEA tOEZ
VALID D ATA-OUT VALID D ATA-OUT
DQ0 ~ DQ3(7) VOH VOL -
tRAC
tD O H
VALID D ATA-OUT
tOEZ
tO E Z
tOLZ tCLZ
VALID DATA-OUT
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = O PEN
CMOS DRAM
t RASP
RAS V IH V IL ¡ó
tRP t RHCP
tCRP
CAS VIH VIL -
tHPC tR C D tCAS t RAD tCSH tC P t CAS
¡ó
tHPC t CP
t RSH tCAS
tASR
A V IH V IL -
tRAH
t ASC
t CAH
tASC
t CAH
¡ó
tASC
t CAH
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
¡ó
COLUMN ADDRESS
t RAL tWCS
W V IH V IL -
tW C H
tW C S
tWCH t WP t CWL
¡ó ¡ó ¡ó
tWCS
tWCH tW P t CWL t RWL
t WP tC W L
OE
VIH VIL -
DQ0 ~ DQ3(7) V IH V IL -
tDS
t DH
VALID D ATA-IN
tD S
tD H
¡ó
VALID D ATA-IN
tDS
tD H
VALID D ATA-IN
¡ó
Don ′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
HYPER PAGE READ-MODIFY-WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP t RSH tHPRWC
t CSH tC R P
tRCD t CAS t RAD t RAH
t CP tCAS t RAL t ASC
COL. ADDR COL. ADDR
tCRP
CAS
V IH V IL -
t ASR
A VIH VIL ROW ADDR
tASC
tCAH
tCAH
tRCS
W VIH VIL -
tC W L tWP t CWD tCWD t AWD tC P W D tOEA tOED
tRWL tCWL tW P
tAWD t RWD
OE V IH V IL -
t OEA
tOED tD H t CAC tAA tOEZ tDS t DH tD S
t CAC t AA
DQ0 ~ DQ3(7) V I/OH V I/OL -
tO E Z
t RAC
t CLZ t OLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
t OLZ
VALID DATA-OUT
VALID DATA-IN
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
HYPER PAGE READ AND WRITE MIXED CYCLE
CMOS DRAM
t RASP
RAS VIH VIL READ( tCAC ) R E A D (t CPA) WRITE R E A D (tAA )
tR P
t HPC t CP
CAS VIH VIL -
tHPC t CP tC P tCAS tASC
COL. ADDR
tR H C P tHPC tCAS
tRAD t ASR t RAH tASC
t CAS t CAH
tCAS t CAH
tCAH
tASC
COLUMN ADDRESS
t ASC
t CAH
COL. ADDR
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tRAL tR C S
W V IH V IL -
tR C H
t RCS
tRCH tWCS
tW C H
t RCH
t WPE tCLZ tC P A
OE VIH VIL -
tWED
DQ0 ~ DQ3(7) V I/OH V I/OL -
tOEA tCAC t AA tRAC
t WEZ
t DH tW E Z
VALID
DATA-OUT
tD S t CLZ
VALID D ATA-IN
t AA
VALID D ATA-OUT
t REZ
VALID D ATA-OUT
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
RAS - ONLY REFRESH CYCLE*
NOTE : W , OE, D IN = Don′t care DOUT = O PEN t RC
RAS V IH V IL -
CMOS DRAM
tR P
t RAS tCRP tRPC tCRP
CAS
V IH V IL -
tASR
A V IH V IL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = D on′t care
tRP
R AS VIH VIL -
tR C t RAS
t RP
tRPC tCP t CSR
tRPC t CHR
CAS
VIH VIL -
tW R P
W VIH V IL -
tWRH
DQ0 ~ DQ3(7) VO H V OL -
tC E Z OPEN
Don ′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC
RAS V IH V IL -
tRP
t RC t RAS
t RP
tRAS
tC R P
CAS V IH V IL -
tRCD
t RSH
t CHR
tRAD tASR
A V IH V IL -
t RAL t ASC tCAH
COLUMN ADDRESS
t RAH
ROW ADDRESS
tR C S
W V IH V IL -
tW R H
tAA
OE V IH V IL -
t OEA tOLZ t CAC t CLZ t CEZ tREZ tWEZ tOEZ
DATA-OUT
DQ0 ~ DQ3(7) VO H VOL -
tRAC OPEN
Don′t care Undefined
* In Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
Industrial Temperature K4E660412E,K4E640412E
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = O PEN
CMOS DRAM
tRC
RAS VIH VIL -
tR P
t RC tR A S
tR P
t RAS t CRP
tRCD
tRSH
tC H R
CAS
V IH V IL -
t RAD t ASR
A VIH VIL -
t RAH
tASC
t RAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWRH tWCS
W V IH V IL -
tWRP tWCH tWP
OE
VIH VIL -
tDS
DQ0 ~ DQ3(7) VIH VIL -
t DH
DATA-IN
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don ′t care
CMOS DRAM
tRP
RAS V IH VIL -
t RASS
tRPS
t RPC tCP t CSR tC H S
t RPC
CAS
V IH VIL -
DQ0 ~ DQ3(7) VOH VOL -
tCEZ OPEN
W
V IH VIL -
tW R P
t WRH
TEST MODE IN CYCLE
NOTE : OE , A = Don ′t care tR C tR A S tRPC tCP
CAS V IH VIL -
t RP
RAS V IH VIL -
tR P
tRPC t CSR tCHR
tWTS
W V IH VIL -
t WTH
DQ0 ~ DQ3(7) VOH VOL -
t OFF OPEN
Don′t care Undefined
Industrial Temperature K4E660412E,K4E640412E
PACKAGE DIMENSION
32 SOJ 400mil
Units : Inches (millimeters)
CMOS DRAM
#32 0 . 4 3 5 ( 11 . 06 ) 0 . 4 4 5 ( 11 . 30 ) 0 .4 0 0 ( 1 0 . 1 6 ) 0 .3 6 0 ( 9 . 1 5 ) 0 .3 8 0 ( 9 . 6 5 ) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.006 (0.15) 0.012 (0.30)
#1 0.027 (0.69) MIN 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0 . 1 4 8 ( 3 .7 6 ) MA X 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
0.0375 (0.95)
0.050 (1.27)
32 TSOP(II) 400mil
Units : Inches (millimeters)
0 .4 0 0 (1 0 . 1 6 )
0. 4 5 5 ( 11 . 5 6 )
0. 4 7 1 ( 11 . 9 6 )
0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)