KFG2816D1M-DIB

OneNAND128 FLASH MEMORY OneNAND SPECIFICATION Product OneNAND128 Part No. KFG2816Q1M-DEB KFG2816D1M-DEB KFG2816U1M-DIB VCC(core & IO) 1.8V(1.7V~1.95V) 2.65V(2.4V~2.9V) 3.3V(2.7V~3.6V) Temperature Extended Extended Industrial PKG 67FBGA(LF)/48TSOP1 67FBGA(LF)/48TSOP1 67FBGA(LF)/48TSOP1 Version: Ver. 1.0 Date: June 15th, 2005 1 OneNAND128 FLASH MEMORY INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their rightful owners. Copyright © 2005, Samsung Electronics Company, Ltd 2 OneNAND128 Document Title OneNAND FLASH MEMORY Revision History Revision No. History 0.0 0.1 1. Initial Issue. 1. Corrected the errata 2. Revised Cold Reset 3. Added TSOP1 Package Information 4. Revised FBGA package type 5. Added 67FBGA Package Information 6. Revised typical tOTP, tLOCK from 300us to 600us 7. Revised max tOTP, tLOCK from 600us to 1000us 8. Deleted Lock All Block, Lock-Tight All Block Operation 9. Added Endurance and Data Retention 10. Revised Load Data into Buffer Operation Sequence 11. Revised Warm Reset 12. Revised Programmable Burst Read Latency Timing Diagram 13. Revised Multi Block Erase Flow Chart 14. Revised Extended Operating Temperature 1. Added Copyright Notice in the beginning 2. Corrected Errata 3. Updated Icc2, Icc4, Icc5, Icc6 and ISB 4. Revised INT pin description 5. Added OTP erase case NOTE 6. Revised case definitions of Interrupt Status Register 7. Added a NOTE to Command register 8. Added ECClogSector Information table 9. Removed ’data unit based data handling’ from description of Device Operation 10. Revised description on Warm/Hot/NAND Flash Core Reset 11. Revised Warm Reset Timing 12. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode 13. Revised OTP operation description 14. Added note for OTPL in Internal Register Reset 15. Removed all block lock default case after cold or warm reset 16. Added explanation for each prohibited case in protect mode 17. Revised the case of writing other commands during Multi Block Erase routine 18. Added note for Erase Suspend/Resume 19. Added supplemental explanation for ECC Operation 20. Removed classification of ECC error from ECC Operation 21. Removed redundant sentance from ECC Bypass Operation 22. Added technical note for Boot Sequence 23. Added technical note for INT pin connection guide 24. Excluded tOEH from Asynchronous Read Table 25. Revised Asycnchronous Read timing diagram for CE don’t care mode 26. Revised Asynchronous Write timing diagram for CE don’t care mode 27. Revised Load operation timing diagram for CE don’t care mode Draft Date Sep. 9, 2004 Oct. 28, 2004 Remark Advance Advance 1.0 Jun. 15, 2005 The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 3 OneNAND128 1. FEATURES • Design Technology: 0.12µm • Voltage Supply - 1.8V device(KFG2816Q1M) : 1.7V~1.95V - 2.65V device(KFG2816D1M) : 2.4V~2.9V - 3.3V device(KFG2816U1M) : 2.7V~3.6V • Organization - Host Interface:16bit • Internal BufferRAM(3K Bytes) - 1KB for BootRAM, 2KB for DataRAM • NAND Array - Page Size : (1K+32)bytes - Block Size : (64K+2K)bytes FLASH MEMORY ♦ Architecture ♦ Performance • Host Interface type - Synchronous Burst Read : Clock Frequency: up to 54MHz : Linear Burst - 4 , 8 , 16 , 32 words with wrap-around : Continuous Sequential Burst(512 words) - Asynchronous Random Read : Access time of 76ns - Asynchronous Random Write • Programmable Read latency • Multiple Sector Read - Read multiple sectors by Sector Count Register(up to 2 sectors) • Multiple Reset - Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset • Power dissipation (typical values, CL=30pF) - Standby current : 10uA@1.8V device, 15uA@2.65V/3.3V device - Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 20mA@2.65V/3.3V device - Load current : 20mA@1.8V device, 20mA@2.65V/3.3V device - Program current: 20mA@1.8V device, 20mA@2.65V/3.3V device - Erase current: 15mA@1.8V device, 18mA@2.65V/3.3V device • Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years ♦ Hardware Features • Voltage detector generating internal reset signal from Vcc • Hardware reset input (RP) • Data Protection - Write Protection mode for BootRAM - Write Protection mode for NAND Flash Array - Write protection during power-up - Write protection during power-down • User-controlled One Time Programmable(OTP) area • Internal 2bit EDC / 1bit ECC • Internal Bootloader supports Booting Solution in system ♦ Software Features • Handshaking Feature - INT pin: Indicates Ready / Busy of OneNAND - Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND • Detailed chip information by ID register ♦ Packaging • Package - 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA - 48 TSOP 1, 12mm x 20mm, 0.5mm pitch 4 OneNAND128 2. GENERAL DESCRIPTION FLASH MEMORY OneNAND is a single-die chip with standard NOR Flash interface using NAND Flash Array. This device is comprised of logic and NAND Flash Array and 3KB internal BufferRAM. 1KB BootRAM is used for reserving bootcode, and 2KB DataRAM is used for buffering data. The operating clock frequency is up to 54MHz. This device is X16 interface with Host, and has the speed of ~76ns random access time. Actually, it is accessible with minimum 4clock latency(host-driven clock for synchronous read), but this device adopts the appropriate wait cycles by programmable read latency. OneNAND provides the multiple sector read operation by assigning the number of sectors to be read in the sector counter register. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. 5 OneNAND128 3. PIN DESCRIPTION Pin Name Host Interface A15~A0 I Address Inputs - Inputs for addresses during operation, which are for addressing BufferRAM & Register. Type Nameand Description FLASH MEMORY DQ15~DQ0 I/O Data Inputs/Outputs - Inputs data during program and commands during all operations, outputs data during memory array/ register read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Interrupt Notifying Host when a command has completed. It is open drain output with internal resistor(~50kohms). After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float to hi-z condition even when the chip is deselected or when outputs are disabled. Ready Indicates data valid in synchronous read modes and is activated while CE is low Clock CLK synchronizes the device to the system bus frequency in synchronous read mode. The first rising edge of CLK in conjunction with AVD low latches address input. Write Enable WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge Address Valid Detect Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one clock cycle. > Low : for asynchronous mode, indicates valid address ;for burst mode, causes starting address to be latched on rising edge on CLK > High : device ignores address inputs Reset Pin When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up and bootloading. Chip Enable CE-low activates internal control logic, and CE-high deselects the device, places it in standby state, and places ADD and DQ in Hi-Z Output Enable OE-low enables the device’s output data buffers during a read cycle. Power for OneNAND Core This is the power supply for OneNAND Core. Power for OneNAND I/O This is the power supply for OneNAND I/O Vcc-IO is internally connected to Vcc-Core, thus should be connected to the same power supply. Ground for OneNAND Do Not Use Leave it disconnected. These pins are used for testing. No Connection Lead is not internally connected. INT O RDY O CLK I WE I AVD I RP I CE I OE Power Supply VCC-Core/Vcc I VCC-IO/Vccq VSS etc. DNU NC NOTE: Do not leave power supply(VCC, VSS) disconnected. 6 OneNAND128 4. PIN CONFIGURATION 4.1 TSOP1 FLASH MEMORY N.C A15 A14 A13 A12 A11 A10 A9 A8 WE VSS VCC INT AVD RP A7 A6 A5 A4 A3 A2 A1 A0 N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Standard Type 12mm x 20mm 0.5mm pitch 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS OE DQ15 DQ7 DQ14 DQ6 VCCQ DQ13 DQ5 DQ12 DQ4 DQ11 DQ3 DQ10 DQ2 VSS DQ9 DQ1 DQ8 DQ0 RDY CLK CE VCC (TOP VIEW, Facing Down) TSOP1 OneNAND Chip 48pin, 12mm x 20mm, 0.5mm pitch TSOP1 7 OneNAND128 4.2 67FBGA FLASH MEMORY NC NC NC NC NC NC WE RP DQ14 VSS VSS DQ13 NC NC DQ12 DQ8 DQ1 OE DQ9 VCC Core VCC IO NC DQ7 DQ4 DQ11 DQ10 DQ3 DQ15 A12 DQ0 A15 DQ5 DQ6 CLK CE DQ2 NC NC A9 A14 A13 AVD A7 A11 A8 NC INT A0 A1 NC A10 A6 NC NC RDY A4 A5 A2 A3 NC NC NC NC NC NC NC NC (TOP VIEW, Balls Facing Down) 67ball FBGA OneNAND Chip 67ball, 7.0mm x 9.0mm x max 1.0mmt , 0.8mm ball pitch FBGA 8 OneNAND128 TERMS, ABBREVIATIONS AND DEFINITIONS B (capital letter) W (capital letter) b (lower-case letter) ECC Calculated ECC Written ECC BufferRAM BootRAM DataRAM Memory Sector Byte, 8bits Word, 16bits Bit Error Correction Code FLASH MEMORY ECC which has been calculated during load or program access ECC which has been stored as data in the NAND Flash Array or in the BufferRAM On-chip Internal Buffer consisting of BootRAM and DataRAM A 1KB portion of the BufferRAM reserved for Bootcode buffering A 2KB portion of the BufferRAM reserved for Data buffering NAND Flash array which is embedded on OneNAND Partial unit of page, of which size is 512B for main area and 16B for spare area data. It is the minimum Load/Program/Copy-Back program unit while one~two sector operation is available Possible data unit to be read from memory to BufferRAM or to be programmed to memory. - 528B of which 512B is in main area and 16B in spare area - 1056B of which 1024B is in main area and 32B in spare area Data unit 9 OneNAND128 5. BLOCK DIAGRAM DQ15~DQ0 A15~A0 CLK CE Host Interface OE WE RP AVD INT RDY (Address/Command/Configuration /Status Registers) DataRAM BufferRAM BootRAM StateMachine Bootloader FLASH MEMORY NAND Flash Array Error Correction Internal Registers Logic OTP (One Block) - Host Interface - BufferRAM(BootRAM, DataRAM) - Command and status registers - State Machine (Bootloader is included) - Error Correction Logic - Memory(NAND Flash Array, OTP) NOTE: 1) At cold reset, bootloader copies boot code(1K byte size) from NAND Flash Array to BootRAM. Figure 1. Internal Block Diagram 10 OneNAND128 FLASH MEMORY Main area data (512B) BootRAM 0 Spare area data (16B) {{ BootRAM 1 DataRAM 0_0 DataRAM 0_1 Main area data (512B) DataRAM 1_0 DataRAM 1_1 { Sector Page:1KB+32B Sector(main area):512B BootRAM DataRAM 0 Spare area data (16B) Block: 64pages 64KB+2KB Sector(spare area):16B { DataRAM 1 (BufferRAM) (NAND array) Figure 2. BufferRAM and NAND array structure Main area 256W Main area 256W Spare area 8W Spare area 8W Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3 ECCm ECCm ECCm 1st 2nd 3rd LSB LSB MSB MSB LSB ECCs 1st ECCs 2nd FFh (Note3) Note4 Note4 NOTE: 1) The 1st word of spare area in 1st and 2nd page of every invalid block is reserved for the invalid block information by manufacturer. Please refer to page 59 about the details. 2) These words are managed by internal ECC logic. So it is recommended that the important data like LSN(Logical Sector Number) are written. 3) These words are reserved for the future purpose by manufacturer. These words will be dedicated to internal logic. 4) These words are for free usage. 5) The 5th, 6th and 7th words are dedicated to internal ECC logic. So these words are only readable. The other words are programmable by command. 6) ECCm 1st, ECCm 2nd, ECCm 3rd: ECC code for Main area data 7) ECCs 1st, ECCs 2nd: ECC code for 2nd and 3rd word of spare area. { { { { { { { { 1W st MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB 2W nd 3W rd 4W th 5W th 6W th 7W th 8W th Figure 3. Spare area of NAND array assignment 11 OneNAND128 6. ADDRESS MAP For OneNAND NAND Array (word order) Block Block0 Block1 Block2 Block3 Block4 Block5 Block6 Block7 Block8 Block9 Block10 Block11 Block12 Block13 Block14 Block15 Block16 Block17 Block18 Block19 Block20 Block21 Block22 Block23 Block24 Block25 Block26 Block27 Block28 Block29 Block30 Block31 Block Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block32 Block33 Block34 Block35 Block36 Block37 Block38 Block39 Block40 Block41 Block42 Block43 Block44 Block45 Block46 Block47 Block48 Block49 Block50 Block51 Block52 Block53 Block54 Block55 Block56 Block57 Block58 Block59 Block60 Block61 Block62 Block63 Block Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) The 2nd bit of Page and Sector address register is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 12 OneNAND128 Block Block64 Block65 Block66 Block67 Block68 Block69 Block70 Block71 Block72 Block73 Block74 Block75 Block76 Block77 Block78 Block79 Block80 Block81 Block82 Block83 Block84 Block85 Block86 Block87 Block88 Block89 Block90 Block91 Block92 Block93 Block94 Block95 Block Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block96 Block97 Block98 Block99 Block100 Block101 Block102 Block103 Block104 Block105 Block106 Block107 Block108 Block109 Block110 Block111 Block112 Block113 Block114 Block115 Block116 Block117 Block118 Block119 Block120 Block121 Block122 Block123 Block124 Block125 Block126 Block127 Block Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 13 OneNAND128 Block Block128 Block129 Block130 Block131 Block132 Block133 Block134 Block135 Block136 Block137 Block138 Block139 Block140 Block141 Block142 Block143 Block144 Block145 Block146 Block147 Block148 Block149 Block150 Block151 Block152 Block153 Block154 Block155 Block156 Block157 Block158 Block159 Block Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block160 Block161 Block162 Block163 Block164 Block165 Block166 Block167 Block168 Block169 Block170 Block171 Block172 Block173 Block174 Block175 Block176 Block177 Block178 Block179 Block180 Block181 Block182 Block183 Block184 Block185 Block186 Block187 Block188 Block189 Block190 Block191 Block Address 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 14 OneNAND128 Block Block192 Block193 Block194 Block195 Block196 Block197 Block198 Block199 Block200 Block201 Block202 Block203 Block204 Block205 Block206 Block207 Block208 Block209 Block210 Block211 Block212 Block213 Block214 Block215 Block216 Block217 Block218 Block219 Block220 Block221 Block222 Block223 Block Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block224 Block225 Block226 Block227 Block228 Block229 Block230 Block231 Block232 Block233 Block234 Block235 Block236 Block237 Block238 Block239 Block240 Block241 Block242 Block243 Block244 Block245 Block246 Block247 Block248 Block249 Block250 Block251 Block252 Block253 Block254 Block255 Block Address 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 15 OneNAND128 Detailed information of Address Map (word order) • BootRAM(Main area) -0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB 0000h~00FFh(512B) BootM 0 (sector 0 of page 0) • DataRAM(Main area) -0200h~05FFh: 4(sector) x 512byte(NAND main area) = 2KB 0200h~02FFh(512B) DataM 0_0 (sector 0 of page 0) • BootRAM(Spare area) -8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B 8000h~8007h(16B) BootS 0 (sector 0 of page 0) • DataRAM(Spare area) -8010h~802Fh: 4(sector) x 16byte(NAND spare area) = 64B 8010h~8017h(16B) DataS 0_0 (sector 0 of page 0) 8018h~801Fh(16B) DataS 0_1 (sector 1 of page 0) 8020h~8027h(16B) DataS 1_0 (sector 0 of page 1) 0300h~03FFh(512B) DataM 0_1 (sector 1 of page 0) 0400h~04FFh(512B) DataM 1_0 (sector 0 of page 1) FLASH MEMORY 0100h~01FFh(512B) BootM 1 (sector 1 of page 0) 0500h~05FFh(512B) DataM 1_1 (sector 1 of page 1) 8008h~800Fh(16B) BootS 1 (sector 1 of page 0) 8028h~802Fh(16B) DataS 1_1 (sector 1 of page 1) *NAND Flash array consists of 1KB page size and 64KB block size. 16 OneNAND128 Spare area assignment Equivalent to 1word of NAND Flash FLASH MEMORY Buf. BootS 0 Word Address 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h Byte Address 10000h 10002h 10004h 10006h 10008h 1000Ah 1000Ch 1000Eh 10010h 10012h 10014h 10016h 10018h 1001Ah 1001Ch 1001Eh 10020h 10022h 10024h 10026h 10028h 1002Ah 1002Ch 1002Eh 10030h 10032h 10034h 10036h 10038h 1003Ah 1003Ch 1003Eh F E D C B A 9 8 BI 7 6 5 4 3 2 1 0 Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1 ) st Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Free Usage BI Reserved for the current and future use FFh(Reserved for the future use) BootS 1 8008h 8009h 800Ah 800Bh 800Ch 800Dh 800Eh 800Fh Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1 ) st Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Free Usage BI Reserved for the current and future use FFh(Reserved for the future use) DataS 0_0 8010h 8011h 8012h 8013h 8014h 8015h 8016h 8017h Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage BI Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use DataS 0_1 8018h 8019h 801Ah 801Bh 801Ch 801Dh 801Eh 801Fh 17 OneNAND128 Equivalent to 1word of NAND Flash FLASH MEMORY Buf. DataS 1_0 Word Byte Address Address 8020h 8021h 8022h 8023h 8024h 8025h 8026h 8027h 10040h 10042h 10044h 10046h 10048h 1004Ah 1004Ch 1004Eh 10050h 10052h 10054h 10056h 10058h 1005Ah 1005Ch 1005Eh F E D C B A 9 8 BI 7 6 5 4 3 2 1 0 Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage BI Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use DataS 1_1 8028h 8029h 802Ah 802Bh 802Ch 802Dh 802Eh 802Fh NOTE: - BI: Invalid block Information >Host can use complete spare area except BI and ECC code area. For example, Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation. >OneNAND automatically generates ECC code for both main and spare data of memory during program operation in case of ’with ECC’ mode , but does not update ECC code to spare bufferRAM. >When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register as it is. 18 OneNAND128 7. Detailed address map for registers Address (word order) F000h F001h F002h F003h F004h F005h F006h F007h~F0FFh F100h F101h F102h F103h F104h F105h F106h F107h F108h~F1FFh Address (byte order) 1E000h 1E002h 1E004h 1E006h 1E008h 1E00Ah 1E00Ch 1E00Eh~1E1FEh 1E200h 1E202h 1E204h 1E206h 1E208h 1E20Ah 1E20Ch 1E20Eh 1E210h~1E3FEh Name Manufacturer ID Device ID Version ID Data Buffer size Boot Buffer size Amount of buffers Technology Reserved Start address 1 Start address 2 Start address 3 Start address 4 Start address 5 Start address 6 Start address 7 Start address 8 Reserved Host Access R R R R R R R R/W R/W R/W R/W R/W Device identification Version identification Data buffer size Boot buffer size FLASH MEMORY Description Manufacturer identification Amount of data/boot buffers Info about technology Reserved for User NAND Flash Block address Reserved Destination Block address for Copy back program Destination Page & Sector address for Copy back program N/A N/A N/A NAND Flash Page & Sector address Reserved for User Number Buffer of for the page data transfer to/from the memory and the start Buffer Address The meaning is with which buffer to start and how many buffers to use for the data transfer Reserved for User Reserved for vendor specific purposes Host control and memory operation commands Memory and Host Interface Configuration N/A Reserved for User Reserved for vendor specific purposes Controller Status and result of memory operation Memory Command Completion Interrupt Status Reserved for User Start memory block address to unlock in Write Protection mode End memory block address to unlock in Write Protection mode Current memory Write Protection status (unlocked/locked/tight-locked) Reserved for User F200h 1E400h Start Buffer R/W F201h~F207h F208h~F21Fh F220h F221h F222h F223h~F22Fh F230h~F23Fh F240h F241h F242h~F24Bh F24Ch F24Dh F24Eh F24Fh~FEFFh 1E402h~1E40Eh 1E410h~1E43Eh 1E440h 1E442h 1E444h 1E446h~1E45Eh 1E460h~1E47Eh 1E480h 1E482h 1E484h~1E496h 1E498h 1E49Ah 1E49Ch 1E49Eh~1FDFEh Reserved Reserved Command System Configuration 1 System Configuration 2 Reserved Reserved Controller Status Interrupt Reserved Unlock Start Block Address Unlock End Block Address Write Protection Status Reserved R/W R, R/W R R/W R/W R/W R - 19 OneNAND128 Address (word order) FF00h FF01h FF02h FF03h FF04h FF05h~FFFFh Address (byte order) 1FE00h 1FE02h 1FE04h 1FE06h 1FE08h 1FE12h~1FF0Ah Name ECC Status Register ECC Result of main area data ECC Result of spare area data ECC Result of main area data ECC Result of spare area data Reserved Host Access R R R R R ECC status of sector FLASH MEMORY Description ECC error position of Main area data error for first selected Sector ECC error position of Spare area data error for first selected Sector ECC error position of Main area data error for second selected Sector ECC error position of Spare area data error for second selected Sector Reserved for vendor specific purposes 20 OneNAND128 7. Address Register (word order) 7.1 Manufacturer ID Register (R): F000h, default=00ECh 15 14 13 12 11 10 9 8 7 6 5 4 FLASH MEMORY 3 2 1 0 ManufID ManufID (Manufacturer ID): manufacturer identification, 00ECh for Samsung Electronics Corp. 7.2 Device ID Register (R): F001h, default=refer to Table1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DeviceID DeviceID (Device ID): Device Identification, Table 1. Device KFG2816Q1M KFG2816D1M KFG2816U1M DeviceID[15:0] 0004h 0005h 0005h 7.3 Version ID Register (R): F002h : N/A 21 OneNAND128 7.4 Data Buffer size Register(R): F003h, default=0400h 15 14 13 12 11 10 9 8 7 6 5 4 FLASH MEMORY 3 2 1 0 DataBufSize DataBufSize: total data buffer size in words in the memory interface used for shrinks Equals two buffers of 512 words each(2x512=2N, N=10) 7.5 Boot Buffer size Register (R): F004h, default=0200h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BootBufSize BootBufSize: total boot buffer size in words in the memory interface (512 words=29, N=9) 7.6 Amount of Buffers Register (R): F005h, default=0201h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataBufAmount DataBufAmount: the amount of data buffer=2(2 , N=1) BootBufAmount: the amount of boot buffer=1(2N, N=0) N BootBufAmount 7.7 Technology Register (R): F006h, default=0000h 15 14 13 12 11 10 9 8 Tech Tech: technology information, what technology is used for the memory 7 6 5 4 3 2 1 0 Tech 0000h 0001h 0002h-FFFFh Technology NAND SLC NAND MLC Reserved 22 OneNAND128 7.8 Start Address1 Register (R/W): F100h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 FLASH MEMORY 3 FBA 2 1 0 Reserved(00000000) FBA (NAND Flash Block Address): NAND Flash block address which will be read or programmed or erased. Device 128Mb Number of Block 256 FBA FBA[7:0] 7.9 Start Address2 Register (R/W): F101h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000000000000000) 7.10 Start Address3 Register (R/W): F102h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 FCBA 3 2 1 0 Reserved(00000000) FCBA (NAND Flash Copy Back Block Address): NAND Flash destination block address which will be copy back programmed. Device 128Mb Number of Block 256 FBA FBA[7:0] 7.11 Start Address4 Register (R/W): F103h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 FCPA 4 3 2 1 0 Reserved(00000000) Reserved FCSA FCPA (NAND Flash Copy Back Page Address): NAND Flash destination page address in a block for copy back program operation. FCPA(default value) = 000000 FCPA range : 000000~111111, 6bits for 64 pages FCSA (NAND Flash Copy Back Sector Address): NAND Flash destination sector address in a page for copy back program operation. FCSA(default value) = 0 FCSA range : 0~1, 1bits for 2 sectors 23 OneNAND128 7.12 Start Address5 Register: F104h : N/A FLASH MEMORY 7.13 Start Address6 Register: F105h : N/A 7.14 Start Address7 Register: F106h : N/A 7.15 Start Address8 Register (R/W): F107h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 FPA 4 3 2 1 Reserved 0 FSA Reserved (00000000) FPA (NAND Flash Page Address): NAND Flash start page address in a block for page read or copy back program or program operation. FPA(default value)=000000 FPA range: 000000~111111 , 6bits for 64 pages FSA (Flash Sector Address): NAND Flash start sector address in a page for read or copy back program or program operation. FSA(default value) = 0 FSA range : 0~1, 1bits for 2 sectors 7.16 Start Buffer Register (R/W): F200h, default=0000h 15 14 13 12 11 10 BSA 9 8 7 6 5 4 3 2 1 0 BSC Reserved(0000) Reserved(0000000) BSC (BufferRAM Sector Count): this field specifies the number of sectors to be read or programmed or copy back programmed. Its maximum count is 2 sectors at 0(default value)value. For a single sector access, it should be programmed as value 1 and it should be programmed as value 0 for two sectors. However internal RAM buffer reached to 1 value(max. value), it counts up to 0 value to satisfy BSC value. for example) if BSA=1101, BSC=0, then selected BufferRAM are ’1101->1100’. BSA (BufferRAM Sector Address): It is the place where data is placed and specifies the sector 0~1 in the internal BootRAM and DataRAM. BSA[3] is the selection bit between BootRAM and DataRAM. BSA[2] is the selection bit between DataRAM0 and DataRAM1. BSA[0] is the selection bit between Sector0 and Sector1 in the internal BootRAM and DataRAM. While one of BootRAM or DataRAM0 interfaces with memory, the other RAM is inaccessible. Main area data BootRAM 0 BootRAM 1 DataRAM 0_0 DataRAM 0_1 Spare area data { BootRAM DataRAM0 DataRAM 1_0 DataRAM1 DataRAM 1_1 { BSA 0000 0001 1000 1001 Sector: (512 + 16)byte BSC 1100 1101 1 0 Number of Sectors 1 sector 2 sectors 24 OneNAND128 7.17 Command Register (R/W): F220h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 FLASH MEMORY 3 2 1 0 Command Command: operation of the memory interface CMD 0000h 0013h 0080h 001Ah 001Bh 0023h 002Ah 002Ch 0071h 0094h 0095h 00B0h 0030h 00F0h 00F3h 0065h Operation Load single/multiple sector data unit into buffer Load single/multiple spare sector into buffer Program single/multiple sector data unit from buffer Program single/multiple spare area sector from buffer Copy back program Unlock NAND array block(s) from start block address to end block address Lock NAND array block(s) from start block address to end block address Lock-tight NAND array block(s) from start block address to end block address Erase Verify Read Block Erase Multi-Block Erase Erase Suspend Erase Resume Reset NAND Flash Core Reset OneNAND 1) OTP Access Acceptable command during busy 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F3h 00F0h, 00F3h 00F0h, 00F3h NOTE: 1)’Reset OneNAND’(=Hot reset) command makes the registers(except RDYpol, INTpol, IOBE, and OTPL bits) and NAND Flash core into default state as the warm reset(=reset by RP pin). This R/W register describes the operation of the OneNAND interface. Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT register.) After any command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h may be accepted during busy state of some operations. Refer to the rightmost column of the command register table above.) 25 OneNAND128 15 R/W RM 14 13 R/W BRL 12 11 10 R/W BL 9 8 R/W ECC 7 R/W RDY pol 6 R/W INT pol 5 R/W IOB E 4 FLASH MEMORY 3 R Reserved(0000) 2 1 0 R BW PS 7.18 System Configuration 1 Register (R, R/W): F221h, default=40C0h RM (Read Mode): this field specifies the selection between asynchronous read mode and synchronous read mode RM 0 1 Read Mode Asynchronous read(default) Synchronous read BRL (Burst Read Latency): this field specifies the initial access latency in the burst read transfer. BRL 000 001 010 011 100 101 110 111 Latency Cycles 8(N/A) 9(N/A) 10(N/A) 3(up to 40MHz) 4(default, min.) 5 6 7 BL (Burst Length): this field specifies the size of burst length during Sync. burst read. Wrap around and linear burst. BL 000 001 010 011 100 101~111 Burst Length(Main) 4 words 8 words 16 words 32 words Reserved Burst Length(Spare) Continuous(default) N/A ECC: Error Correction Operation, 0=with correction(default), 1=without correction(by-passed) RDYpol: RDY signal polarity 0=low for ready, 1=high for ready((default) INTpol: INT Pin polarity 0=low for Interrupt pending , 1=high for Interrupt pending (default) INTpol 0 1 INT bit of Interrupt Status Register 0 0 INT Pin output 1 0 IOBE: I/O buffer enable for INT and RDY signals, INT and RDY outputs are HighZ at power-up, bit 7 and 6 become valid after IOBE is set to1. IOBE can be reset only by Cold reset or by writing 0 to bit 5 of System Configuration 1 register. 0=disable(default), 1=enable BWPS: boot buffer write protect status, 0=locked(fixed) 26 OneNAND128 7.19 System Configuration 2 Register : F222h : N/A FLASH MEMORY 7.22 Controller Status Register (R): F240h, default=0000h 15 OnGo 14 Lock 13 Load 12 Prog 11 Erase 10 Error 9 Sus 8 PRp 7 RSTB 6 OTPL 5 4 3 2 1 0 TO (0) Reserved(000000) OnGo: this bit shows the overall internal status of OneNAND 0=ready, 1=busy Lock: this bit shows whether host loads data from NAND Flash array into locked BootRAM or programs/erases locked block of NAND Flash array. Lock 0 1 Locked/Unlocked Check Result Unlocked Locked Error (Current Sector/Page Write Result): this bit shows current sector/page Load/Program/Copy Back Program/Erase result of flash memory or whether host puts invalid command into the device. Error 0 1 Current Sector/Page Load/Program/CopyBack. Program/Erase Result and Invalid Command Input Pass Fail Sus (Erase Suspend/Resume):this bit shows the Erase Suspend Status. Sus 0 1 Erase Suspend Status Erase Resume(Default) Erase Suspend OTPL (OTP Lock Status):this bit shows OTP block is locked or unlocked. OTPL bit is automatically updated at power-on. OTPL 0 1 OTP Locked/Unlocked Status OTP Block Unlock Status(Default) OTP Block Lock Status(Disable OTP Program/Erase) TO (Time Out): time out for read/program/copy back program/erase 0=no time out(fixed) Load : this bit shows the Load operation status 0=ready(default), 1=busy or error case, refer to the table 3 Prog (Program Busy) : this bit shows the Program operation status 0=ready(default), 1=busy or error case, refer to the table 3 Erase (Erase Busy) : this bit shows the Erase operation status 0=ready(default), 1=busy or error case, refer to the table 3 RSTB (Reset Busy) : this bit shows the Reset operation status 0=ready(default), 1=busy or error case, refer to the table 3 27 OneNAND128 Table 3. Controller Status Register output for modes. Mode Load Ongoing Program Ongoing Erase Ongoing Reset Ongoing Multi-Block Erase Ongoing Erase Verify Read Ongoing Load OK Program OK Erase OK Erase Verify Read OK3) Load Fail1) Program Fail Erase Fail Erase Verify Read Fail3) Load Reset2) Program Reset Erase Reset Erase Suspend Program Lock Erase Lock Load Lock(Buffer Lock) OTP Program Fail(Lock) OTP Program Fail OTP Erase Fail Program Ongoing(Susp.) Load Ongoing(Susp.) Program Fail(Susp.) Load Fail(Susp.) Invalid Command Invalid Command(Susp.) FLASH MEMORY Controller Status Register [15:0] OnGo 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Lock 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 Load 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 Prog 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 Erase 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 1 1 1 1 0 1 Error 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 Sus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 Reserved(0) RSTB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPL Reserved(0) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 TO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE: 1. ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable) 2. ERm and ERs bits in ECC status register at Load Reset case are 00. (No error) 3. Multi Block Erase status should be checked by Erase Verify Read operation. 4. OTP Erase does not update the register and the previous value is kept. 28 OneNAND128 15 INT Bit Address 15 14 13 12 11 10 9 8 7 RI 6 WI 5 EI 4 FLASH MEMORY 3 2 1 0 7.23 Interrupt Status Register (R/W): F241h, default=8080h(after Cold reset),8010h(after Warm/Hot reset) Reserved(0000000) Bit Name INT(interrupt): the master interrupt bit - Set to ’1’ of itself when one or more of RI, WI, EI and RSTI is set to ’1’, or Unlock(0023h), Lock(002Ah), Locktight(002Ch), or Erase Verify Read(0071h), or OTP access(0065h) operation, or "Load Data into Buffer" is completed. - Cleared to ’0’ when by writing ’0’ to this bit or by reset(Cold/Warm/Hot reset). ’0’ in this bit means that INT pin is low status. (This INT bit is directly wired to the INT pin on the chip. INT pin goes low upon writing ’0’ to this bit when INTpol is high and goes high upon writing ’0’ to this bit when INTpol is low. ) 7 RI(Read Interrupt): - Set to ’1’ of itself at the completion of Load Operation (0000h, 0013h, or boot is done.) - Cleared to ’0’ when by writing ’0’ to this bit or by reset (Cold/Warm/Hot reset). 6 WI(Write Interrupt): - Set to ’1’ of itself at the completion of Program Operation (0080h, 001Ah, or 001Bh) - Cleared to ’0’ when by writing ’0’ to this bit or by reset (Cold/Warm/Hot reset). 5 EI(Erase Interrupt): - Set to ’1’ of itself at the completion of Erase Operation (0094h, 0095h, or 0030h) - Cleared to ’0’ when by writing ’0’ to this bit or by reset (Cold/Warm/Hot reset). 4 RSTI(Reset Interrupt): - Set to ’1’ of itself at the completion of Reset Operation (00B0h, 00F0h, 00F3h, or warm reset is released.) - Cleared to ’0’ when by writing ’0’ to this bit. 0 1 0 0 0 0 1 0 RSTI Reserved(0000) Valid States 0 0->1 Function Interrupt Off Interrupt Pending Default State Cold 1 Warm/Hot 1 0 0->1 Interrupt Off Interrupt Pending 0 0->1 Interrupt Off Interrupt Pending 0 0->1 Interrupt Off Interrupt Pending 0 0->1 Interrupt Off Interrupt Pending 7.24 Start Block Address (R/W): F24Ch, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 SBA 3 2 1 0 Reserved(00000000) SBA (Lock/Unlock/Lock-tight Start Block Address): Start NAND Flash block address in Write Protection mode, which follows ’Lock block command’ or ’Unlock block command’ or ’Lock-tight command’. 7.25 End Block Address (R/W): F24Dh, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 EBA 3 2 1 0 Reserved(00000000) EBA (Lock/Unlock/Lock-tight End Block Address): End NAND Flash block address in Write Protection mode, which follows ’Lock block command’ or ’Unlock block command’ or ’Lock-tight command’. EBA should be equal to or larger than SBA. Device 128Mb Number of Block 256 SBA/EBA [7:0] 29 OneNAND128 15 14 13 12 11 10 9 8 7 6 5 4 FLASH MEMORY 3 2 US 1 LS 0 LTS 7.26 NAND Flash Write Protection Status (R): F24Eh, default=0002h Reserved(0000000000000) US (Unlocked Status): ’1’ value of this bit specifies that the current block in NAND Flash is unlocked. LS (Locked Status): ’1’ value of this bit specifies that the current block in NAND Flash is in locked status. LTS (Lock-tighten Status): ’1’ value of this bit specifies that current block in NAND Flash is lock-tighten. 7.27 ECC Status Register(R): FF00h, default=0000h 15 14 13 12 11 10 9 8 7 ERm1 6 5 ERs1 4 3 ERm0 2 1 ERs0 0 Reserved(00000000) ERm (ECC Error for Main area data) & ERs (ECC Error for Spare area data) : ERm0/1 is for first/second selected sector in main of BufferRAM, ERs0/1 is for first/second selected sector in spare of BufferRAM. ERm and ERs show the number of error nits in a sector as a result of ECC check at the load operation. ERm, ERs 00 01 10 11 NOTE: 1. 3bits or more error detection is not supported. ECC Status No Error 1-bit error(correctable) 2-bit error(uncorrectable)1) Reserved 7.28 ECC Result of first selected Sector Main area data Register (R): FF01h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000) ECCposWord0 ECCposIO0 7.29 ECC Result of first selected Sector Spare area data Register (R): FF02h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 ECClogSector0 3 2 1 0 Reserved(0000000000) ECCposIO0 7.30 ECC Result of second selected Sector Main area data Register (R): FF03h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000) ECCposWord1 ECCposIO1 7.31 ECC Result of second selected Sector Spare area data Register (R): FF04h, default=0000h 15 14 13 12 11 10 9 8 7 6 5 4 ECClogSector1 3 2 1 0 Reserved(0000000000) ECCposIO1 NOTE: 1. ECCposWord: ECC error position address that selects one of Main area data(256words) 2. ECCposIO: ECC error position address which selects one of sixteen DQs (DQ 0~DQ 15). 3. ECClogSector: ECC error position address that selects one of the 2nd word and LSB of the 3rd word of spare area. Refer to the below table. ECClogSector Information [5:4] ECClogSector 00 01 10, 11 4. ECCposWord, ECCposIO and ECClogSector are updated in boot loading operation, too. Error Position 2nd word 3rd word Reserved 30 OneNAND128 8. Device Operation FLASH MEMORY The device supports both a limited command based and a register based interface for performing operations on the device, reading device ID, writing data to buffer etc. The command based interface is active in the boot partition, i.e. commands can only be written with a boot area address. Boot area data is only returned if no command has been issued prior to the read. 8.1 Command based operation The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition. Writes outside the boot partition are treated as normal writes to the buffers or registers. The command consists of one or more cycles depending on the command. After completion of the command the device starts its execution. Writing incorrect information which include address and data or writing an improper command will terminate the previous command sequence and make the device go to the ready status. The defined valid command sequences are stated in Table4. Table 4. Command Sequences Command Definition Read Data from Buffer Write Data to Buffer Reset OneNAND Load Data into Buffer3) Read Identification Data 6) Add Data Add Data Add Data Add Data Add Data Cycles 1 1 1 2 2 1st cycle DP 1) 2nd cycle Data DP Data BP2) 00F0h BP 00E0h BP 0090h BP 0000h4) XXXXh5) Data NOTE: 1) DP(Data Partition) : DataRAM Area 2) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh]. 3) Load Data into Buffer operation is available within a block(64KB) 4) Load 1KB unit into DataRAM0. Current Start address(FPA) is automatically incremented by 1KB unit after the load. 5) 0000h -> Data is Manufacturer ID 0001h -> Data is Device ID 0002h -> Current Block Write Protection Status 6) WE toggling can terminate ’Read Identification Data’ operation. 8.1.1 Read Data from Buffer Buffer can be read by addressing a read to a wanted buffer area 8.1.2 Write Data to Buffer Buffer can be written by addressing a write to a wanted buffer area 8.1.3 Reset OneNAND Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device. 8.1.4 Load Data into Buffer Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0. This operation refers to FBA and FPA. FSA, BSA, and BSC are not considered. At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load data in next page to DataRAM0. This page address increment is restricted within a block. The default value of FBA and FPA is 0. Therefore, initial issue of this command after power on will load the first page of memory, which is usually boot code. 8.1.5 Read Identification Data Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given address. The first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in Table5. 31 OneNAND128 Table 5. Identification data description Address 0000h 0001h 0002h Manufacturer ID Device ID Current Block Write Protection Status Data Out FLASH MEMORY 00ECh refer to table 1 refer to NAND Flash Write Protection Status Register 8.2 Device Bus Operations Operation Standby Warm Reset Asynchronous Write CE H X L OE X X H WE X X L ADD0~15 X X Add. In DQ0~15 High-Z High-Z Data In RP H L H CLK X X L AVD X X Asynchronous Read L L H Add. In Data Out H L Load Initial Burst Address L H H Add. In X Burst Data Out High-Z High-Z H Burst Read Terminate Burst Read Cycle Terminate Burst Read Cycle via RP Terminate Current Burst Read Cycle and Start New Burst Read Cycle L L H X H X H X X X H X X X H L X X X X H H Add In High-Z H Note : L=VIL (Low), H=VIH (High), X=Don’t Care. 32 OneNAND128 8.3 Reset Mode Cold Reset FLASH MEMORY At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases internal power-up reset signal which triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data(1KB) from the beginning of memory to the BootRAM. POR triggering level System Power 1) OneNAND Operation Sleep Bootcode copy 2) RP Bootcode - copy done Idle INT High-Z 3) INT bit 0 (default) 1 IOBE bit INTpol bit 0 (default) 1 (default) 1 Note: 1) Bootcode copy operation starts 400us later than POR activation. The system power should reach 1.7V after POR triggering level(typ. 1.5V) within 400us for valid boot code data. 2) 1K bytes Bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of NAND Flash array to BootRAM. Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion. 3) INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge. If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’ Figure 5. Cold Reset Timings 33 OneNAND128 Warm Reset FLASH MEMORY Warm reset means that the host resets the device by RP pin, and then the device stops all logic current operation and executes internal reset operation(Note 1) synchronized with the falling edge of RP and resets current NAND Flash core operation synchronized with the rising edge of RP. The device logic will not be reset in case RP pulses shorter than 200ns, but the device guarantees the logic reset operation in case RP pulse is longer than 200ns. NAND Flash core reset will abort current NAND Flash Core operation. The contents of memory cells being altered are no longer valid as the data will be partially programmed or erased. Warm reset has no effect on contents of BootRAM and DataRAM. CE, OE RP initiated by RP low MuxOneNAND Operation initiated by RP high Operation or Idle internal reset operation NAND Flash core reset Idle Operation Operation or Idle INT High-Z High-Z High-Z RDY Figure 6. Warm Reset Timings 34 OneNAND128 FLASH MEMORY Hot Reset Hot reset means that the host resets the device by reset command(Note 2), and then the device logic stops all current operation and executes internal reset operation(Note 1) , and resets current NAND Flash core operation. Hot reset has no effect on contents of BootRAM and DataRAM. AVD BP(Note 3) or F220h 00F0h or 00F3h A0~A15 DQ0~DQ15 CE WE INT RDY OneNAND Operation High-Z Operation or Idle OneNAND reset Idle Figure 7. Hot Reset Timings NOTE: 1. Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept unchanged after Warm/Hot reset operations. 2. Reset command : Command based reset or Register based reset 3. BP(Boot Partition) : BootRAM area[0000h~01FFh, 8000h~800Fh] 35 OneNAND128 FLASH MEMORY NAND Flash Core Reset Host can reset NAND Flash Core operation by NAND Flash Core reset command. NAND Flash Core Reset will abort the current NAND Flash core operation. During a NAND Flash Core Reset, the content of memory cellls being altered is no longer valid as the data will be partially programmed or erased. NAND Flash Core Reset has an effect on neither contents of BootRAM and DataRAM nor register values. AVD A0~A15 F220h DQ0~DQ15 CE 00F0h WE INT RDY OneNAND Operation High-Z Operation or Idle NAND Flash Core reset Idle Figure 8. NAND Flash Core Reset Timings 36 OneNAND128 Table 6. Internal Register reset Internal Registers F000h F001h F002h F003h F004h F005h F006h F100h F101h F102h F103h F107h F200h F220h F221h F240h F241h F24Ch F24Dh F24Eh FF00h FF01h FF02h FF03h FF04h Manufacturer ID Register (R) Device ID Register (R) Version ID Register (rR) Data Buffer size Register (R) Boot Buffer size Register (R) Amount of Buffers Register (R) Technology Register (R) Start Address1 Register (R/W): FBA Start Address2 Register (R/W): Reserved Start Address3 Register (R/W): FCBA Start Address4 Register (R/W): FCPA, FCSA Start Address8 Register (R/W): FPA, FSA Start Buffer Register (R/W): BSA, BSC Command Register (R/W) System Configuration 1 Register (R/W) Controller Status Register (R) Interrupt Status Register (R/W) Lock/Unlock Start Block Address (R/W) Lock/Unlock End Block Address (R/W) NAND Flash Write Protection Status (R) ECC Status Register (R) (Note2) ECC Result of Sector 0 Main area data Register(R) ECC Result of Sector 0 Spare area data Register (R) ECC Result of Sector 1 Main area data Register(R) ECC Result of Sector 1 Spare area data Register (R) FLASH MEMORY Default Cold Reset 00ECh Note3 0400h 0200h 0201h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 40C0h 0000h 0000h 0000h 0002h 0000h 0000h 0000h 0000h 0000h N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 0000h 40C0h 0000h 8080h 0000h 0000h 0002h 0000h 0000h 0000h 0000h 0000h Warm Reset (RP) N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 0000h O (Note1) 0000h 8010h 0000h 0000h 0002h 0000h 0000h 0000h 0000h 0000h Hot Hot NAND Flash Reset Reset Reset(00F0h) (00F3h) (BP-F0) N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 0000h O (Note1) 0000h 8010h N/A N/A N/A 0000h 0000h 0000h 0000h 0000h N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A NOTE: 1) RDYpol, INTpol, and IOBE are reset by Cold reset. The other bits are reset by Cold/Warm/Hot reset. OTPL is not reset but updated by Cold reset. 2) ECC Status Register & ECC Result Registers are reset when any command is issued. 3) Refer to table 1 37 OneNAND128 Write Protection FLASH MEMORY Write Protection for BootRAM At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which triggers bootcode loading. And the designated size data(1KB) is copied from the beginning of the memory to the BootRAM. After the bootcode loading is completed, the BootRAM is always locked to protect the significant boot code from accidental write. Write Protection for NAND Flash array Write Protection Modes The device offers both hardware and software write protection features for NAND Flash array. The software write protection feature is used by writing Lock command or Lock-tight command to command register; The 002Ah or 002Ch command is written into F220h register. The partial write protection feature is also permitted by writing Partial Lock(002Ah) and Partial Lock-Tight(002Ch) command with the start address and the end address to F24Ch and F24Dh registers. The hardware write protection feature is used by executing cold or warm reset. The default state is locked, and all NAND Flash array goes to locked state after cold or warm reset. Write Protection Commands Individual or consecutive instant secured block protects code and data by allowing any block to be locked or lock-tighten. The write protection scheme offers two levels of protection. The first allows software-only control of write protection(useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed(protects infrequently changed code blocks). The following summarize the locking functionality. > All blocks power-up in a locked state. Unlock command can unlock these blocks with the start and end block address. > Partial Lock-Tight command makes the part of locked block(s) to be lock-tightened by writing the start and end block address. And lock-tightened state can be returned to lock state only when cold or warm reset is asserted. > Only one individual area can be lock-tightened by Partial Lock-tight command; i.e lock-tightening multi area is not available. > Lock-tightened blocks offer the user an additional level of write protection beyond that of a regular locked block. Lock-tightened block can’t have it’s state changed by software, it can be changed by warm reset or cold reset. > Unlock start or end block address is reflected immediately to the device only when Unlock command is issued, and NAND Flash write protection status register is also updated at that time. > Unlocked blocks can be programmed or erased. > Only one area can be released from lock state to unlock state with Unlock command and addresses. This unlocked area can be changed with new Unlock command; when new Unlock command is issued, last unlocked area is locked again and new area is unlocked. > Partial Lock command makes the part of unlocked block(s) to be locked with the start and end block address. > Only one area can be locked with Partial Lock command and address. This locked area can be changed with new Partial Lock command; when new Partial Lock command is issued, last unlocked area is locked again and new area is unlocked. Write Protection Status The block current Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits US, LS, LTS -, which are not cleared by hot reset. These Write Protection status registers are updated when Write Protection command is entered. The followings summarize locking status. example) In default, [2:0] values are 010. -> If host executes unlock block operation, then [2:0] values turn to 100. -> If host executes lock-tight block operation, then [2:0] values turn to 001. 38 OneNAND128 FLASH MEMORY Locked > Command Sequence : Start block address+End block address+Lock block command (002Ah) > All blocks default to be locked after Cold reset or Warm reset > Unlocked blocks can be locked by using the Lock block command and a lock block’s status can be changed to unlock or lock-tight using the appropriate software commands Unlocked > Command Sequence : Start block address+End block address+Unlock block command (0023h) > Unlocked block can be programmed or erased > An unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate software command > Only one sequential area can be released to unlock state from lock state ; Unlocking multi individual area is not available Lock-tighten > Command Sequence : Start block address+End block address+Lock-tight block command (002Ch) > Lock-tighten blocks offer the user an additional level of write : protection beyond that of a regular lock block. A block that is lock-tighten cannot have its state change by software, only by Cold or Warm reset. > Only locked blocks can be lock-tighten by Lock-tight command. > Lock-tighten blocks revert to the locked state at Cold or Warm reset > Lock-tighten area does not change with any command; when new unlock command is issued including the lock-tighten area, new unlocked command is ignored. Figure 9. Operations of NAND Flash Write Protection 39 OneNAND128 SBA, EBA +Partial Lock Command Unlock Lock Lock FLASH MEMORY SBA, EBA +Partial Lock-tight Command Lock Unlock Lock SBA, EBA +Unlock Command Lock Unlock SBA, EBA +Partial Lock Command Lock Unlock SBA, EBA SBA, EBA +Partial Lock-tight +Partial Lock-tight Command Lock-tight Command Lock-tight Lock Lock SBA, EBA +Unlock Command Changed with new SBA, EBA Changed with new SBA, EBA Lock Power On Sustained with last SBA, EBA Lock-tight Lock Unlock Note ; The below cases are prohibited in write protection modes. Even though these cases happen, Error bit of Controller Status Register(F240h)is not updated. Case1. Unlock Lock-tight Lock SBA EBA If this case happens, the command is ignored and last status is sustained. Case2. Lock Lock-tight Unlock SBA EBA If this case happens, the command is ignored and last status is sustained. Case3. Lock-tight Lock Unlock SBA EBA If this case happens, the selected area changes to be lock-tight. Figure 10. State diagram of NAND Flash Write Protection 40 OneNAND128 Load Operation FLASH MEMORY The load operation is initiated by setting up the start address from which the data is to be loaded. The load command is issued in order to initiate the load. The device transfers the data from NAND Flash array into the BufferRAM. The ECC is checked and any detected and corrected error is reported in the status response as well as any unrecoverable error. When the BufferRAM has been filled an interrupt is issued to the host in order to read the contents of the BufferRAM. The read from the BufferRAM consist of asynchronous read mode or synchronous read mode. The status information related to the BufferRAM fill operation can be checked by the host if required. The device provides dual data buffer memory architecture. The device is capable of data-read operation from one data buffer and data-load operation to the other data buffer simultaneously. Refer to the information for more details in "Read while Load operation". Start Write ’Load’ Command Add: F220h DQ=0000h or 0013h Write ’FBA’ of Flash Add: F100h DQ=FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Wait for INT register low to high transition Add: F241h DQ[15]=INT Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Read Controller Status Register Add: F240h DQ[10]=Error Write 0 to interrupt register Add: F241h DQ=0000h DQ[10]=0? YES Host reads data from DataRAM NO Map Out Read completed Figure 11. Load operation flow-chart 41 OneNAND128 Read Operation FLASH MEMORY The device has two read configurations ; Asynchronous read and Synchronous burst read. The initial state machine makes the device to be automatically entered into asynchronous read mode to prevent the memory content from spurious altering upon device power up or after a hardware reset. No commands are required to retrieve data in asynchronous mode. The synchronous mode will be enabled by setting RM bit of System configuration1 register to Synchronous read mode. Asynchronous Read Mode (RM = 0) For the asynchronous read mode a valid address should be asserted on A0-A15, while driving AVD and CE to VIL. WE should remain at VIH . The data will appear on DQ15-DQ0. Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. Synchronous (Burst) Read Mode (RM = 1) The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the initial word(tIAA) is output asynchronously regardless of BRL bit in System Configuration 1 register. But the host should determine BRL bit of System configuration 1 register for the subsequent words of each burst access. The registers also can be read during burst read mode by using AVD signal with a address. To initiate the synchronous read again, a new address during CE and AVD low toggle is needed after the host has completed status reads or the device has completed the program or erase operation. Continuous Linear Burst Read The initial word(tIAA) is output asynchronously regardless of BRL bit in System Configuration 1 register. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around after it reaches the designated location(See Figure 12 for address map information) until the system asserts CE high, RP low or AVD low in conjunction with a new address. The cold/warm/hot reset or asserting CE high or WE low pulse terminate the burst read operation. If the device is accessed synchronously while it is set to asynchronous read mode, it is possible to read out the first data without problems. Division BootM(0.5Kw) BufM 0(0.5Kw) BufM 1(0.5Kw) Reserved Main BootS(16w) BufS 0(16w) BufS 1(16w) Reserved Spare Reserved Reg. Register(4Kw) Add.map(word order) 0000h~01FFh 0200h~03FFh 0400h~05FFh 0600h~7FFFh 8000h~800Fh 8010h~801Fh 8020h~802Fh 8030h~8FFFh 9000h~EFFFh F000h~FFFFh Buffer0 Buffer1 N/A Reg. Not Support Not Support Buffer0 Not Support Buffer1 N/A Reg. Reg. * Reserved area is not available on Synchronous read Figure 12. The boundary of synchronous read 42 OneNAND128 4-, 8-,16-, 32- Word Linear Burst Read FLASH MEMORY As well as the Continuous Linear Burst Mode, there are four(4 & 8 & 16 & 32 word) (Note1) linear wrap-around mode, in which a fixed number of words are read from consecutive addresses. When the last word in the burst mode is reached, assert /CE and /OE high to terminate the operation. In these modes, the start address for burst read can be any address of address map. (Note 1) 32 word linear burst read isn’t available on spare area BufferRAM Table 7. Burst Address Sequences Start Addr. 0 Wrap around 1 2 . . Burst Address Sequence(Decimal) Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... . . 4-word Burst 0-1-2-3-0... 1-2-3-0-1... 2-3-0-1-2... . . 8-word Burst 0-1-2-3-4-5-6-7-0... 1-2-3-4-5-6-7-0-1... 2-3-4-5-6-7-0-1-2... . . 16-word Burst 0-1-2-3-4-....-13-14-15-0... 1-2-3-4-5-....-14-15-0-1... 2-3-4-5-6-....-15-0-1-2... . . 32-word Burst 0-1-2-3-4-....-29-30-31-0... 1-2-3-4-5-....-30-31-0-1... 2-3-4-5-6-....-31-0-1-2... . . Programmable Burst Read Latency The programmable burst read latency feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven active before data will be available. Upon power up, the number of total initial access cycles defaults to four clocks. The number of total initial access cycles is programmable from three to seven cycles. Rising edge of the clock cycle following last read latency triggers next burst data CE ≈ CLK ≈ -1 AVD 0 1 2 3 4 5 6 ≈ tBA A0: A15 DQ0: DQ15 tIAA OE Hi-Z tRDYA tRDYS Valid Address ≈ D6 D7 D0 D1 D2 D3 D7 D0 ≈ Hi-Z ≈ RDY Figure 13. Example of 4 clock Burst Read Latency Handshaking The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable burst read latency configuration.(See "System Configuration1 Register" for details.) The rising edge of RDY which is derived from 1 clock ahead of data fetch clock indicates the initial word of valid burst data. Output Disable Mode When the CE or OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state. 43 OneNAND128 Program Operation FLASH MEMORY The device can be programmed in data unit. Programming is writing 0's into the memory array by executing the internal program routine. In order to perform the Internal Program Routine, command sequence is necessary. First, host sets the address of the BufferRAM and the memory location and loads the data to be programmed into the BufferRAM. Second, program command initiates the internal program routine. During the execution of the Routine, the host is not required to provide further controls or timings. During the Internal Program Routine, commands except reset command written to the device will be ignored. Note that a reset during a program operation will cause data corruption at the corresponding location. The device provides dual data buffer memory architecture. The device is capable of data-write operation from host to one of data buffers during program operation from anther data buffer to Flash simultaneously. Refer to the information for more details in "Read while Load operation". Start Write 0 to interrupt register Add: F241h DQ=0000h Write ’Program’ Command Add: F220h DQ=0080h or 001Ah Write Data into DataRAM1) ADD: DP DQ=Data-in Data Input Completed? YES Write ’FBA’ of Flash Add: F100h DQ=FBA NO Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Add: F240h DQ[10]=Error Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC DQ[10]=0? YES Program completed NO Program Error * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Note 1) Data input could be done anywhere between "Start" and "Write Program Command". Figure 14. Program operation flow-chart 44 OneNAND128 Addressing for program operation FLASH MEMORY Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. Page 63 (64) : Page 63 (64) : Page 31 (32) : Page 31 (1) : Page 2 Page 1 Page 0 (3) (2) (1) Page 2 Page 1 Page 0 (3) (32) (2) Data register From the LSB page to MSB page DATA IN: Data (1) Data (64) Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) 45 OneNAND128 Copy-back Program Operation FLASH MEMORY The copy-back program is configured to quickly and efficiently rewrite data stored in one page by sector unit(1/2 sector) without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. Start Write ’Copy-back Program’ command Add: F220h DQ=001Bh Write ’FBA’ of Flash Add: F100h DQ=FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Wait for INT register low to high transition Add: F241h DQ[15]=INT Write ’FCBA’ of Flash Add: F102h DQ=FCBA Read Controller Status Register Add: F240h DQ[10]=Error Write ’FCPA, FCSA’ of Flash Add: F103h DQ=FCPA, FCSA DQ[10]=0? YES Copy back completed NO Copy back Error Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC1) Write 0 to interrupt register Add: F241h DQ=0000h * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Note 1) Selected DataRAM by BSA & BSC is used for Copy back operation, so previous data is overwritten. Figure 15. Copy back program operation flow-chart 46 OneNAND128 Copy-Back Program Operation with Random Data Input FLASH MEMORY The Copy-Back Program Operation with Random Data Input in OneNAND consists of 2 phase, Load data into DataRAM, Modify data and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host, then programmed into the destination page. As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load operation. Therefore, using hardware ECC of OneNAND, accumulation of 1 bit error can be avoided. Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of source page to destination page while it is being copied. Start DQ[10]=0? YES Random Data Input Add: Random Address in Selected DataRAM DQ=Data NO Map Out Write ’FBA’ of Flash Add: F100h DQ=FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Write ’FBA’ of Flash Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ’Load’ Command Add: F220h DQ=0000h or 0013h Write 0 to interrupt register Add: F241h DQ=0000h Write ’Program’ Command Wait for INT register low to high transition Add: F241h DQ[15]=INT Add: F220h DQ=0080h or 001Ah Read Controller Status Register Add: F240h DQ[10]=Error Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Add: F240h DQ[10]=Error DQ[10]=0? YES Copy back completed NO Copy back Error Figure 16. Copy-Back Program Operation with Random Data Input Flow Chart 47 OneNAND128 Erase Operation FLASH MEMORY The device can be erased in block unit. To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. In order to perform the Internal Erase Routine, command sequence is necessary. First, host sets the block address of the memory location. Second, erase command initiates the internal erase routine. During the execution of the Routine, the host is not required to provide further controls or timings. During the Internal erase routine, commands except reset and erase suspend command written to the device will be ignored. Note that a reset during a erase operation will cause data corruption at the corresponding location. Start Write ’FBA’ of Flash Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’Erase’ Command Add: F220h DQ=0094h Wait for INT register low to high transition Add: F241h DQ=[15]=INT Read Controller Status Register Add: F240h DQ[10]=Error DQ[10]=0? YES Erase completed NO Erase Error Figure 17. Erase operation flow-chart 48 OneNAND128 Multi Block Erase and Multi Block Erase Verify Read Operation FLASH MEMORY The device can be simultaneously erased in multi blocks unit, too. The block address of the memory location and Multi Block Erase command may be repeated for erasing multi blocks. The final block address and Block Erase command initiate the internal multi block erase routine. During Multi Block Erase routine, if the command except Multi Block Erase command is written before Block Erase command is issued, Multi Block Erase operation will be aborted. Erase Suspend command is allowed only when INT is Low after Block Erase command is issued. Pass/fail status of each block in Multi Block Erase operation can be read by writing each block address and Multi Block Erase Verify Read command. But the information of the failed address has to be managed by the firmware. After Block Erase operation, the pass/ fail status can be read with Multi Block Erase Verify Read command, too. Note that a reset during a erase operation will cause data corruption at the corresponding location. Write ’FBA’ of Flash Add: F100h DQ=FBA Read Controller Status Register Add: F240h DQ[10]=Error Write 0 to interrupt register Add: F241h DQ=0000h DQ[10]=0? Write 0 to interrupt register Add: F241h DQ=0000h Write ’Block Erase Command’ Add: F220h DQ=0094h Write ’Multi Block Erase’ Command Add: F220h DQ=0095h Wait for INT register low to high transition Add: F241h DQ=[15]=INT Wait for INT register low to high transition Add: F241h DQ=[15]=INT Write ’FBA’ of Flash Add: F100h DQ=FBA NO NO Final Multi Block Erase Address? YES Multi Block Erase completed Write 0 to interrupt register Add: F241h DQ=0000h Multi Block Erase Verify Read Write ’Multi Block Erase Verify Read Command’ Add: F220h DQ=0071h NO YES Erase completed Start Write ’FBA’ of Flash Add: F100h DQ=FBA Erase Error Final Multi Block Erase? YES Wait for INT register low to high transition Add: F241h DQ=[15]=INT Figure 18. Multi Block Erase operation flow-chart NOTE: 1. If there are the locked blocks in the specified range, the operation works as the follows. Case 1. [BA(1)+0095h] + [BA(2, locked)+0095h] + ... + [BA(N-1)+0095h] + [BA(N)+0094h] = All specified blocks except BA(2) are erased. Case 2. [BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA(N, locked)+0094h] = If the last command, Block Erase command, is put together with the locked block address, Multi Block Erase operation doesn’t start and is suspended until right command and address input. Case 3. [BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA(N, locked)+0094h] + [BA(N+1)+0094h]= All specified blocks except BA(N) are erased. 2. The OnGo bit of Controller Status register is set to ’1’(busy) from the time of writing the 1st block address to be latched until the actual erase has finished. 3. Even though the failed blocked happen during multi block erase operation, the device continues the erase operation until other specified blocks are erased. 49 OneNAND128 Erase Suspend / Resume FLASH MEMORY Erase Suspend command interrupts Block Erase and Multi Block Erase to load or program data in a block that is not being erased. When Erase Suspend command is written during Block Erase and Multi Block Erase operation, the device requires a maximum of 500us to suspend erase operation. After the erase operation has been suspended, the device is available for loading or programming data in a block that is not being erased. For the erase suspend period, Block Erase, Multi Block Erase and Erase Suspend commands are not accepted. When Erase Resume command is executed, Block Erase and Multi Block Erase operation will resume. The Erase Resume operation does not actually resume the erase, but starts it again from the beginning. When Erase Suspend and Erase Resume command is executed, the addresses are in Don’t Care state. Start Write 0 to interrupt register Add: F241h DQ=0000h Write 0 to interrupt register Add: F241h DQ=0000h Write ’Erase Resume Command’ Add: F220h DQ=0030h Write ’Erase Suspend Command’1) Add: F220h DQ=00B0h Wait for INT register low to high transition Add: F241h DQ=[15]=INT Wait for INT register low to high transition for 500us Add: F241h DQ=[15]=INT Check Controller Status Register in case of Block Erase Do Multi Block Erase Verify Read in case of Multi Block Erase Another Operation * * Another Operation ; Load, Program Copy-back Program, OTP Access2), Hot Reset, Flash Reset, CMD Reset, Multi Block Erase Verify, Lock, Lock-tight, Unlock Note 1) Erase Suspend command input is prohibited during Multi Block Erase address latch period. 2) If OTP access mode exit happens with Reset operation during Erase Suspend mode, Reset operation could hurt the erase operation. So if a user wants to exit from OTP access mode without the erase operation stop, Reset NAND Flash Core command should be used. Figure 19. Erase Suspend and Resume operation flow-chart 50 OneNAND128 OTP Operation FLASH MEMORY The device supports one block sized OTP area, which can be read, programmed and locked with the same sequence as normal operation. But this OTP block could not be erased. This block is separated from NAND Flash Array, so it could be accessed by OTP Access command instead of FBA. If user wants to exit from OTP access mode, Cold, Warm and Hot Reset operation should be done. But if OTP access mode exit happens with Reset operation during Erase Suspend mode, Reset operation could hurt the erase operation. So if user wants to exit from OTP access mode without the erase operation stop, ’Reset NAND Flash Core’ command should be used. OTP area is one block size(64KB, 64pages) and is divided by two areas. The first area from page 0 to page 19, total 20pages, is assigned for user and the second area from page 20 to page 63, total 44pages, are occupied for the device manufacturer. The second area is programmed prior to shipping, so this area could not be used by user. This block is fully guaranteed to be a valid block. OTP Block Page Allocation Information Area User Manufacturer Page 0 ~ 19 (20 pages) 20 ~ 63 (44 pages) Use Designated as user area Used by the device manufacturer Page:1KB+32B Sector(main area):512B One Block: 64pages 64KB+2KB Sector(spare area):16B Manufacturer Area : 20pages page 20 to page 63 User Area : 20pages page 0 to page 19 Figure 20. OTP area structure and assignment 51 OneNAND128 OTP Load(OTP Access+Load NAND) FLASH MEMORY OTP area is separated from NAND Flash Array, so it is accessed by OTP Access command instead of FBA. The content of OTP could be loaded with the same sequence as normal load operation after being accessed by the command. If user wants to exit from OTP access mode, Cold, Warm, Hot, and NAND Flash Core Reset operation should be done. Start Write ’FBA’ of Flash1) Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’Load’ Command Write 0 to interrupt register Add: F241h DQ=0000h Add: F220h DQ=0000h or 0013h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Wait for INT register low to high transition Add: F241h DQ[15]=INT Host reads data from DataRAM OTP Load completed Write ’FPA, FSA’ of Add: F107h DQ=FPA, FSA Flash1) Do Cold/Warm/Hot /NAND Flash Core reset Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC OTP Exit Note 1) FBA(NAND Flash Block Address) could be omitted or any address. Figure 21. OTP Load operation flow-chart 52 OneNAND128 OTP Programming(OTP Access+Program NAND) FLASH MEMORY OTP area could be programmed with the same sequence as normal program operation after being accessed by the command. To avoid the accidental write, FBA should point the unlocked area address among NAND Flash Array address map even though OTP area is separated from NAND Flash Array. Start Write ’FBA’ of Flash1) Add: F100h DQ=FBA Write ’FBA’ of Flash Add: F100h DQ=FBA3) Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write 0 to interrupt register Add: F241h DQ=0000h Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Write 0 to interrupt register Add: F241h DQ=0000h Write Program command Add: F220h DQ=0080h or 001Ah Automatically checked OTPL=0? YES NO Automatically updated Write Data into DataRAM2) Add: DP DQ=Data-in Data Input Completed? NO Wait for INT register low to high transition Add: F241h DQ[15]=INT Update Controller Status Register Add: F240h DQ[14]=1(Lock), DQ[10]=1(Error) Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Add: F240h DQ[10]=0(Pass) OTP Programming completed Read Controller Status Register Add: F240h DQ[10]=1(Error) Do Cold/Warm/Hot /NAND Flash Core reset Do Cold/Warm/Hot /NAND Flash Core reset OTP Exit OTP Exit Note 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "Start" and "Write Program Command". 3) FBA should point the unlocked area address among NAND Flash Array address map. Figure 22. OTP program operation flow-chart 53 OneNAND128 OTP Lock(OTP Access+Lock OTP) FLASH MEMORY OTP area could be locked by programming XXXCh to 8th word in sector0 of page0 to prevent the program operation. At the device power-up, the device automatically checks this word and updates OTPL bit of Controller Status register as "1"(lock). If the program operation happens in OTP locked status, the device updates Error bit of Controller Status register as "1"(fail). Start Write ’FBA’ of Flash Add: F100h DQ=FBA3) Write ’FBA’ of Flash1) Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’FPA, FSA’ of Flash Add: F107h DQ=0000h Write ’BSA, BSC’ of DataRAM Add: F200h DQ=0001h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Write Data into DataRAM2) Add: 8th Word in spare0/sector0/page0 DQ=XXXCh Write 0 to interrupt register Add: F241h DQ=0000h Write Program command Add: F220h DQ=0080h or 001Ah Wait for INT register low to high transition Add: F241h DQ[15]=INT Do Cold reset Automatically updated Update Controller Status Register Add: F240h DQ[6]=1(OTPL) OTP lock completed Note 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "Start" and "Write Program Command". 3) FBA should point the unlocked area address among NADND Flash Array address map. Figure 23. OTP lock operation flow-chart 54 Read While Load Int_ reg 0000h LD_ CMD Flash _add 0000h Read Status LD_ CMD DB1 _add CMD_ reg CS_ reg Page B Add_ reg Add_ reg CMD_ reg Int_ reg Data Load 2) _DB1 ADD 0~15 Page A Add_ reg Add_ reg DQ OneNAND128 0~15 Flash _add DB0 _add 1) Data Load _DB0 1) Data Load _DB0 DB0_radd* Data Load 2) _DB1 Data Read _DB0 * WE OE INT 55 1) Load Page A Data Buffer0 Data Buffer1 Page B 2) Load Int_reg : Interrupt Register Address Add_reg : Address Register Address Flash_add : Flash Address to be loaded DBn_add : DataRAM Address to be loaded CMD_reg : Command Register Address LD_CMD : Load Command Data Load_DBn : Load Data from NAND Flash Array to DataRAMn CS_reg : Controller Status Register Address Data Read_DBn : Read Data from DBn DBn_radd : DataRAM Address to be read The device provides dual data buffer memory architecture. The device is capable of data-read operation from one data buffer and data-load operation to another data buffer simultaneously. This is so called the Read while Load operation with dual data buffer architecture, this feature provides the capability of executing reading data from one of data buffers during data-load operation from Flash to the other buffer simultaneously. Refer to the information for more details in "Load operation" before performing read while load operation. Simultaneous load and read operation to same data buffer is prohibited. FLASH MEMORY 2) Read Write While Program Page B Add_ reg CMD_ reg Add_ reg DB1_wadd* 2) DB0 _add 0000h PD_ CMD Flash _add 0000h DB1 _add Read Status PD_ CMD Data PGM _PageA Data Write _DB1 * Add_ reg Int_ reg Data PGM _PageA CS_ reg CMD_ reg Int_ reg DB0_wadd* Data PGM _PageB Page A ADD 0~15 DB0_wadd* 1) Add_ reg OneNAND128 DQ 0~15 Data Write _DB0 * Flash _add Data PGM _PageB Data Write _DB0 * WE OE INT 56 Page A 2) Program Data Buffer0 Data Buffer1 Page B 3) Program Add_reg : Address Register Address DBn_add : DataRAM Address to be programmed DBn_wadd : DataRAM Address to be written Data Write_DBn : Write Data to DataRAMn Flash_add : Flash Address to be programmed Int_reg : Interrupt Register Address CMD_reg : Command Register Address PD_CMD : Program Command Data PGM_PageA : Program Data from DataRAM to PageA CS_reg : Controller Status Register Address The device provides dual data buffer memory architecture. The device is capable of data-write operation and program operation simultaneously. This is so called the write while program operation with dual data buffer architecture, this feature provides the capability of executing data-write operation from host to one of data buffers during program operation from anther data buffer to Flash simultaneously. Refer to the information for more details in "Program operation" before performing write while program operation. Simultaneous program and write operation to same data buffer is prohibited. 1) Write 3) Write FLASH MEMORY 2) Write OneNAND128 ECC Operation FLASH MEMORY While the device transfers data from BufferRAM to NAND Flash Array Page Buffer for Program Operation, the device hiddenly generates ECC(24bits for main area data and 10bits for 2nd and 3rd word data of each sector spare area) and while Load operation, hiddenly generates ECC and detects error number and position and corrects 1bit error. ECC is updated by the device automatically. After Load Operation, host can know whether there is error or not by reading ’ECC Status Register’(refer to ECC Status Register Table). In addition, OneNAND supports 2bit EDC even though it is little probable that 2bit error occurs. Hence, it is not recommeded that Host reads ’ECC Status Register’ for checking ECC error because the built-in Error Correction Logic of OneNAND finds out and corrects ECC error. When the device loads NAND Flash Array main and sprea area data with ECC operation, the device does not place the newly generated ECC for main and spare area into the buffer but places ECC which was generated and written in program operation into the buffer. Ecc operation is done during the boot loading operation. ECC Bypass Operation ECC bypass operation is set by 9th bit of System Configuration 1 register. In ECC Bypass operation, the device neither generates ECC result which indicates error position nor updates ECC code to NAND Flash arrary spare area in program operation(refer to ECC Result Register Tables). During Load operation, the on-chip ECC engine does not generate a new ECC internally and the values of ECC Status and Result Registers are invalid. Hence, in ECC Bypass operation, the error cannot be detected and corrected by OneNAND itself. ECC Bypass operation is not recommended to host. Table 8. ECC Code & Result Status by ECC operation mode Program operation Operation ECC operation ECC bypass Load operation ECC Status & Result Update to Registers Update Invalid 1bit Error Correct Not correct ECC Code Update to NAND ECC Code at BufferRAM Spare Flash Array Spare Area Area Update Not update Pre-written ECC code(1) loaded Pre-written code loaded NOTE: 1. Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation. 57 OneNAND128 Data Protection during Power Down FLASH MEMORY The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.3V. RP pin provides hardware protection and is recommended to be kept at VIL before power-down. VCC typ. 1.3V 0V RP INT OneNAND Operation One NAND Reset Idle NAND Write Protected Figure 24. Data Protection during Power Down 58 OneNAND128 Technical Notes Invalid Block(s) FLASH MEMORY Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block. Identifying Invalid Block(s) All device locations are erased(FFFFh) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFFFh data at the 1st word of sector0. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 24). Any intentional erasure of the original invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Create (or update) Invalid Block(s) Table No * Check " FFFFh" ? Yes Check "FFFFh" at the sector0 1st word of the 1st and 2nd page in the block No Last Block ? Yes End Figure 25. Flow chart to create invalid block table. 59 OneNAND128 Technical Notes (Continued) Error in write or load operation FLASH MEMORY Within its life time, additional invalid blocks may develop with the device. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. Failure Mode Write Load Erase Failure Program Failure Single Bit Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Error Correction by ECC mode of the device Block Replacement 1st (n-1)th nth (page) 1 1st (n-1)th nth (page) { { Block A 1 an error occurs. Data Buffer0 of the device Data Buffer1 of the device (assuming maintain the nth page data) 2 When an error happens in the nth page of the Block ’A’ during program operation. * Step1 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’ via data buffer0. * Step2 Copy the nth page data of the Block ’A’ in the data buffer1 to the nth page of another free block. (Block ’B’) Do not further erase or program Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme. ∼ ∼ Block B 60 OneNAND128 Technical Notes (Continued) Boot Sequence FLASH MEMORY One of the best features OneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader despite the fact that its core architecture is based on NAND Flash. Thus, OneNAND does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system. As the system power is turned on, the boot code originally stored in NAND Flash Arrary is moved to BootRAM automatically and then fetched by CPU through the same interface as SRAM’s or NOR Flash’s if the size of the boot code is less than 1KB. If its size is larger than 1KB and less than or equal to 2KB, only 1KB of it can be moved to BootRAM automatically and fetched by CPU, and the rest of it can be loaded into one of the DataRAMs whose size is 1KB by Load Command and CPU can take it from the DataRAM after finishing the code-fetching job for BootRAM. If its size is larger than 2KB, the 1KB portion of it can be moved to BootRAM automatically and fetched by CPU, and its remaining part can be moved to DRAM through two DataRAMs using dual buffering and taken by CPU to reduce CPU fetch time. A typical boot scheme usually used to boot the system with OneNAND is explained at Figure 26 and Figure 27. In this boot scheme, boot code is comprised of BL1, where BL stands for Boot Loader, BL2, and BL3. Moreover, the size of the boot code is larger than 2KB (the 3rd case above). BL1 is called primary boot loader in other words. Here is the table of detailed explanations about the function of each boot loader in this specific boot scheme. Boot Loaders in OneNAND Boot Loader BL1 BL2 BL3 (Optional) Description Moves BL2 from NAND Flash Array to DRAM through two DataRAMs using dual buffering Moves OS image (or BL3 optionally) from NAND Flash Array to DRAM through two DataRams using dual buffering Moves or writes the image through USB interface NAND Flash Array of OneNAND is divided into the partitions as described at Figure 26 to show where each component of code is located and how much portion of the overall NAND Flash Array each one occupies. In addition, the boot sequence is listed below and depicted at Figure 27. Boot Sequence : 1. Power is on BL1 is loaded into BootRAM 2. BL1 is executed in BootRAM BL2 is loaded into DRAM through two DataRams using dual buffering by BL1 3. BL2 is executed in DRAM OS image is loaded into DRAM through two DataRams using dual buffering by BL2 4. OS is running 61 OneNAND128 Technical Notes (Continued) Block 512 Reservoir Partition 6 Sector 0 Sector 1 File System Block 162 Os Image Block 2 Block 1 Block 0 NBL3 BL3 NBL1 BL1 NBL2 BL2 Partition 3 BL1 Partition Partition 4 BL2 : : FLASH MEMORY Partition 5 Page 63 Page 62 Page 2 Page 1 Page 0 Figure 26. Partition of NAND Flash array Reservoir File System Data Ram 1 Os Image BL1 BL2 1 Data Ram 0 Boot Ram(BL 1) 3 Os Image 2 BL 2 NAND Flash Array Internal BufferRAM OneNAND NOTE: 2 and 3 can be copied into DRAM through two DataRAMs using dual buffering DRAM Figure 27. OneNAND Boot Sequence 62 OneNAND128 Technical Notes (Continued) Methods of Determining Interrupt Status FLASH MEMORY There are two methods of determining Interrupt Status on the OneNAND. Using the INT pin or monitoring the Interrupt Status Register Bit. The OneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a hardware method of signaling the completion of a program, erase, or load operation. In its normal state, the INT pin is high if the INT polarity bit is default. Before a command is written to the command register, the INT bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. Upon completion of the command operation by the OneNAND’s internal controller, INT returns to a high state. INT is an open drain output allowing multiple INT outputs to be Or-tied together. INT does not float to a hi-Z condition when the chip is deselected or when outputs are disabled. Refer to section 2.8 for additional information about INT. INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register. The INT Pin to a Host General Purpose I/O INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation. COMMAND INT This can be configured to operate either synchronously or asynchronously as shown in the diagrams below. 63 OneNAND128 Technical Notes (Continued) Synchronous Mode Using the INT Pin When operating synchronously, INT is tied directly to a Host GPIO. FLASH MEMORY Host CE AVD CLK RDY OE GPIO OneNAND CE AVD CLK RDY OE INT Asynchronous Mode Using the INT Pin When configured to operate in an asynchronous mode, /CE and /AVD of the OneNAND are tied to /CE of the Host. CLK is tied to the Host Vss (Ground). /RDY is tied to a no-connect. /OE of the OneNAND and Host are tied together and INT is tied to a GPIO. Host CE OneNAND CE AVD Vss N.C OE GPIO CLK RDY OE INT Polling the Interrupt Register Status Bit An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT pin. Command INT This can be configured in either a synchronous mode or an asynchronous mode. 64 OneNAND128 Technical Notes (Continued) FLASH MEMORY Synchronous Mode Using Interrupt Status Register Bit Polling When operating synchronously, /CE, /AVD, CLK, /RDY, /OE, and DQ pins on the host and OneNAND are tied together. Host CE AVD CLK RDY OE DQ OneNAND CE AVD CLK RDY OE DQ Asynchronous Mode Using Interrupt Status Register Bit Polling When configured to operate in an asynchronous mode, /CE and /AVD of the OneNAND are tied to /CE of the Host. CLK is tied to the Host Vss (Ground). /RDY is tied to a no-connect. /OE and DQ of the OneNAND and Host are tied together. Host CE OneNAND CE AVD Vss N.C OE DQ CLK RDY OE DQ 65 OneNAND128 Technical Notes (Continued) FLASH MEMORY Determing Rp Value Because the pull-up resistor value is related to tr(INT), an appropriate value can be obtained by the following reference charts. INT pol = ’High’ Internal Vcc ~50k ohm Rp INT Ready Vcc VOH VOL Vss Busy State tf tr @ Vcc = 1.8V, Ta = 25°C , CL = 30pF 5.420 Ibusy [mA] 2.431 ≈ Ibusy tr,tf 1.75 0.18 0.09 0.7727 1.345 1.788 0.06 2.142 ≈ tr[us] tf[ns] 0.089 3.77 0.045 0.036 ≈≈ ≈ 0.000 ≈ 3.77 3.77 3.77 3.77 3.77 1K 10K 20K 30K Rp(ohm) 40K 50K Open(100K) 66 OneNAND128 Technical Notes (Continued) FLASH MEMORY INT pol = ’Low’ Internal Vcc INT Rp ~50k ohm Ready tr Vcc VOH Busy State tf Vss VOL @ Vcc = 1.8V, Ta = 25°C , CL = 30pF 4.05 Ibusy [mA] 1.84 ≈ Ibusy tr,tf 1.75 0.18 0.09 0.586 1.02 1.356 0.06 1.623 ≈ tf[us] 0.067 6.49 0.045 0.036 ≈≈ ≈ 0.000 ≈ tr[ns] 6.49 6.49 6.49 6.49 6.49 1K 10K 20K 30K Rp(ohm) 40K 50K Open(100K) 67 OneNAND128 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Vcc to VSS All Pins Temperature Under Bias Storage Temperature Short Circuit Output Current Operating Temperature Extended Industrial Extended Industrial Symbol Vcc VIN Tbias Tstg IOS TA TA FLASH MEMORY Rating KFG2816Q1M -0.5 to + 2.45 -0.5 to + 2.45 -30 to +125 -65 to +150 5 -30 to + 85 KFG2816D1M -0.6 to + 4.6 -0.6 to + 4.6 -30 to +125 -65 to +150 5 -30 to + 85 KFG2816U1M -0.6 to + 4.6 -0.6 to + 4.6 -30 to +125 -40 to +125 -65 to +150 5 -30 to + 85 -40 to + 85 Unit V °C °C mA °C NOTES: 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V). Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods