KM681001A-15

PRELIMINARY KM681001A Document Title 128Kx8 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Release to final Data Sheet. 2.1. Delete Preliminary Update D.C and A.C parameters. 3.1. Update D.C parameters Previous spec. Items (15/17/20ns part) Icc 190/180/170mA Isb 30mA Isb1 10mA 3.2. Update A.C parameters Previous spec. Items (15/17/20ns part) tCW 12/12/13ns tAW 12/12/13ns tWP1(OE=H) 12/12/13ns tDW 8/9/10ns Draft Data Jan. 18th, 1995 Apr. 22th, 1995 Remark Design Target Preliminary Rev. 2.0 Feb. 29th, 1996 Final Rev. 3.0 Jul. 16th, 1996 Updated spec. (15/17/20ns part) 165/165/160mA 25mA 8mA Updated spec. (15/17/20ns part) 10/11/12ns 10/11/12ns 10/11/12ns 7/8/9ns Jun. 2nd, 1997 Final Rev. 4.0 Update D.C and A.C parameters and add 300mil-SOJ PKG. 4. 1. Add 32-Pin 300mil-SOJ Package. 4. 2. Update D.C and A.C parameters. Previous spec. Updated spec. Items (15/17/20ns part) (15/17/20ns part) Icc 165/165/160mA 125/125/120mA tOW 3/4/5ns 3/3/3ns 4.3. Add the test condition for Voh1 with Vcc=5V±5% at 25°C 4.4. Add timing diagram to define tWP1 as ″(Timing Wave Form of Write Cycle(OE=Low Fixed)″ 5.1. Delete 17ns Part 5.2. Delete 32-SOJ-300 Package Final Rev. 5.0 Feb. 25th, 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 5.0 February 1998 PRELIMINARY KM681001A 128K x 8 Bit High-Speed CMOS Static RAM FEATURES • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating KM681001A - 15 : 125mA(Max.) KM681001A - 20 : 120mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation -No Clock or Refresh required • Three State Outputs • Standard Pin Configuration KM681001AJ : 32-SOJ-400 CMOS SRAM GENERAL DESCRIPTION The KM681001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681001A is packaged in a 400mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) N.C A0 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 Vcc A16 30 CS2 29 28 27 26 WE A15 A14 A13 A12 OE A11 FUNCTIONAL BLOCK DIAGRAM Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A12 A2 A3 A4 Pre-Charge Circuit A5 A6 A7 SOJ 25 24 23 Row Select A8 Memory Array 512 Rows 256x8 Columns A9 A10 I/O1 I/O2 I/O3 22 CS1 21 I/O8 20 I/O7 19 I/O6 18 I/O5 17 I/O4 I/O1 ~I/O8 Data Cont. CLK Gen. I/O Circuit Column Select Vss A8 A9 A10 A11 A13 A14 A15 A16 PIN FUNCTION Pin Name Pin Function Address Inputs Write Enable Chip Selects Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection A0 - A16 WE CS1, CS2 OE I/O1 ~ I/O8 VCC VSS N.C CS2 CS1 WE OE -2- Rev 5.0 February 1998 PRELIMINARY KM681001A ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 Unit V V CMOS SRAM W °C °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA = 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC + 0.5** 0.8 Unit V V V V * VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS1=VIL, CS2=VIH, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS1=VIH or CS2=VIL f=0MHz, CS1≥VCC-0.2V or CS2≤0.2V, VIN≥VCC-0.2V or VIN≤0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 15ns 20ns Min -2 -2 2.4 Max 2 2 125 120 25 8 0.4 3.95 mA mA V V V Unit µA µA mA Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1* * VCC=5.0V, Temp.=25°C CAPACITANCE*(TA=25°C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 6 Unit pF pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 5.0 February 1998 PRELIMINARY KM681001A AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads Value 0V to 3V 3ns 1.5V See below CMOS SRAM Output Loads(A) +5.0V 480Ω D OUT 255Ω 30pF* Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480Ω DOUT 255Ω 5pF* * Including Scope and Jig Capacitance READ CYCLE Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime NOTE: tCO=tCO1, tCO2/ tLZ=tLZ1, tLZ2/ tHZ=tHZ1, tHZ2 Symbol tRC tAA tCO* tOE tLZ* tOLZ tHZ* tOHZ tOH tPU tPD KM681001A-15 Min 15 3 0 0 0 3 0 Max 15 15 8 6 6 15 KM681001A-20 Min 20 3 0 0 0 3 0 Max 20 20 10 8 8 20 Unit ns ns ns ns ns ns ns ns ns ns ns -4- Rev 5.0 February 1998 PRELIMINARY KM681001A WRITE CYCLE Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z NOTE: tWR=tWR1, tWR2 CMOS SRAM Symbol tWC tCW tAS tAW tWP tWP1 tWR* tWHZ tDW tDH tOW KM681001A-15 Min 15 10 0 10 10 15 0 0 7 0 3 Max 8 KM681001A-20 Min 20 12 0 12 12 20 0 0 9 0 3 Max 10 Unit ns ns ns ns ns ns ns ns ns ns ns TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Valid Data tAA Valid Data (Address Controlled, CS1 =OE=VIL, CS2 =WE=VIH) tRC -5- Rev 5.0 February 1998 PRELIMINARY KM681001A TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA CS1 tCO CS2 tOE OE tOLZ Data out VCC Current ICC ISB NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS1 =VIL and CS2 =VIH. 7. Address valid prior to coincident with CS1 transition low and CS2 transition high. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. CMOS SRAM tHZ(3,4,5) tOHZ tOH Valid Data tLZ(4,5) tPU 50% tPD 50% TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS1 tWR(5) CS2 tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) -6- Rev 5.0 February 1998 PRELIMINARY KM681001A TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) CMOS SRAM tWC Address tAW tCW(3) CS1 tWR(5) CS2 tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) tWP1(2) tDH TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 = Controlled) tWC Address tAW tCW(3) CS1 tAS(4) CS2 tWP(2) WE tDW Data in tDH tWR(5) High-Z tLZ tWHZ(6) Valid Data High-Z Data out High-Z High-Z(8) -7- Rev 5.0 February 1998 PRELIMINARY KM681001A TIMING WAVEFORM OF WRITE CYCLE(4) (CS2 = Controlled) CMOS SRAM tWC Address tAW CS1 tAS(4) CS2 tWP(2) WE tDW Data in tLZ Data out tWHZ(6) tDH tCW(3) tWR(5) Data Valid High-Z High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition CS1 going low,a CS2 going high and WE going low ; A write ends at the earliest transition CS1 going high, CS2 going low or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS1 going low or CS2 going high to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high. tWR2 applied in case a write ends as CS2 going low. 6. If OE, CS1 , CS2 and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS1 goes low and CS2 goes high simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS1 is low and CS2 is high : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS1 H X L L L CS2 X L H H H WE X X H H L OE X* X H L X Mode Not Select Not Select Output Disable Read Write I/O Pin High-Z High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ISB, ISB1 ICC ICC ICC * NOTE : X means Don′t Care. -8- Rev 5.0 February 1998 PRELIMINARY KM681001A PACKAGE DIMENSIONS 32-SOJ-400 #32 #17 CMOS SRAM Units:millimeters/Inches 10.1 6 0.40 0 11.18 ±0.12 0.440 ± 0.005 9.40 ± 0.25 0.370 ± 0.010 0.20 #1 21.36 MAX 0.841 20.95 ± 0.12 0.825 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 +0.10 -0.05 +0.004 0.017 -0.002 #16 0.69 0.027 MIN 0.008 +0.10 -0.05 +0.004 -0.002 3.76 MAX 0.148 0.10 MAX 0.004 ( 0.95 ) 0.0375 0.43 1.27 0.050 0.71 0.028 +0.10 -0.05 +0.004 -0.002 -9- Rev 5.0 February 1998