KM684000BLTI-7L

KM684000B Family Document Title 512Kx8 bit Low Power CMOS Static RAM CMOS SRAM Revision History Revision No. 0.0 0.1 History Initial Draft Revise - Changed Operating current by reticle revision ICC at write : 35mA → 45mA ICC1 at read/write : 15/35mA → 10/45mA Finalize - Changed Operating current ICC1 at write : 45mA → 40mA ICC2; 90mA → 80mA - Change test load at 55ns : 100pF → 50pF Revise - Change datasheet format Revise - Industrial product speed bin change:70/100ns → 55/70ns Draft Date December 7, 1996 March 6, 1997 Remark Advance Preliminary 1.0 October 9, 1997 Final 2.0 February 17, 1998 Final 3.0 September 8, 1998 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 3.0 September 1998 KM684000B Family 512Kx8 bit Low Power CMOS Static RAM FEATURES • Process Technology: TFT • Organization: 512Kx8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-DIP-600, 32-SOP-525 32-TSOP2-400F/R CMOS SRAM GENERAL DESCRIPTION The KM684000B families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Max) 100µA 20µA 4.5~5.5V Inderstrial (-40~85°C) 551)/70ns 100µA 50µA 80mA 32-SOP 32-TSOP2-F/R Operating (ICC2, Max) PKG Type KM684000BL KM684000BL-L KM684000BLI KM684000BLI-L Commercial (0~70°C ) 32-DIP,32-SOP 32-TSOP2-F/R 1. The parameter is measured with 50pF test load. PIN DESCRIPTION A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 FUNCTIONAL BLOCK DIAGRAM Clk gen. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O1 I/O8 A18 A16 A14 A12 A7 Precharge circuit. 32-DIP 32-SOP 32-TSOP2 (Forward) 26 25 24 23 22 21 20 19 18 17 32-TSOP2 (Reverse) 7 8 9 10 11 12 13 14 15 16 A6 A5 A4 A1 A0 Row select Memory array 1024 rows 512×8 columns Data cont I/O Circuit Column select Data cont Pin Name WE CS OE A0~A18 I/O1~I/O8 Vcc Vss Function Write Enable Input Chip Select Input Output Enable Input Address Inputs Data Inputs/Outputs Power Ground CS WE OE A9 A8 A13A17 A15 A10 A11 A3 A2 Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 3.0 September 1998 KM684000B Family PRODUCT LIST Commercial Temperature Products(0~70 °C) Part Name KM684000BLP-5 KM684000BLP-5L KM684000BLP-7 KM684000BLP-7L KM684000BLG-5 KM684000BLG-5L KM684000BLG-7 KM684000BLG-7L KM684000BLT-5L KM684000BLT-7L KM684000BLR-5L KM684000BLR-7L Function 32-DIP, 55ns, L-pwr 32-DIP, 55ns, LL-pwr 32-DIP, 70ns, L-pwr 32-DIP, 70ns, LL-pwr 32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP2-F, 55ns, LL-pwr 32-TSOP2-F, 70ns, LL-pwr 32-TSOP2-R, 55ns, LL-pwr 32-TSOP2-R, 70ns, LL-pwr CMOS SRAM Industrial Temperature Products(-40~85 °C) Part Name KM684000BLGI-5 KM684000BLGI-5L KM684000BLGI-7 KM684000BLGI-7L KM684000BLTI-5L KM684000BLTI-7L KM684000BLRI-5L KM684000BLRI-7L Function 32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP2-F, 55ns, LL-pwr 32-TSOP2-F, 70ns, LL-pwr 32-TSOP2-R, 55ns, LL-pwr 32-TSOP2-R, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS H L L L OE X1) H L X1) WE X1) H H L I/O Pin High-Z High-Z Dout Din Mode Deselected Output disbaled Read Write Power Standby Active Active Active 1. X means don′t care.( Must be in low or high state.) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 260°C, 10sec(Lead Only) Unit V V W °C °C °C Remark KM684000BL/L-L KM684000BLI/LI-L - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 3.0 September 1998 KM684000B Family RECOMMENDED DC OPERATING CONDITIONS 1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 - CMOS SRAM Max 5.5 0 Vcc+0.5 2) 0.8 Unit V V V V Note: 1. Commercial Product : TA=0 to 70°C, otherwise specified Industrial Product : TA=-40 to 85°C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width ≤ 30ns 3. Undershoot : -3.0V in case of pulse width ≤ 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) VOL VOH ISB VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIL or VIH, Read Cycle time=1µs, 100% duty, I IO=0mA CS≤0.2V, VIN≥0.2V or VIN ≥ Vcc-0.2V Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL Test Conditions Min -1 -1 Read Write 2.4 KM684000BL - Typ 7.5 4 27 65 2 1 2 1 Max 1 1 15 10 40 80 0.4 3 100 20 100 50 Unit µA µA mA mA mA V V mA µA µA µA µA IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs = V IL or VIH Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc KM684000BL-L KM684000BLI KM684000BLI-L 4 Revision 3.0 September 1998 KM684000B Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL=50pF+1TTL CL1) CMOS SRAM 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM684000B Family:TA=0 to 70°C, KM684000BI Family:TA=-40 to 85°C) Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55*ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol VDR CS ≥Vcc-0.2V Test Condition KM684000BL Min 2.0 0 5 Typ - Max 5.5 50 15 50 20 - Unit V Data retention current IDR Vcc=3.0V, CS ≥Vcc-0.2V KM684000BL-L KM684000BLI KM684000BLI-L µA Data retention set-up time Recovery time tSDR tRDR See data retention waveform ms 5 Revision 3.0 September 1998 KM684000B Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 3.0 September 1998 KM684000B Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC 4.5V tSDR Data Retention Mode tRDR 2.2V VDR CS≥VCC - 0.2V CS GND 7 Revision 3.0 September 1998 KM684000B Family PACKAGE DIMENSIONS 32 PIN DUAL INLINE PACKAGE (600mil) CMOS SRAM Units: millimeter(Inch) 0.25 +0.10 -0.05 +0.004 0.010-0.002 #32 #17 13.60 ±0.20 0.535±0.008 #1 42.31 MAX 1.666 41.91±0.20 1.650±0.008 #16 3.81±0.20 0.150 ±0.008 5.08 0.200 MAX 15 .24 0.6 00 0~15° ( 1.91 ) 0.075 0.46±0.10 0.018 ±0.004 1.52±0.10 0.060 ±0.004 3.30±0.30 0.130±0.012 2.54 0.100 0.38 0.015 MIN 32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #32 #17 14.12±0.30 0.556±0.012 11.43±0.20 0.450±0.008 13.34 0.525 #1 20.87MAX 0.822 20.47±0.20 0.806±0.008 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 0.10 0.20 +0.05 0.004 0.008+0.002 - 0.80±0.20 0.031±0.008 0.10 MAX 0.004 MAX +0.100 -0.050 +0.004 0.016 -0.002 ( 0.71 ) 0.028 0.41 1.27 0.050 0.05 0.002 MIN 8 Revision 3.0 September 1998 KM684000B Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) CMOS SRAM Units: millimeter(Inch) 0.25 ( 0.010 ) #32 #17 0~8° 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 #1 21.35 MAX 0.841 20.95 ±0.10 0.825±0.004 #16 1.00±0.10 0.039±0.004 1.20 0.047MAX 0.10 MAX 0.004 MAX 0.10 0.15 +0.05 +0.004 0.006 -0.002 10 .16 0. 400 ( 0.50 ) 0.020 ( 0.95 ) 0.037 0.40±0.10 0.016 ±0.004 1.27 0.050 0.05 MIN 0.002 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) ( #1 #16 0.25 ) 0.010 0~8 ° 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 #32 21.35 0.841 MAX 20.95±0.10 0.825±0.004 #17 1.00 ±0.10 0.039±0.004 1.20 0.047 MAX 0.10 MAX 0.004 MAX + 0.10 -0.05 + 0.004 0.006 -0.002 10.1 6 0.40 0 0.15 ( 0.50 ) 0.020 ( 0.95 ) 0.037 0.40±0.10 0.016±0.004 1.27 0.050 0.05 MIN 0.002 9 Revision 3.0 September 1998