KS57C2304

KS57C2302/C2304/P2304 MICROCONTROLLER PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The KS57C2302/C2304 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the KS57C2302/C2304 offers an excellent design solution for a wide variety of applications that require LCD functions. Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast response to internal and external events. In addition, the KS57C2302/C2304 's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The KS57C2302/C2304 microcontroller is also available in OTP (One Time Programmable) version, KS57P2304 . The KS57P2304 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The KS57P2304 is comparable to KS57C2302/C2304, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS57C2302/C2304/P2304 MICROCONTROLLER FEATURES Memory — 288 × 4-bit RAM — 2048 × 8-bit ROM (KS57C2302) — 4096 × 8-bit ROM (KS57C2304) I/O Pins — Input only: 4 pins — I/O: 12 pins — Output: 8 pins sharing with segment driver outputs LCD Controller/Driver — Maximum 16-digit LCD direct drive capability — 32 segment, 4 common pins — Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-Bit Basic Timer — Programmable interval timer — Watchdog timer 8-Bit Timer/Counter — Programmable 8-bit timer — External event counter — Arbitrary clock frequency output Watch Timer — Real-time and interval time measurement — Four frequency outputs to BUZ pin — Clock source generation for LCD Bit Sequential Carrier — Support 16-bit serial data transfer in arbitrary format Package Type — 64-pin QFP Oscillation Sources — Crystal, ceramic, or RC for main system clock — Crystal or external oscillator for subsystem clock — Main system clock frequency: 4.19 MHz (typical) — Subsystem clock frequency: 32.768 kHz — CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times — 0.95, 1.91, 15.3 µs at 4.19 MHz (main) — 122 µs at 32.768 kHz (subsystem) Operating Temperature — – 40 °C to 85 °C Operating Voltage Range — 2.0 V to 5.5 V at 4.19 MHz — 1.8 V to 5.5 V at 3 MHz Interrupts — Two internal vectored interrupts — Two external vectored interrupts — Two quasi-interrupts Memory-Mapped I/O Structure — Data memory bank 15 Two Power-Down Modes — Idle mode (only CPU clock stops) — Stop mode (main or sub system oscillation stops) 1-2 KS57C2302/C2304/P2304 MICROCONTROLLER PRODUCT OVERVIEW BLOCK DIAGRAM BASIC TIMER INT0, INT1,INT2 RESET WATCH TIMER P2.3/BUZ Xin XTin Xout XTout P1.3/TCL0 P2.0/TCLO0 8-BIT TIMER/ COUNTER 0 INTERRUPT CONTROL BLOCK CLOCK INSTRUCTION REGISTER LCD DRIVER/ CONTROLLER P6.0–P6.3 / KS0–KS3 I/O PORT 6 INTERNAL INTERRUPTS INSTRUCTION DECODER ARITHMETIC AND LOGIC UNIT PROGRAM COUNTER BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23 P8.0-P8.7/ SEG24-SEG31 PROGRAM STATUS WORD INPUT PORT 1 STACK POINTER I/O PORT 2 P8.0–P8.7 SEG24–SEG31 OUTPUT PORT 8 P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / TCL0 P2.0 / TCLO0 P2.1 P2.2 / CLO P2.3 / BUZ P3.0 / LCDCK P3.1 / LCDSY P3.2 P3.3 288 x 4-BIT DATA MEMORY 2/4 K BYTE PROGRAM MEMORY I/O PORT 3 Figure 1-1. KS57C2302/C2304 Simplified Block Diagram 1-3 PRODUCT OVERVIEW KS57C2302/C2304/P2304 MICROCONTROLLER PIN ASSIGNMENTS COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS Xout Xin TEST XTin XTout RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 KS57C2302 KS57C2304 (TOP VIEW) SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 / P8.0 SEG25 / P8.1 SEG26 / P8.2 SEG27 / P8.3 SEG28 / P8.4 SEG29 / P8.5 SEG30 / P8.6 SEG31 / P8.7 Figure 1-2. KS57C2302/C2304 64-QFP Pin Assignment 1-4 P1.3 / TCL0 P2.0 / TCLO0 P2.1 P2.2 / CLO P2.3 / BUZ P3.0 / LCDCK P3.1 / LCDSY P3.2 P3.3 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / KS3 20 21 22 23 24 25 26 27 28 29 30 31 32 KS57C2302/C2304/P2304 MICROCONTROLLER PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. KS57C2302/C2304 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 Pin Type I Description 4-bit input port. 1-bit or 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 4-bit I/O ports. Pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. Output port for 1-bit data (for use as CMOS driver only) LCD segment signal output LCD segment signal output LCD common signal output LCD power supply. Built-in voltage dividing resistors LCD power control LCD clock output for display expansion Number 17 18 19 20 21 22 23 24 25 26 27 28 Share Pin INT0 INT1 INT2 TCL0 TCLO0 – CLO BUZ LCDCK LCDSY Reset Value Input Circuit Type A-4 I/O Input D I/O Input D P6.0–P6.3 I/O 29–32 KS0–KS3 Input D P8.0–P8.7 SEG0–SEG23 SEG24–SEG31 COM0–COM3 VLC0–VLC2 BIAS LCDCK O O O O – – I/O 40–33 64–41 40–33 1–4 6–8 5 25 SEG24– SEG31 – P8.0–P8.7 – – – P3.0 Output Output Output Output – – Input H-1 H H-1 H – – D 1-5 PRODUCT OVERVIEW KS57C2302/C2304/P2304 MICROCONTROLLER Table 1-1. KS57P2304 Pin Descriptions (Continued) Pin Name LCDSY TCL0 TCLO0 INT0 INT1 Pin Type I/O I I/O I Description LCD synchronization clock output for LCD display expansion External clock input for timer/counter 0 Timer/counter 0 clock output External interrupt. The triggering edge for INT0 and INT1 is selectable. Only INT0 is synchronized with the system clock. Quasi-interrupt with detection of rising edge signals. Quasi-interrupt input with falling edge detection. CPU clock output 2, 4, 8 or 16 kHz frequency output for buzzer sound with 4.19 MHz main system clock or 32.768 kHz subsystem clock. Crystal, ceramic or RC oscillator pins for main system clock. (For external clock input, use XIN and input XIN’s reverse phase to XOUT) Crystal oscillator pins for subsystem clock. (For external clock input, use XTIN and input XTIN’s reverse phase to XTOUT) Main power supply Ground Reset signal Test signal input (must be connected to VSS) Number 26 20 21 17 18 Share Pin P3.1 P1.3 P2.0 P1.0 P1.1 Reset Value Input Input Input Input Circuit Type D A-4 D A-4 INT2 KS0–KS3 CLO BUZ I I/O I/O I/O 19 29–32 23 24 P1.2 P6.0–P6.3 P2.2 P2.3 Input Input Input Input A-4 D D D XIN, XOUT – 12,11 – – – XTIN, XTOUT – 14,15 – – – VDD VSS RESET – – – – 9 10 16 13 – – – – – – Input – – – B – TEST NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode. 1-6 KS57C2302/C2304/P2304 MICROCONTROLLER PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD P-CHANNEL IN N-CHNNEL DATA P-CHANNEL OUT N-CHANNEL OUTPUT DISABLE Figure 1-3. Pin Circuit Type A Figure 1-5. Pin Circuit Type C VDD VDD PULL-UP RESISTOR P-CHANNEL RESISTOR ENABLE PULL-UP RESISTOR RESISTOR ENABLE DATA IN OUTPUT DISABLE CIRCUIT TYPE C P-CHANNEL I/O SCHMITT TRIGGER CIRCUIT TYPE A Figure 1-4. Pin Circuit Type A-4 (P1) Figure 1-6. Pin Circuit Type D (P2, P3, and P6) 1-7 PRODUCT OVERVIEW KS57C2302/C2304/P2304 MICROCONTROLLER VLC0 VDD VLC1 LCD SEGMENT/ COMMON DATA OUT IN SCHMITT TRIGGER VLC2 Figure 1-9. Pin Circuit Type B (RESET) Figure 1-7. Pin Circuit Type H (SEG/COM) VDD VLC0 VLC1 LCD SEGMENT/ & PORT 8 DATA OUT VLC2 Figure 1-8. Pin Circuit Type H-1 (P8) 1-8 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES 2 OVERVIEW ADDRESS SPACES PROGRAM MEMORY (ROM) ROM maps for KS57C2302/C2304 devices are mask programmable at the factory. KS57C2302 has 2K × 8-bit program memory and KS57C2304 has 4K × 8-bit program memory, aside from the differences in the ROM size the two products are identical in other features. In its standard configuration, the device's 4,096 × 8-bit program memory has four areas that are directly addressable by the program counter (PC): — 12-byte area for vector addresses — 96-byte instruction reference area — 20-byte general-purpose area — 1920-byte general-purpose area (KS57C2302) 3968-byte general-purpose area (KS57C2304) General-Purpose Program Memory Two program memory areas are allocated for general-purpose use: One area is 20 bytes in size and the other is 1,920 bytes (KS57C2302) or 3,968 bytes (KS57C2304). Vector Addresses A 12-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corresponding service routines. The 12-byte area can be used alternately as general-purpose ROM. REF Instructions Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte instructions, and 3-byte instructions which are stored in the look-up table. Unused look-up table addresses can be used as general-purpose ROM. Table 2-1. Program Memory Address Ranges ROM Area Function Vector address area General-purpose program memory REF instruction look-up table area General-purpose program memory Address Ranges 0000H–000BH 000CH–001FH 0020H–007FH 0080H–7FFH (KS57C2302) 0080H–0FFFH (KS57C2304) Area Size (in Bytes) 12 20 96 1920 (KS57C2302) 3968 (KS57C2304) 2-1 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER GENERAL-PURPOSE MEMORY AREAS The 20-byte area at ROM locations 000CH–001FH and the 3,968-byte area at ROM locations 0080H–0FFFH are used as general-purpose program memory. Unused locations in the vector address area and REF instruction look-up table areas can be used as general-purpose program memory. However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the ROM. VECTOR ADDRESS AREA The 12-byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines. 12-byte vector addresses are organized as follows: EMB PC7 ERB PC6 0 PC5 0 PC4 PC11 PC3 PC10 PC2 PC9 PC1 PC8 PC0 To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the next page explain how to do this. 0000H VECTOR ADDRESS AREA (12 Bytes) 000BH 000CH 001FH 0020H 7 0000H 6 5 4 3 2 1 0 GENERAL-PURPOSE AREA (20 Bytes) RESET 0002H INSTRUCTION REFERENCE AREA INTB 0004H INT0 007FH 0080H 0006H INT1 GENERAL-PURPOSE AREA (1,920 Bytes 3,968 Bytes) 0008H Reserved 000AH INTT0 7FFH 0FFFH Figure 2-1. ROM Address Structure Figure 2-2. Vector Address Structure 2-2 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES + PROGRAMMING TIP — Defining Vectored Interrupts The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: ORG VENT0 VENT1 VENT2 VENT3 ORG VENT5 0000H 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 000AH 0,0,INTT0 ; EMB ← 0, ERB ← 0; Jump to INTT0 address ; ; ; ; EMB EMB EMB EMB ← ← ← ← 1, ERB 0, ERB 0, ERB 0, ERB ← ← ← ← 0; Jump to RESET address 0; Jump to INTB address 0; Jump to INT0 address 0; Jump to INT1 address 2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations: ORG VENT0 VENT1 ORG VENT3 ORG 0000H 1,0,RESET 0,0,INTB 0006H 0,0,INT1 0010H ; ; ; ; EMB ← 1, ERB ← 0; Jump to RESET address EMB ← 0, ERB ← 0; Jump to INTB address INT0 interrupt not used EMB ← 0, ERB ← 0; Jump to INT1 address 3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a ORG instruction as in Example 2, a CPU malfunction will occur: ORG VENT0 VENT1 VENT3 VENT5 ORG 0000H 1,0,RESET 0,0,INTB 0,0,INT1 0,0,INTT0 0010H ; ; ; ; EMB EMB EMB EMB ← ← ← ← 1, ERB 0, ERB 0, ERB 0, ERB ← ← ← ← 0; Jump to RESET address 0; Jump to INTB address 0; Jump to INT0 address 0; Jump to INT1 address General-purpose ROM area In this example, when an INT1 interrupt is generated, the corresponding vector area is not VENT3 INT1, but VENT5 INTT0. This causes an INT1 interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur. 2-3 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations in the REF look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. By using REF instructions to execute instructions larger than one byte, you can improve program execution time considerably by reducing the number of program steps. In summary, there are three ways you can use the REF instruction: — Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions, — Branching to any location by referencing a branch instruction stored in the look-up table, — Calling subroutines at any location by referencing a call instruction stored in the look-up table. + PROGRAMMING TIP — Using the REF Look-Up Table Here is one example of how to use the REF instruction look-up table: JMAIN KEYCK WATCH INCHL ORG TJP BTSF TCALL LD INCS • • • LD ORG NOP NOP • • • REF REF REF REF REF • • • 0020H MAIN KEYFG CLOCK @HL,A HL ; ; ; ; 0, MAIN 1, KEYFG CHECK 2, CALL CLOCK 3, (HL) ← A ABC MAIN EA,#00H 0080H ; 47, EA ← #00H KEYCK JMAIN WATCH INCHL ABC ; ; ; ; ; ; BTSF KEYFG (1-byte instruction) KEYFG = 1, jump to MAIN (1-byte instruction) KEYFG = 0, CALL CLOCK (1-byte instruction) LD @HL,A INCS HL LD EA,#00H (1-byte instruction) 2-4 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES DATA MEMORY (RAM) OVERVIEW In its standard configuration, the 288 x 4-bit data memory has three areas: — 32 × 4-bit working register area in bank 0 — 224 × 4-bit general-purpose area in bank 0 which is also used as the stack area — 32 × 4-bit area for LCD data in bank 1 — 128 × 4-bit area in bank 15 for memory-mapped I/O addresses To make it easier to reference, the data memory area has three memory banks — bank 0, bank 1, and bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. One exception is the LCD data register area, which is 1-bit and 4-bit addressable only. Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset. However, when RESET signal is generated in power-down mode, the data memory contents are held. 2-5 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER 000H WORKING REGISTERS (32 x 4 Bits) 01FH 020H GENERAL-PURPOSE REGISTERS AND STACK AREA (224 x 4 Bits) BANK 0 0FFH ~ 1E0H 1FFH LCD DATA REGISTERS (32 x 4 Bits) ~ BANK 1 ~ F80H MEMORY-MAPPED I/O AEERESS REGISTERS (128 x 4 Bits) FFFH ~ BANK 15 Figure 2-3. Data Memory (RAM) Map 2-6 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES Memory Banks 0, 1, and 15 Bank 0 (000H–0FFH) The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers; the next 224 nibbles (020H–0FFH) can be used both as stack area and as general-purpose data memory. Use the stack area for implementing subroutine calls and returns, and for interrupt processing. 32 nibbles of bank 1 are used as display registers or general purpose memory. The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed RAM locations for each peripheral hardware address are mapped into this area. Bank 1 Bank 15 (1E0H–1FFH) (F80H–FFFH) Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and bank 15. With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all three data memory banks can be accessed according to the current SMB value. For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to address RAM locations, remember to use the even-numbered register address as the instruction operand. Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 1. Register locations in this area that are not used to store LCD data can be assigned to general-purpose use. 2-7 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER Table 2-2. Data Memory Organization and Addressing Addresses 000H–01FH 020H–0FFH 1E0H–1FFH F80H–FFFH Register Areas Working registers Stack and general-purpose registers LCD Data registers I/O-mapped hardware registers 1 15 1 0, 1 1 15 Bank 0 EMB Value 0, 1 SMB Value 0 + PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1 Clear banks 0 and 1 of the data memory area: RAMCLR BITS SMB LD LD LD INCS JR SMB LD LD INCS JR EMB 1 HL, #0E0H A, #0H @HL, A HL RMCL1 0 HL, #10H @HL, A HL RMCL0 ; RAM (1E0H–1FFH) clear RMCL1 ; RAM (010H–0FFH) clear RMCL0 2-8 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES WORKING REGISTERS Working registers, mapped to RAM address 000H–01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. 000H 001H A E 002H L 003H H 004H X 005H DATA 006H MEMORY BANK 0 007H 008H A 00FH 010H 017H 018H 01FH A W Z Y WORKING REGISTER BANK 0 ... Y ... Y ... Y REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3 A Figure 2-4. Working Register Map 2-9 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER Working Register Banks For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRB n) and by setting the status of the register bank enable flag (ERB). Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. Table 2-3. Working Register Organization and Addressing ERB Setting 0 1 SRB Settings 3 0 0 2 0 0 1 – 0 0 1 1 Paired Working Registers Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E, and A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ, and WL. Registers A, L, X, and Z always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. 0 – 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3 Selected Register Bank (MSB) Y (LSB) (MSB) Z (LSB) W X H L E A Figure 2-5. Register Pair Configuration 2-10 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES Special-Purpose Working Registers Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also be used as a 1-bit accumulator. 8-bit double registers WX, WL, and HL are used as data pointers for indirect addressing. When the HL register serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction. C 1−BIT ACCUMULATOR 4−BIT ACCUMULATOR 8−BIT ACCUMULATOR A EA Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction. 2-11 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER + PROGRAMMING TIP — Selecting the Working Register Area The following examples show the correct programming method for selecting working register area: 1. When ERB = "0": VENT2 INT0 1,0,INT0 PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET SB 2 HL WX YZ EA 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA EA YZ WX HL SB ; EMB ← 1, ERB ← 0, Jump to INT0 address ; ; ; ; ; ; PUSH current SMB, SRB Instruction does not execute because ERB = "0" PUSH HL register contents to stack PUSH WX register contents to stack PUSH YZ register contents to stack PUSH EA register contents to stack ; ; ; ; ; POP EA register contents from stack POP YZ register contents from stack POP WX register contents from stack POP HL register contents from stack POP current SMB, SRB The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values, as shown in Example 2 below. 2. When ERB = "1": VENT2 INT0 1,1,INT0 PUSH SRB SMB LD LD LD INCS LD LD POP IRET SB 2 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA SB ; EMB ← 1, ERB ← 1, Jump to INT0 address ; Store current SMB, SRB ; Select register bank 2 because of ERB = "1" ; Restore SMB, SRB 2-12 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES STACK OPERATIONS STACK POINTER (SP) The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always remain cleared to logic zero. F80H F81H SP3 SP7 SP2 SP6 SP1 SP5 "0" SP4 There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack. The program counter contents and program status word (PSW) are stored in the stack area prior to the execution of a CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) type. The stack area is located in general-purpose data memory bank 0. During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed. The SP can address stack registers in bank 0 (addresses 000H–0FFH) regardless of the current value of the enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00H. This sets the first register of the stack area to 0FFH. NOTE A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. To do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. + PROGRAMMING TIP — Initializing the Stack Pointer To initialize the stack pointer (SP): 1. When EMB = "1": SMB LD LD 2. When EMB = "0": LD LD EA,#00H SP,EA ; Memory addressing area (00H–7FH, F80H–FFFH) 15 EA,#00H SP,EA ; Select memory bank 15 ; Bit 0 of SP is always cleared to "0" ; Stack area initial address (0FFH) ← (SP) – 1 2-13 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decreased by a number determined by the type of push operation and then points to the next available stack location. PUSH Instructions A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH has executed, the SP is decreased by two and points to the next available stack location. CALL Instructions When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to the number of levels permitted in the stack. Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is decreased by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. INTERRUPT PUSH (After PUSH, SP SP – 2) CALL (After CALL, SP SP – 6 SP – 5 SP – 4 SP – 3 0 SP – 6) SP – 6 0 SP – 5 SP – 4 SP – 3 SP – 2 SP – 1 SP (When INT is acknowledged, SP SP – 6) PC11– PC8 0 0 0 0 PC11– PC8 0 0 PC3 – PC0 PC7 – PC4 0 0 0 EMB ERB PSW 0 0 0 PC3 – PC0 PC7 – PC4 IS1 C IS0 EMB ERB PSW SC2 SC1 SC0 SP – 2 SP – 1 SP LOWER REGISTER UPPER REGISTER SP – 2 SP – 1 SP Figure 2-7. Push-Type Stack Operations 2-14 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by the type of operation and points to the next free stack location. POP Instructions A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. After the POP has executed, the SP is incremented by two and points to the next free stack location. RET and SRET Instructions The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location. IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has executed, the SP is incremented by six and points to the next free stack location. POP (SP SP SP + 1 SP + 2 SP + 2) SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0 RET OR SRET (SP SP + 6) SP 0 SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 IS1 C 0 (SP IRET SP + 6) LOWER UPPER PC11 – PC8 0 0 PC11 – PC8 0 0 0 PC3 – PC0 PC7 – PC4 0 EMB ERB PSW 0 0 0 PC3 – PC0 PC7 – PC4 IS0 EMB ERB PSW SC2 SC1 SC0 Figure 2-8. Pop-Type Stack Operations 2-15 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER BIT SEQUENTIAL CARRIER (BSC) The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero. Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the L register. BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately. If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3. Table 2-4. BSC Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H Bit 3 BSC0.3 BSC1.3 BSC2.3 BSC3.3 Bit 2 BSC0.2 BSC1.2 BSC2.2 BSC3.2 Bit 1 BSC0.1 BSC1.1 BSC2.1 BSC3.1 Bit 0 BSC0.0 BSC1.0 BSC2.0 BSC3.0 + PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin: BITS SMB LD LD LD LD SMB LD LDB LDB INCS JR RET EMB 15 EA,#37H BSC0,EA EA,#59H BSC2,EA 0 L,#0H C,BSC0.@L P3.0,C L AGN ; ; BSC0 ← A, BSC1 ← E ; ; BSC2 ← A, BSC3 ← E ; ; ; P3.0 ← C AGN 2-16 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES PROGRAM COUNTER (PC) A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1byte REF instruction which is used to reference instructions stored in the ROM. PROGRAM STATUS WORD (PSW) The program status word (PSW) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW values are mapped as follows: (MSB) FB0H FB1H IS1 C IS0 SC2 EMB SC1 (LSB) ERB SC0 The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag. Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address. When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logical zero. Table 2-5. Program Status Word Bit Descriptions PSW Bit Identifier IS1, IS0 EMB ERB C SC2, SC1, SC0 Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Bit Addressing 1, 4 1 1 1 8 Read/Write R/W R/W R/W R/W R 2-17 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the IPR. When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings. Table 2-6. Interrupt Status Flag Bit Settings IS1 Value 0 0 1 1 IS0 Value 0 1 0 1 Status of Currently Executing Process 0 1 2 – Effect of IS0 and IS1 Settings on Interrupt Request Control All interrupt requests are serviced Only high-priority interrupt(s) as determined in the interrupt priority register (IPR) are serviced No more interrupt requests are serviced Not applicable; these bit settings are undefined Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to re-enable interrupt processing. + PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing: INTB BITR BITS EI DI IS1 IS0 ; ; ; ; Disable interrupt IS1 ← 0 Allow interrupts according to IPR priority level Enable interrupt 2-18 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES EMB FLAG (EMB) The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1, or 15. When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H–07FH of memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the general-purpose areas of bank 0, 1, and 15 can be accessed by using the appropriate SMB value. + PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks EMB flag settings for memory bank selection: 1. When EMB = "0": SMB LD LD LD SMB LD LD SMB LD LD 2. When EMB = "1": SMB LD LD LD SMB LD LD SMB LD LD 1 A,#9H 0E0H,A 0F0H,A 0 90H,A 34H,A 15 20H,A 90H,A ; Select memory bank 1 ; ; ; ; ; ; ; ; (1E0H) ← A, bank 1 is selected (1F0H) ← A, bank 1 is selected Select memory bank 0 (090H) ← A, bank 0 is selected (034H) ← A, bank 0 is selected Select memory bank 15 Program error, but assembler does not detect it (F90H) ← A, bank 15 is selected 1 A,#9H 90H,A 34H,A 0 90H,A 34H,A 15 20H,A 90H,A ; Non-essential instruction since EMB = "0" ; ; ; ; ; ; ; ; (F90H) ← A, bank 15 is selected (034H) ← A, bank 0 is selected Non-essential instruction since EMB = "0" (F90H) ← A, bank 15 is selected (034H) ← A, bank 0 is selected Non-essential instruction, since EMB = "0" (020H) ← A, bank 0 is selected (F90H) ← A, bank 15 is selected 2-19 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (SRB). When an internal reset is generated, bit 6 of program memory address 0000H is written to the ERB flag. This automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is executed. During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions. + PROGRAMMING TIP — Using the ERB Flag to Select Register Banks ERB flag settings for register bank selection: 1. When ERB = "0": SRB LD LD SRB LD SRB LD 2. When ERB = "1": SRB LD LD SRB LD SRB LD 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; Register bank 1 is selected Bank 1 EA ← #34H Bank 1 HL ← Bank 1 EA Register bank 2 is selected Bank 2 YZ ← BANK2 EA Register bank 3 is selected Bank 3 WX ← Bank 3 EA 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; ; Register bank 0 is selected (since ERB = "0", the SRB is configured to bank 0) Bank 0 EA ← #34H Bank 0 HL ← EA Register bank 0 is selected Bank 0 YZ ← EA Register bank 0 is selected Bank 0 WX ← EA 2-20 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESS SPACES SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed. CARRY FLAG (C) The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations involving bit-addressed data memory. If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation SCF RCF CCF BTST C Bit transfer LDB (operand) (1) ,C Instructions Carry Flag Manipulation Set carry flag to "1" Clear carry flag to "0" (reset carry flag) Invert carry flag value (complement carry flag) Test carry and skip if C = "1" Load carry flag value to the specified bit Load contents of the specified bit to carry flag AND the specified bit with contents of carry flag and save the result to the carry flag OR the specified bit with contents of carry flag and save the result to the carry flag XOR the specified bit with contents of carry flag and save the result to the carry flag Save carry flag to stack with other PSW bits Restore carry flag from stack with other PSW bits LDB C,(operand) (1) Boolean manipulation BAND C,(operand) (1) BOR C,(operand) (1) BXOR C,(operand) (1) Interrupt routine Return from interrupt INTn (2) IRET NOTES: 1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b. 2. 'INTn' refers to the specific interrupt being executed and is not an instruction. 2-21 ADDRESS SPACES KS57C2302/C2304/P2304 MICROCONTROLLER + PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator 1. Set the carry flag to logic one: SCF LD LD ADC ; ; ; ; C←1 EA ← #0C3H HL ← #0AAH EA ← #0C3H + #0AAH + #1H, C ← 1 EA,#0C3H HL,#0AAH EA,HL 2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P2.0: LD LDB BAND LDB H,#3H C,@H+0FH.3 C,P3.3 P2.0,C ; ; ; ; ; Set the upper four bits of the address to the H register value C ← bit 3 of 3FH C ← C AND P3.3 Output result from carry flag to P2.0 2-22 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESSING MODES 3 OVERVIEW ADDRESSING MODES The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the addressable area in the RAM is restricted to specific locations. The EMB flag works in connection with the select memory bank instruction, SMB n. You will recall that the SMB n instruction is used to select RAM bank 0, 1, or 15. The SMB setting is always contained in the upper four bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1, or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations are addressable at all times, regardless of the current EMB flag setting. Here are a few guidelines to keep in mind regarding data memory addressing: — When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. — Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing. — With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address. 3-1 ADDRESSING MODES KS57C2302/C2304/P2304 MICROCONTROLLER RAM AREAS 000H 01FH 020H 07FH 080H ADDRESSING MODE DA DA.b EMB = 0 EMB = 1 @HL @H + DA.b EMB = 0 EMB = 1 @WX @WL X mema.b X memb.@L X WORKING REGISTERS SMB = 0 BANK 0 (GENERAL REGISTERS AND STACK) SMB = 0 0FFH ~ ~ ~ ~ 1E0H BANK 1 (DISPLAY REGISTERS) SMB = 1 SMB = 1 1FFH F80H BANK 15 (PERIPHERAL HARDWARE REGISTERS) FFFH FB0H FBFH FC0H SMB = 15 SMB = 15 FF0H NOTES 1. 'X' means don't care. 2. Blank columns indicate RAM areas that are not addressable, given the addressing method and enable memory bank (EMB) flag setting shown in the column headers. Figure 3-1. RAM Address Structure 3-2 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESSING MODES EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine has completed. At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR) despite the current SMB setting. + PROGRAMMING TIP — Initializing the EMB and ERB Flags The following assembly instructions show how to initialize the EMB and ERB flag settings: ORG VENT0 VENT1 VENT2 VENT3 ORG VENT5 • • • BITR 0000H 1,0,RESET 0,1,INTB 0,1,INT0 0,1,INT1 000AH 0,1,INTT0 ; ; ; ; ; ; ; ROM address assignment EMB ← 1, ERB ← 0, branch RESET EMB ← 0, ERB ← 1, branch INTB EMB ← 0, ERB ← 1, branch INT0 EMB ← 0, ERB ← 1, branch INT1 ROM address assignment EMB ← 0, ERB ← 1, branch INTT0 RESET EMB 3-3 ADDRESSING MODES KS57C2302/C2304/P2304 MICROCONTROLLER ENABLE MEMORY BANK SETTINGS EMB = "1" When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0, 1, or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows: If SMB = 0, If SMB = 1, If SMB = 15, EMB = "0" When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. If EMB = "0", the addressable area is restricted to locations 000H–07FH in bank 0 and to locations F80H–FFFH in bank 15 for direct addressing. For indirect addressing, only locations 000H–0FFH in bank 0 are addressable, regardless of SMB value. To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to "1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM address 0000H. EMB-Independent Addressing At any time, several areas of the data memory can be addressed independent of the current status of the EMB flag. These exceptions are described in Table 3-1. 000H–0FFH 1E0H–1FFH F80H–FFFH Table 3-1. RAM Addressing Not Affected by the EMB Value Address 000H–0FFH Addressing Method 4-bit indirect addressing using WX and WL register pairs; 8-bit indirect addressing using SP 1-bit direct addressing 1-bit indirect addressing using the L register Affected Hardware Not applicable LD PUSH POP PSW, SCMOD, IEx, IRQx, I/O BSC, I/O BITS BITR Program Examples A,@WX EA EA EMB IE4 FB0H–FBFH FF0H–FFFH FC0H–FFFH BTST FC3H.@L BAND C,P3.@L 3-4 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESSING MODES SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3-2. During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB instruction. You later restore the value to the SB using the POP SB instruction. SMB (F83H) SB REGISTER SMB 3 SMB 2 SMB 1 SMB 0 0 SRB (F82H) 0 SRB 1 SRB 0 Figure 3-2. SMB and SRB Values in the SB Register Select Register Bank (SRB) Instruction The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, and 3. One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls. RESET clears the 4-bit SRB value to logic zero. Select Memory Bank (SMB) Instruction To select one of the four available data memory banks, you must execute an SMB n instruction specifying the number of the memory bank you want (0, 1, or 15). For example, the instruction 'SMB 1' selects bank 1 and 'SMB 15' selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB flag setting.) The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB value to logic zero. The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls. 3-5 ADDRESSING MODES KS57C2302/C2304/P2304 MICROCONTROLLER DIRECT AND INDIRECT ADDRESSING 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. Indirect addressing specifies a memory location that contains the required direct address. The KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM address must always be used as the instruction operand. 1-BIT ADDRESSING Table 3-2. 1-Bit Direct and Indirect RAM Addressing Operand Notation DA.b Addressing Mode Description Direct: bit is indicated by the RAM address (DA), memory bank selection, and specified bit number (b). mema.b Direct: bit is indicated by addressable area (mema) and bit number (b). Indirect: lower two bits of register L as indicated by the upper 6 bits of RAM area (memb) and the upper two bits of register L. Indirect: bit indicated by the lower four bits of the address (DA), memory bank selection, and the H register identifier. NOTE: x = not applicable. EMB Flag Setting 0 1 Addressable Area 000H–07FH F80H–FFFH 000H–0FFH 1E0H–1FFH F80H–FFFH Memory Bank Bank 0 Bank 15 Bank 0 Bank 1 Bank 15 Bank 15 Hardware I/O Mapping – All 1-bit addressable peripherals (SMB = 15) IS0, IS1, EMB, ERB, IEx, IRQx, Pn.n BSCn.x Pn.n x FB0H–FBFH FF0H–FFFH FC0H–FFFH memb.@L x Bank 15 @H + DA.b 0 1 000H–0FFH 000H–0FFH 1E0H–1FFH F80H–FFFH Bank 0 Bank 0 Bank 1 Bank 15 All 1-bit – addressable peripherals (SMB = 15) 3-6 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESSING MODES + PROGRAMMING TIP — 1-Bit Addressing Modes 1-Bit Direct Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P3.0 ; ; ; ; ; 34H.3 ← 1 F85H.3 ← 1 If FBAH.0 = 1, skip Else if, FBAH.0 = 0, F85H.3 (BMOD.3) ← 1 FF3H.0 (P3.0) ← 1 2. If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P3.0 ; ; ; ; ; 34H.3 ← 1 85H.3 ← 1 If 0BAH.0 = 1, skip Else if 0BAH.0 = 0, 085H.3 ← 1 FF3H.0 (P3.0) ← 1 1-Bit Indirect Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG ; H ← #0BH ; If 0BAH.0 = 1, 0BAH.0 ← 0 and skip ; Else if 0BAH.0 = 0, FBAH.0 ← 1 2.If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG ; H ← #0BH ; If 0BAH.0 = 1, 0BAH.0 ← 0 and skip ; Else if 0BAH.0 = 0, 0BAH.0 ← 1 3-7 ADDRESSING MODES KS57C2302/C2304/P2304 MICROCONTROLLER 4-BIT ADDRESSING Table 3-3. 4-Bit Direct and Indirect RAM Addressing Operand Notation DA Direct: 4-bit address indicated by the RAM address (DA) and the memory bank selection @HL Indirect: 4-bit address indicated by the memory bank selection and register HL 0 1 1 Addressing Mode Description EMB Flag Setting 0 Addressable Area 000H–07FH F80H–FFFH 000H–0FFH 1E0H–1FFH F80H–FFFH 000H–0FFH 000H–0FFH 1E0H–1FFH F80H–FFFH @WX @WL Indirect: 4-bit address indicated by register WX Indirect: 4-bit address indicated by register WL x x 000H–0FFH 000H–0FFH Memory Bank Bank 0 Bank 15 Bank 0 Bank 1 Bank 15 Bank 0 Bank 0 Bank 1 Bank 15 Bank 0 Bank 0 Hardware I/O Mapping – All 4-bit addressable peripherals (SMB = 15) – All 4-bit addressable peripherals (SMB = 15) – NOTE: x = not applicable. 3-8 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESSING MODES + PROGRAMMING TIP — 4-Bit Addressing Modes 4-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A ; ; ; ; ; Non-essential instruction, since EMB = "0" A ← (P3) Non-essential instruction, since EMB = "0" (046H) ← A (F8EH (LCON)) ← A 2. If EMB = "1": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A ; A ← (P3) ; (046H) ← A ; (08EH) ← A 4-Bit Indirect Addressing 1. If EMB = "0", compare bank 0 locations 040H–046H with bank 0 locations 060H–066H: ADATA BDATA EQU EQU SMB LD LD LD CPSE SRET DECS JR RET 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL L COMP ; Non-essential instruction, since EMB = "0" ; A ← bank 0 (040H–046H) ; If bank 0 (060H–066H) = A, skip COMP 2. If EMB = "0", exchange bank 0 locations 040H–046H with bank 0 locations 060H–066H: ADATA BDATA EQU EQU SMB LD LD LD XCHD JR 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS ; Non-essential instruction, since EMB = "0" ; A ← bank 0 (040H–046H) ; Bank 0 (060H–066H) ↔ A TRANS 3-9 ADDRESSING MODES KS57C2302/C2304/P2304 MICROCONTROLLER 8-BIT ADDRESSING Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instruction Notation DA Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection @HL Indirect: the 8-bit address 4-bit indicated by the memory bank selection and register HL; (the L register value must be an even number) 0 1 1 Addressing Mode Description EMB Flag Setting 0 Addressable Area 000H–07FH F80H–FFFH 000H–0FFH 1E0H–1FFH F80H–FFFH 000H–0FFH 000H–0FFH 1E0H–1FFH F80H–FFFH Memory Bank Bank 0 Bank 15 Bank 0 Bank 1 Bank 15 Bank 0 Bank 0 Bank 1 Bank 15 Hardware I/O Mapping – All 8-bit addressable peripherals (SMB = 15) – All 8-bit addressable peripherals (SMB = 15) 3-10 KS57C2302/C2304/P2304 MICROCONTROLLER ADDRESSING MODES + PROGRAMMING TIP — 8-Bit Addressing Modes 8-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU LD SMB LD LD 46H 8EH EA, #0FFH 0 ADATA,EA BDATA,EA ; (046H) ← A, (047H) ← E ; (F8EH) ← A, (F8FH) ← E 2. If EMB = "1": ADATA BDATA EQU EQU SMB LD LD LD 46H 8EH 0 EA, #0FFH ADATA,EA BDATA,EA ; (046H) ← A, (047H) ← E ; (08EH) ← A, (08FH) ← E 8-Bit Indirect Addressing 1. If EMB = "0": ADATA EQU SMB LD LD 46H 1 HL,#ADATA EA,@HL ; Non-essential instruction, since EMB = "0" ; A ← (046H), E ← (047H) 3-11 ADDRESSING MODES KS57C2302/C2304/P2304 MICROCONTROLLER NOTES 3-12 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP 4 OVERVIEW MEMORY MAP To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current EMB value. I/O MAP FOR HARDWARE REGISTERS Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map gives you the following information: — Register address — Register name (mnemonic for program addressing) — Bit values (both addressable and non-manipulable) — Read-only, write-only, or read and write addressability — 1-bit, 4-bit, or 8-bit data manipulation characteristics 4-1 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER Table 4-1. I/O Map for Memory Bank 15 Memory Bank 15 Address F80H F81H F85H F86H F87H F88H F89H F8CH F8DH F8EH F90H F91H F92H F94H F95H F96H F97H F98H F99H F9AH FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H IPR PCON IMOD0 IMOD1 IMOD2 SCMOD WDFLAG PSW WDMOD TREF0 TCNT0 LCON TMOD0 LMOD WMOD BMOD BCNT Register SP Bit 3 .3 .7 .3 .3 .7 .3 .7 .3 .7 "0" (4) Addressing Mode Bit 1 .1 .5 .1 .1 .5 .1 .5 .1 .5 "0" "0" .5 "u" (4) .1 .5 .1 .5 .1 .5 “0” EMB SC1 .1 .1 .1 "0" .1 "0" Bit 0 "0" .4 .0 .0 .4 .0 .4 .0 .4 .0 "0" .4 "u" (4) .0 .4 .0 .4 .0 .4 “0” ERB SC0 .0 .0 .0 .0 .0 .0 W Yes No No W R/W R W W W Yes Yes No IME No No Yes Yes No Yes Yes Yes No No No No Yes W No No Yes W No No Yes R/W R Yes No No No No Yes W W No .3 Yes No No Yes W .3 No Yes W .3 (1) No Yes W R .3 No Yes No No Yes R/W R/W 1-Bit No 4-Bit No 8-Bit Yes Bit 2 .2 .6 .2 .2 .6 .2 "0" .2 .6 .2 .2 .6 TOE0 .2 .6 .2 .6 .2 .6 “0” IS0 SC2 .2 .2 "0" "0" "0" .2 Locations F82H–F84H are not mapped. Locations F8AH–F8BH are not mapped. Location F8FH is not mapped. .3 "0" "u" (4) .3 .7 .3 .7 .3 .7 .3 IS1 C (2) IME .3 .3 "0" "0" .3 Location F93H is not mapped. Locations F9BH–FAFH are not mapped. 4-2 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP Table 4-1. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FB8H FBAH FBCH FBEH FBFH FC0H FC1H FC2H FC3H FD0H FDCH FDDH FE8H FE9H FECH FEDH FF1H FF2H FF3H FF6H Port 1 Port 2 Port 3 Port 6 PMG2 PMG1 Register INT (A) INT (B) INT (C) INT (E) INT (F) BSC0 BSC1 BSC2 BSC3 CLMOD PUMOD Bit 3 "0" “0” "0" IE1 “0” .3 .3 .3 .3 .3 PM.3 "0" PM3.3 PM6.3 “0” "0" .3 .3 .3 .3 Bit 2 "0" “0” "0" IRQ1 “0” .2 .2 .2 .2 "0" PM.2 PM.6 PM3.2 PM6.2 PM2 “0” .2 .2 .2 .2 Bit 1 IEB IEW IET0 IE0 IE2 .1 .1 .1 .1 .1 PM.1 "0" PM3.1 PM6.1 “0” "0" .1 .1 .1 .1 Bit 0 IRQB IRQW IRQT0 IRQ0 IRQ2 .0 .0 .0 .0 .0 "0" "0" PM3.0 PM6.0 “0” "0" .0 .0 .0 .0 R R/W R/W R/W Yes Yes Yes Yes Yes Yes Yes Yes No No No No W No No Yes W No No Yes W W No No Yes No No Yes R/W Yes Yes Yes R/W R/W R/W R/W R/W Addressing Mode 1-Bit Yes Yes Yes Yes 4-Bit Yes Yes Yes Yes 8-Bit No No No No Location FB9H is not mapped Location FBBH is not mapped. Location FBDH is not mapped. Locations FD1H–FDBH are not mapped. Locations FDEH–FE7H are not mapped. Locations FEAH–FEBH are not mapped. Locations FEEH–FF0H are not mapped. Locations FF4H–FF5H are not mapped. Locations FF7H–FFFH are not mapped. NOTES: 1. Bit 3 in the WMOD register is read only. 2. The carry flag can be read or written by specific bit manipulation instructions only. 3. The LCON.3 register must be set to “0”. 4. “u” means that the value is undetermined. 4-3 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER REGISTER DESCRIPTIONS In this section, register descriptions are presented in a consistent format to familiarize you with the memorymapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description format. Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference source when writing application programs. Counter registers and reference registers, as well as the stack pointer and port I/O latches, are not included in these descriptions. More detailed information about how these registers are used is included in Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module descriptions. 4-4 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP Register and bit IDs used for bit addressing Register ID Register name Name of individual bit or related bits Associated hardware module Register location in RAM bank 15 CLMOD− Clock Output Mode Control Register Bit Identifier RESET CPU 1 .1 0 W 4 0 .0 0 W 4 FD0H 3 .3 Value 0 W 4 2 .2 0 W 4 Read/Write Bit Addressing CLMOD.3 Enable/Disable Clock Output Control Bit 0 1 Disable clock output Enable clock output CLMOD.2 Bit 2 0 Always logic zero CLMOD.1 - .0 Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source Select system clock fxx/8 (524 kHz at 4.19 MHz) Select system clock fxx/16 (262 kHz at 4.19 MHz) Select system clock fxx/64 (65.5 kHz at 4.19 MHz) R = Read-only W = Write-only R/W =Read/write Bit value immediately following a RESET Bit number in MSB to LSB order Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) Description of the effect of specific bit settings Bit identifier used for bit addressing Figure 4-1. Register Description Format 4-5 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER BMOD — Basic Timer Mode Register Bit Identifier RESET F85H 1 .1 0 W 4 0 .0 0 W 4 3 .3 0 W 1/4 Value 2 .2 0 W 4 Read/Write Bit Addressing .3 Basic Timer Restart Bit 1 Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero .2–.0 Input Clock Frequency and Signal Stabilization Interval Control Bits 0 0 1 1 0 1 0 1 0 1 1 1 Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: fxx / 212 (1.02 kHz) 220 / fxx (250 ms) fxx / 29 (8.18 kHz) 217 / fxx (31.3 ms) fxx / 27 (32.7 kHz) 215 / fxx (7.82 ms) fxx / 25 (131 kHz) 213 / fxx (1.95 ms) NOTES: 1. Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. The stabilization interval can also be interpreted as "Interrupt Interval Time". 2. When a RESET occurs, the oscillation stabilization time is 31.3 ms (217/fxx) at 4.19 MHz. 3. 'fxx' is the system clock rate given a clock frequency of 4.19 MHz. 4-6 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP CLMOD — Clock Output Mode Register Bit Identifier RESET FD0H 0 .0 0 W 4 3 .3 0 W 4 Value 2 "0" 0 W 4 1 .1 0 W 4 Read/Write Bit Addressing .3 Enable/Disable Clock Output Control Bit 0 1 Disable clock output Enable clock output .2 Bit 2 0 Always logic zero .1–.0 Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source fx/4, fx/8, fx/64 or fxt/4 (1.05 MHz, 524 kHz, 65.5 kHz or 8.192KHz) Select system clock fxx/8 (524 kHz) Select system clock fxx/16 (262 kHz) Select system clock fxx/64 (65.5 kHz) NOTE: 'fxx' and 'fx' is the system clock and the main clock respectively, given a clock frequency of 4.19 MHz. 'fxt' is the sub clock, given a clock frequency of 32.768KHz. 4-7 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER IE0, 1, IRQ0, 1 — INT0, 1 Interrupt Enable/Request Flags Bit Identifier RESET FBEH 3 IE1 0 R/W 1/4 Value 2 IRQ1 0 R/W 1/4 1 IE0 0 R/W 1/4 0 IRQ0 0 R/W 1/4 Read/Write Bit Addressing IE1 INT1 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT1 pin Enable interrupt requests at the INT1 pin IRQ1 INT1 Interrupt Request Flag – Generate INT1 interrupt (This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin.) IE0 INT0 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT0 pin Enable interrupt requests at the INT0 pin IRQ0 INT0 Interrupt Request Flag – Generate INT0 interrupt (This bit is set and cleared automatically by hardware when rising or falling edge detected at INT0 pin.) 4-8 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP IE2, IRQ2 — INT2 Interrupt Enable/Request Flags Bit Identifier RESET FBFH 3 "0" 0 R/W 1/4 Bits 3–2 0 Value 2 "0" 0 R/W 1/4 1 IE2 0 R/W 1/4 0 IRQ2 0 R/W 1/4 Read/Write Bit Addressing .3–.2 Always logic zero IE2 INT2 Interrupt Enable Flag 0 1 Disable INT2 interrupt requests at the INT2 pin Enable INT2 interrupt requests at the INT2 pin IRQ2 INT2 Interrupt Request Flag – Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2. Since INT2 is a quasi-interrupt, IRQ2 flag must be cleared by software.) 4-9 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER IEB, IRQB — INTB Interrupt Enable/Request Flags Bit Identifier RESET FB8H 3 “0” 0 R/W 1/4 Bits 3–2 0 Value 2 “0” 0 R/W 1/4 1 IEB 0 R/W 1/4 0 IRQB 0 R/W 1/4 Read/Write Bit Addressing .3–.2 Always logic zero IEB INTB Interrupt Enable Flag 0 1 Disable INTB interrupt requests Enable INTB interrupt requests IRQB INTB Interrupt Request Flag – Generate INTB interrupt (This bit is set and cleared automatically by hardware when reference interval signal received from basic timer.) 4-10 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP IET0, IRQT0 — INTT0 Interrupt Enable/Request Flags Bit Identifier RESET FBCH 3 "0" 0 R/W 1/4 Bits 3–2 0 Value 2 "0" 0 R/W 1/4 1 IET0 0 R/W 1/4 0 IRQT0 0 R/W 1/4 Read/Write Bit Addressing .3–.2 Always logic zero IET0 INTT0 Interrupt Enable Flag 0 1 Disable INTT0 interrupt requests Enable INTT0 interrupt requests IRQT0 INTT0 Interrupt Request Flag – Generate INTT0 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match.) 4-11 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER IEW, IRQW — INTW Interrupt Enable/Request Flags Bit Identifier RESET FBAH 3 "0" 0 R/W 1/4 Bits 3–2 0 Value 2 "0" 0 R/W 1/4 1 IEW 0 R/W 1/4 0 IRQW 0 R/W 1/4 Read/Write Bit Addressing .3–.2 Always logic zero IEW INTW Interrupt Enable Flag 0 1 Disable INTW interrupt requests Enable INTW interrupt requests IRQW INTW Interrupt Request Flag – Generate INTW interrupt (This bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.) NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software. 4-12 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP IMOD0 — External Interrupt 0 (INT0) Mode Register Bit Identifier RESET FB4H 3 .3 0 W 4 Value 2 "0" 0 W 4 1 .1 0 W 4 0 .0 0 W 4 Read/Write Bit Addressing .3 Interrupt Sampling Clock Selection Bit 0 1 Select CPU clock as a sampling clock Select sampling clock frequency of the selected system clock (fxx/64) .2 Bit 2 0 Always logic zero .1–.0 External Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Interrupt requests are triggered by a rising signal edge Interrupt requests are triggered by a falling signal edge Interrupt requests are triggered by both rising and falling signal edges Interrupt request flag (IRQ0) cannot be set to logic one 4-13 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER IMOD1 — External Interrupt 1 (INT1) Mode Register Bit Identifier RESET FB5H 3 "0" 0 W 4 Bits 3–1 0 Value 2 "0" 0 W 4 1 "0" 0 W 4 0 IMOD1.0 0 W 4 Read/Write Bit Addressing .3–.1 Always logic zero .0 External Interrupt 1 Edge Detection Control Bit 0 1 Rising edge detection Falling edge detection 4-14 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP IMOD2 — External Interrupt 2 (INT2) Mode Register Bit Identifier RESET FB6H 3 "0" 0 W 4 Bits 3–2 0 Value 2 "0" 0 W 4 1 IMOD2.1 0 W 4 0 IMOD2.0 0 W 4 Read/Write Bit Addressing .3–.2 Always logic zero .1–.0 External Interrupt 2 Edge Detection Selection Bit 0 0 1 1 0 1 0 1 Select rising edge at INT2 pin Reserved Select falling edge at KS2–KS3 Select falling edge at KS0–KS3 4-15 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER IPR — Interrupt Priority Register Bit Identifier RESET FB2H 1 .1 0 W 4 0 .0 0 W 4 3 IME 0 W 1/4 Value 2 .2 0 W 4 Read/Write Bit Addressing IME Interrupt Master Enable Bit 0 1 Disable all interrupt processing Enable processing for all interrupt service requests .2–.0 Interrupt Priority Assignment Bits 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Normal interrupt handling according to default priority settings Process INTB interrupt at highest priority Process INT0 interrupt at highest priority Process INT1 interrupt at highest priority Reserved Process INTT0 interrupt at highest priority 4-16 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP LCON — LCD Output Control Register Bit Identifier RESET F8EH 0 .0 0 W 4 3 "0" 0 W 4 Value 2 .2 0 W 4 1 "0" 0 W 4 Read/Write Bit Addressing .3 LCD Bias Selection Bit 0 This bit is used for internal testing only; always logic zero. .2 LCD Clock Output Disable/Enable Bit 0 1 Disable LCDCK and LCDSY signal outputs. Enable LCDCK and LCDSY signal outputs. .1 Bit 1 0 Always logic zero .0 LCD Display Control Bit 0 1 LCD output low, turns display off: cut off current to dividing resistor, and output port 8 latch contents. If LMOD.3 = “0”: turn display off; output port 8 latch contents; If LMOD.3 = “1”: COM and SEG output in display mode; LCD display on. NOTES: 1. You can manipulate LCON.0, when you try to turn ON/OFF LCD display internally. If you want to control LCD ON/OFF or LCD contrast externally, you should set the LCON.0 to "0". refer to chapter 12, if you need more information. 2. To select the LCD bias, you must properly configure both LCON.0 and the external LCD bias circuit connection. 3. The LCON.3 register must be set to “0”. 4-17 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER LMOD — LCD Mode Register Bit Identifier RESET F8DH, F8CH 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 1/8 2 .2 0 W 8 1 .1 0 W 8 0 .0 0 W 8 7 .7 0 W 8 Value Read/Write Bit Addressing .7–.6 LCD Output Segment and Pin Configuration Bits 0 0 1 1 0 1 0 1 Segments 24–27; and 28–31 Segment 24–27; 1-bit output at P8.4–P8.7 Segment 28–31; 1-bit output at P8.0–P8.3 1-bit output only at P8.0–P8.3, and P8.4–P8.7 .5–.4 LCD Clock (LCDCK) Frequency Selection Bits 0 0 1 1 0 1 0 1 fw/29 = 64 Hz fw/28 = 128 Hz fw/27 = 256 Hz fw/26 = 512 Hz .3–.0 Duty and Bias Selection for LCD Display 0 1 1 1 1 1 – 0 0 0 0 1 – 0 0 1 1 0 – 0 1 0 1 0 LCD display off 1/4 duty, 1/3 bias 1/3 duty, 1/3 bias 1/2 duty, 1/2 bias 1/3 duty, 1/2 bias Static NOTE: Watch timer frequency(fw) is assumed to be 32.768KHz. 4-18 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP PCON — Power Control Register Bit Identifier RESET FB3H 1 .1 0 W 4 0 .0 0 W 4 3 .3 0 W 4 Value 2 .2 0 W 4 Read/Write Bit Addressing .3–.2 CPU Operating Mode Control Bits 0 0 1 0 1 0 Enable normal CPU operating mode Initiate idle power-down mode Initiate stop power-down mode .1–.0 CPU Clock Frequency Selection Bits 0 1 1 0 0 1 If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4 NOTE: 'fx' is the main system clock; 'fxt' is the subsystem clock. 4-19 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER PMG1 — Port I/O Mode Flags (Group 1: Ports 3 and 6) Bit Identifier RESET FE9H, FE8H 3 2 PM3.2 0 W 8 1 PM3.1 0 W 8 0 PM3.0 0 W 8 7 PM6.3 0 W 8 Value 6 PM6.2 0 W 8 5 PM6.1 0 W 8 4 PM6.0 0 W 8 PM3.3 0 W 8 Read/Write Bit Addressing PM6.3 P6.3 I/O Mode selection Flag 0 1 Set P6.3 to input mode Set P6.3 to output mode PM6.2 P6.2 I/O Mode Selection Flag 0 1 Set P6.2 to input mode Set P6.2 to output mode PM6.1 P6.1 I/O Mode Selection Flag 0 1 Set P6.1 to input mode Set P6.1 to output mode PM6.0 P6.0 I/O Mode Selection Flag 0 1 Set P6.0 to input mode Set P6.0 to output mode PM3.3 P3.3 I/O Mode Selection Flag 0 1 Set P3.3 to input mode Set P3.3 to output mode PM3.2 P3.2 I/O Mode Selection Flag 0 1 Set P3.2 to input mode Set P3.2 to output mode PM3.1 P3.1 I/O Mode Selection Flag 0 1 Set P3.1 to input mode Set P3.1 to output mode PM3.0 P3.0 I/O Mode Selection Flag 0 1 Set P3.0 to input mode Set P3.0 to output mode 4-20 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP PMG2 — Port I/O Mode Flags (Group 2: Port 2) Bit Identifier RESET FEDH, FECH 3 “0” 0 W 8 2 PM2 0 W 8 1 “0” 0 W 8 0 “0” 0 W 8 7 “0” 0 W 8 Bits 7–3 0 Value 6 “0” 0 W 8 5 “0” 0 W 8 4 “0” 0 W 8 Read/Write Bit Addressing .7–.3 Always logic zero PM2 P2 I/O Mode Selection Flag 0 1 Set P2 to input mode Set P2 to output mode .1–.0 Bits 1–0 0 Always logic zero 4-21 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER PSW — Program Status Word Bit Identifier RESET FB1H, FB0H 6 5 SC1 0 R 8 4 SC0 0 R 8 3 IS1 0 R/W 1/4 2 IS0 0 R/W 1/4 1 EMB 0 R/W 1 0 ERB 0 R/W 1 7 C (1) SC2 0 R 8 Value Read/Write Bit Addressing C R/W (2) Carry Flag 0 1 No overflow or borrow condition exists An overflow or borrow condition exists SC2–SC0 Skip Condition Flags 0 1 No skip condition exists; no direct manipulation of these bits is allowed A skip condition exists; no direct manipulation of these bits is allowed IS1, IS0 Interrupt Status Flags 0 0 1 1 0 1 0 1 Service all interrupt requests Service only the high-priority interrupt(s) as determined in the interrupt priority register (IPR) Do not service any more interrupt requests Undefined EMB Enable Data Memory Bank Flag 0 1 Restrict program access to data memory to bank 15 (F80H–FFFH) and to the locations 000H–07FH in the bank 0 only Enable full access to data memory banks 0, 1, 2, and 15 ERB Enable Register Bank Flag 0 1 Select register bank 0 as working register area Select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (SRB) instruction operand NOTES: 1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during power-down mode (IDLE or STOP), the current value of the carry flag is retained. 2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for detailed information. 4-22 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP PUMOD — Pull-Up Resistor Mode Register Bit Identifier RESET FDDH, FDCH 4 “0” 0 W 8 3 PUR3 0 W 8 2 PUR2 0 W 8 1 PUR1 0 W 8 0 “0” 0 W 8 7 “0” 0 W 8 Bit 7 0 Value 6 PUR6 0 W 8 5 “0” 0 W 8 Read/Write Bit Addressing .7 Always logic zero PUR6 Connect/Disconnect Port 6 Pull-Up Resistor Control Bit 0 1 Disconnect port 6 pull-up resistor Connect port 6 pull-up resistor .5–.4 Bits 5–4 0 Always logic zero PUR3 Connect/Disconnect Port 3 Pull-Up Resistor Control Bit 0 1 Disconnect port 3 pull-up resistor Connect port 3 pull-up resistor PUR2 Connect/Disconnect Port 2 Pull-Up Resistor Control Bit 0 1 Disconnect port 2 pull-up resistor Connect port 2 pull-up resistor PUR1 Connect/Disconnect Port 1 Pull-Up Resistor Control Bit 0 1 Disconnect port 1 pull-up resistor Connect port 1 pull-up resistor .0 Bit 0 0 Always logic zero NOTE: Pull-up resistors for all I/O ports are automatically disabled when they are configured to output mode. 4-23 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER SCMOD — System Clock Mode Control Register Bit Identifier RESET FB7H 0 .0 0 W 1 3 .3 0 W 1 Value 2 .2 0 W 1 1 "0" 0 W 1 Read/Write Bit Addressing .3, .2 and .0 CPU Clock Selection and Main System Clock Oscillation Control Bits 0 0 0 1 0 1 0 0 0 0 1 1 Select main system clock (fx); enable main system clock Select main system clock (fx); disable sub system clock Select sub system clock (fxt); enable main system clock Select sub system clock (fxt); disable main system clock .1 Bit 1 0 Always logic zero NOTE: SCMOD bits 3 and 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions. 4-24 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP TMOD0 — Timer/Counter 0 Mode Register Bit Identifier RESET F91H, F90H 4 .4 0 W 8 3 .3 0 W 1/8 2 .2 0 W 8 1 "0" 0 W 8 0 "0" 0 W 8 7 "0" 0 W 8 Bit 7 0 Value 6 .6 0 W 8 5 .5 0 W 8 Read/Write Bit Addressing .7 Always logic zero .6–.4 Timer/Counter 0 Input Clock Selection Bits 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 External clock input at TCL0 pin on rising edge External clock input at TCL0 pin on falling edge Select clock: fxx/210 (4.09 kHz at 4.19 MHz) Select clock: fxx/28 (16.4 kHz at 4.19 MHz) Select clock: fxx/26 (65.5 kHz at 4.19 MHz) Select clock: fxx/24 (262 kHz at 4.19 MHz) .3 Clear Counter and Resume Counting Control Bit 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is cleared automatically when counting starts.) .2 Enable/Disable Timer/Counter 0 Bit 0 1 Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0 .1–.0 Bits 1–0 0 Always logic zero 4-25 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER TOE — Timer Output Enable Flag Register Bit Identifier RESET F92H 0 "u" – – – 3 "u" – – – Bit3 u Value 2 TOE0 0 R/W 1 1 "u" 0 – – Read/Write Bit Addressing .3 Unknown value TOE0 Timer/Counter 0 Output Enable Flag 0 1 Disable timer/counter 0 output at the TCLO0 pin Enable timer/counter 0 output at the TCLO0 pin .1–.0 Bits 1–0 u Unknown value NOTES: 1. “u” means that the bit is unknown. 4-26 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP WDFLAG — Watchdog Timer Counter Clear Flag Register Bit Identifier RESET F9AH 3 WDTCF 0 W 1/4 Value 2 “0” 0 W 1/4 1 “0” 0 W 1/4 0 “0” 0 W 1/4 Read/Write Bit Addressing WDTCF Watchdog Timer Counter Clear Flag 1 Clears the watchdog timer counter .2–.0 Bits 2–0 0 Always logic zero NOTE: After watchdog timer is cleared by writing “1”, this bit is cleared to “0” automatically. Instruction that clear the watchdog timer (“BITS WDTCF”) should be executed at proper points in a program within a given period. If not executed within a given period and watchdog timer overflows, RESET signal is generated and system is restarted with reset status. 4-27 MEMORY MAP KS57C2302/C2304/P2304 MICROCONTROLLER WDMOD — Watchdog Timer Mode Register Bit Identifier RESET F99H, F98H 4 .4 0 W 8 3 .3 0 W 8 2 .2 1 W 8 1 .1 0 W 8 0 .0 1 W 8 7 .7 1 W 8 Value 6 .6 0 W 8 5 .5 1 W 8 Read/Write Bit Addressing WDMOD Watchdog Timer Enable/Disable Control 5AH Any other value Disable watchdog timer function Enable watchdog timer function 4-28 KS57C2302/C2304/P2304 MICROCONTROLLER MEMORY MAP WMOD — Watch Timer Mode Register Bit Identifier RESET F89H, F88H 4 .4 0 W 8 3 .3 (note) 7 .7 0 W 8 Value 6 "0" 0 W 8 5 .5 0 W 8 2 .2 0 W 8 1 .1 0 W 8 0 .0 0 W 8 Read/Write Bit Addressing .7 R 1 Enable/Disable Buzzer Output Bit 0 1 Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output .6 Bit 6 0 Always logic zero .5–.4 Output Buzzer Frequency Selection Bits 0 0 1 1 0 1 0 1 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output .3 XTin Input Level Control Bit 0 1 Input level to XTin pin is low; 1-bit read-only addressable for tests Input level to XTin pin is high; 1-bit read-only addressable for tests .2 Enable/Disable Watch Timer Bit 0 1 Disable watch timer and clear frequency dividing circuits Enable watch timer .1 Watch Timer Speed Control Bit 0 1 Normal speed; set IRQW to 0.5 seconds High-speed operation; set IRQW to 3.91 ms .0 Watch Timer Clock Selection Bit 0 1 Select system clock (fxx)/128 as the watch timer clock Select a subsystem clock as the watch timer clock NOTE: RESET sets WMOD.3 to the current input level of the subsystem clock, XTin. If the input level is high, WMOD.3 is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register. 4-29 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET 5 SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction operand in place of the actual address. Other important features of the SAM47 instruction set include: — 1-byte referencing of long instructions (REF instruction) — Redundant instruction reduction (string effect) — Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple operand formats. Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb, b, and so on. Using instruction labels can greatly simplify program writing and debugging tasks. INSTRUCTION SET FEATURES In this Chapter, the following SAM47 instruction set features are described in detail: — Instruction reference area — Instruction redundancy reduction — Flexible bit manipulation — ADC and SBC instruction skip condition NOTE The ROM size accessed by instruction may change for KS57C2302 and KS57C2304. 5-1 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER Instruction Reference Area Using the 1-byte REF (Reference) instruction, you can reference instructions stored in addresses 0020H–007FH of program memory (the REF instruction look-up table). The location referenced by REF may contain either two 1-byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must always be an even number. 3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte instructions, the 2-byte pseudo commands TJP and TCALL must be written in the reference. The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction execution sequence resumes at the address immediately following the REF instruction. By using REF instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the program size. To summarize, the REF instruction can be used in three ways: — Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions; — Branching to any location by referencing a branch address that is stored in the look-up table; — Calling subroutines at any location by referencing a call address that is stored in the look-up table. If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions. Two-byte instructions can be referenced by using a REF instruction. (An exception is XCH A,DA*) If the MSB value of the first 1-byte instruction in the reference area is “0”, the instruction cannot be referenced by a REF instruction. Therefore, if you use REF to reference two 1-byte instructions stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. These combinations are described in Table5-1. Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups First 1-Byte Instruction Instruction LD Operand A,#im Second 1-Byte Instruction Instruction INCS* INCS DECS* LD A,@RRq INCS* INCS DECS* LD @HL,A INCS* INCS DECS* Operand R RRb R R RRb R R RRb R NOTE: If the MSB value of the first one-byte binary code in instruction is "0", the instruction cannot be referenced by a REF instruction. 5-2 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET Reducing Instruction Redundancy When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also ignored. In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows it is interpreted as redundant and is ignored: LD LD A,#im EA,#imm ; Load 4-bit immediate data (#im) to accumulator ; Load 8-bit immediate data (#imm) to extended ; accumulator In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored: BITR LD LD LD LD EMB A,#1H A,#2H A,#3H 23H,A ; ; ; ; Execute instruction Ignore, redundant instruction Ignore, redundant instruction Execute instruction, 023H ← #1H If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are detected, only the first LD is executed and the LDs which immediately follow are ignored. For example, LD LD LD LD LD HL,#10H HL,#20H A,#3H EA,#35H @HL,A ; ; ; ; ; HL ← 10H Ignore, redundant instruction A ← 3H Ignore, redundant instruction (10H) ← 3H If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply: — If the instruction preceding the REF has a redundancy effect, this effect is canceled and the referenced instruction is not skipped. — If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped. + PROGRAMMING TIP — Example of the Instruction Redundancy Effect ABC ORG LD ORG • • • LD REF • • • REF LD 0020H EA,#30H 0080H ; Stored in REF instruction reference area EA,#40H ABC ; Redundancy effect is encountered ; No skip (EA ← #30H) ABC EA,#50H ; EA ← #30H ; Skip 5-3 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear, the SAM47 instruction set can also perform bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit addressing modes. Three types of bit addressing are supported: — mema.b — memb.@L — @H+DA.b The parameters of these bit addressing modes are described in more detail in Table 5-2. Table 5-2. Bit Addressing Modes and Parameters Addressing Mode mema.b memb.@L @H+DA.b Addressable Peripherals ERB, EMB, IS1, IS0, IEx, IRQx Ports 1, 2, 3, 6 Ports 1, 2, 3, 6, and BSC All bit-manipulable peripheral hardware FB0H–FBFH FF0H–FFFH FC0H–FFFH All bits of the memory bank specified by EMB and SMB that are bit-manipulable Address Range Instructions Which Have Skip Conditions The following instructions have a skip function when an overflow or borrow occurs: XCHI XCHD LDI LDD INCS DECS ADS SBS If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. However, the carry flag value is unaffected. The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. Instructions Which Affect the Carry Flag The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: ADC SBC SCF RCF CCF LDB BAND BOR BXOR C,(operand) C,(operand) C,(operand) C,(operand) 5-4 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET ADC and SBC Instruction Skip Conditions The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ADS A,#im'. If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If, however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and 'SBC A,@HL' skip feature. Table 5-3. Skip Conditions for ADC and SBC Instructions Sample Instruction Sequences ADC A,@HL ADS A,#im xxx xxx SBC A,@HL ADS A,#im xxx xxx 1 2 3 4 1 2 3 4 If the result of instruction 1 is: Overflow No overflow Borrow No borrow Then, the execution sequence is: 1, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 3, 4 Reason ADS cannot skip instruction 3, even if it has a skip function. ADS cannot skip instruction 3, even if it has a skip function. 5-5 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER SYMBOLS and CONVENTIONS Table 5-4. Data Type Symbols Symbol d a b r f i t Data Type Immediate data Address data Bit data Register data Flag data Indirect addressing data memc × 0.5 immediate data @ src dst (R) .b im imm # Table 5-5. Register Identifiers Full Register Name 4-bit accumulator 4-bit working registers 8-bit extended accumulator 8-bit memory pointer 8-bit working registers Select register bank 'n' Select memory bank 'n' Carry flag Program status word Port 'n' 'm'-th bit of port 'n' Interrupt priority register Enable memory bank flag Enable register bank flag A E, L, H, X, W, Z, Y EA HL WX, YZ, WL SRB n SMB n C PSW Pn Pn.m IPR EMB ERB SB XOR OR AND [(RR)] ID ADR ADRn R Ra RR RRa RRb RRc mema memb memc Table 5-6. Instruction Operand Notation Symbol DA Definition Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 000H–1FFFH immediate address 'n' bit address A, E, L, H, X, W, Z, Y E, L, H, X, W, Z, Y EA, HL, WX, YZ HL, WX, WL HL, WX, YZ WX, WL FB0H–FBFH, FF0H–FFFH FC0H–FFFH Code direct addressing: 0020H–007FH Select bank register (8 bits) Logical exclusive-OR Logical OR Logical AND Contents addressed by RR 5-6 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET OPCODE DEFINITIONS Table 5-7. Opcode Definitions (Direct) Register A E L H X W Z Y EA HL WX YZ r2 0 0 0 0 1 1 1 1 0 0 1 1 r1 0 0 1 1 0 0 1 1 0 1 0 1 r0 0 1 0 1 0 1 0 1 0 0 0 0 Table 5-8. Opcode Definitions (Indirect) Register @HL @WX @WL i2 1 1 1 i1 0 1 1 i0 1 0 1 i = Immediate data for indirect addressing r = Immediate data for register CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected using the PCON register. In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped — whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB instructions. The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows: Case 1: No skip Case 2: Skip is 1-byte or 2-byte instruction Case 3: Skip is 3-byte instruction S = 0 cycles S = 1 cycle S = 2 cycles NOTE: REF instructions are skipped in one machine cycle. 5-7 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER HIGH-LEVEL SUMMARY This Chapter contains a high-level summary of the SAM47 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category. These tables are a useful quick-reference resource when writing application programs. If you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. The following information is provided for each instruction: — Instruction name — Operand(s) — Brief operation description — Number of bytes of the instruction and operand(s) — Number of machine cycles required to execute the instruction The tables in this Chapter are arranged according to the following instruction categories: — CPU control instructions — Program control instructions — Data transfer instructions — Logic instructions — Arithmetic instructions — Bit manipulation instructions 5-8 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET Table 5-9. CPU Control Instructions — High-Level Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand Operation Description Set carry flag to logic one Reset carry flag to logic zero Complement carry flag Enable all interrupts Disable all interrupts Engage CPU idle mode Engage CPU stop mode No operation Select memory bank Select register bank Reference code Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location Bytes 1 1 1 2 2 2 2 1 2 2 1 2 Cycles 1 1 1 2 2 2 2 1 2 2 3 2 Table 5-10. Program Control Instructions — High-Level Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR JP JPS JR ADR12 ADR12 #im @WX @EA CALL CALLS RET IRET SRET ADR12 ADR11 – – – Operation Description Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Jump to direct address (12 bits) Jump direct in page (12 bits) Jump to immediate address Branch relative to WX register Branch relative to EA Call direct address (12 bits) Call direct address within 2 K (11 bits) Return from subroutine Return from interrupt Return from subroutine and skip Bytes 2 2 2 1 2 2 3 2 1 2 2 3 2 1 1 1 Cycles 2+S 2+S 2+S 1+S 2+S 2+S 3 2 2 3 3 4 3 3 3 3+S 5-9 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER Table 5-11. Data Transfer Instructions — High-Level Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH POP A,@HL A,@HL EA,@WX EA,@EA A RR SB RR SB Operation Description Exchange A and direct data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Exchange A and indirect data memory contents; increment contents of register L and skip on carry Exchange A and indirect data memory contents; decrement contents of register L and skip on carry Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Load indirect data memory to A; increment register L contents and skip on carry Load indirect data memory contents to A; decrement register L contents and skip on carry Load code byte from WX to EA Load code byte from EA to EA Rotate right through carry bit Push register pair onto stack Push SMB and SRB values onto stack Pop to register pair from stack Pop SMB and SRB values from stack Bytes 2 1 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 1 1 1 1 1 1 2 1 2 Cycles 2 1 1 2 2 2 2+S 2+S 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 2+S 2+S 3 3 1 1 2 1 2 5-10 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET Table 5-12. Logic Instructions — High-Level Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A Operation Description Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Complement accumulator (A) Bytes 2 1 2 2 2 1 2 2 2 1 2 2 2 Cycles 2 1 2 2 2 1 2 2 2 1 2 2 2 Table 5-13. Arithmetic Instructions — High-Level Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS INCS R RR R DA @HL RRb Operation Description Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Add 4-bit immediate data to A and skip on carry Add 8-bit immediate data to EA and skip on carry Add indirect data memory to A and skip on carry Add register pair (RR) contents to EA and skip on carry Add EA to register pair (RRb) and skip on carry Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 1 2 2 1 Cycles 1 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1+S 2+S 1+S 2+S 2+S 1+S 5-11 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER Table 5-14. Bit Manipulation Instructions — High-Level Summary Name BTST C DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b BOR C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b LDB mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load specified memory bit to carry bit Load specified indirect memory bit to carry bit Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Exclusive-OR carry with specified memory bit Logical-OR carry with specified memory bit Logical-AND carry flag with specified memory bit Clear specified memory bit to logic zero Set specified memory bit 2 2 Test specified bit; skip and clear if memory bit is set Test specified memory bit and skip if bit equals "0" Operand Operation Description Test specified bit and skip if carry flag is set Test specified bit and skip if memory bit is set Bytes 1 2 Cycles 1+S 2+S 5-12 KS57C2302/C2304/P2304 MICROCONTROLLER SAM47 INSTRUCTION SET BINARY CODE SUMMARY This Chapter contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM47 instruction set. The same binary values and notation are also included in the detailed descriptions of individual instructions later in Chapter 5. If you are reading this user's manual for the first time, please just scan this very detailed information briefly. Most of the general information you will need to write application programs can be found in the high-level summary tables in the previous Chapter. The following information is provided for each instruction: — Instruction name — Operand(s) — Binary values — Operation notation The tables in this Chapter are arranged according to the following instruction categories: — CPU control instructions — Program control instructions — Data transfer instructions — Logic instructions — Arithmetic instructions — Bit manipulation instructions 5-13 SAM47 INSTRUCTION SET KS57C2302/C2304/P2304 MICROCONTROLLER Table 5-15. CPU Control Instructions — Binary Code Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 t7 E M B 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 t6 E R B 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 t5 0 Binary Code 0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 t4 0 0 0 0 1 0 1 0 1 0 1 0 0 1 d3 1 0 t3 1 1 1 1 0 1 0 1 0 1 0 0 1 d2 1 0 t2 1 1 1 1 1 1 1 1 1 1 1 0 0 d1 0 d1 t1 a9 1 0 0 1 0 0 0 1 1 1 1 0 1 d0 1 d0 t0 a8 Operation Notation C←1 C←0 C←C IME ← 1 IME ← 0 PCON.2 ← 1 PCON.3 ← 1 No operation SMB ← n (n = 0, 1, 15) SRB ← n (n = 0, 1, 2, 3) PC11–0 = memc7–4, memc3–0