KS57C2504

KS57C2504 4-BIT CMOS Microcontroller Product Specification OVERVIEW The S3C7254 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM4 (Samsung Arrangeable Microcontrollers).With a two-channel comparator, up-to320-dot LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7254 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C7254's advanced CMOS technology provides for low power consumption and a wide operating voltage range. FEATURES Memory • • 512 × 4-bit RAM 4096 × 8-bit ROM 8-Bit Timer/Counter • • • 27 I/O Pins • • • I/O: 15 pins Input only: 4 pins Output only: 8 pins • • Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider Serial I/O interface clock generator • • Four external vectored interrupts Two quasi-interrupts Bit Sequential Carrier • Supports 16-bit serial data transfer in arbitrary format Memory-Mapped I/O Structure • Data memory bank 15 Comparator • • Two-channel mode: internal reference (4-bit resolution) One-channel mode: external reference Watch Timer • • • Time interval generation: 0.5 s, 3.9 ms at 32768 Hz Four frequency outputs to BUZ pin Clock source generation for LCD Two Power-Down Modes • • Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) LCD Controller/Driver • • • • 40 segments and 8 common terminals 3, 4 and 8 common selectable Internal resistor circuit for LCD bias All dot can be switched on/off 8-Bit Serial I/O Interface • • • • 8-bit transmit/receive mode 8-bit receive only mode LSB-first or MSB-first transmission selectable Internal or external clock source Oscillation Sources • • • Crystal, ceramic, or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 4.19 MHz (typical) Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64) • 8-Bit Basic Timer • 4 interval timer functions Interrupts • Three internal vectored interrupts • 4–1 PRODUCT SPECIFICATION S3C7254 Instruction Execution Times • • 0.95, 1.91, 15.3 µs at 4.19 MHz 122 µs at 32.768 kHz Operating Temperature • – 40 °C to 85 °C Package Type • 80-pin QFP Operating Voltage Range • 2.7 V to 6.0 V XIN RESET BASIC TIMER WATCH TIMER SIO P0.0 / SCK / K0 P0.1 / SO / K1 P0.2 / SI / K2 P0.3 / BUZ / K3 INTERNAL INTERRUPTS I/O PORT 0 INTERRUPT CONTROL BLOCK XTIN XOUT XTOUT LCD DRIVER/ CONTROLLER VLC1–VLC5 COM0–COM7 SEG0–SEG31 P5.0/SEG32– P5.7/SEG39 P2.0–P2.3 P3.0 P3.1 P3.2 / LCDSY P3.3 / LCDCK P4.0/CLO P4.1/TCL0 P4.2/TCLO0 CLOCK STACK POINTER I/O PORT 2 PROGRAM COUNTER I/O PORT 3 INSTRUCTION DECODER PROGRAM STATUS WORD I/O PORT 4 COMPARATOR P1.0 / INT0 / CIN0 P1.1 / INT1 / CIN1 P1.2 / INT2 P1.3 / INT4 ARITHMETIC LOGIC UNIT FLAGS INPUT PORT 1 512 x 4-BIT DATA MEMORY 4-KB PROGRAM MEMORY 8-BIT TIMER/ COUNTER Figure 1. S3C7254 Simplified Block Diagram 4–2 S3C7254 PRODUCT SPECIFICATION SEG30 SEG31 P5.0 / SEG32 P5.1 / SEG33 P5.2 / SEG34 P5.3 / SEG35 P5.4 / SEG36 P5.5 / SEG37 P5.6 / SEG38 P5.7 / SEG39 VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 VLC1 VLC2 VLC3 VLC4 VLC5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 S3C7254 KS57C2504 (TOP VIEW) (TOP VIEW) SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 XTOUT XTIN XIN XOUT VDD TEST RESET P4.2 / TCLO0 P4.1 / TCL0 P4.0 / CL O Figure 2. S3C7254 80–Pin QFP Assignment Diagram P0.0 / SCK / K0 P0.1 / SO / K1 P0.2 / SI / K2 P0.3 / BUZ / K3 P1.0 / INT0 / CIN0 P1.1 / INT1 / CIN1 P1.2 / INT2 P1.3 / INT4 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 LCDSY / P3.2 LCDCK / P3.3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4–3 PRODUCT SPECIFICATION S3C7254 Table 1. S3C7254 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit or 4-bit read and test are possible. The 1-bit unit pull-up resistors are assigned to input pins by software. An interrupt is generated by digital input at P1.0, P1.1. Same as port 0 except that 8-bit read/write and test is possible. Number 25 26 27 28 Share Pin K0/SCK K1/SO K2/SI K3/BUZ P1.0 P1.1 P1.2 P1.3 I 29 30 31 32 INT0/CIN0 INT1/CIN1 INT2 INT4 P2.0–P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P5.0–P5.7 SCK SO SI BUZ K0–K3 INT0 INT1 INT2 INT4 I/O 33–36 37 38 39 40 – – – LCDSY LCDCK CLO TCL0 TCLO0 SEG32– SEG39 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P0.0–P0.3 P1.0/CIN0 P1.1/CIN1 P1.2 P1.3 I/O Same as port 0 except that port 4 is 3-bit I/O port. 41 42 43 3–10 25 26 27 28 25–28 29 30 31 32 O I/O I/O I/O I/O I/O I I I Output port for 1-bit data Serial I/O interface clock signal Serial data output Serial data input 2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output for buzzer sound External interrupt. The triggering edge is selectable. External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising or falling edges External interrupts with detection of rising and falling edges 4–4 S3C7254 PRODUCT SPECIFICATION Table 1. S3C7254 Pin Descriptions (Continued) Pin Name CIN0 CIN1 LCDSY LCDCK CLO TCL0 TCLO0 SEG32–SEG39 SEG0–SEG29 SEG30–SEG31 COM0–COM7 VLC1–VLC5 XIN, XOUT XTIN, XTOUT VDD VSS RESET TEST Pin Type I Description 2-channel comparator input. CIN0: comparator input or external reference input CIN1: comparator input only. LCD synchronization clock output for display expansion LCD clock output for display expansion Clock output External clock input for timer/counter 0 Timer/counter 0 clock output LCD segment signal output LCD segment signal output LCD common signal output LCD power supply. Voltage dividing resistors are assignable by mask option. Crystal, ceramic or RC oscillator pins for system clock. Crystal oscillator pins for subsystem clock. Main power supply Ground Chip reset signal input Chip test signal input (must be connected to VSS) Number 29 30 39 40 41 42 43 3–10 51–80 1–2 12–19 20–24 48, 47 49, 50 46 11 44 45 Share Pin P1.0/INT0 P1.1/INT1 P3.2 P3.3 P4.0 P4.1 P4.2 P5.0–P5.7 – – – – – – – – – I/O I/O I/O I/O I/O O O O – – – – – I I NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode. 4–5 PRODUCT SPECIFICATION S3C7254 Table 2. S3C7254 Pin Descriptions Pin Name P0.0–P0.3 P1.0–P1.1 P1.2–P1.3 P2.0–P2.3 P3.0–P3.1 P3.2–P3.3 P4.0, P4.2 P4.1 P5.0–P5.7 COM0–COM7 SEG0–SEG31 VDD VSS RESET VLC1–VLC5 XIN, XOUT XTIN, XTOUT TEST Pin Type I/O I I I/O I/O I/O I/O I/O O O O – – I – – – I Share Pin SCK/K0, SO/K1, SI/K2, BUZ/K3 INT0/CIN0, INT1/CIN1 INT2, INT4 – – LCDSY, LCDCK CLO, TCLO0 TCL0 SEG32–SEG39 – – – – – – – – – Circuit Type 6 10 3 5 5 5 5 6 7 8 8 – – 2 – – – – Reset Value Input Comparator Input Input Input Input Input Input High High High – – – – – – – 4–6 S3C7254 PRODUCT SPECIFICATION VDD VDD P-CHANNEL IN IN N-CHANNEL SCHMITT TRIGGER PULL-UP RESISTOR Figure 3. Pin Circuit Type 1 Figure 4. Pin Circuit Type 2 VDD PULL-UP RESISTOR PULL-UP RESISTOR ENABLE VDD DATA P-CHANNEL OUT N-CHANNEL P-CHANNEL IN SCHMITT TRIGGER OUTPUT DISABLE Figure 5. Pin Circuit Type 3 Figure 6. Pin Circuit Type 4 4–7 PRODUCT SPECIFICATION S3C7254 VDD PULL-UP RESISTOR VDD PULL-UP RESISTOR PNE VDD PNE VDD P-CH RESISTOR ENABLE I/O DATA P-CH RESISTOR ENABLE I/O DATA N-CH OUTPUT DISABLE N- CH OUTPUT DISABLE CIRCUIT TYPE 1 SCHMITT TRIGGER Figure 7. Pin Circuit Type 5 Figure 8. Pin Circuit Type 6 V DD SEG OUTPUT DISABLE CIRCUIT TYPE 9 V LC1 V LC2 P-CH SEG/COM DATA OUT DATA CIRCUIT TYPE 4 I/O V LC3 N-CH V LC4 V LC5 Figure 9. Pin Circuit Type 7 Figure 10. Pin Circuit Type 8 4–8 S3C7254 PRODUCT SPECIFICATION V DD V LC1 V LC2 P-CHANNEL SEG/COM DATA OUTPUT DISABLE OUT N- CHANNEL V LC3 V LC4 V LC5 Figure 11. Pin Circuit Type 9 VDD PULL-UP RESISTOR RESISTOR ENABLE SCHMITT TRIGGER (Digital) IN INT0/1 REF (P1.0 ONLY) P–CH. IN (Analog) IN + _ COMPARATOR REF DIGITAL OR ANALOG SELECTABLE BY SOFTWARE Figure 12. Pin Circuit Type 10 4–9 PRODUCT SPECIFICATION S3C7254 PROGRAM MEMORY (ROM) ROM maps for S3C7254 devices are mask programmable at the factory. In its standard configuration, the device's 4,096 × 8-bit program memory has three areas that are directly addressable by the program counter (PC): — 16-byte area for vector addresses — 96-byte instruction reference area — 16-byte general-purpose area — 3,968-byte general-purpose area 0000H 000FH 0010H VECTOR ADDRESS AREA (16 Bytes) GENERAL-PURPOSE AREA (16 Bytes) 7 0000H 0002H 6 5 4 3 2 1 0 RESET INTB/INT4 001FH 0020H 0004H INSTRUCTION REFERENCE AREA (96 Bytes) INT0 0006H INT1 007FH 0080H 0008H INTS GENERAL-PURPOSE AREA (3,968 Bytes) 000AH INTT0 000CH INTK FFFH Figure 13. ROM Address Structure 4–10 S3C7254 PRODUCT SPECIFICATION DATA MEMORY (RAM) In its standard configuration, the 512 x 4-bit data memory has five areas: — 32 × 4-bit working register area in bank 0 — 224 × 4-bit general-purpose area in bank 0 which is also used as the stack area — 176 × 4-bit general-purpose area in bank 1 — 80 × 4-bit area for LCD data in bank 1 — 128 × 4-bit area in bank 15 for memory-mapped I/O addresses 000H WORKING REGISTERS (32 x 4 Bits) 01FH 020H GENERAL -PURPOSE REGISTERS AND STACK AREA (224 x 4 Bits) 0FFH 100H GENERAL -PURPOSE REGIS TERS (176 x 4 Bits) BANK 1 LCD DATA REGISTERS (80 x 4 Bits) MEMORY-MAPPED I/O ADDRESS REGISTERS (128 x 4 Bits) BANK 0 1AFH 1B0H 1FFH F8 0H BANK 15 FFFH Figure 14. Data Memory (RAM) Map 4–11 PRODUCT SPECIFICATION S3C7254 ADDRESSING MODES ADD RESSI NG MOD E RAM AR EAS 000 H 0 1F H 020 H 07F H 080 H WOR KIN G REGI STE RS DA DA .b EMB = 0 EMB = 1 @H L @H + DA. b EMB = 0 EMB = 1 @W X @ WL X mem a.b X m emb. @L X BANK 0 (GENER AL REGI STE RS AN D STAC K) SMB = 0 S MB = 0 0FF H 100 H BAN K 1 (GEN ERAL REGISTER S) SMB = 1 SMB = 1 1AF H 1B0 H BA NK 1 (D ISPLAY RE G IST ERS) SMB = 1 S MB = 1 1FF H F80 H FB0 H BAN K 15 (PERIPHER AL HAR DW ARE REGISTER S) SMB = 15 SMB = 15 FBF H FC0 H FF0 H FF FH NO T ES: 1. 'X' means don't c are. 2. Blank c olumns indic ate RAM areas that are not addres sable, giv en t he addres sing met hod and enable m emory bank (EM B) f lag s ett ing s hown in t he c olumn headers. Figure 15. RAM Address Structure 4–12 S3C7254 PRODUCT SPECIFICATION Table 3. I/O Map for Memory Bank 15 Memory Bank 15 Address F80H F81H • • • F85H F86H F87H F88H F89H F8AH F8BH F8CH F8DH F8EH F8FH F90H F91H F92H F93H F94H F95H F96H F97H • • • FA6H FA7H PNE1 .3 .2 .1 .0 W No Yes No TREF0 W No No Yes TCNT0 R No No Yes TMOD0 .3 "0" "0" .2 .6 TOE0 "0" .5 "0" "0" .4 "0" R/W Yes Yes No W .3 No Yes LCON LMOD .3 .7 .3 .2 .6 .2 .1 .5 "1" .0 .4 .0 W No Yes No W No No Yes WMOD .3 .7 .2 "0" .1 .5 .0 .4 W .3 (1) No Yes BMOD BCNT .3 .2 .1 .0 W R .3 No Yes No No Yes Register SP Bit 3 .3 .7 Bit 2 .2 .6 Bit 1 .1 .5 Bit 0 "0" .4 R/W R/W Addressing Mode 1-Bit No 4-Bit No 8-Bit Yes 4–13 PRODUCT SPECIFICATION S3C7254 Table 3. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FA8H FA9H FAAH • • • FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H • • • BSC0 BSC1 BSC2 BSC3 Yes "0" "0" "0" "0" IE1 "0" "0" "0" "0" "0" IRQ1 "0" IEW IEK IET0 IES IE0 IE2 IRQW IRQK IRQT0 IRQS IRQ0 IRQ2 R/W Yes Yes Yes R/W Yes Yes No IPR PCON IMOD0 IMOD1 IMODK SCMOD PSW IS1 C (2) IME .3 .3 "0" "0" .3 IE4 IS0 SC2 .2 .2 "0" "0" .2 "0" IRQ4 EMB SC1 .1 .1 .1 "0" .1 "0" IEB ERB SC0 .0 .0 .0 .0 .0 .0 IRQB R/W R W W W W W W R/W Yes No IME No No No No Yes Yes Yes No Yes Yes Yes Yes Yes No Yes No No No No No No No Yes PNE3 Register PNE2 Bit 3 .3 .7 "0" Bit 2 .2 .6 .2 Bit 1 .1 .5 .1 Bit 0 .0 .4 .0 Yes No R/W W Addressing Mode 1-Bit No 4-Bit No 8-Bit Yes 4–14 S3C7254 PRODUCT SPECIFICATION Table 3. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FD0H FD1H FD2H FD3H FD4H FD5H FD6H FD7H FD8H FD9H FDAH FDBH FDCH FDDH FDEH FDFH FE0H FE1H FE2H FE3H FE4H FE5H FE6H FE7H FE8H FE9H • • • PMG2 PMG1 .3 "0" .3 .7 .2 .6 .2 .6 .1 .5 .1 .5 .0 .4 .0 .4 W No No Yes SBUF R/W No No Yes P1MOD SMOD .3 .7 "0" .2 .6 "0" .1 .5 .1 .0 "0" .0 W No Yes No W .3 No Yes PUMOD2 PUMOD1 .3 "0" .3 .2 "0" .2 "0" "0" .1 .0 .4 .0 W No Yes No W No No Yes IMOD2 "0" "0" "0" .0 W No Yes No CMOD .3 .7 .2 .6 .1 .5 .0 "0" R/W No No Yes CMPREG .3 .2 .1 .0 R No Yes No Register CLMOD Bit 3 .3 Bit 2 "0" Bit 1 .1 Bit 0 .0 R/W W Addressing Mode 1-Bit No 4-Bit Yes 8-Bit No 4–15 PRODUCT SPECIFICATION S3C7254 Table 3. I/O Map for Memory Bank 15 (Concluded) Memory Bank 15 Address FF0H FF1H FF2H FF3H FF4H • • • FFFH NOTES: 1. 2. Bit 3 in the WMOD register is read only. The carry flag can be read or written by specific bit manipulation instructions only. Addressing Mode Bit 1 .1 .1 .1 .1 / .5 .1 Bit 0 .0 .0 .0 .0 / .4 .0 R/W R/W R R/W R/W R/W Yes Yes No Yes Yes Yes 1-Bit Yes 4-Bit Yes 8-Bit No Register Port 0 (P0) Port 1 (P1) Port 2 (P2) Port 3 (P3) Port 4 (P4) Bit 3 .3 .3 .3 .3 / .7 "0" Bit 2 .2 .2 .2 .2 / .6 .2 4–16 S3C7254 PRODUCT SPECIFICATION OSCILLATOR CIRCUITS The S3C7254 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. The main system clock frequencies can be divided by 4, 8, or 64 by manipulating PCON bits 1 and 0. The system clock mode control register, SCMOD, lets you select a main system clock (fx) or a subsystem clock (fxt) as the CPU clock and to start (or stop) main system clock oscillation. The watch timer, buzzer and LCD display operate normally with a subsystem clock source, since they operate at very slow speeds and with very low power consumption (as low as 122 µs at 32.768 kHz). MAIN SYSTEM OSCILLATOR CIRCUIT fx fxt SUBSYSTEM OSCILLATOR CIRCUIT WATCH TIMER LCD CONTROLLER SELECTOR Xin Xout fxx Xin Xout OSCILLATOR STOP FREQUENCY DIVIDING CIRCUIT 1/2 1/16 LCD CONTROLLER BASIC TIMER TIMER/COUNTERS 0 SERIAL I/O INTERFACE WATCH TIMER CLOCK OUTPUT CIRCUIT SCMOD.3 SCMOD.0 SELECTOR 1/4 CPU CLOCK CPU STOP SIGNAL (IDLE MODE) PCON.0 PCON.1 IDLE STOP PCON.2 PCON.3 OSCILLATOR CONTROL CIRCUIT WAIT RELEASE SIGNAL INTERNAL RESET SIGNAL POWER-DOWN RELEASE SIGNAL PCON.3,2 CLEAR Figure 16. Clock Circuit Diagram 4–17 PRODUCT SPECIFICATION S3C7254 MAIN SYSTEM OSCILLATOR CIRCUITS SUBSYSTEM OSCILLATOR CIRCUITS Xin XTin Xout 32.768 kHz XTout Figure 17. Crystal/Ceramic Oscillator (fx) Figure 20. Crystal/Ceramic Oscillator (fxt) XTin EXTERNAL CLOCK Xin XTout Xout Figure 18. External Oscillator (fx) Figure 21. External Oscillator (fxt) Xin R Xout Figure 19. RC Oscillator (fx) 4–18 S3C7254 PRODUCT SPECIFICATION POWER CONTROL REGISTER (PCON) The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. PCON bits 3 and 2 are addressed by the STOP and IDLE instructions, respectively, to engage the idle and stop power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. There are two basic choices: — Main system clock (fx) or subsystem clock (fxt); — Divided fx frequency of 4, 8, or 64. PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If SCMOD.0 = "0" the main system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 = "1" the subsystem clock is selected. Table 4. Power Control Register (PCON) Organization PCON Bit Settings PCON.3 0 0 1 PCON.2 0 1 0 Normal CPU operating mode Idle power-down mode Stop power-down mode Resulting CPU Clock Frequency If SCMOD.0 = "0" fx/64 fx/8 fx/4 If SCMOD.0 = "1" — — fxt/4 Resulting CPU Operating Mode PCON Bit Settings PCON.1 0 1 1 PCON.0 0 0 1 + PROGRAMMING TIP — Setting the CPU Clock To set the CPU clock to 0.95 µs at 4.19 MHz: BITS SMB LD LD EMB 15 A,#3H PCON,A 4–19 PRODUCT SPECIFICATION S3C7254 INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on whether the main system clock Table 5. Instruction Cycle Times for CPU Clock Rates Selected CPU Clock fx/64 fx/8 fx/4 fxt/4 Resulting Frequency 65.5 kHz 524.0 kHz 1.05 MHz 8.19 kHz (fx) or a subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 5 shows corresponding cycle times in microseconds. Oscillation Source fx = 4.19 MHz Cycle Time (µsec) 15.3 1.91 0.95 fxt = 32.768 kHz 122.0 SYSTEM CLOCK MODE REGISTER (SCMOD) The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control main system clock oscillation. Only its least significant and most significant bits can be manipulated by 1-bit write instructions. Subsystem clock oscillation cannot, of course, be stopped internally. Also, if you have selected fx as the CPU clock, setting SCMOD.3 to "1" will not stop main system clock oscillation. This can only be done by a STOP instruction. Table 6. System Clock Mode Register (SCMOD) Organization SCMOD Register Bit Settings SCMOD.3 0 0 1 SCMOD.0 0 1 1 Resulting Clock Selection CPU Clock fx fxt fxt fx Oscillation On On Off 4–20 S3C7254 PRODUCT SPECIFICATION SWITCHING THE CPU CLOCK Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD, determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies. SCMOD.3 and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the selected fx or fxt clock by 4, 8, or 64. NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications — the previously selected clock continues to run for a certain number of machine cycles. For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1". This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all SCMOD values to logic zero. Following a RESET, CPU operation starts with the lowest main system clock frequency of 15.3 µsec at 4.19 MHz after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6–4 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect. Table 7. Elapsed Machine Cycles During CPU Clock Switch AFTER BEFORE PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 SCMOD.0 = 1 N/A N/A fx / 4fxt (M/C) N/A 16 MACHINE CYCLES 16 MACHINE CYCLES N/A fx / 4fxt 8 MACHINE CYCLES N/A 8 MACHINE CYCLES N/A PCON.1 = 0 N/A PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 N/A SCMOD.0 = 1 1 MACHINE CYCLE 1 MACHINE CYCLE NOTES: 1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered. 2. Since the Xin input is connected internally to VSS to avoid current leakage due to the crystal oscillator in stop mode, do not set SCMOD.3 to "1" when an external clock is used as the main system clock. 3. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6–4. 4. 'N/A' means 'not available'. 4–21 PRODUCT SPECIFICATION S3C7254 + PROGRAMMING TIP — Switching Between Main System and Subsystem Clock 1. Switch from the main system clock to the subsystem clock: MA2SUB DLY80 DEL1 BITS CALL BITS RET LD NOP NOP DECS JR RET SCMOD.0 DLY80 SCMOD.3 A,#0FH A DEL1 ; Switches to subsystem clock ; Delay 80 machine cycles ; Stop the main system clock 2. Switch from the subsystem clock to the main system clock: SUB2MA BITR CALL BITR RET SCMOD.3 DLY80 SCMOD.0 ; Start main system clock oscillation ; Delay 80 machine cycles ; Switch to main system clock 4–22 S3C7254 PRODUCT SPECIFICATION CLOCK OUTPUT MODE REGISTER (CLMOD) The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4bit write instructions only. RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without initiating clock oscillation), and disables clock output. CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64. Table 6– 5. Clock Output Mode Register (CLMOD) Organization Table 8. Clock Output Mode Register (CLMOD) Organization CLMOD Bit Settings CLMOD.1 0 0 1 1 CLMOD.3 0 1 CLMOD.0 0 1 0 1 Clock Source CPU clock (fx/4, fx/8, fx/64, fxt/4) fxx/8 fxx/16 fxx/64 Resulting Clock Output Frequency 1.05 MHz, 524 kHz, 65.5 kHz, 8.19 kHz 524 kHz, 4.096 kHz 262 kHz, 2.048 kHz 65.5 kHz, 0.512 kHz Result of CLMOD.3 Setting Clock output is disabled Clock output is enabled NOTE: Frequencies assume that fxx is 4.19 MHz and fxt is 32.768 kHz. CLMOD.3 CLMOD.2 4 CLMOD.1 CLMOD.0 CLOCK SELECTOR P4.0 OUTPUT LATCH PM4.0 CLO CLOCKS (fxx/8, fxx/16, fxx/64, CPU clock) Figure 22. CLO Output Pin Circuit Diagram 4–23 PRODUCT SPECIFICATION S3C7254 + PROGRAMMING TIP — CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin: BITS SMB LD LD BITR LD LD EMB 15 EA,#10H PMG1,EA P4.0 A,#9H CLMOD,A ; P4.0 ← Output mode ; Clear P4.0 output latch 4–24 S3C7254 PRODUCT SPECIFICATION INTERRUPTS The S3C7254 has four external, three internal and two quasi interrupts. Table 9 shows the conditions for each interrupt generation. The request flags that allow the interrupts to be generated are cleared to logic zero by hardware when the service routine is vectored. The quasi interrupt (INT2, IRQW) request flags must be cleared by software. IMOD1 IMOD0 IE2 IEW IEK IET0 IES IE1 IE0 IE4 IEB INTB INT4 INT0 INT1 IRQB IRQ4 # @ @ IRQ0 IRQ1 INTS INTT0 IRQT0 IRQS IRQK @ INTW IMODK INT2 IRQW IRQ2 @ IMOD2 POWER-DOWN MODE RELEASE SIGNAL IME IPR * INTERRUPT CONTROL UNIT IS1 IS0 # = NOISE FILTERING CIRCUIT @ = EDGE DETECTION CIRCUIT VECTOR INTERRUPT * When fxx/64 is selected as a sampling clock for INT0, idle mode can be released by INT0. GENERATOR Figure 23. Interrupt Control Circuit Diagram 4–25 PRODUCT SPECIFICATION S3C7254 Table 9. Interrupt Request Flag Conditions and Priorities Interrupt Source INTB INT4 INT0 INT1 INTS INTT0 INTK INT2 * INTW Internal / External I E E E I I E E I Pre-condition for IRQx Flag Setting Reference time interval signal from basic timer Both rising and falling edges detected at INT4 Rising or falling edge detected at INT0 pin Rising or falling edge detected at INT1 pin Completion signal for serial transmit-and-receive or receive-only operation Signals for TCNT0 and TREF0 registers match When a rising or falling edge detected at any one of the K0–K3 pins Rising or falling edge detected at INT2 Time interval of 0.5 second or 3.19 ms Interrupt Priority 1 1 2 3 4 5 6 — — IRQ Flag Name IRQB IRQ4 IRQ0 IRQ1 IRQS IRQT0 IRQK IRQ2 IRQW NOTE: The quasi-interrupt INT2 is only used for testing incoming signals. INTERRUPT ENABLE FLAGS (IEX) IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled. Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag. Table 10. Interrupt Enable and Request Flag Address FB8H FBAH FBBH FBCH FBDH FBEH FBFH Bit 3 IE4 0 0 0 0 IE1 0 Bit 2 IRQ4 0 0 0 0 IRQ1 0 Bit 1 IEB IEW IEK IET0 IES IE0 IE2 Bit 0 IRQB IRQW IRQK IRQT0 IRQS IRQ0 IRQ2 3. 4. IEx = 0 is interrupt disable mode. IEx = 1 is interrupt enable mode. INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic zero. Before the IPR can be modified by 4bit write instructions, all interrupts must first be disabled by a DI instruction. By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. NOTES: 1. IEx refers generically to all interrupt enable flags. 2. IRQx refers generically to all interrupt request flags. 4–26 S3C7254 PRODUCT SPECIFICATION Table 11. Standard Interrupt Priorities Interrupt INTB, INT4 INT0 INT1 INTS INTT0 INTK Default Priority 1 2 3 4 5 6 1 1 0 1 1 0 Process INTT0 interrupts only Process INTK interrupts only NOTE: When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt requested first will have high priority. Therefore, the first- request interrupt cannot be superceded by any other interrupt. The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the current enable memory bank (EMB) value. Table 12. Interrupt Priority Register Settings IPR.2 0 IPR.1 0 IPR.0 0 Result of IPR Bit Setting Process all interrupt requests at low priority (NOTE) EXTERNAL INTERRUPT 0, 1 AND 2 MODE REGISTERS (IMOD0, IMOD1 AND IMOD2) The following components are used to process external interrupts at the INT0, INT1 and INT2 pins: — Noise filtering circuit for INT0 — Edge detection circuit — Three mode registers, IMOD0, IMOD1 and IMOD2 The mode registers are used to control the triggering edge of the input signal. IMOD0, IMOD1 and IMOD2 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. Since INT2 is a qusiinterrupt, the interrupt request flag (IRQ2) must be cleared by software. IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. 0 0 0 1 0 1 1 0 1 0 1 0 Process INTB and INT4 interrupts only Process INT0 interrupts only Process INT1 interrupts only Process INTS interrupts only 4–27 PRODUCT SPECIFICATION S3C7254 Table 13. IMOD0, 1 and 2 Register Organization IMOD0 IMOD0.3 0 1 0 0 1 1 IMOD1 IMOD2 0 0 0 0 1 0 1 IMOD1.0 IMOD2.0 0 1 0 IMOD0.1 IMOD0.0 Effect of IMOD0 Settings Select CPU clock for sampling Select fxx/64 sampling clock Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1" Effect of IMOD1 and IMOD2 Settings Rising edge detection Falling edge detection When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: — To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input. — you can use INT0 to release idle mode, when fxx/64 is selected as a sampling clock. 4–28 S3C7254 PRODUCT SPECIFICATION CPU CLOCK fxx/64 IMOD0 CLOCK SELECTOR 2 INT0 NOISE FILTER EDGE DETECTION IRQ0 INT1 EDGE DETECTION IRQ1 INT2 EDGE DETECTION IRQ2 IMOD2 P1.2 P1.1 P1.0 IMOD1 Figure 24. Circuit Diagram for INT0, INT1 and INT2 Pins 4–29 PRODUCT SPECIFICATION S3C7254 EXTERNAL KEY INTERRUPT MODE REGISTER (IMODK) The mode register for external key interrupts at the K0–K3 pins, IMODK, is addressable only by 4-bit write instructions. RESET clears all IMODK bits to logic zero. Table 14. IMODK Register Bit Settings IMODK 0 IMODK.2 0, 1 IMODK.1 0 0 1 1 Rising or falling edge can be detected by bit IMODK.2 settings. If a rising or falling edge is detected at any one of the selected K pin by the IMODK register, the IRQK flag is set to logic one and a release signal for power-down mode is generated. IMODK.0 0 1 0 1 Effect of IMODK Settings Disable key interrupt Enable edge detection at the K0–K1 pins Enable edge detection at the K0–K2 pins Enable edge detection at the K0–K3 pins IMODK.2 0 1 Falling edge detection Rising edge detection NOTE: 1. To generate a key interrupt, the selected pins must be configured to input mode. If any one pin of the selected pins is configured to output mode, only falling edge can be detected. 2. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge detection and pins by setting IMODK register. P0.3/ K3 P0.2/ K2 P0.1/ K1 P0.0/ K0 R ISING/ FALLLING ED GE SELEC TOR PIN SELEC TOR IR Q K I MODK Figure 25. Circuit Diagram for INTK 4–30 S3C7254 PRODUCT SPECIFICATION POWER-DOWN The S3C7254 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. The effect of stop mode on specific peripheral hardware components — CPU, basic timer, serial I/O, timer/ counter 0, watch timer, and LCD controller — and on external interrupt requests, is detailed in Table 15. Table 15. Hardware Operation During Power-Down Modes Operation System clock status Clock oscillator Basic timer Serial I/O interface Timer/counter 0 Watch timer LCD controller External interrupts CPU Mode release signal Stop Mode (STOP) Can be changed only if the main system clock is used Main system clock oscillation stops Basic timer stops Operates only if external SCK input is selected as the serial I/O clock Operates only if TCL0 is selected as the counter clock Operates only if subsystem clock (fxt) is selected as the counter clock Idle Mode (IDLE) Can be changed if the main system clock or subsystem clock is used CPU clock oscillation stops (main and subsystem clock oscillation continues) Basic timer operates (with IRQB set at each reference interval) Operates if a clock other than the CPU clock is selected as the serial I/O clock Timer/counter 0 operates Watch timer operates Operates only if a subsystem clock is se- LCD controller operates lected as LCDCK INT1, INT2, INT4, and INTK are acknowledged; INT0 is not serviced All CPU operations are disabled INT1, INT2, INT4, INT0, and INTK are acknowledged (NOTE) All CPU operations are disabled Interrupt request signals (except INT0) Interrupt request signals are enabled by are enabled by an interrupt enable flag or an interrupt enable flag or by RESET by RESET input input (NOTE) NOTE: INT0 can be operated in idle mode only when fxx/64 is selected as a sampling clock. 4–31 PRODUCT SPECIFICATION S3C7254 + PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. In this example, the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on: KEYCLK DI CALL SMB LD LD LD LD SMB BITR BITR BITS BITS CALL BTSTZ JR CALL EI RET IDLE NOP NOP JPS MA2SUB 15 EA,#00H P2,EA A,#3H IMODK,A 0 IRQW IRQK IEW IEK WATDIS IRQK CIDLE SUB2MA ; Main system clock → subsystem clock switch subroutine ; All key strobe outputs to low level ; Select K0–K3 enable CLKS1 ; Execute clock and display changing subroutine ; Subsystem clock → main system clock switch subroutine ; Engage idle mode CIDLE CLKS1 4–32 S3C7254 PRODUCT SPECIFICATION RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 16. Table 16. Unused Pin Connections for Reduced Power Consumption Pin/Share Pin Names P0.0 / SCK / K0 P0.1 / SO / K1 P0.2 / SI / K2 P0.3 / BUZ / K3 P1.0 / CIN0 / INT0 P1.1 / CIN1 /INT1 P1.2 / INT2 P1.3 / INT4 P2.0–P2.3 P3.0–P3.1 P3.2 / LCDSY P3.0 / LCDCK P4.0 / CLO P4.1 / TCL0 P4.2 / TCLO0 P5.0 / SEG32–P5.7 / SEG39 SEG0–SEG29 SEG30–SEG31 COM0–COM7 VLC1–VLC5 XTin XTout TEST NOTES 1. Digital mode at P1.0 and P1.1 2. Used as segment Recommended Connection Input mode: Connect to VDD Output mode: No connection Connect to VDD (1) Input mode: Connect to VDD Output mode: No connection Input mode: Connect to VDD Output mode: No connection No connection (2) No connection No connection Connect XTin to VSS or VDD No connection Connect to VSS 4–33 PRODUCT SPECIFICATION S3C7254 RESET Table 17 provides detailed information about hardware register values after a RESET occurs during power-down mode or during normal operation. Table 17. Hardware Register Values After RESET RESET Hardware Component or Subcomponent Program counter (PC) If RESET Occurs During RESET Power-Down Mode Lower six bits of address 0000H are transferred to PC11–8, and the contents of 0001H to PC7–0. 0, 0 0 If RESET Occurs During RESET Normal Operation Lower six bits of address 0000H are transferred to PC11–8, and the contents of 0001H to PC7–0. 0, 0 0 Bank selection registers (SMB, SRB) BSC register (BSC0–BSC3) Program Status Word (PSW): Carry flag (C) Skip flag (SC0–SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Retained 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Undefined 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Stack pointer (SP) Data Memory (RAM): Working registers E, A, L, H, X, W, Z, Y General-purpose registers Clocks: Power control register (PCON) Clock output mode register (CLMOD) System clock mode register (SCMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INT2 mode register (IMOD2) INTK mode register (IMODK) Values retained Values retained (note) Undefined Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE: The values of the 0F8H-0FDH are not retained when a RESET signal is input. 4–34 S3C7254 PRODUCT SPECIFICATION Table 17. Hardware Register Values After RESET (Continued) RESET Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD1/2) Basic Timer: Count register (BCNT) Mode register (BMOD) Timer/Counters 0 and 1: Count registers (TCNT0) Reference registers (TREF0) Mode registers (TMOD0) Output enable flags (TOE0) Watch Timer: Watch timer mode register (WMOD) LCD Driver/Controller: LCD mode register (LMOD) LCD control register (LCON) Display data memory Output buffers Serial I/O Interface: SIO mode register (SMOD) SIO interface buffer (SBUF) N-Channel Open-Drain Mode Register PNE1/2/3 Comparator Comparator mode register (CMOD) Comparison result register 0 Undefined 0 Undefined 0 0 0 Values retained 0 Undefined 0 0 Values retained Off 0 0 Undefined Off 0 0 0 FFH 0 0 0 FFH 0 0 Undefined 0 Undefined 0 Off 0 0 0 Off 0 0 0 If RESET Occurs During RESET Power-Down Mode If RESET Occurs During RESET Normal Operation 4–35 PRODUCT SPECIFICATION S3C7254 I/O PORTS The S3C7254 has 6 ports. There are total of 4 input pins, 8 output pin and 15 configurable I/O pins, for a maximum number of 27 pins. PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. Table 18. Port Mode Group Flags PM Group ID PMG1 PMG2 Address FE6H FE7H FE8H FE9H Bit 3 PM0.3 "0" PM2.3 PM3.3 Bit 2 PM0.2 PM4.2 PM2.2 PM3.2 Bit 1 PM0.1 PM4.1 PM2.1 PM3.1 Bit 0 PM0.0 PM4.0 PM2.0 PM3.0 When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears all port mode flags to logical zero, automatically configuring the corresponding I/O ports to input mode. NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit ="1", the pin is set to output mode: PM0.0 for P0.0, PM0.1 for P0.1, etc,. All flags are cleared to logic zero following RESET. + PROGRAMMING TIP — Configuring I/O Ports to Input or Output Configure ports 0 and 2 as an output port: BITS SMB LD LD EMB 15 EA,#7FH PMG1,EA ; P0 and P4 ← Output 4–36 S3C7254 PRODUCT SPECIFICATION PORT 1 MODE REGISTER (P1MOD) P1MOD register settings determine if port 1 is used for digital input or for analog input. The P1MOD register is a 4-bit write only register. P1MOD is mapped to address FE2H. A reset operation initializes all P1MOD values to logic zero, configuring port 1 as an analog input port. When a P1MOD bit is "0", the corresponding pin is configured as a analog input pin. When set to "1", it is configured as an digital input pin: P1MOD.0 corresponds to P1.0, and P1MOD.1 to P1.1. NOTE INT0 and INT1 can occur only when the port is configured to digital input. If you change the input mode from digital to analog using P1MOD settings, IRQ0 and IRQ1 will be set. When you use analog input, you must clear the corresponding interrupt enable flag (IEx). That is, clear IE0 when P1.0 is an analog input and clear IE1 when P1.1 is an analog input. PULL-UP RESISTOR MODE REGISTER (PUMOD) The pull-up resistor mode registers (PUMOD1 and PUMOD2) are used to assign internal pull-up resistors by software to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting. Table 19. Pull-Up Resistor Mode Register (PUMOD) Organization PUMOD ID PUMOD1 PUMOD2 Address FDCH FDDH FDEH Bit 3 PUR3 0 PUR1.3 Bit 2 PUR2 0 PUR1.2 Bit 1 “0” 0 PUR1.1 Bit 0 PUR0 PUR4 PUR1.0 NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2, and so on. + PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors P6 and P7 enable pull-up resistors. BITS SMB LD LD EMB 15 EA,#0CH PUMOD1,EA ; P2 and P3 enable write instructions only and PNE2 by 8-bit write instructions only. PNE ID PNE1 PNE2 PNE3 ADDRESS FA6H FA8H FA9H FAAH Bit 3 P0.3 P2.3 P3.3 0 Bit 2 P0.2 P2.2 P3.2 P4.2 Bit 1 P0.1 P2.1 P3.1 P4.1 Bit 0 P0.0 P2.0 P3.0 P4.0 N-CHANNEL OPEN-DRAIN MODE REGISTER The n-channel open-drain mode register (PNE) is used to configure ports 0, 2, 3 and 4 to n-channel open-drain or as push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-channel, open-drain; when set to "0", the output pin is configured to push-pull. The PNE register consists of an 8-bit register and a 4-bit register; PNE1 and PNE3 can be addressed by 4-bit 4–37 PRODUCT SPECIFICATION S3C7254 PORT 0 CIRCUIT DIAGRAM PUR0 VDD PNE1.2 PNE1.1 PNE1.0 PNE1.3 PM0.3 PM0.2 PM0.1 PM0.0 P0.0 / SCK /K0 P0.1 /SO /K1 P0.2 /SI /K2 P0.3 /BUZ /K3 CMOS PUSH- PULL or N-CHANNEL OPEN-DRAIN OUTPUT LATCH 1, 4 M U X 1, 4 NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD). Figure 26. Port 0 Circuit Diagram 4–38 S3C7254 PRODUCT SPECIFICATION PORT 1 CIRCUIT DIAGRAM V DD VDD V DD V DD INT0 INT1 INT2 INT4 PUR1.0 PUR1.1 PUR1.2 PUR1.3 N/R CIRCUIT IMOD0 P1.0 /INT0 /CIN0 Digital Input Analog Input External Reference P1.1 /INT1 /CIN1 Digital Input Analog Input P1.2 / INT2 Digital Input P1.3 / INT4 Digital Input N/R = NOISE REDUCTION Figure 27. Input Port 1 Circuit Diagram 4–39 PRODUCT SPECIFICATION S3C7254 PORTS 2 AND 3 CIRCUIT DIAGRAM VDD x = 2, 3 b = 0, 1, 2, 3 PNE2 PURx PMx.b Px.b OUTPUT LATCH 1, 4, 8 M U X 1, 4, 8 NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD). Figure 28. Ports 2 and 3 Circuit Diagram 4–40 S3C7254 PRODUCT SPECIFICATION PORT 4 CIRCUIT DIAGRAM VDD PNE3.2 PUR3 PNE3.0 PNE3.1 PM4.2 PM4.1 PM4.0 P4.0 /CLO P4.1 /TCL0 P4.2 /TCLO0 CMOS PUSH-PULL or N-CHANNEL OPEN-DRAIN OUTPUT LATCH 1, 4 M U X 1, 4 NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD). Figure 29. Port 4 Circuit Diagram 4–41 PRODUCT SPECIFICATION S3C7254 BASIC TIMER (BT) The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET. Interval Timer Function The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT clock pulses. To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2–BMOD.0. The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs. An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting continues from 00H. Oscillation Stabilization Interval Control Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. When a RESET signal is generated, the standard stabilization interval for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz. "CLEAR" SIGNAL CLEAR BCNT CLEAR IRQB INTERRUPT REQUEST BITS INSTRUCTION 4 BMOD.3 BMOD.2 BMOD.1 BMOD.0 CLOCK BCNT SELECTOR 8 CPU CLOCK START SIGNAL (POWER-DOWN RELEASE) OVERFLOW IRQB 1-BIT R/W CLOCK INPUT (fxx/212, fxx/29, fxx/27, fxx/25) Figure 30. Basic Timer Circuit Diagram 4–42 S3C7254 PRODUCT SPECIFICATION BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is used to select the input frequency and the oscillation stabilization time. The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted. Table 20. Basic Timer Mode Register (BMOD) Organization BMOD.3 1 Basic Timer Restart Bit Restart basic timer; clear IRQB, BCNT, and BMOD.3 to "0" BMOD.2 0 0 1 1 BMOD.1 0 1 0 1 BMOD.0 0 1 1 1 Basic Timer Input Clock fxx/212 (1.02 kHz) fxx/29 (8.18 kHz) fxx/27 (32.7 kHz) fxx/25 (131 kHz) Oscillation Stabilization 220/fxx (250 ms) 217/fxx (31.3 ms) 215/fxx (7.82 ms) 213/fxx (1.95 ms) NOTES: 1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 MHz. 2. fxx = selected system clock frequency. 3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. The data in the table column 'Oscillation Stabilization' can also be interpreted as "Interrupt Interval Time." 4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz. BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. When BCNT has incremented to hexadecimal 'FFH' (255 clock pulses), it is cleared to '00H' and an overflow is generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the latter value as valid data. Until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. 4–43 PRODUCT SPECIFICATION S3C7254 + PROGRAMMING TIP — Using the Basic Timer 1. To read the basic timer count register (BCNT): BITS EMB SMB 15 BCNTR LD EA,BCNT LD YZ,EA LD EA,BCNT CPSE EA,YZ JR BCNTR 2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: BITS SMB LD LD STOP NOP NOP EMB 15 A,#0BH BMOD,A ; Wait time is 31.3 ms ; Set stop power-down mode CPU OPERATION NORMAL OPERATING MODE STOP MODE IDLE MODE (31.3 ms) NORMAL OPERATING MODE STOP INSTRUCTION STOP MODE IS RELEASED BY INTERRUPT 3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz): BITS SMB LD LD EI BITS EMB 15 A,#0FH BMOD,A IEB ; Basic timer interrupt enable flag is set to "1" 4. Clear BCNT and the IRQB flag and restart the basic timer: BITS SMB BITS EMB 15 BMOD.3 4–44 S3C7254 PRODUCT SPECIFICATION 8-BIT TIMER/COUNTER 0 (TC0) OVERVIEW Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC0 can be used to measure specific time intervals. TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by counter logic. An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into the TMOD0 register during program execution. Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface. CLOCKS 10, fxx/2 6, fxx/2 4, fxx) (fxx/2 TCL0 TMOD0.7 TMOD0.6 8 TMOD0.5 TMOD0.4 CLEAR TMOD0.3 TMOD0.2 TMOD0.1 TMOD0.0 CLEAR IRQT0 SET CLEAR INVERTED TOL0 SERIAL I/O TCLO0 CLOCK SELECTOR 8 TCNT0 8-BIT COMPARATOR 8 TREF0 PM4.2 P4.2 LATCH TOE0 Figure 31. TC0 Circuit Diagram 4–45 PRODUCT SPECIFICATION S3C7254 TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated. To generate an interrupt request, the TC0 interrupt request flag (IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H and TC0 continues counting. The interrupt request Table 20-1. TMOD0 Settings for TCL0 Edge Detection TMOD0.5 0 0 TMOD0.4 0 1 mechanism for TC0 includes an interrupt enable flag (IET0) and an interrupt request flag (IRQT0). TC0 EVENT COUNTER FUNCTION Timer/counter 0 can monitor or detect system 'events' by using the external clock input at the TCL0 pin as the counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs. With the exception of the different TMOD0.4– TMOD0.6 settings, the operation sequence for TC0's event counter function is identical to its programmable timer/counter function. To activate the TC0 event counter function, P4.1/TCL0 must be set to input mode. . TCL0 Edge Detection Rising edges Falling edges the output to the TCLO0 pin, the following conditions must be met: — TC0 output enable flag TOE0 must be set to "1" — I/O mode flag for P4.2 must be set to output mode ("1") — Output latch value for P4.2 must be set to "0" TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected by loading the desired reference value into the reference register TREF0. To enable + PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin Output a 30 ms pulse width signal to the TCLO0 pin: BITS SMB LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA EA,#40H PMG1,EA P4.2 TOE0 ; P4.2 ← output mode ; P4.2 clear 4–46 S3C7254 PRODUCT SPECIFICATION TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, Table 21. TC0 Mode Register (TMOD0) Organization Bit Name TMOD0.7 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.3 1 0,1 Setting 0 Always logic zero counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are retained until TC0 is re-enabled. Resulting TC0 Function Address F91H Specify input clock edge and internal frequency Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes.) Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0 Always logic zero Always logic zero F90H TMOD0.2 TMOD0.1 TMOD0.0 0 1 0 0 Table 22. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings TMOD0.6 0 0 1 1 1 1 TMOD0.5 0 0 0 0 1 1 TMOD0.4 0 1 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fxx/210 (4.09 kHz) fxx /26 (65.5 kHz) fxx/24 (262 kHz) fxx = 4.19 MHz NOTE: 'fxx' = selected system clock of 4.19 MHz. + PROGRAMMING TIP — Restarting TC0 Counting Operation 1. Set TC0 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS BITS SMB BITS EMB 15 EA,#4CH TMOD0,EA IET0 EMB 15 TMOD0.3 2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation: 4–47 PRODUCT SPECIFICATION S3C7254 TC0 REFERENCE REGISTER (TREF0) TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval. Use the following formula to calculate the correct value to load to the TREF0 reference register: 1 TC0 timer interval = (TREF0 value + 1) × TMOD0 frequency setting (TREF0 value≠0) TC0 OUTPUT ENABLE FLAG (TOE0) The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. (MSB) F92H “0” TOE0 "0" (LSB) "0" When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. + PROGRAMMING TIP — Setting a TC0 Timer Interval To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter clock = fxx/210, and TREF0 is set to FFH): 2. Calculate the TREF0 value: 30 ms = TREF0 value + 1 4.09 kHz 30 ms 244 µs = 122.9 = 7AH TREF0 + 1 = TREF0 value = 7AH – 1 = 79H 3. Load the value 79H to the TREF0 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA 4–48 S3C7254 PRODUCT SPECIFICATION WATCH TIMER Watch timer functions include real-time and watchtime measurement and interval timing for the main and subsystem clock. It is also used as a clock source for the LCD controller and for generating buzzer (BUZ) output. Real-Time and Watch-Time Measurement To start watch timer operation, set bit 2 of the watch timer mode register (WMOD.2) to logic one. The watch timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. Using a Main System or Subsystem Clock Source The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if WMOD.0 = "0", the main system clock (fx) is used as the signal source, according to the following formula: Main system clock (fx) 128 = 32.768 kHz (fx = 4.19 MHz) the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby releasing stop mode. Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller (fLCD). Therefore, if the watch timer is disabled, the LCD controller does not operate. Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the desired BUZ frequency , load the appropriate value to the WMOD register. This output can then be used to actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met: — The WMOD.7 register bit is set to "1" — The output latch for I/O port 0.3 is cleared to "0" — The port 0.3 output mode flag (PM0.3) set to 'output' mode Timing Tests in High-Speed Mode By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. High-speed mode is useful for timing events for program debugging sequences. Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the input level at the XTin pin is high; if WMOD.3 is "0", the input level at the XTin pin is low. Watch timer clock (fw) = This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using 4–49 PRODUCT SPECIFICATION S3C7254 P0.3 LATCH PM0.3 WMOD.7 WMOD.6 WMOD.5 WMOD.4 8 MUX fw/16 (2 kHz) BUZ WMOD.3 ENABLE / DISABLE fw/8 (4 kHz) fw/4 (8 kHz) fw/2 (16 kHz) SELECTOR CIRCUIT WMOD.2 WMOD.1 WMOD.0 IRQW fw/2 7 CLOCK SELECTOR fw 32.768 kHz FREQUE NCY DIVIDING CIRCUIT fw/214 (2 Hz) f LCD fx = MAIN SYSTEM CLOCK (4.19 MHz) fxt = SUBSYSTEM CLOCK (32.768 KHz) fw = WATCH TIMER FREQUENCY fxt fx/128 Figure 32. Watch Timer Circuit Diagram 4–50 S3C7254 PRODUCT SPECIFICATION WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. Table 23. Watch Timer Mode Register (WMOD) Organization Bit Name WMOD.7 Values 0 1 WMOD.6 WMOD.5 – .4 0 0 1 1 WMOD.3 0 1 WMOD.2 WMOD.1 WMOD.0 0 1 0 1 0 1 0 0 1 0 1 Function Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output Always logic zero 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output Input level to XTin pin is low Input level to XTin pin is high Disable watch timer; clear frequency dividing circuits Enable watch timer Normal mode; sets IRQW to 0.5 seconds High-speed mode; sets IRQW to 3.91 ms Select (fx/128 ) as the watch timer clock (fw) Select subsystem clock as watch timer clock (fw) F88H F89H Address NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fxt) is assumed to be 32.768 kHz. + PROGRAMMING TIP — Using the Watch Timer 1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable: BITS SMB LD LD BITR LD LD BITS EMB 15 EA,#8H PMG1,EA P0.3 EA,#85H WMOD,EA IEW ; P0.3 ← output mode 2. Sample real-time clock processing method: CLOCK BTSTZ RET • • • IRQW ; 0.5 second check ; No, return ; Yes, 0.5 second interrupt generation ; Increment HOUR, MINUTE, SECOND 4–51 PRODUCT SPECIFICATION S3C7254 LCD CONTROLLER/DRIVER The S3C7254 microcontroller can directly drive an up-to-320–dot (40 segments x 8 commons) LCD panel. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and idle modes. LCD RAM ADDRESS AREA RAM addresses of bank 1 are used as LCD data memory. These locations can be addressed by 1-bit, 4-bit, or 8-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0–SEG40 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to generalpurpose use. S E G 2 S E G 3 8 S E G 3 9 S E G 0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 b0 b1 b2 b3 b0 b1 b2 b3 1B1H 1B0H S E G 1 1B2H 1B4H 1FCH 1FEH ...... 1B3H 1B5H 1FDH 1FFH Figure 33. LCD Display Data RAM Organization Table 24. Common and Segment Pins per Duty Cycle Duty 1/8 1/4 1/3 1-BIT OUTPUT The eight output pins (P5.0-P5.7) of the 40-segment output pins can be set in 4 bits for 1-bit level output by LMOD.6 and LMOD.7. At this time, the bit 0 of the even addressed display RAM is used as the output latch of 1bit output pins. The 1F0H.0 in LCD display RAM is used as the output latch for P5.0, 1F2H.0 is for P5.1,…… and 1FEH.0 is for P5.7. These 1-bit output pins cannot be used as 4 bits and 8 bits. Common Pins COM0–COM7 COM0–COM3 COM0–COM2 Segment Pins 32–40 pins Dot Number 256 dots–320 dots 128 dots–160 dots 96 dots–120 dots 4–52 S3C7254 PRODUCT SPECIFICATION LCD CIRCUIT DIAGRAM SEG39 / P5.7 SEG32 / P5.0 DISPLAY RAM (BANK"1") 80 MUX 40 SELECTOR SEG31 SEG0 f LCD DATA BUS COM7 LMOD TIMING CONTROLLER COM CONTROL COM0 LCON LCD VOLTAGE CONTROL VLC5 VLC1 L CDSY L CDCK P3.3 LATCH P3.2 LATCH PM3.3 PM3.2 Figure 34. LCD Circuit Diagram 4–53 PRODUCT SPECIFICATION S3C7254 LCD CONTROL REGISTER (LCON) The LCD control register (LCON) is used to turn the LCD display on and off, to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD display expansion, and to control the flow of current Table 25. LCD Control Register (LCON) Organization LCON Bit LCON.3 LCON.2 LCON.1, LCON.0 Setting 0 1 0 1 0,0 1,0 1,1 1/4 bias select 1/3 bias select to dividing resistors in the LCD circuit. The effect of the LCON.0 setting is dependent upon the current setting of bits LMOD.0 and LMOD.1. Description Disable LCDCK and LCDSY signal outputs. Enable LCDCK and LCDSY signal outputs. LCD display off LCD display on when using an external resistor for contrast control. LCD display on when not using an external resistor for contrast control. NOTES: 1. In case of LCON.0, you should turn on/off ‘LCD display’ using internal resistor. If you want to turn on/off LCD or to control ‘LCD contrast’’ internally, you should set the LCON.0 to “0”. 2. To select LCD bias, you must use both the LCON.3 setting and an external LCD bias circuit connection. 3. If you turn the LCD display off (LCON.0 = "0"), you reduce the current flowing through the LCD dividing resistorrs. Table 26. LMOD.1–0 Bits Settings LMOD.1–LMOD.0 0, 0 0, 1 1, 0 COM0–COM 7 SEG0–SEG39 SEG32/P5.0–SEG39/P5.7 1-bit output function Power Supply to the Dividing Resistor On All of the LCD dots off All of the LCD dots on Common and segment signal output corresponds to display data (normal display mode) 4–54 S3C7254 PRODUCT SPECIFICATION LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and display on/off. LMOD can be manipulated using 8-bit write instructions. The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This is also referred to as the 'frame frequency. Since LCDCK is generated by dividing Table 27. LCD Clock Signal (LCDCK) Frame Frequency LCDCK Display Duty Cycle 1/8 1/4 1/3 NOTE: fw = 32.768 kHz the watch timer clock (fw), the watch timer must be enabled when the LCD display is turned on. The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. The LCD mode register LMOD controls the output mode of the 8 pins used for normal outputs (P5.0–P5.7). Bits LMOD.7–5 define the segment output and normal bit output configuration. 128 Hz – – 42.7 Hz 256 Hz – 64 Hz 85.3 Hz 512 Hz 64 Hz 128 Hz 170.7 Hz 1024 Hz 128 Hz 256 Hz 341.3 Hz 2048 Hz 256 Hz 512 Hz – 4096 Hz 512 Hz – – COM0 1 FRAME 4–55 PRODUCT SPECIFICATION S3C7254 Table 28. LCD Mode Register (LMOD) Organization Segment /Output Port Selection Bits LMOD.7 0 0 1 1 LCD Clock Selection Bits LMOD.5 0 0 1 1 LMOD.4 1/8 duty (COM0–COM7) 0 1 0 1 fw/ 26 (512 Hz) fw/ 25 (1024 Hz) fw/ 24 (2048 Hz) fw/ 23 (4096 Hz) LCD Clock (LCDCK) 1/4 duty (COM0–COM3) fw/ 27 (256 Hz) fw/ 26 (512 Hz) fw/ 25 (1024 Hz) fw/ 24 (2048 Hz) 1/3 duty (COM0–COM2) fw/ 28 (128 Hz) fw/ 27 (256 Hz) fw/ 26 (512 Hz) fw/ 25 (1024 Hz) LMOD.6 0 1 0 1 SEG39–36 SEG port SEG port Output port Output port SEG35–32 SEG port Output port SEG port Output port Total Number of Segment 40 36 36 32 NOTE: LCDCK is supplied only when the watch timer operates. To use the LCD controller, bit 2 in the watch mode register WMOD should be set to 1. Duty Selection Bits LMOD.3 0 1 1 LMOD.2 0 0 1 1/8 duty (COM0–COM7 select) 1/4 duty (COM0–COM3 select) 1/3 duty (COM0–COM2 select) Duty Display Mode Selection Bits LMOD.1 0 0 1 LMOD.0 0 1 0 All LCD dots off All LCD dots on Normal display Function 4–56 S3C7254 PRODUCT SPECIFICATION LCD VOLTAGE DIVIDING RESISTORS On-chip voltage dividing resistors for the LCD drive power supply can be configured by mask option to the VLC1–VLC5 pins. Power can be supplied without an external dividing resistor. Figure 12–4 shows the bias connections for the S3C7254 LCD drive power supply. 1/4 Bias 1/3 Bias S3C7254 KS57C2504 VLC1 VLC2 VLC3 VLC4 VLC5 S3C7254 KS57C2504 VLC1 VLC2 VLC3 VLC4 VLC5 Figure 35. LCD Bias Circuit Connection 4–57 PRODUCT SPECIFICATION S3C7254 APPLICATION WITHOUT CONTRAST CONTROL If you use an internal transistor (LCON.0) to turn on/off 'LCD display', you can get a merit that peripheral circuits are simple. But in that case, you can't control LCD contrast. Application With Internal Resistor Application With External resistor S3C7254 KS57C2504 VDD S3C7254 KS57C2504 MASK OPTION VDD VDD VLC1 VLC2 VLCD VLC3 VLC4 VLC5 LCON.0 (3) LCON.0(3) VLC1 VLC2 VLC3 VLC4 VLC5 VSS VSS VDD or VLCN N: 1, 2, 3, 4, 5 LCON.1 LCD DATA OUT LCON.1 VDD or VLCN N: 1, 2, 3, 4, 5 COM & SEG LCD DATA OUT VSS or VLCN COM & SEG VSS or VLCN Figure 36. Connection For LCD On/Off Using Internal Transistor NOTES: 1. A 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for Figure 35. 2. When you turn off the LCD display using LCON settings, the amount of current flowing through the dividing resistors is reduced more than when you use LMOD to turn off the display. 3. When LCON.0–.1 = #00B, LCD display is turned off. When LCON.0–.1 = #11B, LCD display is turned on. 4–58 S3C7254 PRODUCT SPECIFICATION APPLICATION WITH CONTRAST CONTROL If you turn on/off 'LCD display' using external output pin, you can control LCD contrast using variable resistor. Application With Internal Resistor Application With External resistor S3C7254 KS57C2504 V DD S3C7254 KS57C2504 MASK OPTION VDD VDD VLC1 VLC2 VLCD VLC3 VLC4 VLC5 LCON.0 (Always "0") VLC1 VLC2 VLC3 VLC4 VLC5 LCON.0 (Always "0") VR VR Px.b (3) Px.b (3) VSS VDD or V LCN N: 1, 2, 3, 4, 5 LCON. 1 LCD DATA OUT LCON. 1 VSS V DD or VLCN N: 1, 2, 3, 4, 5 COM & SEG LCD DATA OUT COM & SEG V SS or V LCN VSS or VLCN Figure 37. Connection For LCD On/Off Using External Output Pin NOTES: 1. A 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for Figure 35. 2. When you turn off the LCD display using LCON settings, the amount of current flowing through the dividing resistors is reduced more than when you use LMOD to turn off the display. 3. When LCON.0–.1 = #00B and Px.b = #1B, LCD display is turned off. When LCON.0–.1 = #10B and Px.b = #0B, LCD display is turned on. 4–59 PRODUCT SPECIFICATION S3C7254 COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. — In 1/8 duty mode, COM0–COM7 pins are selected — In 1/4 duty mode, COM0–COM3 pins are selected — In 1/3 duty mode, COM0–COM2 pins are selected SEGMENT (SEG) SIGNALS The 40 LCD segment signal pins are connected to corresponding display RAM locations at bank 1. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. 4–60 S3C7254 PRODUCT SPECIFICATION COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 0 1 2 34 5 6 70 1 2 34 56 7 V DD FR 1 FRAME V DD V LC1 COM0 V LC2 (V LC3) V LC4 V LC5 V DD V LC1 COM1 V LC2 (V LC3) V LC4 V LC5 V DD V LC1 COM2 V LC2 (V LC3) V LC4 V LC5 V DD V LC1 SEG0 V LC2 (V LC3) V LC4 V LC5 V SS + VLCD + 1/4 VLCD SEG0–COM0 0V - 1 /4 VLCD - V LCD Figure 38. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) 4–61 PRODUCT SPECIFICATION S3C7254 0123456701234567 VDD VSS FR 1 FRAME V DD SEG1 V LC1 V LC2 (V LC3 ) V LC4 V LC5 + V LCD SEG1–COM0 +1/4 V LCD 0V -1/4 V LCD –V LCD Figure 39. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued) 4–62 S3C7254 PRODUCT SPECIFICATION SEG0 SEG1 CO M0 CO M1 CO M2 CO M3 1 FRAME 0 1 2 3 0 1 2 3 VDD VSS VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 + VLCD +1/3 VLCD 0V -1/3 VLCD - V LCD C OM0 C OM1 C OM2 C OM3 SEG0 SEG1 COM0–SEG0 Figure 40. LCD Signal Waveforms (1/4 Duty, 1/3 Bias) 4–63 PRODUCT SPECIFICATION S3C7254 SEG2 SEG1 SEG0 COM0 COM1 COM2 0 1 2 0 1 2 VDD 1 FRAME VSS VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 VDD VLC1 (VLC2 ) VLC3 (VLC4 ) VLC5 + V LCD +1/3 VLCD COM0 COM1 COM2 SEG0 SEG1 COM0–SEG0 0V -1/3 V LCD - V LCD Figure 41. LCD Signal Waveforms (1/3 Duty, 1/3 Bias) 4–64 S3C7254 PRODUCT SPECIFICATION COMPARATOR P1.0 and P1.1 can be used as a analog input port for a comparator. The reference voltage for the 2channel comparator can be supplied either internally or externally at P1.0. When an internal reference voltage is used, two channels (P1.0–P1.1) are used for analog inputs and the internal reference voltage is varied in 16 levels. If an external reference voltage is input at P1.0, the other P1.1 pins are used for analog input. When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial values of the CMPREG are undefined and the comparator operation is disabled by a RESET. The comparator module has the following components: P1.0 /CIN0 /INT0 M P1.1 /CIN1 /INT1 U X VREF (EXTERNAL) + – COMPARISON RESULT REGISTER (CMPREG) 4 M INTERNAL BUS U VDD X CMOD.7 CMOD.6 1/2R R R M U X 1/2R VREF (INTERNAL) CMOD.5 0 CMOD.3 CMOD.2 CMOD.1 CMOD.0 8 Note: INT occures only for digital input selecting: for analog input, any INT doesn't. Figure 42. Comparator Circuit Diagram 4–65 PRODUCT SPECIFICATION S3C7254 COMPARATOR MODE REGISTER (CMOD) The comparator mode register CMOD is an 8-bit register that is used to select the operation mode of the comparator. CMOD.7 CMOD.6 CMOD.5 "0" CMOD.3 CMOD.2 CMOD.1 CMOD.0 FD6H–FD7H Reference voltage (V REF ) selection: VDD x (n + 0.7)/16, n = 0 to 15 1: CIN0; external reference, CIN1; analog input 0: Internal reference, CIN0–1; analog input 1: Conversion time(4 x 24 /fx, 15.6 µs @4.19MHz) 0: Conversion time(4 x 27 /fx, 122.2 µs @4.19MHz) 1: Comparator operation enable 0: Comparator operation disable Figure 43. Comparator Mode Register (CMOD) Organization 4–66 S3C7254 PRODUCT SPECIFICATION PORT 1 MODE REGISTER (P1MOD) P1MOD register settings determine if P1.0 and P1.1 are used for analog or digital input. The P1MOD register is 4-bit write-only register. P1MOD is mapped to address FE2H. A reset operation initializes all P1MOD register values to zero, configuring P1.0 and P1.1 as a analog input port. COMPARATOR OPERATION The comparator compares analog voltage input at CIN0-CIN1 with an external or internal reference voltage (VREF) that is selected by the CMOD register. The result is written to the comparison result register CMPREG at address FD4H. The comparison result at internal reference is calculated as follows: If "1" If "0" Analog input voltage >=VREF + 150 mV Analog input voltage