KS57P5312

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVERVIEW The KS57C5204/C5208/C5304/C5308/C5312 single-chip CMOS microcontroller has been designed for highperformance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy consumption and low operating voltage. You can select from three ROM sizes: 4K, 8K, or 12K bytes. Except for the difference in ROM size, the features and functions of the KS57C5204 and the KS57C5208 are identical and the KS57C5304, KS57C5308, and the KS57C5312 are identical. With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, the KS57C5204/C5208 /C5304/C5308/C5312 offers an excellent design solution for a wide variety of telecommunication applications. Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the KS57C5204/C5208, and up to 23 pins of the available 30-pin SDIP or 32-pin SOP package for the KS57C5304/C5308/C5312 can be assign to I/O. Six vectored interrupts for KS57C5204/C5208 and four vectored interrupts for KS57C5304/C5308/C5312 provide fast response to internal and external events. In addition, the KS57C5204/C5208/C5304/C5308/C5312's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The KS57C5204/C5208 microcontroller is also available in OTP (One Time Programmable) version, KS57P5208. The KS57C5304/C5308/C5312 microcontroller is also available in OTP (One Time Programmable) version, KS57P5308/P5312. The KS57P5208/P5308/P5312 microcontroller has an on-chip 8K-byte (P5208/P5308) or 12K-byte (P5312) one-time-programable EPROM instead of masked ROM. The KS57P5208 is comparable to KS57C5204/C5208, both in function and in pin configuration. Also, the KS57P5308/P5312 is comparable to the KS57C5304/C5308/C5312, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 FEATURES Memory • 768 × 4-bit RAM 4,096 × 8-bit ROM (KS57C5204/C5304) 8,192 × 8-bit ROM (KS57C5208/C5308) 12,288 × 8-bit ROM (KS57C5312) format Interrupts • 3 external interrupt vectors (KS57C5204/C5208) 1 external interrupt vectors (KS57C5304/C5308/C5312) 3 internal interrupt vectors 2 quasi-interrupts I/O Pins • • • Input only: 4 pins (KS57C5204/C5208) 1 pins (KS57C5304/C5308/C5312) I/O: 35 pins (KS57C5204/C5208) 23 pins (KS57C5304/C5308/C5312) N-channel open-drain I/O: 8 pins • • Power-Down Modes • • Idle: Only CPU clock stops Stop: System clock stops Memory-Mapped I/O Structure • Data memory bank 15 Oscillation Sources • • • Crystal, or ceramic for main system clock Main system clock frequency: 0.4–6.0 MHz (typical) CPU clock divider circuit (by 4, 8, or 64) DTMF Generator • 16 dual-tone frequencies for tone dialing 8-Bit Basic Timer • • Programmable interval timer Watchdog timer Instruction Execution Times • • • 0.95, 1.91, and 15.3 µs at 4.19 MHz 1.12, 2.23, 17.88 µs at 3.58 MHz 0.67, 1.33, 10.7 µs at 6.0 MHz Two 8-Bit Timer/Counters • • • Programmable 8-bit timer External event counter function Arbitrary clock frequency output Operating Temperature • – 40 °C to 85 °C Watch Timer • • Real-time and time interval generation Four frequency outputs to the BUZ pin Operating Voltage Range • 1.8 V to 5.5 V Package Types • • 42 SDIP, 44 QFP (KS57C5204/C5208) 30 SDIP, 32 SOP (KS57C5304/C5308/C5312) Bit Sequential Carrier • Supports 16-bit serial data transfer in arbitrary 1-2 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW BLOCK DIAGRAM INT0, INT1, INT2, INT4 8-Bit Timer/ Counter 0 8-Bit Timer/ Counter 1 P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 P8.0 - P8.3 P9.0 - P9.2 I/O Port 6 I/O Port 7 RESET XIN XOUT Watchdog Timer Interrupt Control Block Clock Stack Pointer Basic Timer Watch Timer Input Port 1 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 P3.2 P3.3 P4.0/BTCO P4.1-4.3 P5.0-P5.3 Internal Interrupts Instruction Decoder Arithmetic and Logic Unit Program Counter Program Status Word I/O Port 2 Flags I/O Port 3 I/O Port 8 I/O Port 9 I/O Port 4 768x4-Bit Data Memory Program Memory KS57C5204/C5304: 4KBytes KS57C5208/C5308: 8KBytes KS57C5312: 12KBytes I/O Port 5 DTMF Generator DTMF NOTE: KS57C5304/C5308/C5312 does not use P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2, INT4, P8.0-P8.3, and P9.0-P9.2. Figure 1-1. KS57C5204/C5208/C5304/C5308/C5312 Simplified Block Diagram 1-3 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 PIN ASSIGNMENTS P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 VDD VSS XOUT XIN TEST P4.0/BTCO P4.1 RESET P3.2 P3.3 P4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 Figure 1-2. KS57C5204/C5208 Pin Assignment Diagram (42-SDIP) KS57C5204/C5208 (42-SDIP-600) 1-4 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW Figure 1-3. KS57C5204/C5208 Pin Assignment Diagram (44-QFP) P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 VDD VSS XOUT XIN TEST P4.0/BTCO P4.1 1 2 3 4 5 6 7 8 9 10 11 DTMF P9.0 P9.1 P9.2 NC P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 KS57C5204 /C5208 (44-QFP-1010B) P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 NC P4.2 P3.3 P3.2 RESET 1-5 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57C5304/C5308/C5312 (30-SDIP-400) VSS XOUT XIN TEST P4.0/BTCO P4.1 RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 1-4. KS57C5304/C5308/C5312 Pin Assignment Diagram (30-SDIP) VSS XOUT XIN TEST P4.0/BTCO P4.1 RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 NC DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 1-5. KS57C5304/C5308/C5312 Pin Assignment Diagram (32-SOP) KS57C5304/C5308/C5312 (32-SOP-450A) 1-6 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. KS57C5204/C5208 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 I/O I Pin Reset Type Value I I Description 4-bit input port. 1-bit and 4-bit read and test is possible. Each pull-up resistors are assignable by software. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. N-channel open-drain or push-pull output can be selected by software (1-bit unit) Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 8 and 9 can be paired to enable 8-bit data transfer. Pin Number 1 (39) 2 (40) 3 (41) 4 (42) 5 (43) 6 (44) 7 (1) 8 (2) 9 (3) 10 (4) 19 (13) 20 (14) 16 (10) 17 (11) 21 (15) 22 (17) 27-30 (22-25) Share Pin INT0 INT1 INT2 INT4 TCLO0 TCLO1 CLO BUZ TCL0 TCL1 Circuit Type A-4 I/O I D-2 D-4 BTCO E-2 P6.0-P6.3 P7.0-P7.3 I/O I 31-34 (26-29) 35-38 (30-33) KS0-KS3 KS4-KS7 D-4 P8.0-P8.3 P9.0-P9.2 I/O I 23-26 (18-21) 40-42 (35-37) – D-2 1-7 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 1-1. KS57C5204/C5208 Pin Descriptions (Continued) Pin Name Pin Reset Type Value O I/O I I I I/O I/O I/O I/O – I I I I I I I I DTMF output. Basic timer clock output External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising edges External interrupt with detection of rising and falling edges. Timer/counter 0 clock output Timer/counter 1 clock output Clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound External clock input for timer/counter 0 External clock input for timer/counter 1 Quasi-interrupt inputs with falling edge detection Description Pin Number 39 (34) 16 (10) 1 (39) 2 (40) 3 (41) 4 (42) 5 (43) 6 (44) 7 (1) 8 (2) Share Pin – P4.0 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 Circu it Type G-6 E-2 A-4 A-4 A-4 D-2 D-2 D-2 D-2 DTMF BTCO INT0 INT1 INT2 INT4 TCLO0 TCLO1 CLO BUZ TCL0 TCL1 KS0-KS3 KS4-KS7 VDD VSS RESET I/O I/O I/O I I I 9 (3) 10 (4) 31-34 (26-29) 35-38 (30-33) 11 (5) 12 (6) 18 (12) 14 (8) 13 (7) 15 (9) (16, 38) P3.0 P3.1 P6.0-P6.3 P7.0-P7.3 D-4 D-4 D-4 – – – – – – – – Power supply Ground RESET – – – – – – B – signal XIN XOUT TEST NC Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Chip test input pin, Hold GND when the device is operating. No connection – – – – – – – – NOTE: Parentheses indicate pin number for 44 QFP package. 1-8 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions Pin Name P1.0 Pin Type I Description 1-bit input port. 1-bit and 4-bit read and test is possible. Each bit pull-up resistors are assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. The N-channel open-drain or push-pull output can be selected by software (1-bit unit). Ports 4 and 5 can be paired to enable 8-bit data transfer. 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. Pin Number 23 (25) Share Pin INT0 Circuit Type A-4 P2.0 P2.1 P2.2 P2.3 I/O 24 (26) 25 (27) 26 (28) 27 (29) TCLO0 TCLO1 CLO BUZ D-2 P3.0 P3.1 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 I/O 28 (30) 29 (31) 5 (5) 6 (6) 8 (8) 9 (10) 10-13 (11-14) TCL0 TCL1 BTCO D-4 E-2 P6.0-P6.3 P7.0-P7.3 I/O 14-17 (15-18) 18-21 (19-22) KS0-KS3 KS4-KS7 D-4 1-9 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions (Continued) Pin Name DTMF INT0 TCLO0 TCLO1 CLO BUZ I/O Type O I I/O I/O I/O I/O DTMF output. External interrupt input. The triggering edge for INT0 is selectable. Timer/counter 0 clock output Timer/counter 1 clock output Clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound External clock input for timer/counter 0 External clock input for timer/counter 1 Basic timer clock output Power supply Ground Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) No connection Chip test input pin, Hold GND when the device is operating. RESET Description Pin Number 22 (23) 23 (25) 24 (26) 25 (27) 26 (28) 27 (29) Share Pin – P1.0 P2.0 P2.1 P2.2 P2.3 Circuit Type G-6 A-3 D-2 D-2 D-2 D-2 TCL0 TCL1 BTCO VDD VSS XIN XOUT NC TEST RESET I/O I/O I/O – – – 28 (30) 29 (31) 5 (5) 30 (32) 1 (1) 3 (3) 2 (2) (9, 24) 4 (4) 7 (7) 14-17 (15-18) 18-21 (19-22) P3.0 P3.1 P4.0 – – – D-4 D-4 E-2 – – – – – – I/O – – – P6.0-P6.3 P7.0-P7.3 – – B D-4 signal KS0-KS3 KS4-KS7 Quasi-interrupt inputs with falling edge detection NOTE: Parentheses indicate the pin number for 32-SOP package. 1-10 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD P-Channel Pull-Up Resistor In In N-Channel Schmitt Trigger Figure 1-6. Pin Circuit Type A Figure 1-8. Pin Circuit Type B VDD VDD Pull-Up Resistor P-Channel In Resistor Enable Data P-Channel Out Output DIsable Schmitt Trigger N-Channel Figure 1-7. Pin Circuit Type A-4 Figure 1-9. Pin Circuit Type C 1-11 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 VDD Pull-up Resistor Pull-up Enable Data Output DIsable P-Channel VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O VDD Circuit Type C Data I/O P-Channel Output Disable N-Channel Figure 1-10. Pin Circuit Type D-2 Figure 1-12. Pin Circuit Type E-2 VDD Pull-up Resistor Pull-up Enable Data Output Disable P-Channel Circuit Type C DTMF Out I/O Output Disable Schmitt Trigger Figure 1-11. Pin Circuit Type D-4 Figure 1-13. Pin Circuit Type G-6 1-12 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA 13 OVERVIEW — I/O capacitance ELECTRICAL DATA In this section, information on KS57C5204/C5208/C5304/C5308/C5312 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — System clock oscillator characteristics — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at XIN and XOUT — TCL timing — Input timing for RESET — Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 13-1 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL All I/O ports – One I/O port active All I/O ports active Output Current Low One I/O port active Conditions – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 15 – 35 + 30 (Peak value) + 15 All I/O ports active Operating Temperature Storage Temperature TA Tstg – – Duty . (note) Units V V V mA mA + 100 (Peak value) + 60 (note) – 40 to + 85 – 65 to + 150 °C °C NOTE: The values for output current low ( IOL ) are calculated as peak value × Table 13-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Conditions All input pins except those specified below for VIH2 – VIH3 Ports 1, 3, 6, 7, and RESET XIN and XOUT All input pins except those specified below for VIL2–VIL3 Ports 1, 3, 6, 7, and RESET XIN and XOUT Min 0.7 VDD 0.8 VDD VDD – 0.1 – – Typ – Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V 13-2 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Output high voltage Output low voltage Symbol VOH VOL1 IOH = – 1 mA Ports except 1 VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 4 and 5 only VDD = 1.8 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL= 4 mA, all out ports except 4,5 VDD = 1.8 to 5.5 V, IOL = 1.6mA Input high leakage current ILIH1 VI = VDD All input pins except those specified below VI = VDD XIN and XOUT VI = 0 V All input pins except below and RESET VI = 0 V XIN and XOUT only VO = VDD All out pins VO = 0 V All out pins VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL2 VDD = 5 V; VI = 0 V; RESET VDD = 3 V – – 25 50 100 200 – – 47 95 220 450 – – Conditions Min VDD – 1.0 – – – – – Typ – – – – – – Max – 2 0.4 2 0.4 3 µA V Units V V ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RL1 20 –3 – 20 3 –3 100 200 400 800 µA µA kΩ µA 13-3 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (DTMF on) Conditions Run mode; VDD = 5 V ± 10% (2) 3.58 MHz crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% Run mode; VDD = 5 V ± 10% crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz Min – Typ 2.5 Max 5.0 Units mA 1.4 – 2.5 1.6 1.2 0.7 – 0.7 0.6 0.3 0.2 – 0.01 0.01 3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 3 2 dBV dB µA mA mA IDD2 (DTMF off) IDD3 Idle mode; = VDD = 5 V ± 10% crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% IDD4 Stop mode; VDD = 5 V ± 10% Stop mode; VDD = 3 V ± 10% Row tone level Ratio of column to row tone Distortion (Dual tone) VROW dBCR VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C VDD = 2.0 V to 5.5 V 1MHz band; RL= 12 kΩ Temp = – 30 °C to 60 °C – 16.0 – 14.0 – 11.0 1 2 3 THD – – 5 % NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 13-4 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA Table 13-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ – Max 6.0 Units MHz C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator XIN XOUT 0.4 – 0.4 – – – 3 4 6.0 ms MHz VDD = 3 V VDD = 2.7 V to 5.5 V Oscillation frequency (1) C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock XIN XOUT 0.4 – 0.4 – – – 3 10 6.0 ms MHz VDD = 3 V VDD = 2.7 V to 5.5 V XIN input frequency (1) VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) – 0.4 83.3 – – 3 1250 ns NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 13-5 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 13-4. Recommended Oscillator Constants (TA = – 40 °C to + 85 °C) Manufacturer Series Number (1) Frequency Range Load Cap (pF) C1 TDK FCR FCR CCR M5 MC5 MC3 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33 (2) Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5 Remarks C2 33 (2) Leaded Type On-chip C Leaded Type On-chip C SMD Type (3) (3) NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. Table 13-5. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min – – – Typ – – – Max 15 15 15 Units pF pF pF 13-6 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA Table 13-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0, TCL1 Input Frequency fTI0, fTI1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5V TCL0, TCL1 Input High, Low Width tTIH0, tTIL0 tTIH1, tTIL1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Interrupt Input High, Low Width RESET Min 0.67 1.33 0 Typ – Max 64 Units µs – 1.5 1 MHz MHz µs 0.48 1.8 10 10 – – tINTH, tINTL tRSL INT0, INT1, INT2, INT4, KS0-KS7 Input – – – – µs µs Input Low Width 13-7 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 CPU Clock 1.5 MHz Main Oscillator Frequency (Divided by 4) 6 MHz 0.75 MHz 3 MHz 15.625 kHz 1 2 1.8 3 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 5 6 7 Figure 13-1. Standard Operating Voltage Range Table 13-7. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions – VDDDR = 1.8 V – Released by RESET Released by interrupt Min 1.8 – 0 – Typ – 0.1 – 2 /fx (2) 17 Max 5.5 10 – – Unit V µA µs ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 13-8 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction RESET tWAIT tSREL Figure 13-2. Stop Mode Release Timing When Initiated by RESET Idle Mode Stop Mode Data Retention Normal Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request 13-9 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Timing Waveforms (continued) 0.8 VDD Measurement Points 0.2 VDD 0.8 VDD 0.2 VDD Figure 13-4. A.C. Timing Measurement Points (Except for XIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 13-5. Clock Timing Measurement at XIN 1/fTI tTIL tTIH TCL 0.8 VDD 0.2 VDD Figure 13-6. TCL Timing 13-10 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 13-7. Input Timing for RESET Signal tINTL tINTH INT0, 1, 2, 4, KS0 to KS7 0.8 VDD 0.2 VDD Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts 13-11 ELECTRICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 NOTES 13-12 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA 14 OVERVIEW #42 MECHANICAL DATA The KS57C5204/C5208 microcontroller are available in a 42-pin SDIP package (42-SDIP-600), and a 44-pin QFP package (44-QFP-1010B). The KS57C5304/C5308/C5312 microcontrollers are available in a 30-pin SDIP package (30-SDIP-400) and a 32-pin SOP package (32-SOP-450A). #22 0-15 14.00 ± 0.2 #1 #21 39.50 MAX 39.10 ± 0.2 0.51 MIN 0.50 ± (1.77) 1.00 ± 0.1 0.1 1.778 NOTE : Dimensions are in millimeters. Figure 14-1. 42-SDIP-600 Package Dimensions 3.30 ± 0.3 5.08 MAX 3.50 ± 0.2 0.2 5 14-1 +0 - 0 .1 .05 42-SDIP-600 15.24 MECHANICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 13.20 ± 0.3 0-8 10.00 ± 0.2 0.15 + 0.10 - 0.05 13.20 ± 0.3 10.00 ± 0.2 44-QFP-1010B 0.80 ± 0.20 #1 0.80 + 0.10 0.10 MAX #44 0.35 - 0.05 (1.00) 0.05 MIN 2.05 ± 0.10 2.30 MAX NOTE : Dimensions are in millimeters. Figure 14-2. 44-QFP-1010B Package Dimensions 14-2 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA #30 #16 0-15 8.94 ± 0.2 #1 #15 27.88 MAX 27.48 ± 0.2 0.51 MIN 0.56 ± (1.77) 1.12 ± 0.1 0.1 1.778 NOTE : Dimensions are in millimeters. Figure 14-3. 30-SDIP-400 Package Dimensions 3.30 ± 0.3 5.08 MAX 3.81 ± 0.2 0.2 5 +0 - 0 .1 .05 30-SDIP-400 10.16 14-3 MECHANICAL DATA KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 #32 #17 12.00 ± 0.3 8.34 ± 0.2 2.00 ± 0.2 2.40 MAX #1 19.90 ± 0.2 #16 0.20 + 0.1 - 0.05 (0.43) 0.40 ± 0.1 1.27 NOTE: Dimensions are in millimeters Figure 14-4. 32-SOP-450A Package Dimensions 14-4 0.05 MIN 0.78 ± 0.2 32-SOP-450A 11.43 0-8 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP 15 OVERVIEW KS57P5208/P5308/P5312 OTP The KS57P5208/P5308/P5312 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C5204/C5208/C5304/C5308/C5312 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The KS57P5208/P5308/P5312 is fully compatible with the KS57C5208/C5308/C5312, both in function and in pin configuration. Because of its simple programming requirements, the KS57P5208/P5308/P5312 is ideal for use as an evaluation chip for the KS57C5208/C5308/C5312. P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ SDAT /P3.0/TCL0 SCLK /P3.1/TCL1 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 RESET/RESET P3.2 P3.3 P4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 Figure 15-1. KS57P5208 Pin Assignment Diagram (42-SDIP) KS57P5208 (42-SDIP-600) 15-1 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Figure 15-2. KS57P5208 Pin Assignment Diagram (44-QFP) 15-2 P2.2/CLO P2.3/BUZ SDAT/P3.0/TCL0 SCLK/P3.1/TCL1 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 1 2 3 4 5 6 7 8 9 10 11 DTMF P9.0 P9.1 P9.2 NC P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 KS57P5208 (44-QFP-1010B) P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 NC P4.2 P3.3 P3.2 RESET/ RESET KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 RESET/RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD/VDD P3.1/TCL1/SCLK P3.0/TCL0/SDAT P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 15-3. KS57P5308/P5312 Pin Assignment Diagram (30-SDIP) KS57P5308/P5312 (30-SDIP-400) VSS/VSS XOUT XIN VPP/TEST P4.0/BTCO P4.1 RESET/RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD/VDD P3.1/TCL1/SCLK P3.0/TCL0/SDAT P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 NC DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 Figure 15-4. KS57P5308/P5312 Pin Assignment Diagram (32-SOP) KS57P5308/P5312 (32-SOP-450A) 15-3 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 15-1. KS57P5208 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name P3.0 Pin Name SDAT Pin No. 9 (3) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OPT is operating. Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.1 TEST SCLK VPP (TEST) 10 (4) 15 (9) I/O I RESET RESET 18 (12) 11/12 (5/6) I I VDD / VSS VDD / VSS NOTE: Parentheses indicate pin numbers of 44 QFP package. Table 15-2. KS57P5308/P5312 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name P3.0 Pin Name SDAT Pin No. 28 (30) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OPT is operating. Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.1 TEST SCLK VPP (TEST) 29 (31) 4 (4) I/O I RESET RESET 7 (7) 30/1 (32/1) I I VDD / VSS VDD / VSS NOTE: Parentheses indicate pin numbers of 32 SDIP package. 15-4 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Table 15-3. Comparison of KS57P5208 and KS57C5208 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS57P5208 8 K byte EPROM 1.8 V (3 MHz) to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 42 SDIP / 44 QFP User Program 1 time KS57C5208 8 K byte mask ROM 1.8 V (3 MHz) to 5.5 V – 42 SDIP / 44 QFP Programmed at the factory Table 15-4. Comparison of KS57P5308/P5312 and KS57C5308/C5312 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS57P5308/P5312 8 K byte EPROM / 12 K (P5312) 1.8 V (3 MHz) to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 30 SOP / 32 SOP User Program 1 time KS57C5308/C5312 8 K byte mask ROM / 12 K (C5312) 1.8 V (3 MHz) to 5.5 V – 30 SOP / 32 SOP Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the Vpp(TEST) pin of the KS57P5208/P5308/P5312, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-5. Operating Mode Selection Criteria VDD 5V Vpp (TEST) 5V 12.5V 12.5V 12.5V REG/ MEM Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read Mode 0 0 0 1 EPROM program EPROM verify EPROM read protection NOTE: "0" means Low level; "1" means High level. 15-5 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 OTP ELECTRICAL DATA Table 15-6. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL All I/O ports – One I/O port active All I/O ports active Output Current Low One I/O port active Conditions – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 15 – 35 + 30 (Peak value) + 15 All I/O ports active Operating Temperature Storage Temperature TA Tstg – – Duty . (note) Units V V V mA mA + 100 (Peak value) + 60 (note) – 40 to + 85 – 65 to + 150 °C °C NOTE: The values for output current low ( IOL ) are calculated as peak value × Table 15-7. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Conditions All input pins except those specified below for VIH2 – VIH3 Ports 1, 3, 6, 7, and RESET XIN and XOUT All input pins except those specified below for VIL2–VIL3 Ports 1, 3, 6, 7, and RESET XIN and XOUT Min 0.7 VDD 0.8 VDD VDD – 0.1 – – Typ – Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V 15-6 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Table 15-7. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Output high voltage Output low voltage Symbol VOH VOL1 Conditions IOH = – 1 mA Ports except 1 VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 4 and 5 only VDD = 1.8 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL= 4 mA, all out ports except 4,5 VDD = 1.8 to 5.5 V, IOL = 1.6mA Input high leakage current ILIH1 VI = VDD All input pins except those specified below VI = VDD XIN and XOUT VI = 0 V All input pins except below and RESET VI = 0 V XIN and XOUT only VO = VDD All out pins VO = 0 V All out pins VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL2 VDD = 5 V; VI = 0 V; RESET VDD = 3 V – – 25 50 100 200 – – 47 95 220 450 – – Min VDD – 1.0 – – – – – Typ – – – – – – Max – 2 0.4 2 0.4 3 µA V Units V V ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RL1 20 –3 – 20 3 –3 100 200 400 800 µA µA kΩ µA 15-7 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 15-7. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (DTMF on) Conditions Run mode; VDD = 5 V ± 10% (2) 3.58 MHz crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% Run mode; VDD = 5 V ± 10% crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz Min – Typ 2.5 Max 5.0 Units mA 1.4 – 2.5 1.6 1.2 0.7 – 0.7 0.6 0.3 0.2 – 0.01 0.01 3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 3 2 dBV dB % µA mA mA IDD2 (DTMF off) IDD3 Idle mode; = VDD = 5 V ± 10% crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% IDD4 Stop mode; VDD = 5 V ± 10% Stop mode; VDD = 3 V ± 10% Row tone level Ratio of column to row tone Distortion (Dual tone) VROW dBCR THD VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C VDD = 2.0 V to 5.5 V RL = 12 kΩ, Temp = – 30 °C to 60 °C VDD = 2.0 V to 5.5 V 1MHz band; RL= 12 kΩ Temp = – 30 °C to 60 °C – 16.0 – 14.0 – 11.0 1 – 2 – 3 5 NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 15-8 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP Table 15-8. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ – Max 6.0 Units MHz C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator XIN XOUT 0.4 – 0.4 – – – 3 4 6.0 ms MHz VDD = 3 V VDD = 2.7 V to 5.5 V Oscillation frequency (1) C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock XIN XOUT 0.4 – 0.4 – – – 3 10 6.0 ms MHz VDD = 3 V VDD = 2.7 V to 5.5 V XIN input frequency (1) VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) – 0.4 83.3 – – 3 1250 ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 15-9 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 Table 15-9. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min – – – Typ – – – Max 15 15 15 Units pF pF pF Table 15-10. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0, TCL1 Input Frequency fTI0, fTI1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5V TCL0, TCL1 Input High, Low Width tTIH0, tTIL0 tTIH1, tTIL1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Interrupt Input High, Low Width RESET Min 0.67 1.33 0 Typ – Max 64 Units µs – 1.5 1 MHz MHz µs 0.48 1.8 10 10 – – tINTH, tINTL tRSL INT0, INT1, INT2, INT4, KS0-KS7 Input – – – – µs µs Input Low Width 15-10 KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 KS57P5208/P5308/P5312 OTP CPU Clock 1.5 MHz Main Oscillator Frequency (Divided by 4) 6 MHz 0.75 MHz 3 MHz 15.625 kHz 1 2 1.8 3 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 5 6 7 Figure 15-5. Standard Operating Voltage Range Table 15-11. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions – VDDDR = 1.8 V – Released by RESET Released by interrupt Min 1.8 – 0 – Typ – 0.1 – 2 /fx (2) 17 Max 5.5 10 – – Unit V µA µs ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 15-11 KS57P5208/P5308/P5312 OTP KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312 NOTES 15-12