KS88C0716

KS88C0716/P0716 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels. KS88C0716/P0716 MICROCONTROLLERS KS88C0716/P0716 single-chip 8-bit microcontrollers are based on the powerful SAM87 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. The KS88C0716 has 16-Kbyte mask-programmable ROM. The KS88P0716 has 16-Kbyte one-time-programmable EPROM. Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core: — Seven programmable I/O ports (total 56 pins) — One 8-bit basic timer for oscillation stabilization and watchdog functions — One synchronous operating mode and three full-duplex asynchronous UART modes — Two 8-bit timers with interval timer and PWM modes — Two 16-bit general-purpose timer/counters OTP The KS88C0716 microcontroller is also available in OTP (One Time Programmable) version, KS88P0716. KS88P0716 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM. The KS88P0716 is comparable to KS88C0716, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS88C0716/P0716 FEATURES CPU • SAM87 CPU core General I/O • • Memory • • • 272-byte general purpose register area 16-Kbyte internal program memory ROM-less operating mode Timers • External Interface • • 64-Kbyte external data memory area 64-Kbyte external program memory area (ROMless mode) Two 8-bit timers with interval timer and PWM modes • Four nibble-programmable ports One bit-programmable port Two bit-programmable ports for external interrupts Timer/Counters • Two 16-bit general-purpose timer/counters Instruction Set • • 78instructions IDLE and STOP instructions for power-down mode Basic Timer • One 8-bit basic timer (BT) for oscillation stabilization control and watch dog timer function. Serial Port • One synchronous operating mode and three fullduplex asynchronous UART modes Instruction Execution Time • 500 ns at 12 MHz fCPU (Min.) Operating Temperature Range Interrupts • • • • 17 interrupt sources 17 interrupt vectors Eight interrupt levels Fast interrupt processing Package Types • 64-pin SDIP, 64-pin QFP • – 40°C to + 85°C Operating Voltage Range • 2.7 V to 5.5 V 1-2 KS88C0716/P0716 PRODUCT OVERVIEW Table 1-1. Comparison Table Feature Core ROM RAM I/O Port 6 I/O option Timer SAM8 16 K bytes 272 bytes 54 Open drain (9 V drive) None 8-bit back-up timer Timer A, B — 8-bit — Interval/PWM mode — Timer A match interrupt Timer C, D — Gate function — Timer/counter Watchdog timer SIO None UART — 8-bit/9-bit UART — SIO External × 12 — P2.4–P2.7, P4.0–P4.7 Internal × 6 — Timer A, C, D, SI, SO, Back-up Power down Oscillator CPU clock divider Execution time (Min.) Operating frequency Operating voltage OTP/MTP Pin assignment Package Start address P5CON, P6CON Interrupt pending bit clear 64SDIP/64QFP 0020h BANK0 Write "1" Stop/idle Crystal, ceramic 1/2 0.6 µs at 20 MHz (fCPU = 10 MHz) Max. 20 MHz (fCPU = 10 MHz) 4.5–5.5 V MTP – KS88C0116 SAM87 Same Same 56 (add two pins) Normal C-MOS output Same None Same (some differ in interval mode, see manual) Same KS88C0716 Watchdog timer (with BT) Same Interrupt Same Internal × 5 — Timer A, C, D, SI, SO Same Same 1/1, 1/2, 1/8, 1/16 0.5 µs at 12 MHz (fCPU = 12 MHz) Max. 12 MHz (at 4.5 V) (2) Max. 4 MHz (at 2.7 V) 2.7–5.5 V at 4 MHz 4.5–5.5 V at 12 MHz OTP Different Same 0100h BANK1 Write "0" NOTES: 1. The KS88C0716 can replace the KS88C0116. Their functions are mostly the same, but there are some differences. Table 1-1 shows the comparison of KS88C0716 and KS88C0116. 1-3 PRODUCT OVERVIEW KS88C0716/P0716 2. Operating frequency is maximum CPU clock; the maximum oscillation frequency is 22.1184 MHz. BLOCK DIAGRAM P0.0–P0.7 (A8–A15) P1.0–P1.7 (AD0–AD7) P2.0–P2.3, P2.4/INT0–P2.7/INT3 RESET EA PORT 0 PORT 1 PORT 2 XIN XOUT MAIN OSC SAM87 BUS PORT 3 PORT I/O and INTERRUPT CONTROL P4.0/INT4 (TCG) P4.1/INT5 (TDG) P4.2/INT6– P4.7/INT11 P3.0–P3.7 BASIC TIMER PORT 4 TA TB TIMERS A and B SAM87 CPU PORT 5 TCCK TDCK TIMERS C and D P5.0–P5.3 P5.4–P5.7 RxD TxD SERIAL PORT 16-KB ROM 272-BYTE REGISTER FILE PORT 6 P6.0–P6.7 Figure 1-1. KS88C0716 Block Diagram 1-4 KS88C0716/P0716 PRODUCT OVERVIEW P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P4.7/INT11 P4.6/INT10 P4.5/INT9 P4.4/INT8 P4.3/INT7 P4.2/INT6 P4.1/INT5/TDG P4.0/INT4/TCG VDD1 VSS1 XOUT XIN EA P5.6 P5.7 RESET P3.7/RxD P3.6/TxD P3.5/TB P3.4/TA P3.3 P3.2 P3.1/TDCK P3.0/TCCK P6.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 KS88C0716 64-SDIP (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P0.7/A15 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDD2 VSS2 P2.0/ AS P2.1/ DS P2.2/R/ W P2.3/ DM P2.4/INT0/ WAIT P2.5/INT1 P2.6/INT2 P2.7/INT3 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 Figure 1-2. KS88C0716 Pin Assignments (64-SDIP) 1-5 PRODUCT OVERVIEW KS88C0716/P0716 P1.4/AD4 P1.3/AD3 P1.2/AD2 P1.1/AD1 P1.0/AD0 P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P4.7/INT11 P4.6/INT10 P4.5/INT9 P4.4/INT8 P4.3/INT7 P4.2/INT6 P4.1/INT5/TDG P4.0/INT4/TCG VDD1 VSS1 XOUT XIN EA P5.6 P5.7 RESET KS88C0716 64-QFP (Top View) P3.7/RxD P3.6/TxD P3.5/TB 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDD2 VSS2 P2.0/ AS P2.1/ DS P2.2/R/ W P2.3/ DM P2.4/INT0/ WAIT P2.5/INT1 P2.6/INT2 P2.7/INT3 Figure 1-3. KS88C0716 Pin Assignments (64-QFP) 32 31 30 29 28 27 26 25 24 23 22 21 20 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P3.0/TCCK P3.1/TDCK P3.2 P3.3 P3.4/TA 1-6 KS88C0716/P0716 PRODUCT OVERVIEW Table 1-2. KS88C0716 Pin Descriptions (64-SDIP) Pin Name P0.0–P0.7 Pin Type I/O Pin Description I/O port with nibble-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups; also configurable as external interface address lines A8-A15. Same general characteristics as port 0; also configurable as external interface address/data lines AD0–AD7. I/O port with bit-programmable pins; Input or push-pull output. Lower nibble pins 0–3 are configurable for external interface signals; upper nibble pins 4–7 are bitprogrammable for external interrupts INT0– INT3. P2.4 can also be used for external input. I/O port with bit-programmable pins; Input or push-pull output. Alternate functions include software-selectable UART transmit and receive on pins 3.7 and 3.6, timer B and timer A outputs at pins 3.5 and 3.4, and timer D and C clock inputs at pins 3.1 and 3.0. I/O port with bit-programmable pins; Input or push-pull output; software-assignable pull-ups. Alternate functions include external interrupt inputs INT4-INT11 (with interrupt enable and pending control) and timer C and D gate input at P4.0 and P4.1. I/O port with nibble-programmable pins; Input or push-pull, open-drain output; software-assignable pull-ups. Output port with nibble-programmable pins; push-pull, open-drain output; softwareassignable pull-ups. Bi-directional serial data input pin Serial data output pin Timer A and B output pins Timer C and D external clock input pins External interrupts. I/O pin 2.4 (share pin with INT0) is also configurable as a WAIT signal input pin for the external interface. Circuit Number E SDIP Pin Number 1–7, 64 Share Pins A8–A15 P1.0–P1.7 I/O E 56–63 AD0–AD7 P2.0–P2.3 I/O D-1 (lower nibble); D-1 (upper nibble; with noise filter) D-1 40–47 AS, DS, DM, R/W P2.4–P2.7 INT0–INT3, WAIT P3.0–P3.7 I/O 24– 31 TCCK, TDCK, TA, TB, TxD, RxD P4.0–P4.7 I/O D (with noise filter) 8–15 INT4– INT11, TCG, TDG P5.0–P5.7 I/O E 21, 22, 50–55 32–39 – P6.0–P6.7 O E-8 – RxD TxD TA, TB TCCK, TDCK INT0–INT3 I/O I/O I/O I/O I/O – – 4 D-1 D-1 (with noise filter) 24 25 27, 26 30, 31 40–43 P3.7 P3.6 P3.4, P3.5 P3.0, P3.1 P2.4–P2.7 1-7 PRODUCT OVERVIEW KS88C0716/P0716 Table 1-2. KS88C0716 Pin Descriptions (Continued) Pin Name INT4–INT11 Pin Type I/O Pin Description Bit-programmable external interrupt input pins with interrupt pending and enable /disable control System clock input and output pins System reset pin (internal pull-up: 280 KΩ) External access (EA) pin with three modes: 0 V: Normal operation (internal ROM) 5 V: ROM-less operation (external interface) Power input pins for port output (external) Power input pins for CPU (internal) Circuit Number D (with noise filter) – B – SDIP Pin Number 8–15 Share Pins P4.0–P4.7 XIN, XOUT RESET – I I 18, 19 23 20 – – – EA VDD2, VSS2 VDD1, VSS1 – – – – 49, 48 16, 17 – – 1-8 KS88C0716/P0716 PRODUCT OVERVIEW PIN CIRCUIT VDD Pull-Up Resistor (Typical Value: 47 KΩ) Pull-Up Enable VDD Data Open-Drain Output Disable In/Out In Figure 1-4. Pin Circuit Type E (Ports 0, 1, 5) VDD Pull-Up Resistor (Typical Value: 47 KΩ) Pull-Up Enable VDD Open-Drain Data In/Out VSS Figure 1-5. Pin Circuit Type E-8 (Ports 6) 1-9 PRODUCT OVERVIEW KS88C0716/P0716 Select VDD Port 2 (Low Byte) Data External Interface (AS, DS, R/ W, DM ) M U X Data In/Out Output Disable VSS In Figure 1-6. Pin Circuit Type D-1 (P2.0–P2.3) VDD Port 2 (High Byte) Data In/Out Output Disable Normal Input or WAIT Input External Interrupt Noise Filter VSS Figure 1-7. Pin Circuit Type D-1 (P2.4–P2.7) 1-10 KS88C0716/P0716 PRODUCT OVERVIEW Select VDD Port 3 Data Control Output M U X Data In/Out Output Disable VSS In Figure 1-8. Pin Circuit Type D-1 (Port 3) VDD Pull-Up Resistor (Typical Value: 47 KΩ) Pull-Up Enable VDD Data In/Out Output Disable Input External Interrpt Input VSS Noise Filter Figure 1-9. Pin Circuit Type D (Port 4) 1-11 PRODUCT OVERVIEW KS88C0716/P0716 VDD Pull-up Resistor (Typical 210 K Ω) RESET Figure 1-10. Pin Circuit Type B (RESET) 1-12 KS88C0716/P0716 ELECTRICAL DATA 14 OVERVIEW — I/O capacitance ELECTRICAL DATA In this section, KS88C0716 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time 14-1 ELECTRICAL DATA KS88C0716/P0716 Table 14-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO I OH I OL All ports (in input mode) All ports (in output mode) One I/O pin active All I/O pins active Output current low One I/O pin active Total pin current for ports 0–4 Total pin current for ports 5 and 6 Operating temperature Storage temperature TA TSTG Conditions Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 10 – 60 + 30 + 100 + 100 – 40 to + 85 – 65 to + 150 °C °C Unit V V mA mA 14-2 KS88C0716/P0716 ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Input high voltage Input low voltage Symbol VIH1 VIH2 VIL1 VIL2 Output high voltage VOH1 Conditions All input pins except VIH2 XIN All input pins except VIL2 XIN VDD= 4.5 V to 5.5 V IOH = – 4 mA Port 5, 6 VDD = 4.5 V to 5.5 V IOH = – 1 mA All output pins except port 5, 6 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 5 and 6 IOL = 2 mA Ports 0–4 VIN = VDD All input pins except XIN, XOUT VIN = VDD, XIN, XOUT VIN = 0 V All input pins except XIN, XOUT VIN = 0 V, XIN, XOUT VOUT = VDD All output pins VOUT = 0 V VIN = 0 V; VDD = 5 V Ports 0, 1, 4, 5 and 6 VIN = 0 V; VDD = 5 V RESET only – – 30 110 – – 47 210 – – – – – – 1.0 V VDD – 1.0 – Min 0.8 VDD VDD – 0.5 – – 0.2 VDD 0.4 – V V Typ – Max VDD Unit V VOH2 Output low voltage VOL1 VOL2 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RL1 RL2 0.4 3 20 –3 – 20 5 –5 70 310 µA µA KΩ µA µA 14-3 ELECTRICAL DATA KS88C0716/P0716 Table 14-2. D.C. Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (2) Conditions VDD = 5 V ± 10% 12-MHz oscillation 4-MHz oscillation VDD = 3 V ± 10% 12-MHz oscillation 4-MHz oscillation Min – Typ 12 4.5 6 2.5 3 1.5 1.2 0.6 0.1 Max 25 10 15 7 10 4 3 1.5 3 Unit mA IDD2 (2) Idle mode; VDD = 5 V ± 10% 12-MHz oscillation 4-MHz oscillation Idle mode; VDD = 3 V ± 10% 12-MHz oscillation 4-MHz oscillation IDD3 Stop mode: VDD = 5 V ± 10% µA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. At supply current, the CPU clock frequency is same with oscillation frequency (CPU use non divided clock). Table 14-3. Data Retention Supply Voltage in Stop Mode (TA = – 40°C to + 85°C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 2.0 V Min 2 – Typ – – Max 6 3 Unit V µA NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull–up resistors and external output current loads. 14-4 KS88C0716/P0716 ELECTRICAL DATA Stop Mode Data Retention Mode Idle Mode (Oscillation Stabilzation Time) VDD ∼ ∼ ∼ ∼ VDDDR Execution of Stop Instruction EXT INT 0.8 V DD 0.2 V DD NOTE: t WAIT is the same as 16 x BT clock. t WAIT Normal Operating Mode Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt Reset Occurs Stop Mode Data Retention Mode Oscillation Stabilzation Time VDD ∼ ∼ ∼ ∼ VDDDR RESET Execution of Stop Instruction Normal Operating Mode NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. t WAIT Figure 14-2. Stop Mode Release Timing When Initiated by a Reset 14-5 ELECTRICAL DATA KS88C0716/P0716 Table 14-4. Input/Output Capacitance (TA = – 40°C to + 85°C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min – Typ – Max 10 Unit pF Table 14-5. A.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Interrupt input high, low width Symbol tINTH, tINTL tRSL Conditions P2.4–P2.7 P4.0–P4.7 RESET input low width Min 100 100 10 Typ – Max – Unit ns Input – – µs NOTE: User must keep the larger value with the min value. t INTL t INTH 0.8 V DD 0.2 V DD Figure 14-3. Input Timing for External Interrupts (Port 2 and 4) 14-6 KS88C0716/P0716 ELECTRICAL DATA t RSL RESET 0.2 V DD Figure 14-4. Input Timing for RESET Table 14-6. Oscillation Characteristics (TA = – 20°C + 85°C, VDD = 4.5 V to 5.5 V) Oscillator Crystal XIN C1 Clock Circuit Test Condition Oscillation frequency Min 1 Typ – Max 22.1184 Unit MHz C2 XOUT Ceramic XIN C1 Oscillation frequency 1 – 22.1184 MHz C2 XOUT External clock XIN XOUT XIN input frequency 1 – 22.1184 MHz 14-7 ELECTRICAL DATA KS88C0716/P0716 Table 14-7. Main Oscillator Clock Stabilization Time (tST1) (TA = – 20°C + 85°C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Ceramic Test Condition VDD = 4.5 V to 5.5 V Stabilization occurs when VDD is equal to the minimum oscillator voltage range. Min – – Typ – – Max 20 10 Unit ms ms NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released by a RESET signal. CPU clock 12 MHz 4 MHz 1 MHz 1 2 2.7 3 4 4.5 5 5.5 6 7 VDD Figure 14-5. Frequency vs. Voltage 14-8 KS88C0716/P0716 MECHANICAL DATA MECHA 15 OVERVIEW #64 17.00 ± 0.2 MECHANICAL DATA The KS88C0716 microcontroller is available in a 64-pin SDIP package (64-SDIP-750) and a 64-pin QFP package (64-QFP-1420F). #33 0−15 ° 19.05 #1 #32 57.80 ± 0.2 4.10 ± 0.2 (1.34) 1.00 ± 0.1 1.778 NOTE : Dimensions are in millimeters . Figure 15-1. 64-SDIP-750 Package Dimensions 0.51MIN 0.45 ± 0.1 3.30 ± 0.3 5.08MAX 58.20 MAX 0.25 +0.1 64-SDIP-75 0 – 0.05 15-1 MECHANICAL DATA KS88C0716/P0716 13.20 ± 0.3 10.00 ± 0.2 0-8° 0.15 - 0.05 +0.10 13.20 ± 0.3 10.00 ± 0.2 44-QFP-1010B 0.10 MAX #44 0.05 MIN 2.05 ± 0.10 #1 0.80 0.35 +0.10 - 0.05 (1.00) 2.30 MAX NOTE : Dimensions are in millimeters. Figure 15-2. 64-QFP-1420F Package Dimensions 15-2 0.80 ±0.20 KS88C0716/P0716 KS88P0716 OTP 16 OVERVIEW KS88P0716 OTP The KS88P0716 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS88C0716 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. KS88P0716 is fully compatible with KS88C0716, both in function and in pin configuration. As it has simple programming requirements, KS88P0716 is ideal for use as an evaluation chip for the KS88C0716. 16-1 KS88P0716 OTP KS88C0716/P0716 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P4.7/INT11 P4.6/INT10 P4.5/INT9 P4.4/INT8 P4.3/INT7 P4.2/INT6 SDATA / P4.1/INT5/TDG SCLK /P4.0/INT4/TCG VDD /V DD1 VSS/VSS1 XOUT XIN VPP/EA P5.6 P5.7 RESET / RESET P3.7/RxD P3.6/TxD P3.5/TB P3.4/TA P3.3 P3.2 P3.1/TDCK P3.0/TCCK P6.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 KS88P0716 64-SDIP (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P0.7/A15 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDD2 VSS2 P2.0/ AS P2.1/ DS P2.2/R/ W P2.3/ DM P2.4/INT0/ WAIT P2.5/INT1 P2.6/INT2 P2.7/INT3 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 Figure 16-1. KS88P0716 Pin Assignments (64-SDIP Package) 16-2 KS88C0716/P0716 KS88P0716 OTP P1.4/AD4 P1.3/AD3 P1.2/AD2 P1.1/AD1 P1.0/AD0 P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P4.7/INT11 P4.6/INT10 P4.5/INT9 P4.4/INT8 P4.3/INT7 P4.2/INT6 SDATA / P4.1/INT5/TDG SCLK /P4.0/INT4/TCG VDD /V DD1 VSS/V SS1 XOUT XIN VPP/EA P5.6 P5.7 RESET / RESET KS88P0716 64-QFP (Top View) P3.7/RxD P3.6/TxD P3.5/TB 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDD2 VSS2 P2.0/ AS P2.1/ DS P2.2/R/ W P2.3/ DM P2.4/INT0/ WAIT P2.5/INT1 P2.6/INT2 P2.7/INT3 Figure 16-2. KS88P0716 Pin Assignments (64-QFP Package) 32 31 30 29 28 27 26 25 24 23 22 21 20 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P3.0/TCCK P3.1/TDCK P3.2 P3.3 P3.4/TA 16-3 KS88P0716 OTP KS88C0716/P0716 Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P4.1 Pin Name SDAT Pin No. 14 (7) During Programming I/O I/O Function Serial Data Pin (Output when reading, Input when writing) Input and Push-pull Output Port can be assigned. Serial Clock Pin (Input Only Pin) EPROM Cell Writing Power Supply Pin (Indicates OTP Mode Entering) When writing 12.5V is applied and when reading 5 V is applied (Option). Chip Initialization Logic Power Supply Pin. VDD should be tied to 5V during programming. P4.0 EA SCLK VPP 15 (8) 20 (13) I I RESET RESET 23 (9) 16/17 (9/10) I I VDD1/VSS1 VDD/VSS NOTE: Parentheses indicate 64-QFP pin number. Table 16-2. Comparison of KS88P0716 and KS88C0716 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS88P0716 16 K byte EPROM 2.7 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5V 64 SDIP, 64 QFP User Program 1 time 64 SDIP, 64 QFP Programmed at the factory KS88C0716 16 K bytes mask ROM 2.7 V to 5.5V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of KS88P0716, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM ADDRESS (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read MODE 0 0 0 1 EPROM program EPROM verify EPROM read protection NOTE: "0" means Low level; "1" means High level. 16-4 KS88C0716/P0716 KS88P0716 OTP D.C. ELECTRICAL CHARACTERISTICS Table 16-4. D.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage VIL1 VIL2 Output High Voltage VOH1 Conditions All input pins except VIH2 XIN All input pins except VIL2 XIN VDD = 4.5 V to 5.5 V IOH = – 4 mA Port 5, 6 VDD = 4.5 V to 5.5 V IOH = – 1 mA All output pins except port 5, 6 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 5 and 6 IOL = 2 mA Ports 0 - 4 VDD – 1.0 Min 0.8 VDD VDD – 0.5 0.2 VDD 0.4 V V Typ Max VDD Unit V VOH2 VDD – 1.0 Output Low Voltage VOL1 1.0 V VOL2 0.4 16-5 KS88P0716 OTP KS88C0716/P0716 Table 16-4. D.C. Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 ILIH2 Input Low Leakage Current ILIL1 ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH ILOL RL1 RL2 Supply Current (1) IDD1 (2) Conditions VIN = VDD All input pins except XIN, XOUT VIN = VDD, XIN, XOUT VIN = 0 V All input pins except XIN, XOUT VIN = 0 V, XIN, XOUT VOUT = VDD All output pins VOUT = 0 V VIN = 0 V; VDD = 5 V Ports 0, 1, 4, 5 and 6 VIN = 0 V; VDD = 5 V RESET only VDD = 5 V ± 10% 12-MHz oscillation 4-MHz oscillation VDD = 3 V ± 10% 12-MHz oscillation 4-MHz oscillation IDD2 (2) Min – Typ – Max 3 20 Unit uA – – –3 – 20 uA – – 30 110 – – – 47 210 12 4.5 6 2.5 2.5 1.5 1.2 0.6 0.1 5 –5 70 310 25 10 15 7 6 4 3 1.5 3 uA uA KΩ mA Idle mode; VDD = 5 V ± 10% 12-MHz oscillation 4-MHz oscillation Idle mode; VDD = 3 V ± 10% 12-MHz oscillation 4-MHz oscillation IDD3 Stop mode: VDD = 5 V ± 10% uA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. At supply current, the CPU clock frequency is the same as oscillation frequency (CPU use non divided clock). 16-6 KS88C0716/P0716 KS88P0716 OTP START Address= First Location VDD =5V, V PP=12.5V x=0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte FAIL Last Address NO Increment Address VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 16-3. OTP Programming Algorithm 16-7 KS88P0716 OTP KS88C0716/P0716 NOTES 16-8