M312L2923BG0-A2

1GB, 2GB Registered DIMM DDR SDRAM DDR SDRAM Registered Module (60FBGA) 184pin Registered Module based on 512Mb B-die (x4, x8) with 1,200mil Height & 72-bit ECC Revision 1.1 August. 2003 Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Revision History Revision 1.0 (July, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. DDR SDRAM Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM 184Pin Registered DIMM based on 512Mb B-die FBGA (x4, x8) Ordering Information Part Number M312L2923BG0-CB3/A2/B0 M312L2920BG0-CB3/A2/B0 M312L5720BG0-CB3/A2/B0 Density 1GB 1GB 2GB Organization 128M x 72 128M x 72 256M x 72 DDR SDRAM Component Composition 64Mx8( K4H510838B) * 18EA 128Mx4( K4H510438B) * 18EA 128Mx4( K4H510438B) * 36EA Height 1,125mil 1,125mil 1,200mil Operating Frequencies B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3 Feature • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Pin Configuration (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS *CK2 */CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7 DDR SDRAM Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back /RAS DQ45 VDDQ /CS0 /CS1 DM5/DQS14 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 KEY VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 are NC for 1row module [M312L2920BG0] & used for 2row module [M312L2923BG0, M312L5720BG0 ] 3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module). Pin Description Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name DM0 ~ DM8 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power/Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM No connection Function Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM 1GB, 128M x 72 ECC Module (M312L2923BG0) (Populated as 2 bank of x8 DDR SDRAM Module) Functional Block Diagram RCS1 RCS0 DQS0 DM0 DM/ CS DQS DM/ CS DQS DQS4 DM4 DM/ CS DQS DM/ CS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D0 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D4 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D13 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D1 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D10 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D5 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D14 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D11 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D6 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D15 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D3 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D12 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D7 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D16 DM/ CS DQS DM/ CS DQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D8 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D17 Serial PD SCL WP A0 SA0 A1 SA1 A2 SDA VDDSPD VDD/VDDQ SPD D0 - D17 D0 - D17 VREF D0 - D17 D0 - D17 SA2 VSS CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK PCK R E G I S T E R RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE RESET BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 : DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE: DDR SDRAM D0 - D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM 1GB, 128M x 72 ECC Module (M312L2920BG0) (Populated as 1 bank of x4 DDR SDRAM Module) Functional Block Diagram VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS9 (DM0) DQ4 DQ5 DQ6 DQ7 D0 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D9 DQS1 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS10 (DM1) DQ12 DQ13 DQ14 DQ15 D1 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D10 DQS2 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS11 (DM2) DQ20 DQ21 DQ22 DQ23 D2 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D11 DQS3 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 D3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D12 DQS4 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS13 (DM4) DQ36 DQ37 DQ38 DQ39 D4 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D13 DQS5 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS14 (DM5) DQ44 DQ45 DQ46 DQ47 D5 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D14 DQS6 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS15 (DM6) DQ52 DQ53 DQ54 DQ55 D6 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM Serial PD SCL WP A0 A1 SA1 A2 SA2 SDA D15 DQS7 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS16 (DM7) DQ60 DQ61 DQ62 DQ63 D7 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM SA0 VDDSPD VDD/VDDQ D16 DQS8 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS17 (DM8) CB4 CB5 CB6 CB7 SPD D0 - D17 D0 - D17 D8 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D17 VREF VSS D0 - D17 D0 - D17 CS0 RCS0_1 R E G I S T E R RCS0_2 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0A RCKE0B RWE RESET BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 :DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE:DDR SDRAM D0 - D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM 2GB, 256M x 72 ECC Module [M312L5720BG0] (Populated as 2 bank of x4 DDR SDRAM Module) Functional Block Diagram VSS RCS1 RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS9 (DM0) DQ4 DQ5 DQ6 DQ7 D0 D18 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D9 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D27 DQS1 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS10 (DM1) DQ12 DQ13 DQ14 DQ15 D1 D19 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D10 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D28 DQS2 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS11 (DM2) DQ20 DQ21 DQ22 DQ23 D2 D20 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D11 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D29 DQS3 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 D21 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D12 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D30 DQS4 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D4 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS13 (DM4) DQ36 DQ37 DQ38 DQ39 D22 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D13 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D31 DQS5 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS14 (DM5) DQ44 DQ45 DQ46 DQ47 D5 D23 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D14 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D32 DQS6 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS15 (DM6) DQ52 DQ53 DQ54 DQ55 D6 D24 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D15 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D33 DQS7 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D7 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS16 (DM7) DQ60 DQ61 DQ62 DQ63 D25 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D16 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D34 DQS8 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D8 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS17 (DM8) CB4 CB5 CB6 CB7 D26 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D17 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D35 Serial PD SCL WP A0 SA0 CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK PCK VDDSPD VDD/VDDQ SDA A2 SA2 SPD D0 - D35 D0 - D35 A1 SA1 VREF VSS D0 - D35 D0 - D35 R E G I S T E R RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE RAS: BA0-BA1: DDR SDRAM D0 - D35 A0-A12: DDR SDRAM D0 - D35 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams DDR SDRAM D0 - D35 CAS: DDR SDRAM D0 - D35 CKE: DDR SDRAM D0 - D17 CKE: WE: DDR SDRAM D18 - D35 DDR SDRAM D0 - D35 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. RESET Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD,VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 * # of component 50 DDR SDRAM Unit V V °C W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Power & DC Operating Conditions (SSTL_2 In/Out) Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C) Parameter Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V Symbol VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 VDDQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 2 5 V V V V V V V uA uA mA mA mA mA 3 1 2 4 4 Unit Note Notes : 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM IDD spec table M312L2923BG0 [ (64M x 8) * 18 , 1GB Module ] DDR SDRAM (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3 (DDR333@CL=2.5) 2,450 2,680 590 1,420 950 1,040 1,780 2,810 3,040 3,580 590 560 4,930 A2 (DDR266@CL=2) 2,190 2,370 540 1,290 810 990 1,650 2,420 2,550 3,360 540 510 4,170 B0 (DDR266@CL=2.5) 2,190 2,370 540 1,290 810 990 1,650 2,420 2,550 3,360 540 510 4,170 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M312L2920BG0 [ (128M x 4) * 18 , 1GB Module ] (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3 (DDR333@CL=2.5) 3,000 3,450 470 1,290 830 920 1,650 3,720 4,170 5,250 670 430 7,950 A2 (DDR266@CL=2) 2,610 2,970 420 1,170 690 870 1,530 3,060 3,330 4,950 420 380 6,570 B0 (DDR266@CL=2.5) 2,610 2,970 420 1,170 690 870 1,530 3,060 3,330 4,950 420 380 6,570 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM IDD spec table M312L5720BG0 [ (128M x 4) * 36, 2GB Module ] DDR SDRAM (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3 (DDR333@CL=2.5) 4,030 4,480 680 1,960 1,400 1,580 2,680 4,750 5,200 6,280 680 610 8,980 A2 (DDR266@CL=2) 3,630 3,990 630 1,830 1,170 1,530 2,550 4,080 4,350 5,970 630 560 7,590 B0 (DDR266@CL=2.5) 3,630 3,990 630 1,830 1,170 1,530 2,550 4,080 4,350 5,970 630 560 7,590 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 Max DDR SDRAM Unit V V V V Note 3 3 1 2 0.5*VDDQ+0.2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output Capacitance Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK0 ) Input capacitance(DM0~DM8) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 Min 9 9 9 11 10 10 10 (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz) M312L2920BG0 Max 11 11 11 12 11 11 11 pF pF pF pF pF pF pF Unit Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0,CKE1) Input capacitance( CS0, CS1) Input capacitance( CLK0, CLK0 ) Input capacitance(DM0~DM8) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 M312L2923BG0, M312L5720BG0 Min 9 9 9 11 13 13 13 Max 11 11 11 12 15 15 15 Unit pF pF pF pF pF pF pF Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active Write recovery time Last data in to Read command Col. address to Col. address Clock cycle time CL=2.0 CL=2.5 DDR SDRAM Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRE tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR B3 (DDR333@CL=2.5)) Min 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 +0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.4 1.1 0.6 1.25 70K A2 (DDR266@CL=2) Min 65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 +0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K B0 (DDR266@CL=2.5) Min 65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 +0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K Max Max Max Uni Note t ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ V/ ns V/ i,5.7~ i,5.7~ i, 6~9 i, 6~9 1 1 3 12 Clock high level width Clock low level width DQS-out access time from Output data access time Data strobe edge to ouput Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK risDQS falling edge from CK DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input Address and Control Input Address and Control Input Address and Control Input Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM A2 (DDR266@CL=2) Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input DQ & DM input pulse width Power down exit time Exit self refresh to non-Read Symbol tMRD tDS tDH tIPW tDIPW tPDEX tXSNR B3 (DDR333@CL=2.5)) Min 12 0.45 0.45 2.2 1.75 6 75 200 B0 (DDR266@CL=2.5) Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 0.75 0.6 Unit Note ns ns ns ns ns ns ns tCK us ns ns ns tCK 4 11 10, 11 11 2 j, k j, k 8 8 Max Max Max Exit self refresh to read com- tXSRD Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tREFI tQH tHP tQHS tWPST tRAP tHP -tQHS tCLmin or tCHmin 0.5 0.4 18 (tWR/tCK) + (tRP/tCK) 0.6 tDAL tCK 13 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD DDR200 MIN 0.5 MAX 4.0 Units V/ns Notes a, m Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes i i i Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes k k k Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps ps Notes j j j DDR SDRAM Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Notes e,m Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. DDR SDRAM Test point Output 50Ω VSSQ Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. VDDQ 50Ω Output Test point Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotony. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H H L H CKEn X X H L H X CS L L L L H L RAS L L L H X L DDR SDRAM (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) CAS L L L H X H WE BA0,1 A10/AP L L H H X H V A0 ~ A9 A11, A12 Note 1, 2 1, 2 3 3 3 3 OP CODE OP CODE X X Row Address (A0~A9, A11,A12) L H L H X V X L H X X Column Address Column Address Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable H H H H H L H L H H X X X X L H L H L L L L H L X H L H L H L H H H L X V X X H X V X X H L L H H X V X X H X V X H H L L L X V X X H X V V V 4 4 4 4, 6 7 5 Active Power Down X X X H X 8 9 9 X Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM DDR SDRAM Physical Dimensions: 128Mx72 (M312L2923BG0), (M312L2920BG0) Units : Millimeters 133.35 A 128.95 A 2x 3.00 MIN W1 4x 4.00+/-0.1 V1 12.00 Tolerances : ± 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838B-G***, K4H510438B-G*** 28.575 +/-0.15 B 19.80 B1 10.00 B2 1 a 64.77 P2 120.65 P1 49.53 P3 b 92 6.35 3.99 MAX 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 0.20 +/-0.15 T 2.50 G 3.80 W V 1.80 MAX 0.178 D1 E 1.27 Detail A Detail B Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Physical Dimensions: 256Mx72 (M312L5720BG0) DDR SDRAM Units : Millimeters 133.35 A 128.95 A 2x 3.00 MIN W1 12.0 4x 4.00+/-0.1 V1 19.80 B1 Tolerances : ± 0.005(.13) unless otherwise specified The used device is 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No : K4H510438B-G*** 30.48 +/-0.15 B 10.0 10.00 B2 1 a 64.77 P2 120.65 P1 49.53 P3 b 92 3.99 MAX 6.35 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 0.20 +/-0.15 T 2.50 G 3.80 W V 1.80 MAX 0.178 D1 E 1.27 Detail A Detail B Rev. 1.1 August. 2003