S1T8531

WIDEBAND FM/FSK IF RECEIVER S1T8531 INTRODUCTION 16-SOP-225 The S1T8531 is a wideband FM / FSK receiver designed for wideband FSK data and analog FM applications. It is fabricated using Samsung’s ASP5HB 0.5um advanced BiCMOS process. The S1T8531 contains high gain IF amplifier with received signal strength indicator (RSSI), a wideband FM quadrature demodulator, a baseband filter amplifier and a high speed data slicer with sample & hold function. The IF amplifier has 100dB small signal gain and 2MHz through 40MHz bandwidth. The wideband FM quadrature demodulator has demodulation bandwidth greater than 1MHz. The baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter. The data slicer is a comparator that is designed to square up the data signal with data rates up to 2Mbps. FEATURES • • • • • • • Operating voltage range Typical supply current : 2.2 to 5.5V : 5.5mA at 3.6V Operating frequency range : 2MHz to 40MHz High Gain (100dB) and Wideband (2MHz to 40MHz) IF Amplifier Quadrature Demodulator with Greater than 1MHz Bandwidth High Speed Data Slicer Operating Upto 2Mbps with Sample & Hold RSSI Dynmic range : Typ : 60dB APPLICATION • Wideband FM / FSK Wireless Communication Systems ORDERING INFORMATION Device +S1T8531X01-S0B0 + : New Product Package 16-SOP-225 Operating Temperature - 10°C to + 70°C 1 S1T8531 WIDEBAND FM/FSK IF RECEIVER BLOCK DIAGRAM IFIN 16 IFIP 15 GND2 14 SHEN 13 RSSI 12 DSO 11 SHO 10 DSIN 9 Sample Hold A RSSI 5pF 1 1 2 3 4 5 6 7 8 GND1 VCC1 QIN VCC2 QOUT BIN BOUT DSIP PIN CONFIGURATION GND1 VCC1 QIN VCC2 QOUT BIN BOUT DSIP 1 2 3 4 16 15 14 13 IFIN IFIP GND2 SHEN RSSI DSO SHO DSIN S1T8531 5 6 7 8 12 11 10 9 2 WIDEBAND FM/FSK IF RECEIVER S1T8531 PIN DESCRIPTION Pin 1 2 3 Name GND1 VCC1 QIN VCC 3 Schematic Description Ground. (Pin1 and Pin14 are connected internally) Supply. (Pin2 and Pin4 are connected internally) Quadrature demodulator tank input. 4 5 VCC2 QOUT VCC Supply. (Pin2 and Pin4 are connected internally) Quadrature demodulator output. 5 6 7 BIN BOUT VCC Baseband filter buffer amplifier input. Baseband filter buffer amplifier output. 6 7 8 9 DSIP DSIN 8 VCC Data slicer positive input. Data slicer negative input. 9 3 S1T8531 WIDEBAND FM/FSK IF RECEIVER PIN DESCRIPTION (Continued) Pin 10 Name SHO Schematic Description Sample and hold output. 7 11 DSO VCC 11 Data slicer output. 12 RSSI VCC RSSI output. 12 13 SHEN VCC Sample and hold enable input. High signal input enable sample and hold function and low signal input disable sample and hold function . 13 14 15 16 GND2 IFIP IFIN Ground. (Pin1 and Pin14 are connected internally) IF amplifier differential inputs. DC blocking is required. VCC 15 16 4 WIDEBAND FM/FSK IF RECEIVER S1T8531 ABSOLUTE MAXIMUM RATINGS Characteristic Maximum Supply Voltage Operating temperature Storage Temperature Symbol VCC Ta TSTG Value 6 -10 to + 70 -55 to + 150 Unit V °C °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Voltage applied to any pin Symbol VCC VIN Value 2.2 to 5.5 - 0.3 to Vcc + 5.5 Unit V V 5 S1T8531 WIDEBAND FM/FSK IF RECEIVER ELECTRICAL CHARACTERISTICS ( Vcc = 3.6V, IF = 10.7MHz, fdev = ± 75kHz, fmod = 10kHz,Ta = 25°C, IFin = -47dBm unless otherwise noted. ) Characteristic Current consumption IF Input Frequency 20dB SINAD Sensitivity (Note 2) IF Amplifire Bandwidth (Note 1) IF Amplifier Voltage Gain (Note 1) IF Amplifier Input Impedance (Note 1) Quadrature Demodulator Output Voltage Demodulator Bandwidth (Notes 1 and 2) Baseband Filter Buffer Amplifier Bandwidth Baseband Filter Buffer Amplifier Voltage Gain Data Slicer Maximum Operating Frequency (Notes 1 and 2) RSSI Dynamic Range RSSI Output Level Symbol Icc IFfreq VSEN BWIF ∆G IF RIIIF Vo(DEM) BWDEM BWAMP DG AMP BWDS RSSI Vo(RSSI) Test Condition Min 2 2 95 100 0.6 1 -3 1 50 0.5 Typ 5.5 10.7 -95 101 1.5 150 1 2 0 2 60 Max 7.0 40 -81 40 200 +3 2.0 Unit mA MHz dBm MHz dB kΩ mVrms MHz MHz dB Mbps dB V NOTES: 1. Not 100% AC tested but guaranteed by design and characterization. 2. Measured result on evaluation board with proper impedance matching. 6 WIDEBAND FM/FSK IF RECEIVER S1T8531 FUNCTIONAL DESCRIPTION General The S1T8531 is a wideband FM / FSK receiver designed for use in analog FM and digital FSK systems such as 900MHz / 2.4GHz ISM band analog / digital cordless phones and wideband data links with data rates up to 2Mbps. It contains IF amplifier, quadrature detector, baseband filter amplifier and data slicer with sample and hold function. IF Amplifier The IF amplifier section is composed of seven differential stage with total gain of 100dB at 10.7MHz. The input impedance at 10.7MHz is 1.5kΩ. For 10.7MHz ceramic filter applications, an external 430Ω resistor must be placed between IFP(Pin15) and IFN(pin16) to provide the equivalent load impedance of 330Ω that is required by the filter. Quadrature Demodulator The quadrature demodulator requires tank circuit with loaded Q depending on detection bandwidth. Following figure shows external components required for 10.7MHz operation. QUAD IN QUAD OUT 3 47pF 4.255uH Rdamp VCC 5 Baseband Filter Buffer Amplifier3 Baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter. Following figure shows the external components required. Cutoff frequency = 1 / [2π*SQRT(R1R2C1C2)] Quality factor = SQRT(R1R2C1C2) / (R1C2 + R2C2) The component value of R1 should contain the quadrature detector output resistance. C1 Vout Vin R1 R2 C2 6 BUF IN 7 BUF OUT 7 S1T8531 WIDEBAND FM/FSK IF RECEIVER Data Slicer with Sample and Hold The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the baseband filter output can be DC coupled to the data slicer DS-INP(Pin 9). The S1T8531’s data slicer incorporates an sample and hold used to derive the data slicer reference voltage by means of an external integration circuit. The sample and hold is “ON“ during reception of the preamble data pattern, and is otherwise “OFF“ in TDD (Time Division Duplex) system. The external integration circuit is formed by an RC low pass circuit placed between SHO (Pin 10) and ground. The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift close to the threshold voltage, the time constant is longer. ‘The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the settling time. When the sample and hold is “OFF“ the output (SHO) is in high impedance state with extremely low leakage current. ‘Following figure shows the internal block diagram. DS INP DS INN SHO SHEN 8 11 DS OUT 9 10 13 +1 The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommeded that an external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of ground and supply currents in the S1T8531 which might desensitize the chip. The data slicer can be used as a carrier detector also. Following figure shows application example. In this case, sample and hold should be off. 8 9 11 12 RSSI Reference Voltage Carrier Detect 8 WIDEBAND FM/FSK IF RECEIVER S1T8531 TEST CIRCUIT VCC IF Input 50Ω 10n 16 Data RSSI Output 1u 100n 100n 1n 14 13 12 11 10n 15 1.8kΩ 10 9 IFN IFP GND SHEN RSSI DSO SHO DSIN S1T8531 GND VCC 1 2 QIN 3 VCC QOUT BIN BOUT DSIP 4 5 6 7 8 1n 39kΩ 100n VCC 20kΩ 20kΩ 15kΩ 68p 100p Audio Output 9 S1T8531 WIDEBAND FM/FSK IF RECEIVER APPLICATION CIRCOUT IF2 BNC VCC Sample &hold diable C18 100n T2 10.7MHz C17 10nF C16 120p R12 56K Sample &hold enable R14 0 R13 0 1 R15 330 C19 56p VCC2 TP5 RSSI TP4 DSOUT VCC2 C13 100n 1 R11 10K C15 10nF C14 10nF 15 14 13 12 11 10 9 R10 1.8K R16 10K 1 C20 10n 16 C10 C11 C12 1u 3.3n 56p IFN IFIP GND2 SHEN RSSI DSO SHO DSIN S1T8531 GND1 VCC1 QIN GND 1 VCC2 QOUT BIN BOUT DSIP 4 5 6 7 8 R8 1 1 VCC1 2 3 POWER C1 3.3n C2 56p 51 *C7 68p *C8 100p R9 5.6K 1 TP2 BUFOUT R1 51 VCC2 L1 CX1 CX1 R2 R7 39K R6 15K Quad. coil C3 3.3nF VCC 1 *C9 4.7n AUDIOOUT TP3 1 C4 56p VCC1 C5 100n C6 56p R3 51 TP1 QUADOUT R5 20K R4 20K POWER VCC * Changable value for each application C7 68p 100p C8 100p 220p C9 4.7n 820p * Quadrature Coil L1 360u 2.7u VCC2 Analog Digital Quad. coil Ext. coil CX1 120p 56p CV1 N/A 1-3p R2 7.5K 2.4K 10