LB1987H

Ordering number : ENN6109A Monolithic Digital IC LB1987, 1987D, 1987M, 1987H Three-Phase Brushless Motor Driver for VCR Capstan Motors Overview The LB1987, LB1987D, LB1987M, and LB1987H are optimal capstan motor drivers for use in VCR sets. 3147B-DIP28H [LB1987D] 28 15 Functions • Three-phase full-wave current-linear drive • Torque ripple correction circuit (fixed correction ratio) • Current limiter circuit with control characteristics gain switching • Oversaturation prevention circuits for both the upper and lower sides of the output stage (No external capacitors are required.) • FG amplifier • Thermal shutdown circuit R1.7 12.7 11.2 8.4 1 20.0 27.0 14 1.93 1.78 0.6 1.0 4.0 4.0 SANYO: DIP28H 3129-MFP36S-LF [LB1987M] 36 19 Package Dimensions 3240-QFP34H-B 15.3 2.25 2.5max 9.2 10.5 7.9 unit: mm 1.6 1.6 23 13.2 10.0 4.8 0.8 18 17 1.0 1.0 0.4 0.8 0.85 0.1 0.2 SANYO: MFP36S-LF 24 13.2 10.0 0.8 0.35 8.4 3233-HSOP28H [LB1987H] 15.3 0.65 6.2 2.7 34 7 1 6 28 15 0.1 1.0 4.0 2.2 1 0.85 0.8 0.3 14 0.25 1.3 2.5max 2.25 SANYO: HSOP28H Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 81299RM (OT) No. 6109-1/17 0.1 10.5 7.9 4.9 SANYO: QFP34H-B 0.65 [LB1987] 1 18 0.25 0.4 LB1987, 1987D, 1987M, 1987H Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Maximum output current Symbol VCC max VS max IO max (LB1987) Allowable power dissipation Pd max (LB1987D) (LB1987M) (LB1987H) Operating temperature Storage temperature Topr Tstg Conditions Ratings 7 24 1.3 0.77 3.0 0.95 0.77 –20 to +75 –55 to +150 Unit V V A W W W W °C °C Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage Hall input amplitude GSENSE pin input range Symbol VS VCC VHALL VGSENSE Between Hall inputs Relative to the control system ground Conditions Ratings 5 to 22 4.5 to 5.5 ±30 to ±80 –0.20 to +0.20 Unit V V mVo-p V Electrical Characteristics at Ta = 25°C, VCC = 5 V, VS = 15 V Parameter VCC current drain [Outputs] Vosat1 Output saturation voltage Vosat2 Output leakage current [FR] FR pin input threshold voltage FR pin input bias current [Control] CTLREF pin voltage CTLREF pin input range CTL pin input bias current CTL pin control start voltage CTL pin control switching voltage CTL pin control Gm1 CTL pin control Gm2 [Current Limiter] LIM current limiter offset voltage LIM pin input bias current LIM pin current limit level [Hall Amplifiers] Input offset voltage Input bias current Common-mode input voltage Torque ripple correction ratio [FG Amplifier] FG amplifier input offset voltage FG amplifier input bias current Voff(FG) Ib(FG) –8 –100 0.5 0.5 4.0 +8 mV nA V V Voff(HALL) Ib(HALL) Vcm(HALL) TRC At the bottom and top of the Rf waveform when IO = 200 mA. (Rf = 0.5 Ω) (Note 1) 1.3 9 –6 1.0 +6 3.0 3.3 mV µA V % Voff(LIM) Ib(LIM) ILIM Rf = 0.5 Ω, VCTL = 5 V, IO ≥ 10 mA With the Hall input logic states fixed at (U, V, W = H, H, L) VCTL = 5 V, VCREF: open, VLIM = 0 V Rf = 0.5 Ω, VCTL = 5 V, VLIM = 2.06 V With the Hall input logic states fixed at (U, V, W = H, H, L) 140 –2.5 830 900 970 200 260 mV µA mA VCREF VCREFIN Ib(CTL) VCTL(ST) VCTL = 5 V, CTLREF: open Rf = 0.5 Ω, VLIM = 5 V, IO ≥ 10 mA With the Hall input logic states fixed at (U, V, W = H, H, L) 2.20 3.00 0.52 1.20 2.35 3.15 0.65 1.50 2.37 1.70 2.50 2.63 3.50 8.0 2.50 3.30 0.78 1.80 V V µA V V A/V A/V VFSR Ib(FSR) 2.25 –5.0 2.50 2.75 V µA IOleak IO = 500 mA, Rf = 0.5 Ω, Sink + Source, VCTL = VLIM = 5 V (With saturation prevention) IO = 1.0 A, Rf = 0.5 Ω, Sink + Source, VCTL = VLIM = 5 V (With saturation prevention) 2.1 2.6 2.6 3.5 1.0 V V mA Symbol ICC Conditions RL = ∞, VCTL = 0 V (Quiescent) Ratings min typ 12 max 18 Unit mA VCTL(ST2) Rf = 0.5 Ω, VLIM = 5 V Rf = 0.5 Ω, ∆IO = 200 mA Gm1(CTL) With the Hall input logic states fixed at (U, V, W = H, H, L) Gm2(CTL) Rf = 0.5 Ω, ∆VCTL = 200 mV With the Hall input logic states fixed at (U, V, W = H, H, L) FG amplifier output saturation voltage Vosat(FG) At the sink side internal pull-up resistor. FG amplifier common-mode input voltage VCM(FG) Continued on next page. No. 6109-2/17 LB1987, 1987D, 1987M, 1987H Continued from preceding page. Parameter [Saturation Prevention] Saturation prevention circuit lower side voltage setting [Schmitt Amplifier] Duty ratio DUTY Under the specified conditions 47 4.8 0.2 32 * 50 170 60 50 53 % V V mV °C Vosat(DET) IO = 10 mA, Rf = 0.5 Ω, VCTL = LVIM = 5 V, The voltage between each OUT and Rf. 0.175 0.25 0.325 V Symbol Conditions Ratings min typ max Unit Upper side output saturation voltage Vsatu(SH) Lower side output saturation voltage Vsatd(SH) Hysteresis Thermal shutdown operating temperature Vhys T-TSD Note: * Items marked with an asterisk are design target values and are not measured. Note: 1. The torque ripple correction ratio is determined from the Rf voltage waveform as shown below. Vp Vb 1 2 3 4 5 6 Hall Logic Settings GND level 2 · (Vp – Vb) Correction ratio = ——————— 100 · (%) Vp + Vb A12204 Truth Table and Control Functions Source → sink 1 V→W W→V U→W W→U U→V V→U W→V V→W W→U U→W V→U U→V Hall input U H V H W L FR H L H L H L H L H L H L 3. Since this drive technique is a 180° power application technique, the phase that is neither the source phase nor the sink phase does not turn completely off. Note: 1. The “H” state for FR means a voltage of 2.75 V or higher, and the “L” state means a voltage of 2.25 V or lower. (When VCC = 5 V.) 2. For the Hall inputs, the input “H” state means the state in which the (+) input for that phase is at least 0.01 V higher than the (–) input for that phase. Similarly, the “L” state means the state in which the (+) input for that phase is at least 0.01 V lower than the (–) input for that phase. 2 H L L 3 H L H 4 L L H 5 L H H 6 L H L No. 6109-3/17 LB1987, 1987D, 1987M, 1987H Control and Current Limiting Functions Control characteristics VLIM = = V V VLIM 5 5 CTLREF: open CTLREF: OPEN Current limiting characteristics VCTL = = V V VCTL 5 5 CTLREF: open CTLREF: OPEN IOUT Gm2 = 1.50 A/V typ Gm2 = 1.50 A/Vtyp Gm1 == 0.65 A/Vtyp Gm1 0.65 A/V typ IOUT Slope = 0.50 A/V typ 0 1 2 3 4 5 0 200 mV typ 200 mVtyp 1 2 3 VLIM 4 5 VCTL 2.35 V typ 3.15 V typ 2.35 Vtyp 3.15 Vtyp Pin Functions Pin UIN+ UIN– Function U phase Hall element input. Logic H refers to the state where IN+ > IN– (+) inputs VIN+ VIN– V phase Hall element input. Logic H refers to the state where IN+ > IN– 200 Ω 100 µA Equivalent circuit diagram (–) inputs 200 Ω WIN+ WIN– UOUT VOUT WOUT VS W phase Hall element input. Logic H refers to the state where IN+ > IN– U phase output. V phase output. W phase output. A12207 (These pins include internal spark killer diodes.) Vs VCC Output block power supply. OUT for each phase 150 µA Output current detection. Current feedback is applied to the control block by inserting the resistor Rf between these pins and ground. Also, both the lower side saturation Rf(POWER) prevention circuit and the torque ripple correction circuit operate according to Rf(SENSE) the voltage on this pin. In particular, since this voltage sets the oversaturation prevention level, the lower side oversaturation prevention operation can be degraded if the value of this resistor is set too low. Note that the PWR pin and the SENSE pin must be connected together. Speed control. This circuit implements constant current drive based on current feedback from the Rf pin. Gm = 0.58 A/V typ at Rf = 0.5 Ω CTL 200 Ω 30 kΩ Lower side oversaturation prevention circuit input block V CC 10 µA 200 kΩ Rf(POWER) Rf(SENSE) A12208 CTL VCC VCC 5 kΩ VCC 200 µA max LIM 200 Ω 100 µA CTLREF (LB1987/D) 5 kΩ LIM Current limiter function control. The output current can be modified linearly by the voltage on this pin. Slope = 0.5 A/V typ at Rf = 0.5 Ω CTLREF 200 Ω 200 Ω A12209 Continued on next page. No. 6109-4/17 LB1987, 1987D, 1987M, 1987H Continued from preceding page. Pin Function Forward/reverse selection. The direction (forward or reverse) is selected by the voltage applied to this pin. (Vth = 2.5 Vtyp at VCC = 5 V) External torque ripple correction ratio adjustment. To adjust the correction ratio, apply the stipulated voltage to the ADJ pin from a low-impedance external circuit. If the applied voltage is increased, the correction ratio falls, and if the applied voltage is lowered, the correction ratio increases. The range of variation is from 0 to two times the correction ratio when the pin is left open. (This pin is set to about VCC/2 internally, and has an input impedance of about 5 kΩ.) Input used when the FG amplifier inverting input is used. Connect a feedback resistor between the FGOUT pin and this pin. FGin(–) FR 200 Ω 1/2 VCC Equivalent circuit diagram FR VCC VCC VCC 20 µA VCC ADJ 10 kΩ ADJ 10 kΩ A12210 FGIN– 5 µA FGin(+) 300 Ω FGIN+ Non-inverting input used when the FG amplifier is used as a differential input amplifier. No bias is applied internally. VCC 300 Ω A12211 VCC VCC 10 kΩ 2 kΩ FGOUT FG amplifier output. This pin includes an internal load resistor. FGOUT 300 Ω 100 Ω 10 kΩ FC FC Speed control loop frequency characteristics correction. A12212 GND Ground for all systems other than the output transistors. Note that the lowest potential of the output transistors is determined by the Rf pin. VCC 10 kΩ VCC VCC 5 kΩ FGS FGS FG pulse output. This pin includes an internal load resistor. (The output impedance is about 3 kΩ.) A12517 VCC Power supply for all IC internal circuits other than the output block. This power supply must be stabilized to prevent ripple or other noise from entering the circuit. Ground sensing. The influence of the common ground impedance on Rf can be excluded by connecting this pin to ground near the Rf resistor side of the motor ground wiring that includes Rf. (This pin must not be left open.) GSENSE 13.2 kΩ GSENSE A12518 No. 6109-5/17 10 kΩ 6 kΩ 500 Ω 6 kΩ 10 kΩ 200 µA LB1987, 1987D, 1987M, 1987H Pin Assignment FRAME FRAME WIN– 18 17 WIN+ 16 VIN– 15 VIN+ 14 UIN– 13 UIN+ 12 FC 11 LIM 10 CTLREF 9 8 7 CTL FGS FGOUT 6 FGIN+ GND 23 22 21 20 19 RF(PWR) 24 25 26 UOUT 27 28 VOUT 29 30 WOUT 31 32 RF(SENSE) 33 GSENSE 34 LB1987 1 FR 2 GND 3 FRAME 4 FRAME FGIN– VCC 5 Vs Top view A12217 Note: The FRAME pins must be connected to ground for ground potential stabilization. Pd max — Ta Allowable power dissipation, Pdmax — W 1.0 0.8 0.77 W 0.6 0.4 0.46 W 0.2 0 –20 0 20 40 60 80 100 Ambient temperature, Ta — °C No. 6109-6/17 LB1987, 1987D, 1987M, 1987H Pin Assignment RF(SENSE) RF(PWR) GSENSE WOUT FGIN– UOUT VOUT GND GND 16 13 WIN– 28 27 26 25 24 23 22 21 20 19 18 17 15 LB1987D 1 FGIN+ 2 FGOUT 3 FGS 4 CTL 5 CTLREF 6 LIM 7 FC 8 UIN+ 9 UIN– 10 VIN+ 11 VIN– 12 WIN+ 14 VCC VS FR Top view A12214 Pd max — Ta 3.5 Allowable power dissipation, Pdmax — W 3.0 W 3.0 2.5 2.0 1.8 W 1.5 1.0 0.5 0 –20 0 20 40 60 80 100 Ambient temperature, Ta — °C No. 6109-7/17 LB1987, 1987D, 1987M, 1987H Pin Assignment RF(SENSE) RF(PWR) GSENSE FRAME FRAME FRAME 20 17 FRAME 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 19 LB1987M 1 FRAME 2 FRAME 3 FGIN– 4 FGIN+ 5 FGOUT 6 FGS 7 CTL 8 LIM 9 FC 10 UIN+ 11 UIN– 12 VIN+ 13 VIN– 14 WIN+ 15 WIN– 16 VCC 18 FRAME FRAME WOUT UOUT VOUT GND GND NC NC NC NC VS FR Top view A12216 Note: Although the FRAME pins and the GND pin are not connected internally in the IC, the FRAME pins must be connected to the GND pin externally for ground potential stabilization. Pd max — Ta 1.2 Allowable power dissipation, Pdmax — W 1.0 0.95 W 0.8 0.6 0.57 W 0.4 0.2 0 –20 0 20 40 60 80 100 Ambient temperature, Ta — °C No. 6109-8/17 LB1987, 1987D, 1987M, 1987H Pin Assignment FRAME GND RF(PWR) UOUT VOUT WIN+ WIN– 28 27 26 25 24 23 22 21 20 19 18 17 16 LB1987H 1 WOUT 2 NC 3 NC 4 RF(SENSE) 5 GSENSE 6 FR 7 GND FRAME GND 8 FGIN– 9 FGIN+ 10 FGOUT 11 FGS 12 CTL 13 LIM FC Top view A12215 Pd max — Ta 1.0 Allowable power dissipation, Pdmax — W 0.8 0.77 W 0.6 0.46 W 0.4 0.2 0 –20 0 20 40 60 80 100 Ambient temperature, Ta — °C UIN+ 15 14 UIN– VIN+ VIN– GND VCC NC NC VS No. 6109-9/17 FC VS Block Diagram UIN+ UIN– VIN+ VIN– Inverse logarithmic conversion and differential distribution WIN+ Synthesized output logarithmic compression WIN– FR CTLREF LB1987, 1987D, 1987M, 1987H CTL + + – + – LIMREF Feedback amplifier Control amplifier 2 LIM TSD Bandgap 1.2 V FG amplifier VCC Reference voltage No. 6109-10/17 RF(SENSE) FGIN+ FGIN– – + + – + + + – – + UOUT VOUT WOUT Hall input synthesis block (Linear matrix) + – Differential distribution and torque ripple correction block Upper side saturation prevention control + – + Drive distribution circuit and lower side saturation prevention control – – Forward/ reverse selection RF(PWR) Control amplifier 1 + Schmitt amplifier 5 kΩ – + FGOUT FGS A12213 Forward/reverse command applied pin 0.1 µF 0.5 Ω 0.1 µF 0.1 µF Power system ground We recommend the use of GaAs devices as Hall element. 34 33 32 31 30 29 28 27 26 25 24 1 2 3 21 22 23 Ground Hall output Hall output Sample Application Circuit (LB1987) L Vs L L LB1987 The Hall bias resistor R must be selected according to the sensor output. Hall output R 0.1 µF 5 6 39 kΩ 39 kΩ 4 20 19 18 7 8 9 10 11 12 13 14 15 16 17 0.1 µF Hall input Current limiter setting voltage applied pin CTLREF voltage applied pin LB1987, 1987D, 1987M, 1987H MR VCC FG output Bias of VCC/2 Torque command voltage applied pin A12218 No. 6109-11/17 Note: The component values shown in this application circuit example are merely provided as examples, and circuit operating characteristics are not guaranteed. Forward/reverse command applied pin 0.1 µF 0.1 µF 0.5 Ω Ground Power system ground 0.1 µF 0.1 µF Vs We recommend the use of GaAs devices as Hall element. Hall output Hall output 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R Sample Application Circuit (LB1987D) L L L LB1987D 39 kΩ 39 kΩ 1 0.1 µF 2 3 4 5 6 7 8 9 10 11 12 13 14 The Hall bias resistor R must be selected according to the sensor output. R Hall output VCC Hall input Current limiter setting voltage applied pin CTLREF voltage applied pin Torque command voltage applied pin LB1987, 1987D, 1987M, 1987H MR FG output A122219 Bias of VCC/2 No. 6109-12/17 Note: The component values shown in this application circuit example are merely provided as examples, and circuit operating characteristics are not guaranteed. VCC We recommend the use of GaAs devices as Hall element. Forward/reverse command applied pin Hall output Hall output Power system ground L 0.1 µF 0.1 µF L L Ground Hall output Sample Application Circuit (LB1987M) R 0.1 µF Vs 36 NC FR NC NC NC VOUT GND UOUT WOUT RF(SENSE) FRAME FRAME GSENSE RF(PWR) 35 34 33 32 31 30 29 28 27 26 25 24 23 22 GND 21 VS 20 FRAME 19 FRAME LB1987M FC FRAME WIN– VIN+ LIM VIN– FRAME WIN+ UIN+ VCC UIN– CTL FRAME FGOUT FGS FGIN+ FGIN– 2 3 4 5 6 7 8 9 10 11 LB1987, 1987D, 1987M, 1987H FRAME 1 12 13 14 15 16 17 18 Hall input Supply voltage 39 kΩ 39 kΩ Current limiter setting voltage applied pin Torque command voltage applied pin Bias of VCC/2 FG pulse output A12220 VCC 0.1 µF MR pin MR No. 6109-13/17 VCC We recommend the use of GaAs devices as Hall element. Hall output Hall output 0.5 Ω 0.1 µF 0.1 µF Vs Power system ground L L L Hall output Sample Application Circuit (LB1987H) R 0.1 µF Hall input VCC 28 VS RF NC WIN+ GND GND WIN– NC VCC FRAME VOUT UOUT 27 26 25 24 23 22 21 20 19 18 VIN– 17 VIN+ 16 UIN– 15 UIN+ LB1987, 1987D, 1987M, 1987H LB1987H GND GSENSE GND NC RF FR LIM FGIN+ FGIN– NC 2 3 4 5 6 7 VCC MR 0.1 µF FC FRAME FGOUT WOUT 1 CTL FGS 8 9 10 11 12 13 14 0.1 µF Current limiter setting voltage applied pin 39 kΩ Ω 39 k Torque command voltage applied pin Forward/reverse command applied pin No. 6109-14/17 Bias of VCC/2 FG pulse output A12221 Test Circuit 1 Im 5 A So Vs 15 V Sq V 0.5 Ω Vm3 VFR A VLIM A 36 FR NC NC NC VS NC GND GND VOUT UOUT WOUT FRAME FRAME FRAME GSENSE 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 FRAME VCTL V Vm2 RF(PWR) RF(SENSE) Sh 1 Sg 2 Sj VIN+ VIN– LIM FC FGIN+ WIN+ UIN– CTL FGOUT FGIN– UIN+ FGS FRAME FRAME LB1987/D/M/H FRAME FRAME WIN– VCC 0.5 A 0.5 A 3 1A 10 mA 10 1 0.1 µF VFG2 VFG1 2 3 4 5 6 7 8 9 10 11 12 13 Unless specified otherwise: VCT = 5 V VS = 15 V VFR = 5 V, VLIM = 5 V VCTR = 5 V VCREF = 2.5 V VFG1 = VFG = 2.5 V 1 14 15 16 17 18 Sk 2 Switch states: O: Closed X: Open LB1987, 1987D, 1987M, 1987H 3 Sa 1 Sc Sb 12 212 Sd 1 2 Se 121 Sf 2 A 0.1 µF 0.1 µF 0.1 µF 2 4 3 2.4 kΩ 2.4 kΩ V VCC 5V 200 kΩ 200 kΩ 2.4 kΩ 2.4 kΩ Vm1 Sm Sn 1 4Ω 4Ω 4Ω Im2 A A12222 No. 6109-15/17 4Ω 0.1 µF 0.5 Ω V Vm7 0.1 µF 0.1 µF VS 15 V Vm4 Vm1 Test Circuit 2 V U V V 4Ω V Vm5 Vm6 Vm2 V V V W 4Ω VCC 5 V 36 NC NC GND NC FR VS NC UOUT VOUT WOUT GND RF(SENSE) FRAME RF(PWR) FRAME FRAME GSENSE FRAME 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 LB1987/1987D/1987M/1987H FC LIM FRAME FGOUT FGIN+ VIN+ VIN– FGS CTL FGIN– WIN+ WIN– UIN– UIN+ FRAME 2 0.1 µF Sm 1 2 VCTL Ω 10 kΩ V Vm9 Sa V Vm8 1 2 3 1 2 1 kΩ 1 kΩ Sb 3 1 2 Sc 3 Sd 1 2 3 1 2 Se 3 1 2 Sf 3 V 1 MΩ 2 Sh 1 3 4 5 6 7 8 9 10 11 12 13 14 15 FRAME VCC FRAME 1 Unless specified otherwise: VCC = 5 V VS = 15 V VCTL = 0 V VH1 = 2.6 V VH2 = 2.4 V VH3 = 2.6 V VFGF = 2.5 V VFGIN = 2.5 V 16 17 18 Switch states: O: Closed X: Open LB1987, 1987D, 1987M, 1987H S1 Sf f I= 1 kHZ = 1 kHz Sk 13 kΩ Vp-p = 1.0 V Vp-p = 1.0 V VFGIN Im1 A ±15 V VH1 VH2 1 Sg 2 VH3 + 100 kΩ –20 dB 0.1 µF Si – LA6358 f = 1 kHz A12223 No. 6109-16/17 LB1987, 1987D, 1987M, 1987H Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1999. Specifications and information herein are subject to change without notice. PS No. 6109-17/17