LV24230LP-A

Ordering number : ENA0891A LV24230LP-A Overview Bi-CMOS LSI Compact Portable Equipment 1-Chip FM Tuner IC The LV24230LP-A is an I2C-controlled single-chip FM tuner IC that integrates external components which are necessary for tuning in a compact VQLP package with dimensions of only 4×4×0.8mm3. Equipped with a state machine, the LV24230LP-A has the capability to perform automatic tuning/seek and dissipates less power than conventional LV24000series tuner ICs. Features • FM FE • FM IF • MPX stereo decoder • Tuning • Standby Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Symbol VCC max VDD max Maximum input voltage VIN1 max VIN2 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Conditions Analog block supply voltage Digital block supply voltage SCL, SDA, Int External_clk_in Ta ≤ 70°C Ratings 5.0 4.0 VDD+0.3 VDD+0.3 140 -20 to +70 -40 to +125 Unit V V V V mW °C °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D1207 MS / 0209707 MS PC 20070705-S00003 No.A0891-1/17 LV24230LP-A Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Symbol VCC VDD Operating supply voltage range VCC op VDD op VIO op Interface voltage Conditions Analog block supply voltage Digital block supply voltage Ratings 3.0 3.0 2.6 to 4.0 2.5 to 4.0 1.62 to 4.0 Unit V V V V V Note : Supply voltage VIO equal VDD, or VIO < VDD & VIO > 0.65 VDD Operating Characteristics at Ta = 25°C, VCC = 3.0V, VDD = 3.0V, Volume set at maximum, Soft Mute = 1/Soft Stereo = off with the designated test circuit Output level set with Radio Control 1 of control register map (0Dh Bit0, Bit1 set to ‘1’, ‘1’) In addition, Set IF_OSC = 150kHz, IF_BW = 100% (Radio Control 1 : 0D Bit6, Bit7 set to ‘1’, ’1’) Parameter Current drain (in operation) Current drain (in standby) FM receive band Symbol ICCA ICCD ICCA ICCD F_range Conditions min Analog block at 60dBµV EMF input Digital block at 60 dBµV EMF input Analog standby mode Digital standby mode Refer to PCB mounting conditions to cover the FM receive band of 76M to 108MHz FM receive characteristics; MONO : fc = 80MHz, fm = 1kHz, 22.5kHzdev. Note that Soft_mute = 1, Soft_stereo function OFF, IHF-BPF used 3dB sensitivity Practical sensitivity 1 Practical sensitivity 2 (Reference) Demodulation output Channel balance Signal-to-noise ratio Total harmonic distortion 1 (MONO) Total harmonic distortion 2 (MONO) Field intensity display level FS Reg1Dh_bit0 = OFF Input level at which Reg02h_bit1-3 change from 1 to 2. Mute attenuation Mute-Att. 60dBµV EMF, pin 19 output 60 70 dB FM receive characteristics ; STEREO characteristics : fc = 80MHz, fm = 1kHz, VIN = 60dBµV EMF, Pilot = 10% (7.5kHzdev), MPX-Filter used Separation Total harmonic distortion (Main) SEP THD-ST1 L-mod, pin 19 / pin 18 output L+R signals = 30% (22.5kHz dev.) Main-mod (for L + R input), 19 output IHF_BPF L+R signals = 30% (22.5kHzdev.) 0.6 1.8 % 20 35 dB 3 10 20 dBµV EMF THD2 60dBµV EMF, pin 19 output, 75.0kHz dev. 1.3 3 % -3dB LS QS1 QS2 Vo CB S/N THD1 60dBµV, 22.5kHzdev output standard, -3dB input. Input at S/N = 30dB De-emphasis = 75µs, SG open display Input at S/N = 26dB De-emphasis = 75µs, SG terminal display 60dBµV EMF, pin 19 output 60dBµV EMF, pin 18 output/pin 19 output 60dBµV EMF, pin 19 output 60dBµV EMF, pin 19 output, 22.5kHz dev. 80 -2 48 110 0 58 0.4 1.5 160 2 mVrms dB dB % 1.10 8 16 5 17 dBµV EMF dBµV EMF µV 76 Ratings typ 12 0.3 3 3 max 17 0.8 30 30 108 mA mA µA µA MHz Unit Interface block allowable operation range at Ta = -20 to +70°C, VSS = 0V Parameter Supply voltage Digital block input Symbol VDD VIH VIL Digital block output IOL VOL External clock operating frequency fclk_ext High-level input voltage range Low-level input voltage range Output current at Low level Output voltage at Low level IOL = 2mA Clock frequency for external input 32k 32.768k Conditions min 2.5 0.7VDD 0 2.0 0.6 20M Ratings typ max 4.0 VDD 0.1VDD V V V mA V Hz Unit Note : External clock input (pin 12) allows also input of the sine wave signal. No.A0891-2/17 LV24230LP-A Package Dimensions unit : mm (typ) 3347 TOP VIEW 4.0 SIDE VIEW (0.0625) BOTTOM VIEW 0.35 (0.15) 4.0 0.5 2 0.25 0.5 1 (0.75) 0.0NOM 0.85MAX SIDE VIEW SANYO : VQLP24(4.0X4.0) Pin Assignment Line_out_R Vstabi MPX 24 (0.75) 0.35 18 17 16 15 14 13 Line_out_L 19 Package-GND 20 Package-GND 21 Package-GND 22 Package-GND 23 GND 24 1 FM_ANT1 VCC NC NC 12 Ext_CLK_IN 11 Package-GND 10 Package-GND 9 Package-GND 8 Package-GND 7 SCL 2 FM_ANT2 3 VIO 4 VDD 5 INT 6 SDA No.A0891-3/17 LV24230LP-A Block Diagram Line_out_R Vstabi MPX 18 17 16 15 14 13 Line_out_L 19 Line SW And Mute Voltage Stabilizer To Each Block V CC NC NC 12 Ext_CLK_IN Package_GND 20 Buffer AMP 11 Package_GND FM Package_GND 21 Demodulator Stereo Decorder Deemphasis 10 Package_GND Package_GND 22 FM Selectivity Filter FLL Tuning Quadrature Oscillator To Each Block 2 FM_ANT2 3 VIO 4 V DD Tuning System Power Manage ment Digital Interface I2C Conversion 9 Package_GND Package_GND 23 RF and FM Quadrature Mixer 8 Package_GND GND 24 To Each Block 1 FM_ANT1 7 SCL 5 INT 6 SDA No.A0891-4/17 LV24230LP-A Pin Function Pin No. 1 2 3 4 5 Pin name FM-ANT1 FM-ANT2 VI/O VDD INT Description Antenna input Antenna GND Digital interface supply voltage Digital supply voltage Interrupt line Pin voltage 1V 1V Antenna input pin Antenna input pin. For pin 1 single input, pin 2 is set to AC_GND via capacity Power pin dedicated to the interface input/output elements Power pin for digital block Output pin dedicated to interrupt (hardware output: used for options) Addition of pull-up or pull-down resistor recommended to cope with initial instability 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDA SCL Package-GND Package-GND Package-GND Package-GND Ext_CLK_IN VCC NC Vstabi. NC MPX LINE-OUT-R LINE-OUT-L Package-GND Package-GND Package-GND Package-GND GND MPX-signal output Radio Rch Line-output Radio Lch Line-output GND for package-shield GND for package-shield GND for package-shield GND for package-shield GND (Analog and Digital GND) 2.3V 1.2V 1.2V Stabilizer voltage 2.6V Digital interface DATA ine) Digital interface Clock line) GND for package-shield GND for package-shield GND for package-shield GND for package-shield Reference clock-source input for measurement Analog supply voltage Bidirectional data line. Pull up to Vio line with 2.2k resistor Clock wire. Pull up to Vio line with 2.2k resistor BND pin for package shield BND pin for package shield BND pin for package shield BND pin for package shield External standard CLK input pin. Connect X’tal, if used, to GND. (CITIZEN CFS-206, CM31S recommended) Power pin for analog (tuner) block Keep this open. Local oscillator reference bias pin. NC pin to be used Keep this open. Stereo decoder input monitor pin. NC pin to be used Audio R_ch output Audio L_ch output GND pin for package shield GND pin for package shield GND pin for package shield GND pin for package shield GND pin for analog (FM tuner) block and digital (control) block Supplement No.A0891-5/17 LV24230LP-A Format of Bus Transfers Bus transfers are primarily based on the I2C primitives • Start condition • Repeated start condition • Stop condition • Byte write • Byte read Start, restart, and stop conditions are specified as shown in Table 1 below. Start Repeated start Stop SCL SCL SCL SDA SDA SDA Fig. 1 the I2C start, repeated start and stop conditions. For details, like timing, etc., refer to specifications of I2C. 8-bit write 8-bit data is sent from the master microcomputer to LV24230LP-A. Data bit consists of MSB first and LSB last. Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC. Do not change data while SCL remains HIGH. LV24230LP-A outputs the ACK bit between eighth and ninth falling edges of SCL SCL D7 D6 D5 D4 D3 D2 D1 D0 Ack SDA Fig. 2 Signal pattern of the I2C byte write Read is of the same form as write, only except that the data direction is opposite. Eight data bits are sent from LV24230LP-A to the master while Ack is sent from the master to LV24230LP-A. SCL D7 D6 D5 D4 D3 D2 D1 D0 Ack SDA Fig. 3 Signal pattern of the I2C byte read The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24230LP-A in synchronization with the falling edge while the master side performs latching at the rising edge. No.A0891-6/17 LV24230LP-A LV24230LP-A latches ACK at the rising edge. The sequence to write data D into the register A of LV24230LP-A is shown below. • Start condition • write the device address (C0h) • write the register address, A • write the target data, D • stop condition start SCL DA7 DA6...1 Ack write device address SDA write register address write data byte stop A7 A6...1 Ack D7 D6...0 Ack Fig. 4 Register write through I2C When one or more data has been provided for writing, only the first data is allowed to be written. Read sequence • start condition • write the device address (C0h) • write the register address, A • repeated start condition (or stop + start in a single master network) • write the device address + 1 (C1h) • read the register contents D, transmit NACK (no more data to be read) • stop condition start SCL DA7 write device address write register address rep. SDA start DA6...1 Ack A7 A6...0 Ack write device address + 1 read data byte with NACK stop DA7 DA6...1 Ack D7 D6...0 Fig. 5 Register read through I2C Interrupt Pin INT LV24230LP-A has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected. The INT output pin is kept floating while the PWRAD bit is cleared during initialization. Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by means of the pull-up or pull-down resistor. This enables direct INT output connection to non-masking interruption of the host CPU. No.A0891-7/17 LV24230LP-A Digital interface specification (interface specification : reference) (1). Characteristics of SDA and SCL bus line relative to the I2C bus interface START Condition Tf SCL Repeated START Tr TLOW THIGH Tf SDA Tr THD;STA THD;DAT TSU;DAT TSU;STA Standard-mode Parameter SCL clock frequency Fall time of both SDA and SCL Rise time of both SDA and SCL High time of SCL Low time of SCL Hold time of STAT condition Hold time of Data Set-up time of STAT condition Set-up time of STOP condition Set-up time of Data Bus free time between a STOP and Capacitivie load for each bus line *Cb = Total capacitance of one bus line Symbol FSCL Tf Tr THIGH TLOW THD ; STA THD ; DAT TSU ; STA TSU ; STO TSU ; DAT TBUF Cb 4.0 4.7 4.0 0 4.7 4.0 250 4.7 400 3.45 min 0 max 100 300 1000 High_Speed-mode min 0 20+0.1Cb 20+0.1Cb 0.6 1.3 0.6 0 0.6 0.6 100 1.3 400 0.9 max 400 300 300 unit kHz ns ns µs µs µs µs µs µs ns µs pF (2). Register map (On Register Map) Following is Sub address map of LV24230LP-A. Each register becomes 8-bit constitution. Address 00h 02h 0Bh 0Dh 0Eh 0Fh 10h 11h 19h 1Ah 1Bh 1Dh 1Eh 1Fh CHIP_ID RADIO_STAT RFCAP RADIO_CTRL1 RADIO_CTRL2 RADIO_CTRL3 TNPL TNPH_STAT REF_CLK_PRS REF_CLK_DIV REF_CLK_OFF SCN_CTRL TARGET_VAL_L TARGET_VAL_H R/W : Read and Write register Register Name Mode R/W R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W Chip ID Status of Radio Station RF Cap bank Radio Control 1 Radio Control 2 Radio Control 3 Tune Position Low Tune Position High and Status Reference clock pre-scalar Reference clock divider Reference clock offset Scan control Target value Low Target value High Remark R : Read only register No.A0891-8/17 LV24230LP-A (3). Register description (ON Contents of each Register) Register 00h – CHIP_ID – Chip identify register (Read/Write) 7 6 5 4 ID [7 : 0] bit 7-0 : ID [7 : 0] : 8-bit chip ID. LV24230LP-A : 12h Note : To abort the command, write any value in this register. 3 2 1 0 Register 02h – RADIO_STAT – Radio station status (Read-Only) 7 RAD_IF bit 7 : 6 N/A 5 N/A 4 MO_ST 3 2 FS [2 : 0] 1 0 SF5DB RAD_IF : Radio interrupt flag. 0 = no interrupt 1 = interrupt Note : When status (field strength, stereo/mono) changes, this bit is set. If Interrupt of IRQ pin is enabled, Interrupt pin is set by following IPOL register condition. This bit is cleared by register read. In stand-by mode (PW_RAD = 0), this bit is 1 bit 6-5 : bit 4 : NA [1 : 0] : NA 0 fixed MO_ST : Mono/stereo indicator 0 = Forced monaural 1 = Normal (Receiving in stereo mode) bit 3-1 FS [2 : 0] : Fieldstrength : 0 = Low field strength … 7 = High field strength bit 0 : SF5DB : Fieldstrength +5dB : 0 = FS5dB no UP 1 = FS5dB UP For details, refer to Application note. Register 0Bh – RFCAP – RF Cap bank (Read/Write) 7 6 5 4 RFCAP [7 : 0] bit 7-0 : RFCAP [7 : 0] : RF Oscillator CAP bank 3 2 1 0 No.A0891-9/17 LV24230LP-A Register 0Dh – RADIO_CTRL1 – Radio control 1 (Read/Write) 7 IF_SEL bit 7 : 6 IFBWSEL 0 = 130kHz 1 = 150kHz bit 6 : IFBWSEL : IF band width setting 0 = 50% 1 = 100% bit 5 : AGC_SPD : AGC Speed setting 0 = Normal 1 = High bit 4 : DEEM : de-emphasis 0 = 50µs : Korea, China, Europe, Japan 1 = 75µs : USA bit 3 : ST_M : Stereo/mono setting 0 = Stereo enabled 1 = Stereo disabled (mono mode) bit 2 : nMUTE : Audio Mute 0 = Mute On 1 = Mute Off bit 1-0 : VOL [1 : 0] : Volume Setting 0 : Min … 3 : Max 5 AGC_SPD 4 DEEM 3 ST_M 2 nMUTE 1 VOL [1 : 0] 0 IF_SEL : IF Frequency Setting Register 0Eh – RADIO_CTRL2 – Radio control 2 (Read/Write) 7 6 SOFTST [2 : 0] bit 7-5 : SOFTST [2 : 0] : Soft Stereo setting 000b = Soft stereo level 3 001b = Disable soft stereo 010b = Soft stereo level 1 (*) 100b = Soft stereo level 2 Note : do not use without these value. (*) : recommended setting bit 4-2 : SOFTMU [2 : 0] : Soft audio mute setting 000b = Soft audio mute level 3 001b = Disable soft audio mute 010b = Soft audio mute level 1 100b = Soft audio mute level 2 (*) Note : do not use without these value. (*) : recommended setting bit 1 : bit 0 : Reserved : 0 (Fix) STABI_BP : Internal regulator by-pass bit 0 = Internal regulator operate (normal) 1 = Internal regulator by-pass 5 4 3 SOFTMU [2 : 0] 2 1 N/A 0 STABI_BP No.A0891-10/17 LV24230LP-A Register 0Fh – RADIO_CTRL3 – Radio control 3 (Read/Write) 7 IPOL bit 7 : 6 SM_IE 5 RAD_IE 4 SD_PM 3 nIF_PM 2 1 0 PW_RAD EXT_CLK_CFG [1 : 0] IPOL : Interrupt (IRQ) Polarity 0 = IRQ active high 1 = IRQ active low bit 6 : SM_IE : Command end interrupt 0 = Disable 1 = Enable bit 5 : RAD_IE : Radio Interrupt (field strength/stereo changes) 0 = Disable 1 = Enable bit 4 : SD_PM : Stereo decoder clock PLL mute 0 = SD PLL On (Normal Operation) 1 = SD PLL Off (Adjustment) bit 3 : nIF_PM : IF PLL mute 0 = IF PLL Off (Adjustment) 1 = IF PLL On (Normal Operation) bit 2-1 : EXT_CLK_CFG [1 : 0] : External Clock Setting EXT_CLK_CFG [1 : 0] 00 01 10 11 Reference clock Off 32768Hz crystal oscillator Oscillator clock source / 32 (for high frequency source) Oscillator clock source (for low frequency source) bit 0 : PW_RAD : Radio Circuit Power 0 = Power Off (Stand-by). 1 = Power On Note : At the time of start, PW_RAD becomes 0 (Stand-by) Register 10h – TNPL – Tune position low (Read-Only) 7 6 5 4 TUNEPOS [7 : 0] bit 7-0 : TUNEPOS [7 : 0] : Current RF Frequency (Low 8bit) 3 2 1 0 No.A0891-11/17 LV24230LP-A Register 11h – TNPH_STAT – Tune position high/status (Read-Only) 7 6 ERROR [2 : 0] bit 7-5 : ERROR [2 : 0] : Error Code ERROR [2 : 0] 0 1 2 3 6 7 Remark OK, Command end (No Error) Default value after or during reset Band Limit Error DAC Limit Error Command forced End Command busy 5 4 SM_IF 3 TUNED 2 NA 1 TUNEPOS [9 : 8] 0 bit 4 : SM_IF : Command End interrupt flag 0 = No Interrupt 1 = Interrupt This bit is set when the command is over. When the IRQ pin interrupt is allowed, the pin status is changed, Reading this register causes clearing. bit 3 : TUNED : Radio tuning Flag 0 = No tune 1 = Tuned Note : This flag is set when Tuned or a station search succeeded. This flag is cleared under 3 conditions as below. (1) PW_RAD = 0 (2) Tuning Frequency (3) FM station searching bit 2 : bit 1 : 0 : NA : 0 (Fix) TUNEPOS [9 : 8] : Current RF frequency (High 2 bit) Register 19h – REF_CLK_PRS – Reference clock prescaler (Read/Write) 7 6 REFPRE [2 : 0] bit [7 : 5] : REFPRE [2 : 0] : Reference Clock pre- scaler 0=1:1 1=1:2 … 7 = 1:128 bit [4 : 0] : REFMOD [4 : 0] : 5-bit slope correction 5 4 3 2 REFMOD [4 : 0] 1 0 Register 1Ah – REF_CLK_DIV – Reference clock divider (Read/Write) 7 6 5 4 REFDIV [7 : 0] Bit 7-0 : REFDIV [7 : 0] : Reference Clock Divider 0 : Divider Value = 1 1 : Divider Value = 2 … 255 : Divider Value = 256 3 2 1 0 Register 1Bh –REF_CLK_OFF – Reference clock offset (Read/Write) 7 6 5 4 REFOFFS [7 : 0] Bit 7-0 : REFOFFS [7 : 0] : Offset register for the spread of reference clock 3 2 1 0 No.A0891-12/17 LV24230LP-A Register 1Dh – SCN_CTRL – Scan control (Read/Write) 7 GRID [1 : 0] bit 7-6 : 6 5 FLL_ON 4 FLL_MODE 3 2 FS [2 : 0] 1 0 SHF5DB GRID [1 : 0] : FM station search frequency interval : 0 = IFSD set 1 = 50kHz grid 2 = 100kHz grid 3 = 200kHz grid bit 5 : FLL_ON : FLL Control 0 = FLL OFF 1 = FLL ON During setting of the FM frequency and during seek, keep this OFF. Turn it ON after tuning. bit 4 : bit 3-1 : Set 1 for setting of IFSD. bit 0 : SHF5DB : Scan stop level +5dB Reserved : 0 (Fix) FS [2 : 0] : Field strength setting at the time of FM station search and a frequency adjustment bit Register1Eh – TARGET_VAL_L – Target Value Low Register (Read/Write) 7 6 5 4 TARGET [7 : 0] bit 7-0 : TARGET [7 : 0] : Target frequency low 8 bit : 3 2 1 0 Tuning frequency or Limit Frequency for FM Station Search Register 1Fh – TARGET_VAL_H – Target Value High Register (Read/Write) 7 6 5 4 TARGET [15 : 8] bit 7-0 : TARGET [15 : 8] : Target frequency High 8 bit : 3 2 1 0 Target value of oscillator calibration, Tuning frequency value or limit frequency value for station search Note : GRID [1 : 0] is not 0 TARGET [15 : 14] has different definition With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is executed. No.A0891-13/17 LV24230LP-A Test Circuit Line_out_R 1.0µF 22µF 0.1µF VCC + VCC External_CLK_IN Voltage 12 Source 11 10 18 19 17 16 15 14 13 SW Line_out_L 1.0µF 20 21 Top View Package GND GND FM_ANT R:50Ω 1000pF 1000pF 22 23 24 1 2 3 4 5 6 9 8 7 Package GND SCL Pull-up R:2.2kΩ VIO INT INT VDD SDA SCL (CLOCK) VIO Voltage Source SW SW 0.1µF VDD Voltage Source I2C_Bus MPU Extenal CLK_IN SDA (DATA) No.A0891-14/17 LV24230LP-A Application Circuit Not necessary when the CD cut capacity is on the receive side Line_out_R 1µF 4.7µH or R:4.7Ω 22µF 0.1µF 18 19 17 16 15 14 Line_out_L 1 µF Changeover of resistor possible depending on the state of power supply VCC 13 External_CLK_IN Voltage 12 Source 11 10 VCC + SW 20 21 Top View Package GND GND FM_ANT 1µH 100 to 1000pF 22 23 24 1 2 3 4 5 6 9 8 7 Package GND SCL R1 R2 27pF 47pF 120nH Winding type R3 200Ω to 1kΩ VIO INT VDD SDA R4 SCL (CLOCK) VDD Voltage Source 2.2µH or R:12Ω SW Changeover of resistor possible depending on the state of power supply 0.1µF R5 Voltage for I2C interface pull-up R6 I2C_Bus MPU Cautions for mounting of IC Note1 : For external part constant, the recommended value is described. Since the constant may differ during actual use with the set mounted, be sure to consider optimization. Note2 : The differential input antenna application is described. Single input with pin 1 only is also possible. Note3 : If the spike noise between MPU and IC is large during communication, it is recommended to add limiting resistors R1, R2, and R3 between MPU and IC. 0Ω at 1.8V. Note4 : To reduce noise from power supply, add a capacitor between VCC - GND and between VDD - GND. Note5 : The I2C bus communication line requires pull-up resistors R5 and R6. The commonly-employed resistance value is 2.2k. Set the pull-up voltage to the same one of VIO of LV24230LP-A. (Supply from the same source as VIO and VDD is recommended. Note6 : Please use the INT pin arbitrarily. Recommended to open when unused. The INT pin becomes unstable at IC startup. To protect MPU from any effects during startup, it is recommended to add either the pull-up or pull-down resistor to set the non-active mode. (This is not necessary when the MPU can be set to non-active by a software during initialization. Extenal CLK_IN SDA (DATA) INT No.A0891-15/17 LV24230LP-A PCB Mounting Conditions to cover the FM Receiving Area of 76M to 108MHz LV24230LP-A's PCB mounting conditions LV24230LP Printed Circuit Board X = 0mm LAYER • LV24230LP-A has an inductor for local oscillator on the package bottom side. In order to cover the receiving frequency range of 76MHz to 108MHz, provide the GND layer to the first layer of Side A of PCB that is directly below the package bottom side, as shown in the figure. Recommended layout of PCB substrate 4.0 × 4.0 4.0 × 4.0 0.25 0.75 PCB GND Layer 0.50 1.92 3.08 0.35 0.50 X = 3.00 0.50 IC backside_LV24230LP-A IC directly-below_PCB recommended GND patten diagram • With this SPL, the receiving frequency is measured under the following conditions : • The X-value can be set freely between Min = 2.4mm and Max = 3.0mm with reference to IC. (The X-value for Sanyo Demo Board is 2.8mm.) • The Y-value can be set freely between Min = 2.0mm and Max = 3.0mm with reference to IC. (The Y-value for Sanyo Demo Board is 2.6mm.) • Avoid providing another wiring within 0.4mm of bottom layer of PCB_GND as much as possible. No.A0891-16/17 0.70 Y = 2.60 0.34 2.60 0.70 LV24230LP-A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2007. Specifications and information herein are subject to change without notice. PS No.A0891-17/17