SC2453ITSTR

High Performance Quad Output Switching Regulator POWER MANAGEMENT Description SC2453 is a high performance multi-output converter controller that can be configured for a variety of applications. The SC2453 utilizes synchronous rectified buck topologies where efficiency is most important. It also provides dedicated programmable positive and negative linear regulators using external transistors in conjunction with coupled windings to generate positive and negative voltages. Power up sequencing prevents converter latchups. The two buck converters are out of phase, reducing input ripple, allowing for fewer input capacitors. All converters are synchronized to prevent beat frequencies. High frequency operation will reduce ripple and minimize noise. It also reduces the size of output inductors and capacitors. Other features include soft start, power-good signaling, bootstrapping for high side MOSFETs, and frequency synchronization. SC2453 PRELIMINARY Features Two synchronized converters for low noise Power up sequencing to prevent latch-ups Out of phase operation for low input ripple Over current protection Wide input range, 4.5 to 30V Programmable frequency up to 700KHz Two synchronous bucks for high efficiency at high current One dedicated programmable positive linear regulator and one dedicated programmable negative linear regulator –40 to 105 degree C operating temperature Output voltage as low as 0.5V Small package TSSOP-28 Applications DSL applications with multiple input voltage requirements Mixed-Signal applications requiring positive and negative voltages Cable modem power management Base station power management Typical Application Circuit +8-30V Q1 C29 C30 C29 R28 C32 16 C29 6 9 R31 7 8 AVCC SS OSC SYNC/SHDN POK 22 PVCC 28 BDI 27 VIN BST2 GD2H PH2 GD2L FB2 Q2 R31 4 BD4 SC2453 EO2 BST1 5 R31 C32 11 BD3 C31 10 C32 R32 C32 FB3 AGND PGND 15 21 ILIM2 14 ILIM1 1 R28 R31 FB4 GD1H PH1 GD1L FB1 EO1 17 18 19 20 13 12 26 25 24 23 2 3 D10 D11 D11 C31 Q11 L8 C30 +3.3V C33 R30 +3.3V C32 C29 Q11 R33 R32 C35 C31 Q14 L9 C34 +2.5V +1.5V C38 R35 Q15 -12V Q12 R32 C41 C42 R39 R38 R28 R32 +3.3V Revision 5, August 2002 1 www.semtech.com SC2453 POWER MANAGEMENT Absolute Maximum Ratings Parameter BST1, BST2 to PGND VIN to PGND PVCC, AVCC to PGND PGND to AGND PH1 to BST1, PH2 to BST2 GD1H to PH1, GD2H to PH2 GD1L, GD2L to PGND ILIM1, ILIM2 to AGND OSC, SYNC, POK, SS to AGND BDI, BD3, BD4 to PGND FB1, FB2, FB3, FB4, EO1, EO2 to AGND GD1H, GD1L, GD2H, DG2L Source or Sink Current Storage Temperature Range Junction Temperature Lead Temperature (Soldering) 10 Sec. Maximum 35 30 7 ±0.3 -6 to 0.3 7 7 7 7 7 7 1 -60 to +150 -40 to +125 260 PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Units V V V V V V V V V V V A °C °C °C Electrical Characteristics Unless specified: TA = 25°C, VCC = 12V, fs = 600KHz, SYNC/SHDN = 5V Parameter Pow er Supply Quiescent Current Operating Current AVCC PVC C Undervoltage Lockout Start Threshold UVLO Hysteresis PWM Comparator Delay to Output  2002 Semtech Corp. Test Conditions Min Typ Max Unit SS/SHDN = 0V No load VIN > 5.5V VIN > 5.5V 4.5 4.5 7 5 5 12 5.5 5.5 µA mA V V 4.312 4.4 0.1 4.488 V V 70 2 nS www.semtech.com SC2453 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Positive Linear Regulator Feedback Voltage Feedback Input Leakage Current Amplifier Transconductance Drive Sink Current Negative Linear Regulator Feedback Voltage Feedback Input Leakage Current Amplifier Trandconductance Driver Source Current Error Amplifier Feedback Voltage Input Bias Current Input Offset Voltage Open Loop Gain Unity Gain Bandwidth Output Sink Current Output Source Current Slew Rate Oscillator Frequency Range Frequency CT Peak Voltage CT Valley Voltage SYNC Input High Pulse Width SYNC Rise/Fall Time SYNC Frequency Range SYNC High/Low Threshold FOSC 1.5 100 50 FOSC ± 10% RT = TBD 100 540 600 3.0 0.1 700 660 KHz KHz V V nS nS kHz V 90 3 2 2 1 0.49 0.5 0.51 200 5 V nA mV dB MHz mA mA V/µS VFB3 = 0V, IFB3 = 0.5 to 5mA (source) -1.5 5 -25 0 25 mV µA mV mA VFB4 = 0.5V, IB04 = 0.5 to 5mA (sink) -2 5 0.49 0.5 0.51 V µA mV mA Test Conditions Min Typ PRELIMINARY Max Unit  2002 Semtech Corp. 3 www.semtech.com SC2453 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, VCC = 12V, fs = 600KHz PRELIMINARY Parameter Duty Cycle PWM 1 & 2 Maximum Duty Cycle PWM 1 & 2 Maximum Duty Cycle PWM 1 & 2 Minimum Duty Cycle Current Limit CH1& 2 ILIM Set Voltage Soft Start/Shut Dow n Charge Current Discharge Current Disable Threshold Voltage Disable Low to Shut Down Output Gate Drive On-Resistance(H) Gate Drive On-Resistance(L) Rise Time Fall Time Pow er Good FB1 & FB2 High Trip Level Hysteresis FB1 & FB2 Low Trip Level Hysteresis PWR OK Output Low Level PWR OK Output High Leakage Test Conditions Min Typ Min Units fs = 100kHz fs = 700kHz 96 77 5 % % % 2 V 5 2 0.5 50 µA mA V µs 2 2 C OUT = 1000pF COUT = 1000pF 20 20 Ω Ω nS nS 0.55 1 0.45 1 V % V % V µA  2002 Semtech Corp. 4 www.semtech.com SC2453 POWER MANAGEMENT Pin Configuration Top View PRELIMINARY Ordering Information Part Number SC2453ITSTR P ackag e TSSOP-28 Temp. Range (TJ) -40°C to +85°C Note: Only available in tape and reel packaging. A reel contains 2500 devices. (28 Pin TSSOP) Marking Information TOP nnnn = Part Number (Example: 1406) yyww = Date Code (Example: 0012) xxxxx = Semtech Lot No. (Example: P94A01)  2002 Semtech Corp. 5 www.semtech.com SC2453 POWER MANAGEMENT Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name ILIM1 FB 1 EO1 BD 4 FB 4 SS/SHDN SYNC POK OSC FB 3 BD 3 EO2 FB 2 ILIM2 AGND AVCC BST2 GD2H PH2 GD2L PGND PVC C GD1L PH1 GD1H BST1 VIN BD I Pin Function Current limit threshold set for the OUTPUT1. An external resistor adjusts the limit. Feedback input for OUTPUT1. Error amplifier output for compensation of OUTPUT1. Positive linear regulator base driver. Feedback input for OUTPUT4. Soft start pin. Hold low to shutdown part. Oscillator synchronization pin. Open drain power good output. Connect a resistor to AGND for programming the oscillator frequency. Feedback input for OUTPUT3. Negative linear regulator base driver. Error amplifier output for compensation of OUTPUT2. Feedback input for OUTPUT2. Current limit threshold set for OUTPUT2. An external resistor adjusts the limit. Analog signal ground. Supply voltage for analog circuitry. Boost capacitor connection for the OUTPUT2 high side gate drive. Connect an external capacitor and a diode as shown in the Typical Application Circuit. Gate drive output for OUTPUT2. It is 180 degrees out of phase with GD1H. Switching node for OUTPUT2 external inductor connection. Gate drive output for OUTPUT2, low side N-Channel MOSFET. Power ground. Supply voltage for output drivers. Gate drive output for OUTPUT1, low side N-Channel MOSFET. Switching node for OUTPUT1 external inductor connection. Gate drive output for OUTPUT1, high side N-Channel MOSFET. Boost capacitor connection for the OUTPUT1 high side gate drive. Connect an external capacitor and a diode as shown in the Typical Application Circuit. Input supply voltage. Base drive for AVCC/PVCC regulator. PRELIMINARY  2002 Semtech Corp. 6 www.semtech.com SC2453 POWER MANAGEMENT Block Diagram PRELIMINARY  2002 Semtech Corp. 7 www.semtech.com SC2453 POWER MANAGEMENT Applications Information The SC2453 is designed to control and drive two N-Channel MOSFET synchronous rectified buck and two LDOs, one positive and the other negative. The two bucks are synchronized and out of phase operation for low input ripple and noise. The switching frequency is programmable to optimize design. The SC2453 switching regulator section features lossless current sensing while it provides a programmable cycle by cycle over current limit. The SC2453 linear sections are low dropout regulators. The voltage for the linear controllers LDO1 and LDO2 are programmable. SUPPLIES Supplies VIN, PVCC and AVCC from the input source are used to power the SC2353. An external PNP transistor as a linear regulator supplies AVCC and PVCC. The VIN supply provides the bias for the Internal Reference and UVLO circuitry. The AVCC supply provides the bias for the oscillator, the switchers, the LDO controllers, and the Power Good circuitry. PVCC is used to drive the low side MOSFET gate. START UP SEQUENCE A 5uA current source pulls up on the SS pin. When the SS pin reaches 0.5V, the first converter will start. The reference input of the error amplifier is ramped up with the soft-start signal. When the SS pin reaches 2V the SS pin is pulled down to approximately 0.7V and the second converter will begin to soft-start in an identical fashion to the first converter. When the SS pin reaches 2V for the second time, the SS pin is pulled to approximately 0.7V again and the LDOs are started. The reference of the positive LDO is ramped with the SS pin while the negative LDO should be soft-started externally by ramping the positive supply of the feedback resistors. The SS pin will then be pulled up to supply, i.e. AVCC. The SS time is controlled by the value of the SS cap. If the SS pin is pulled below 0.5V, the SC2453 is disabled. The power-okay circuitry monitors the FB inputs of the converter error amplifiers. If the voltage on these inputs goes above 0.55V or below 0.45V then the POK pin is pulled low. The power-okay circuitry monitors the FB inputs of the converter error amplifiers. If the voltage on these inputs goes above 0.55V or below 0.45V then the POK pin is pulled low. The POK pin is held low until the end of the start-up sequence.  2002 Semtech Corp. 8 PRELIMINARY OSCILLATOR The switching frequency of the SC2453 is set by an external resistor using the following formula: R freq = 1 10p • 8.4 • fs OVER CURRENT SC2453 monitors any voltage drop in the lower MOSFETs Rdson voltage due to an over current condition. This method of current sensing minimizes any unnecessary losses due to external sense resistance. The SC2453 utilizes an internal current source and an external resistor connected from the ILIM pins to the AGND pin to program a current limit level. This limit is programmable by choosing the resistor relative to the level required. The value of the resistor can be selected by the following formula: Ri lim = 2000 /(IIim * Rdson) An internal comparator with a reference from the level set by the external resistor monitors the voltage drop across the lower MOSFET. Once the Vdson of the MOSFET exceeds this level, the low side gate is turned on and the upper MOSFET is turned off. GATE DRIVERS The low side gate driver is supplied from PVCC and provides a peak source/sink current of 1A. The high side gate drive is also capable of sourcing and sinking peak currents of 1A. The high side MOSFET gate drive can be provided by an external 12V supply that is connected from BST to GND. The actual gate to source voltage of the upper MOSFET will approximately equal 7V (12V-VCC). If the external 12V supply is not available, a classical bootstrap technique can be implemented from the PVCC supply. A bootstrap capacitor is connected from BST to Phase while PVCC is connected through a diode (Schottky or other fast low VF diode) to the BST. This will provide a gate to source voltage approximately equal to the VCCVdiode drop. Shoot through control circuitry provides a 30ns dead time to ensure both the upper and lower MOSFET will not turn on simultaneously and cause a shoot through condition. www.semtech.com SC2453 POWER MANAGEMENT Applications Information (Cont.) PWM CONTROLLER SC2453 is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below: G VD (s) = VIN 1 + sR C C L 1 + s + s 2LC R PRELIMINARY The transfer function of the compensation network is as follows: ω GCOMP (s ) = I ⋅ s (1 + s )(1 + ωZ1 s (1 + )(1 + ωP1 s ) ωZ 2 s ) ωP 2 where, ω Z1 = ωI = 1 1 , ωZ 2 = R 2 C1 (R1 + R 3 )C 2 1 C1C 3 R2 C1 + C 3 1 1 , ωP1 = , ωP 2 = R 1 ( C1 + C 3 ) R3C2 where, ωO = 1 LC The design guidelines are as following: 1. Set the loop gain crossover frequency ωC for given switching frequency. 2. Place an integrator in the origin to increase DC and low frequency gains. 3. Select ωZ1 and ωZ2 such that they are placed near ωO to dampen peaking; the loop gain has –20dB rate to go across the 0dB line for obtaining a wide bandwidth. 4. Cancel ωESR with compensation pole ωP1 (ωP1 = ωESR ). 5. Place a high frequency compensation pole ωP2 at the half switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with the adequate phase lag at ωC. T ω Z1 ωo L – Output inductance C – Output capacitance RC – Output capacitor ESR VIN – Input voltage C3 C2 R1 + Vref R3 R2 C1 Loop gain T(s) ω Z2 Gd 0dB ωc ω p1 ω p2 Figure 1. Voltage Mode Buck Converter Compensation Network ω ESR Figure 2. Asymptotic diagram of buck power stage and its compensated loop gain.  2002 Semtech Corp. 9 www.semtech.com SC2453 POWER MANAGEMENT Applications Information (Cont.) DUAL LDO CONTROLLERS The SC2453 provides positive and negative adjustable linear regulator controllers. The positive linear regulator uses a PNP transistor to regulate output voltage. This is set by a voltage divider connected from the output to FB to AGND. Referring to the front page Application Circuit, select R8 in the 5KΩ to 20KΩ range. Calculate R7 with the following equation:  V R 7 = R 8  OUT − 1   0.5 PRELIMINARY and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of QT, QB and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. The top FET gate charge currents flow in this trace. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC2453 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin, QT, QB loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. 6) A separate analog ground plane connects to the SC2453 AGND pin. All analog grounding paths including decoupling capacitors, feedback resistors, compensation components, and current-limit setting resistors should be connected to this plane. 7) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s). The negative linear regulator uses a NPN transistor to regulate output voltage. This is set by a voltage divider connected from the output to FB to a positive reference. Referring to the front page Application Circuit, select R16 in the 5KΩ to 20KΩ range. Calculate R12 with the following equation: V R12 = R16  OUT V  REF     where VREF is the positive voltage reference. LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC2453 PWM controller. High switching current is present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used. The number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, such as the input capacitor or the bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (QT) and the Bottom FET (QB) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide  2002 Semtech Corp. 10 www.semtech.com  2002 Semtech Corp. J1 1 2 C50 1uF R50 20K TP1 C5 0.1uF D2 D1 1N5819HW 1N5819HW D3 B150 C7 470uF 7 TP4 3 L1 VPH2-0083(1:4) R5 11.3K R7 47 C14 8.2nF TP8 C15 680pF C16 0.1uF R12 2 R14 2 R16 20K TP11 TP12 Q6 SUD50N03-10CP C19 3.3nF R18 150 Q5 SUD50N03-10CP L2 10uH TP9 R10 2.0K C11 470uF C10 0.01uF BST2 18 19 20 13 12 26 25 24 23 2 3 C24 680pF 15 C25 4.7nF R21 20K 21 R2214 26.1K 1 R23 20K R19 10K R9 20K 2 R6 TP6 2 TP5 Q3 SUD50N03-10CP R4 6 17 TP3 4 C9 0.1uF Q2 SUD50N03-10CP J3 C51 47uF/16V C4 0.1uF C1 470uF/25V C2 470uF/25V C3 470uF/25V CON2 Q1 FZT749 POWER MANAGEMENT Evaluation Board Schematic J2 C6 1uF 16 C8 0.1uF 6 SS/SD OSC SYNC POK GD2L FB2 4 BD4 SC2453 BST1 5 FB4 PH1 11 BD3 FB1 10 FB3 EO1 AGND PGND ILIM2 ILIM1 GD1L GD1H TP10 R15 C21 2.2nF 470 C18 10nF EO2 PH2 AVCC PVCC GD2H BDI VIN 9 R3 20K 7 8 TP7 22 28 27 R1 10K TP2 R2 10 1 2 3 4 CON4 R51 10K +3.3V/1.5A 1 2 3 4 5 6 7 8 CON8 +3.3V/1.5A C12 2.2nF 11 TP13 TP14 TP15 TP16 C13 10uF R8 Q4 FZT749 220 +2.5V/0.5A C17 10uF R11 40.2K +1.5V/2A C20 470uF R13 10K C52 100pF -12V/0.1A Q7 FZT649 R17 220 +2.5V/0.5A R20 100pF 36.5K C53 C22 C23 10uF 10uF -12V/0.1A R24 10K +3.3V/1.5A PRELIMINARY SC2453 www.semtech.com SC2453 POWER MANAGEMENT Bill of Materials - Evaluation Board Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Qty. Reference 3 4 2 3 1 1 2 4 1 2 1 1 1 1 2 2 1 1 1 2 4 1 5 1 6 4 1 1 2 1 1 1 C1,C2,C3 C4,C5,C9,C16 C6,C50 C7,C11,C20 C8 C 10 C12,C21 C13,C17,C22,C23 C 14 C15,C24 C 18 C 19 C 25 C 51 C52,C53 D1,D2 D3 L1 L2 Q1,Q2 Q2,Q3,Q5,Q7 Q7 R1,R13,R19,R24, R51 R2 R3,R9,R16,R21,R23R50 R4,R6,R12,R14 R5 R7 R8,R17 R10 R11 R15 Value 470uF/16V 0.1uF 1uF 470uF/16V 0.1uF 0.01uF 2.2nF 68uF/16V 8.2nF 680pF 10nF 3.3nF 4.7nF 47uF/4V 100pF 1N5819HW B 150 VPH2-0083 (1:4) 15uH FZT749 SUD50N03-10CP FZT649 10K 10 20K 2 11.3K 47 220 2.0K 40.2K 470 12 PRELIMINARY Description/Part No. Rubycon P/N: 16ZA470 Foot Print CPCYL/D.400/LS.200/.034 1206 12.6 Panasonic P/N: ECA-1CHG471 CAP_RADIAL_V8X11P 1206 1206 1206 Panasonic P/N: EEU-FC1C680 CPCYL/D.200/LS.100/.031 1206 1206 1206 1206 1206 Sanyo P/N: 4TPB330ML 7343 1206 Diodes Inc. P/N: 1N5819HW-7 Diodes Inc. P/N: B150-13 Coiltronics P/N: VPH2-0083 Coilcraft P/N: DO5022P-153 Zetex Inc. P/N: FZT749TA Vishay P/N: SUD50N03-10CP Zetex Inc. P/N: FZT649TA SOD-123 SM/SMA VP2 DO3316 SOT-223 SOT-223 SOT-223 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 www.semtech.com  2002 Semtech Corp. SC2453 POWER MANAGEMENT Bill of Materials - Evaluation Board Item 33 34 35 36 Qty. Reference 1 1 1 1 R18 R20 R22 U1 Value 150 36.5K 26.1K S C 2453 Semtech Corp. P/N: SC2453ITSTR Description/Part No. PRELIMINARY Foot Print 1206 1206 1206 TSSOP-28  2002 Semtech Corp. 13 www.semtech.com SC2453 POWER MANAGEMENT Outline Drawing - TSSOP-28 PRELIMINARY Land Pattern - TSSOP-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2002 Semtech Corp. 14 www.semtech.com