SGM5200
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
GENERAL DESCRIPTION
FEATURES
The SGM5200 is a 12-bit, multi-channel input, successive
● 12-Bit Resolution
approximation (SAR) analog-to-digital converter (ADC).
● 16 Channels
The SGM5200 analog power supply range is 2.7V to
5.25V. The SGM5200 has an SPI-compatible interface
that digital power supply range is 1.7V to 5.25V.
The input signal is sampled on the nCS falling edge.
The ADC conversion is droved by external clock SCLK.
The SGM5200 supports manual channel selection and
two kinds of auto channel scan modes.
The input range of SGM5200 is software configurable,
0 to reference voltage or 0 to two times of reference
voltage. It also supports two programmable alarm
thresholds for each channel.
● Sampling Rate: Up to 1MHz
● Supply Voltage Ranges:
Analog Supply: 2.7V to 5.25V
Digital Supply: 1.7V to 5.25V
● Two Software Selectable Unipolar Input Ranges:
Range 1: 0V to VREF
Range 2: 0V to 2 × VREF
● Supports Auto and Manual Channel Selections
● Individually Configurable GPIOs Function:
Four GPIOs in TSSOP Package
One GPIO in TQFN Package
● 20MHz SPI-Compatible Serial Interface
● Power-Down Current: 1.4μA (TYP)
The SGM5200 provides power-down mode.
● Input Bandwidth: 45MHz (TYP) at -3dB
The SGM5200 is available in Green TSSOP-38 and
● Typical Power Consumption:
TQFN-5×5-32L packages. It operates over an ambient
temperature range -40℃ to +125℃.
24mW at 1MSPS (VA = 5V, VBD = 3V)
● Available in Green TSSOP-38 and TQFN-5×5-32L
Packages
APPLICATIONS
PLC
Optical Module Signal Monitoring
Digital Power Supplies
Industrial Automation Systems
SG Micro Corp
www.sg-micro.com
SEPTEMBER 2022 – REV. A. 1
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
PACKAGE/ORDERING INFORMATION
MODEL
PACKAGE
DESCRIPTION
SPECIFIED
TEMPERATURE
RANGE
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
TSSOP-38
-40℃ to +125℃
SGM5200XTS38G/TR
SGM5200
XTS38
XXXXX
Tape and Reel, 4000
TQFN-5×5-32L
-40℃ to +125℃
SGM5200XTQL32G/TR
SGM5200
XTQL32
XXXXX
Tape and Reel, 3000
SGM5200
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
XXXXX
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
Voltage Range (with Respect to AGND)
+VA .................................................................... -0.3V to 6V
AINP or CHx ........................................... -0.3V to VA + 0.3V
Voltage Range (with Respect to BGND)
+VBD ................................................................. -0.3V to 6V
Digital Input Voltage ........................................... -0.3V to 6V
Digital Output Voltage ............................. -0.3V to VA + 0.3V
Input Current to Any Pin except Supply Pins
....................................................................... -10mA to 10mA
Junction Temperature .................................................+150℃
Storage Temperature Range ....................... -65℃ to +150℃
Lead Temperature (Soldering, 10s) ............................+260℃
ESD Susceptibility
HBM ............................................................................. 4000V
CDM ............................................................................ 1000V
RECOMMENDED OPERATING CONDITIONS
Analog Supply Voltage Range ..........................2.7V to 5.25V
Digital I/O Supply Voltage Range .......................... 1.7V to VA
Reference Voltage Range.........................................2V to 3V
SCLK Frequency ........................................................ 20MHz
Operating Temperature Range .................... -40℃ to +125℃
SG Micro Corp
www.sg-micro.com
OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failure to observe proper handling and installation procedures
can cause damage. ESD damage can range from subtle
performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SEPTEMBER 2022
2
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
PIN CONFIGURATIONS
(TOP VIEW)
GPIO2
1
38
GPIO1
GPIO3
2
37
GPIO0
REFN
3
36
+VBD
REFP
4
35
BDGND
+VA
5
34
SDO
AGND
6
33
SDI
MXO
7
32
SCLK
AINP
8
31
nCS
AINN
9
30
AGND
AGND
10
29
+VA
CH15
11
28
CH0
CH14
12
27
CH1
CH13
13
26
CH2
CH12
14
25
CH3
CH11
15
24
CH4
CH10
16
23
CH5
CH9
17
22
CH6
CH8
18
21
CH7
AGND
19
20
AGND
TSSOP-38
AGND
1
+VA
REFP
REFN
GPIO0
+VBD
BDGND
SDO
SDI
(TOP VIEW)
32
31
30
29
28
27
26
25
24
SCLK
MXO
2
23
nCS
AINP
3
22
AGND
21
+VA
20
CH0
AINN
4
CH15
5
CH14
6
19
CH1
CH13
7
18
CH2
CH12
8
17
CH3
12
13
14
15
16
CH7
CH6
CH5
CH4
CH10
11
CH8
10
CH9
9
CH11
AGND
TQFN-5×5-32L
SG Micro Corp
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SEPTEMBER 2022
3
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
PIN DESCRIPTION
PIN
TSSOP-38
TQFN-5×5-32L
1
‒
2
‒
3
30
4
31
NAME
TYPE (1)
GPIO2
DIO
FUNCTION
General-Purpose Input or Output.
Selects ADC Input Range.
High (1): select Range 2 (0V to 2 × VREF).
Low (0): select Range 1 (0V to VREF).
Range
DI
GPIO3
DIO
nPD
DI
Power-Down Input. Active low.
REFN
AI
Reference Ground.
REFP
AI
Reference Input.
General-Purpose Input or Output.
5, 29
21, 32
+VA
‒
Analog Power Supply.
6, 10, 19, 20, 30
1, 22
AGND
‒
Analog Ground.
7
2
MXO
AO
Multiplexer Output.
8
3
AINP
AI
ADC Input Signal.
9
4
AINN
AI
ADC Input Ground.
11
5
CH15
AI
12
6
CH14
AI
13
7
CH13
AI
14
8
CH12
AI
15
9
CH11
AI
16
10
CH10
AI
17
11
CH9
AI
18
12
CH8
AI
21
13
CH7
AI
22
14
CH6
AI
23
15
CH5
AI
24
16
CH4
AI
25
17
CH3
AI
26
18
CH2
AI
27
19
CH1
AI
28
20
CH0
AI
31
23
nCS
DI
Chip Select. Active low.
32
24
SCLK
DI
Serial Clock Input.
33
25
SDI
DI
Serial Data Input.
34
26
SDO
DI
Serial Data Output.
35
27
BDGND
‒
Digital Ground.
36
28
+VBD
‒
Digital Power Supply.
GPIO0
DIO
General-Purpose Input or Output.
37
29
Alarm
DO
Alarm Output. Active high. Refer to Programming section for a detailed
configuration.
38
‒
GPIO1
DIO
General-Purpose Input or Output.
Low Alarm
DO
Low Alarm Output Indication. Active high.
Analog Channel Inputs for Multiplexer.
NOTE:
1. AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input or Output.
SG Micro Corp
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SEPTEMBER 2022
4
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
ELECTRICAL CHARACTERISTICS
(VA = 2.7V to 5.25V, VBD = 1.7V to VA, VREF = 2.5V ± 0.1V, fSAMPLE = 1MHz, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input
Full-Scale Input Span (1)
Absolute Input Range
Range 1
0
VREF
Range 2 while 2 × VREF ≤ VA
0
2 × VREF
Range 1
-0.2
VREF + 0.2
Range 2 while 2 × VREF ≤ VA
-0.2
2 × VREF + 0.2
Input Capacitance
Input Leakage Current
TA = +125℃
V
V
31
pF
60
nA
12
Bits
System Performance
Resolution
No Missing Codes
Integral Linearity
Differential Linearity
Offset Error (3)
Gain Error
Total Unadjusted Error
TUE
Range 1
11
Range 2
12
Range 1
-3.50
±1.6
2.60
Range 2
-1.32
±0.8
1.32
Bits
Range 1
-1.00
-1/+1.3
2.20
Range 2
-0.99
±0.5
1.00
Range 1
-8.00
±1.2
8.00
Range 2
-5.60
±1.6
5.60
Range 1
-5.20
±0.8
4.40
Range 2
-4.10
±0.8
3.10
LSB (2)
LSB
LSB
LSB
Range 1
±1.8
Range 2
±1.9
20MHz SCLK
800
ns
325
ns
LSB
Sampling Dynamics
Conversion Time
Acquisition Time
Maximum Throughput Rate
20MHz SCLK
1
Aperture Delay
6
MHz
ns
Dynamic Characteristics
Total Harmonic Distortion (4)
THD
100kHz
Signal-to-Noise Ratio
SNR
100kHz
Signal-to-Noise + Distortion
100kHz
Spurious Free Dynamic Range
100kHz
Small Signal Bandwidth
At -3dB
Channel-to-Channel Crosstalk
SG Micro Corp
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Range 1
-77
Range 2
-79
Range 1
66.4
70.4
Range 2
67.9
71.4
Range 1
65.6
69.5
Range 2
66.7
70.7
Range 1
78
Range 2
81
45
Any off-channel with 100kHz, full-scale
input to channel being sampled with DC
input (isolation crosstalk)
-100
From previously sampled to channel with
100kHz, full-scale input to channel being
sampled with DC input (memory crosstalk)
-84
dB
dB
dB
dB
MHz
dB
SEPTEMBER 2022
5
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
ELECTRICAL CHARACTERISTICS (continued)
(VA = 2.7V to 5.25V, VBD = 1.7V to VA, VREF = 2.5V ± 0.1V, fSAMPLE = 1MHz, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
2.5
3
V
External Reference Input
Reference Voltage at REFP (5)
VREF
Reference Input Resistance
fSAMPLE = 1MHz
31
kΩ
Alarm Setting
High Threshold Range
0
4092
LSB
Low Threshold Range
0
4092
LSB
Digital Input/Output
VBD = 5.25V
3.10
VBD = 1.7V
1.25
High Input Voltage
VIH
Low Input Voltage
VIL
High Output Voltage
VOH
ISOURCE = 200μA
Low Output Voltage
VOL
ISINK = 200μA
V
VBD = 5.25V
1.90
VBD = 1.7V
0.45
VBD - 0.2
Data Format MSB First
V
V
0.4
V
MSB First
Power Requirements
Analog Supply Voltage
VA
Digital I/O Supply Voltage
VBD
VA = 2.7V to 3.6V and 1MHz throughput
Analog Supply Current
(Normal Mode)
IA
IBD
3.3
5.25
V
1.7
3.3
5.25
V
3
VA = 2.7V to 3.6V static state
1.1
VA = 4.7V to 5.25V and 1MHz throughput
4.1
5.4
VA = 4.7V to 5.25V static state
1.1
2.2
Power-Down State Supply
Current
Digital I/O Supply Current
2.7
VA = 5.25V, fSAMPLE = 1MHz
mA
1.4
μA
1.3
mA
Power-Up Time
1
μs
Invalid Conversions after
Power-Up or Reset
1
Conversion
NOTES:
1. Ideal input span; not consider gain error and offset error.
2. LSB = Least Significant Bit.
3. The measurement is performed relative to the ideal full-scale input.
4. The calculation is performed on the first nine harmonics of the input frequency.
5. The device is designed to operate that reference voltage is 2V to 3V. While, when VREF < 2.4V, it expects lower noise
performance It is due to SNR degradation resulting from lowered signal range.
SG Micro Corp
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SEPTEMBER 2022
6
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TIMING CHARACTERISTICS
(VA = 2.7V to 5.25V, Full = -40℃ to +125℃, unless otherwise noted.)
PARAMETER
Conversion Time
SYMBOL
tCONV
Delay Time
(nCS Low to First Data DO15 Out)
t1
Hold Time
(SCLK Falling to SDO Data Bit Valid)
t2
Delay Time
(SCLK Falling to SDO Next Data Bit Valid)
t3
Setup Time
(SDI Valid to Rising Edge of SCLK)
t4
Hold Time
(Rising Edge of SCLK to SDI Valid)
t5
Delay Time
(16th SCLK Falling Edge to SDO 3-State)
Minimum Quiet Sampling Time Needed from Bus
3-State to Start of Next Conversion
Pulse Duration nCS High
Setup Time
(nCS Low to First Rising Edge of SCLK)
Pulse Duration SCLK High
Pulse Duration SCLK Low
SCLK Frequency
t6
t7
t8
t9
t10
t11
(1) (2)
(See Figure 1 and Figure 2)
CONDITIONS
MIN
TYP
MAX
VBD = 1.8V
16
VBD = 3V
16
VBD = 5V
16
VBD = 1.8V
38
VBD = 3V
27
VBD = 5V
17
VBD = 1.8V
13
VBD = 3V
12
VBD = 5V
12
35
VBD = 3V
27
VBD = 5V
17
2
VBD = 3V
3
VBD = 5V
4
VBD = 1.8V
12
VBD = 3V
10
VBD = 5V
6
VBD = 3V
22
VBD = 5V
13
VBD = 3V
40
VBD = 5V
40
VBD = 1.8V
20
VBD = 3V
20
VBD = 5V
20
VBD = 1.8V
8
VBD = 3V
6
VBD = 5V
4
VBD = 1.8V
20
VBD = 3V
20
VBD = 5V
20
VBD = 1.8V
20
VBD = 3V
20
VBD = 5V
20
ns
ns
26
40
ns
ns
VBD = 1.8V
VBD = 1.8V
SCLK
ns
VBD = 1.8V
VBD = 1.8V
UNITS
ns
ns
ns
ns
ns
ns
VBD = 1.8V
20
VBD = 3V
20
VBD = 5V
20
MHz
NOTES: 1. 1.6V to 1.9V range is applied for 1.8V specifications; 2.7V to 3.6V range is applied for 3V specifications; 4.75V to 5.25V
range is applied for 5V specifications.
2. With 50pF load.
SG Micro Corp
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SEPTEMBER 2022
7
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TIMING DIAGRAM
Frame N
Frame N+1
nCS
1
SCLK
2
14
3
15
16
1
MUX Channel Change
2
14
3
15
16
MUX Channel Change
MUX
Analog Input Setting after Channel Change
Acquisition
Analog Input Setting after Channel Change
Input sampling instance
Acquisition Phase tACQ
Conversion
Conversion Phase tCNV
GPO
Conversion Phase tCNV
Data Written in Frame N (through SDI)
Data Written in Frame N-1 (through SDI)
GPI
GPI input is latched on the falling edge of nCS and shifted to SDO in frame N+1
SDO
16-Bit Data Output
16-Bit Data Output
SDI
16-Bit Data Input
16-Bit Data Input
Figure 1. Device Operation Timing Diagram
Single Frame
nCS
2
1
SCLK
t2
DO15
4
5
DO14
16
15
t11
t3
t1
SDO
t8
t10
t9
DO12
MSB
/DO11
LSB+1
/DO1
t6
LSB
/DO0
t7
t4
SDI
DI15
DI14
DI1
DI0
t5
Figure 2. Serial Interface Timing Diagram
SG Micro Corp
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SEPTEMBER 2022
8
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TYPICAL PERFORMANCE CHARACTERISTICS
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
70
69
68
67
66
65
Signal-to-Noise Ratio vs. Supply Voltage (Range 2)
Signal-to-Noise Ratio vs. Supply Voltage (Range 1)
2.7
3.1
3.5
3.9
73
Signal-to-Noise Ratio (dB)
Signal-to-Noise Ratio (dB)
71
4.3
4.7
5.1
72
71
70
69
68
67
5.5
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
5.0
5.1
Signal-to-Noise + Distortion vs. Supply Voltage (Range 1)
69
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
68
67
66
65
64
63
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-74
-75
-76
3.5
3.9
4.3
4.7
Supply Voltage (V)
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5.1
5.5
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
-73
3.1
5.4
5.5
70
69
68
67
66
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
Total Harmonic Distortion vs. Supply Voltage (Range 1)
-71
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
-72
2.7
5.3
Signal-to-Noise + Distortion vs. Supply Voltage (Range 2)
72
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
71
Supply Voltage (V)
-77
5.2
Supply Voltage (V)
Signal-to-Noise Ratio + Distortion (dB)
Signal-to-Noise Ratio + Distortion (dB)
Supply Voltage (V)
Total Harmonic Distortion vs. Supply Voltage (Range 2)
-73
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
-74
-75
-76
-77
-78
-79
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
SEPTEMBER 2022
9
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
Spurious Free Dynamic Range (dB)
Spurious Free Dynamic Range vs. Supply Voltage (Range 1)
78
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
77
76
75
74
73
72
2.7
3.1
3.5
3.9
4.3
4.7
5.1
Spurious Free Dynamic Range (dB)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Spurious Free Dynamic Range vs. Supply Voltage (Range 2)
80
VBD = 3V, fS = 1MSPS,
fIN = 100kHz, TA = +25℃
79
78
77
76
75
74
5.5
5.0
5.1
5.2
Supply Voltage (V)
Signal-to-Noise Ratio vs. Input Frequency
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
72
71
70
69
68
67
10
30
50
70
90
110
130
70
69
68
67
66
150
10
30
Spurious Free Dynamic Range (dB)
Total Harmonic Distortion (dB)
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
-75
-77
-79
10
30
50
70
90
110
Input Frequency (kHz)
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70
90
110
130
150
Spurious Free Dynamic Range vs. Input Frequency
85
-73
-81
50
Input Frequency (kHz)
Total Harmonic Distortion vs. Input Frequency
-71
5.5
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
71
Input Frequency (kHz)
-69
5.4
Signal-to-Noise + Distortion vs. Input Frequency
72
Signal-to-Noise + Distortion (dB)
Signal-to-Noise Ratio (dB)
73
5.3
Supply Voltage (V)
130
150
VA = 5V, VBD = 3V,
fS = 1MSPS, TA = +25℃,
MXO Shorted to AINP
83
81
79
77
75
73
10
30
50
70
90
110
130
150
Input Frequency (kHz)
SEPTEMBER 2022
10
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Signal-to-Noise Ratio vs. Temperature
Signal-to-Noise + Distortion vs. Temperature
72
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
71.0
Signal-to-Noise + Distortion (dB)
Signal-to-Noise Ratio (dB)
71.5
70.5
70.0
69.5
69.0
68.5
-50
-25
0
25
50
75
Temperature (℃)
100
125
71
70
69
68
67
66
150
Total Harmonic Distortion vs. Temperature
-74
-75
-76
-77
-78
-50
-25
0
25
50
75
Temperature (℃)
100
125
0.6
DNL MAX
0.2
0.0
-0.2
DNL MIN
-0.4
-0.6
125
150
77
76
-50
-25
0
25
50
75
Temperature (℃)
100
125
150
Integral Nonlinearity Variation Across Channels
0.8
0.6
0.4
VA = 5V, VBD = 5V, fS = 1MSPS
INL MAX
0.2
0.0
-0.2
-0.4
-0.6
INL MIN
-0.8
-0.8
-1.0
100
78
1.0
VA = 5V, VBD = 5V, fS = 1MSPS
0.4
25
50
75
Temperature (℃)
79
75
150
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSBs)
0.8
0
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
80
Differential Nonlinearity Variation Across Channels
1.0
-25
Spurious Free Dynamic Range vs. Temperature
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
-73
-50
81
Spurious Free Dynamic Range (dB)
Total Harmonic Distortion (dB)
-72
VA = 5V, VBD = 3V,
fS = 1MSPS, fIN = 100kHz
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel Number
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-1.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel Number
SEPTEMBER 2022
11
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain Error Variation Across Channels
1.0
VA = 5V, VBD = 5V, fS = 1MSPS
0.8
0.6
0.6
0.4
0.4
0.2
0.0
-0.2
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
VA = 5V, VBD = 5V, fS = 1MSPS
0.8
Offset Error (LSB)
Gain Error (LSB)
Offset Error Variation Across Channels
1.0
-1.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel Number
Channel Number
Signal-to-Noise Ratio Variation Across Channels
71.0
Signal-to-Noise Ratio (dB)
Signal-to-Noise + Distortion (dB)
VA = 5V, VBD = 5V, fS = 1MSPS
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
66.5
66.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Signal-to-Noise + Distortion Variation Across Channels
70.0
VA = 5V, VBD = 5V, fS = 1MSPS
69.5
69.0
68.5
68.0
67.5
67.0
66.5
66.0
65.5
65.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel Number
Channel Number
Crosstalk vs. Input Frequency
120
Input Leakage Current vs. Temperature
98
Isolation
80
Input Leakage Current (nA)
Crosstalk (dB)
100
Memory
60
40
20
0
VA = 5V, VBD = 5V,
fS = 1MSPS, CH0, CH1
0
50
100
150
Input Frequency (kHz)
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200
250
VA = 5V, VBD = 5V
78
58
VINP = 2.5V
VINP = 1.25V
VINP = 0.12V
38
18
-2
-50
-25
0
25
50
75
Temperature (℃)
100
125
150
SEPTEMBER 2022
12
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain Error vs. Temperature (Range 1)
2.0
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
1.5
1.0
0.5
0.0
-0.5
-1.0
1.5
1.0
0.5
0.0
-0.5
-50
-25
0
25
50
75
Temperature (℃)
100
125
-1.0
150
-50
Offset Error vs. Temperature (Range 1)
0.6
Offset Error (LSB)
0.0
-0.2
-0.4
-0.6
125
150
0.4
0.2
0.0
-0.2
-0.4
125
-0.6
150
-50
-25
0
30
25
TUE MAX (LSB)
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5
0
1.6
1.45
1.4
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
0.95
5
10
1.5
10
150
15
1.4
15
125
20
1.3
Percentage of Devices (%)
30
20
100
Total Unadjusted Error (TUE Maximum) (Range 2)
35
25
25
50
75
Temperature (℃)
2.5
100
2.4
75
2.3
50
2.2
25
2
0
2.1
-25
1.9
-50
Total Unadjusted Error (TUE Maximum) (Range 1)
Percentage of Devices (%)
100
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
Temperature (℃)
0
25
50
75
Temperature (℃)
1.8
Offset Error (LSB)
0.6
0.2
-0.8
0
Offset Error vs. Temperature (Range 2)
0.8
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
0.4
-25
1.7
-1.5
VA = 5.5V, VBD = 1.8V, fS = 1MSPS
2.0
Gain Error (LSB)
Gain Error (LSB)
Gain Error vs. Temperature (Range 2)
2.5
TUE MAX (LSB)
SEPTEMBER 2022
13
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Total Unadjusted Error (TUE Minimum) (Range 1)
Total Unadjusted Error (TUE Minimum) (Range 2)
TUE MIN (LSB)
10
-1.35
-1.45
-1.55
-1.65
-1.75
0
-1.85
5
-1.95
-1.5
-1.55
-1.6
-1.65
-1.7
-1.75
-1.8
-1.85
-2
0
-1.9
5
15
-2.05
10
20
-2.15
15
25
-2.25
20
-2.35
Percentage of Devices (%)
30
-1.95
Percentage of Devices (%)
25
TUE MIN (LSB)
Typical FFT Plot
0
VA = 5V, VBD = 5V,
fS = 1MSPS, fIN = 100kHz,
Npoints = 16384
-20
Amplitude (dB)
-40
-60
-80
-100
-120
-140
-160
0
100
200
300
400
500
Frequency (kHz)
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14
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
FUNCTIONAL BLOCK DIAGRAM
MXO
AINP
REFP
+VA
AGND
CH0
CH1
CH2
SDO
Control Logic
&
Sequencing
ADC
SDI
SCLK
nCS
CH15
GPIO0
GPIO3 (1)
BDGND
+VBD
NOTE:
1. Four GPIOs for TSSOP package and one GPIO for TQFN package.
Figure 3. Block Diagram
TYPICAL APPLICATION CIRCUIT
High Input Impedance PGA
(or Non-Inverting Buffer
Such as SGM8604-1)
MXO
AINP
GPIO3
CH0
GPIO2
CH1
GPIO1
CH2
GPIO0
Logic
&
Sequence
ADC
SDO
SDI
SCLK
CH15
nCS
REFP
REF
SGM4029-2.5
REFN
10μF
Figure 4. Typical Application Circuit
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SGM5200
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
DETAILED DESCRIPTION
Overview
The SGM5200 is a 12-bit, SAR ADC. It needs an external
voltage reference. An Amplifier can be used between MXO
and AINP for signal conditioning. Figure 1 and Figure 2
show the chip operating time sequences.
The SGM5200 output data is composed of 4-bit channel
address and 12-bit ADC conversion result. To read and
write GPIOs, more details refer to Table 1, Table 2 and
Table 5.
The SGM5200 switches to new multiplexer channel on the
nd
2 falling edge of SCLK. The input acquisition phase (equal
th
input capacitor starts charging) begins on the 14 falling
edge of SCLK. The input signal is sampled on the nCS
falling edge.
The TSSOP package of the SGM5200 has four
general-purpose IO (GPIO) pins, and the TQFN package
has one GPIO pin.
The chip refreshes the GPIO status (Input and output) at
the nCS falling edge. The GPI data will be in the same
frame starting with the nCS falling edge (if GPI read
enabled).
The operating time sequence is shown in Figure 2, the
falling edge of nCS clocks out DO15, the remain bits are
shifted out on the falling edge of SCLK. The ADC result is a
th
12-bit binary data, MSB is shifted out on the 4 falling edge
th
of SCLK, and LSB is shifted out on the 15 falling edge of
SCLK. Refer to Figure 2, when the ADC conversion ends
th
on the 16 SCLK falling edge, SDO goes to 3-state. The
chip 16-bit data (on SDI pin) is shifted in on the every rising
edge of SCLK.
The SGM5200 has threshold alarm function per channel. If
ADC results exceed these limits (high and low), the chip
can give alert on GPIO0/GPIO1 pins (detail configurations
in Table 9). If there is an alarm, the alert will be set on the
th
12 SCLK falling edge in the same frame of ADC
th
conversion in progress. It will reset on the 10 SCLK falling
edge in the next frame.
Reference
The SGM5200 needs an external reference.
Power Saving
The SGM5200 provides two kinds of ways to power down
the chip. The first way is command control. It depends on
setting DI5 = '1', more details see Table 1, Table 2 and
Table 5. If DI5 is set, the chip will be powered down on the
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th
16 falling edge of SCLK in the next frame. If D15 is reset,
the chip will be powered up on the nCS falling edge. The
second way is asynchronous control by GPIO3. GPIO3 can
be configured as an nPD input (see Table 9). Its output is
active low. The chip goes to power-down at same time
when nPD is '0'. The chip will be powered up when nPD is
'1'.
Device Functional Modes
Channel Sequencing Modes
The SGM5200 has three channel sequencing modes:
manual mode, auto-1 mode and auto-2 mode. Mode
selection is configured by the mode control register (see
Table 1, Table 2 and Table 5). The new channel selection is
nd
valid on the 2 SCLK falling edge in the next frame in all
three modes (refer to Figure 1).
Once the chip is configured to working in a selected mode,
it keeps working in this mode until the chip is powered down,
reset or reprogrammed. Allows it to exit multiple times and
re-enter this mode without disturbing program register
settings.
Manual Mode
When power-up or after reset the default channel is
'channel 0' and the default mode is manual mode.
Auto-1 Mode
In auto-1 mode, the chip scans all selected channels in
ascending order. The selected channels are configured in a
program register. The auto-1 program register setting is
shown in Table 3 and Table 4. The auto-1 program register
is reset to '0hFFFF'.
Auto-2 Mode
In auto-2 mode, the chip scans all selected channels from
channel 0 to the last channel. The last channel is configured
in a program register. The auto-2 program register setting is
shown in Table 6. The auto-2 program register are reset to
'0hF'.
Device Programming and Mode Control
The chip has two kinds of registers named mode registers
and program registers.
Power-Up Sequence
After power-up, the chip is in default manual mode and
channel 0 is set as default channel. User needs to configure
program register and mode register to set the chip working
in target mode.
SEPTEMBER 2022
16
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Operating in Manual Mode
and channel CH5 is selected, internal MUX is switched to
nd
channel CH3 on the 2 falling edge of SCLK. In the frame
N+2, keep in manual mode and channel CH7 is selected,
on the falling edge of nCS, channel CH3 input signal is
sampling and conversion result is sent out in this frame,
internal MUX is switched to CH5. And the chip repeats this
sequence and sends out ADC conversion result data of
CH5 and CH7 in the following two frames.
The mode control register settings for manual mode are
shown in Table 1. In manual mode, no program register is
required.
The example for the chip how to work in manual mode and
scan channels CH3, CH5 and CH7 is shown in Figure 5. In
this sequence, in the frame N manual mode and channel
CH3 is selected. In the frame N+1, keep in manual mode
Table 1. Mode Control Register Details for Manual Mode
BITS
DI[15:12]
DI11
DI[10:7]
RESET
STATE
DESCRIPTION
0001 = Selects manual mode
0001
0 = Chip retains values of DI[6:0] from the previous frame
1 = Enables programming of bits DI[6:0]
0
The 4-bit data means the next channel address to be selected in the next frame. DI10 is MSB and DI7 is LSB. For
example, 0000 = channel 0, 0001 = channel 1 and so on.
0000
DI6
0 = Selects 0V to VREF input range (Range 1)
1 = Selects 0V to 2 × VREF input range (Range 2)
0
DI5
0 = Normal operation (no power-down).
1 = Powers down on the 16th SCLK falling edge.
0
DI4
DI[3:0]
0 = SDO outputs current channel address of the channel on DO[15:12], and the 12-bit conversion results on
DO[11:0]
1 = GPIO3 to GPIO0 data (both input and output) corresponds to DO[15:12] in the following order as shown. Lower
data bits DO[11:0] means 12-bit conversion result for the current channel
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data of the channels is used as output. The data of the channel configured as input will be ignored by the
device. The SDI bits and corresponding GPIO are shown below.
DI3
DI2
DI1
DI0
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
0
0000
NOTE: 1. GPIO1 to GPIO3 are available only for TSSOP package. TQFN packaged device offers GPIO0 only.
Sample
CHy
Sample
CHx
Sample
CH5
Sample
CH3
Frame N+1
Frame N
Frame N+2
nCS
MUX Switch to CH3
1
2
3
16
1
2
3
MUX Switch to CH5
16
1
2
3
16
SCLK
SDI
Configure Manual Mode and
Select CH3
Keep Manual Mode and
Select CH5
SDO
Data CHx
Data CHy
Keep Manual Mode and
Select CH7
Data CH3
Figure 5. Example for Manual Mode Timing Diagram
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Operating in Auto-1 Mode
The mode control register settings for auto-1 mode are
shown in Table 2. There are both mode registers and
program registers for auto-1 mode operation.
To let the chip work in auto-1 mode, it is necessary to
configure auto-1 program register firstly to select which
channels are going to be scanned.
The program register settings for auto-1 mode are shown in
Table 3 and Table 4.
Before running in auto-1 mode, the target channels CH2,
CH3 and CH5 (examples) must be configured in auto-1
program registers (details see auto-1 program registers
configuration sequence).
The example for the chip how to work in auto-1 mode and
scan channels CH2, CH3 and CH5 automatically is shown
in Figure 6. In this sequence, in the frame N sent entering
auto-1 mode command and channel CH2 is selected
automatically (the chip find the first selected channel in
ascending order automatically). In the frame N+1, the chip
switches MUX to CH2. In the frame N+2, the chip samples
the CH2 input and gives out ADC conversion result, and the
MUX is switched to CH3 automatically. In the frame N+3,
the chip samples CH3 and gives out ADC conversion
results, and the MUX is switched to CH5 automatically, and
so on. This process repeats until the last selected channel
is reached, and the process loops back from the first
selected channel.
In any case, re-entering auto-1 mode (It may be from auto-1
mode, manual mode and auto-2 mode) will cause the chip
channel scan sequence restarts from the first selected
channel.
Note that changing the auto-1 program register during the
chip is working in auto-1 mode, the chip scan restarts from
the first selected channel in ascending.
Figure 7 shows how the auto-1 program registers is
configured. It is used to pre-select the channels for auto-1
scanning. It needs two operation frames for a complete
configuration. More setting details are shown in Table 3 and
Table 4.
Table 2. Mode Control Register Details for Auto-1 Mode
BITS
DI[15:12]
RESET
STATE
DESCRIPTION
0010 = Selects auto-1 mode
0001
DI11
0 = Chip retains values of DI[10:0] from previous frame
1 = Enables programming of bits DI[10:0]
0
DI10
0 = The channel counter increments every conversion (no reset)
1 = The channel counter is reset to the lowest programmed channel in the auto-1 program register
0
DI[9:7]
DI6
DI5
DI4
DI[3:0]
xxx = Do not care
000
0 = Selects 0V to VREF input range (Range 1)
1 = Selects 0V to 2 × VREF input range (Range 2)
0
0 = Normal operation (no power-down).
1 = Powers down on the 16th SCLK falling edge.
0 = SDO outputs current channel address of the channel on DO[15:12], and the 12-bit conversion results on
DO[11:0]
1 = GPIO3 to GPIO0 data (both input and output) corresponds to DO[15:12] in the following order as shown. Lower
data bits DO[11:0] means 12-bit conversion result for the current channel
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data of the channels is used as output. The data of the channel configured as input will be ignored by the
device. The SDI bits and corresponding GPIO are shown below.
DI3
DI2
DI1
DI0
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
0
0
0000
NOTE: 1. GPIO1 to GPIO3 are available only for TSSOP package. TQFN packaged device offers GPIO0 only.
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Sample
CHy
Sample
CHx
Sample
CH3
Sample
CH2
Frame N
Frame N+1
Sample
CH5
Frame N+2
Frame N+3
nCS
1
2
3
16
1
2
MUX Switch to CH2
3
16
1
2
MUX Switch to CH3
3
16
1
2
MUX Switch to CH5
3
16
1
2
MUX Switch to CH2
3
16
SCLK
SDI
Enter Auto-1 Mode
SDO
Keep Auto-1 Mode
Keep Auto-1 Mode
Data CHx
Data CHy
Keep Auto-1 Mode
Keep Auto-1 Mode
Data CH2
Data CH3
Data CH5
Figure 6. Example for Auto-1 Mode Timing Diagram
Frame N+1
Frame N
nCS
1
2
3
1
16
2
3
16
SCLK
DI[15:12] = 1000
Enter auto-1 program register configuration
SDI
DI[15:0] = XX
Per Table 3 and Table 4 for channel selected
Do Not Care
SDO
Do Not Care
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 7. Auto-1 Program Register Setting
Table 3. Program Register Details for Auto-1 Mode
BITS
RESET
STATE
DESCRIPTION
Frame 1
DI[15:12]
1000 = Enters the sequence of auto-1 program. Configuration is done in the next frame
NA
DI[11:0]
Do not care.
NA
Frame 2
1 (Individual Bit) = According bit is set to '1' means the according channel is selected in scanning sequence.
The channel numbers are one-to-one associated with the SDI bits. For example, DI15 corresponds to CH15, DI14
corresponds to CH14 … DI0 corresponds to CH0
0 (Individual Bit) = According bit is set to '0' means the according channel is skipped in scanning sequence.
The channel numbers are one-to-one associated with the SDI bits. For example, DI15 corresponds to CH15, DI14
corresponds to CH14 … DI0 corresponds to CH0
DI[15:0]
All '1'
Table 4. Channels Mapping to SDI Bits for the SGM5200
Device (1)
16 Chan
SDI Bits
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
DI7
DI6
DI0
DI4
DI3
DI2
DI1
DI0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
NOTE:
1. The chip only scans the selected channels when in auto-1 mode.
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Operating in Auto-2 Mode
The mode control register settings for auto-2 mode are
shown in Table 5. There are both mode registers and
program registers for auto-1 mode operation.
To let the chip work in auto-2 mode, it is necessary
configure auto-2 program register firstly to configure the last
channel which is going to be reached.
The program register settings for auto-2 mode are shown in
Table 6.
Before running in auto-2 mode, the last target channel CH2
(example) must be configured in auto-2 program registers
(details see auto-2 program registers configuration
sequence).
The example about the chip how to work in auto-2 mode
and scan channels CH0, CH1 and CH2 automatically is
shown in Figure 8. In this sequence, in the frame N sent
entering auto-2 mode command and channel CH0 is
selected automatically (the chip switches to CH0
automatically). In the frame N+1, the chip switches MUX to
CH02. In the frame N+2, the chip samples the CH0 input
and gives out ADC conversion result, and the MUX is
switched to CH1 automatically. In the frame N+3, the chip
samples CH1 and gives out ADC conversion, and the MUX
is switched to CH2 automatically, and so on. This process
repeats until the last selected channel is reached (In this
example, the last channel is CH2), and the process loops
back from channel CH0.
In any case, re-entering auto-2 mode possibly from auto-1
mode, manual mode and auto-2 mode will cause the chip
channel scan sequence to restart from the channel CH0.
Note that changing the auto-2 program register during the
chip is working in auto-2 mode, the chip scan restarts from
channel CH0.
Figure 9 shows how the auto-2 program registers is
configured. It’s for pre-select the last channel for auto-2
scanning. It needs one operation frames for a complete
configuration. Refer to Table 6 for more setting details
Table 5. Mode Control Register Details for Auto-2 Mode
BITS
RESET
STATE
DESCRIPTION
DI[15:12]
0011 = Selects auto-2 mode
0001
DI11
0 = Chip retains values of DI[10:0] from the previous frame
1 = Enables programming of bits DI[10:0]
0
DI10
0 = Channel counter increments every conversion (no reset)
1 = Channel number is reset to CH0
0
DI[9:7]
xxx = Do not care
000
DI6
0 = Selects VREF input range (Range 1)
1 = Selects 2 × VREF input range (Range 2)
0
DI5
0 = Normal operation (no power-down)
1 = Powers down on the 16th SCLK falling edge
0
DI4
DI[3:0]
0 = SDO outputs current channel address of the channel on DO[15:12], and the 12-bit conversion results on
DO[11:0]
1 = GPIO3 to GPIO0 data (both input and output) corresponds to DO[15:12] in the following order as shown. Lower
data bits DO[11:0] means 12-bit conversion result for the current channel
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data of the channels is used as output. The data of the channel configured as input will be ignored by the
device. The SDI bits and corresponding GPIO are shown below.
DI3
DI2
DI1
DI0
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
0
0000
NOTE: 1. GPIO1 to GPIO3 are available only for TSSOP package. TQFN packaged device offers GPIO0 only.
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Sample
CHy
Sample
CHx
Sample
CH1
Sample
CH0
Frame N
Frame N+1
Sample
CH2
Frame N+2
Frame N+3
nCS
1
2
3
16
1
2
MUX Switch to CH0
3
16
1
2
MUX Switch to CH1
3
16
1
MUX Switch to CH2
3
16
2
1
2
MUX Switch to CH0
3
16
SCLK
SDI
Enter Auto-2 Mode
Keep Auto-2 Mode
SDO
Data CHx
Data CHy
Keep Auto-2 Mode
Data CH0
Keep Auto-2 Mode
Keep Auto-2 Mode
Data CH1
Data CH2
Figure 8. Example for Auto-2 Mode Timing Diagram
Frame N
nCS
1
2
16
3
SCLK
SDI
DI[15:12] = 1001
DI[9:6] = xxxx, the address of last channel
SDO
Do Not Care
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 9. Auto-2 Program Register Setting
Table 6. Program Register Details for Auto-2 Mode
BITS
RESET
STATE
DESCRIPTION
DI[15:12]
DI[11:10]
1001 = Configure auto-2 program register
NA
Do not care.
NA
DI[9:6]
aaaa = The 4-bit data means the address of the last channel in the scanning sequence. In auto-2 mode, the
channel counter begins at CH0, increasing each frame until equal to 'aaaa'. The channel counter roles over to CH0
in the next frame
NA
DI[5:0]
Do not care.
NA
Continued Operation in a Selected Mode
When the chip is configured to working in one mode, the user may want to keep working in this mode. How to continue operating
in a selected mode is shown in Table 7.
Table 7. Continued Operation in a Selected Mode
BITS
DESCRIPTION
RESET
STATE
DI[15:12]
0000 = The chip continues to operate in current mode. When in auto-1 and auto-2 modes, the channel counter
increments automatically; when in the manual mode, it continues with the last selected channel. The chip ignores
datas on DI[11:0] and continues operating with the previous settings. SDI can be held low when there is no
changes are required in the mode control register
0001
DI[11:0]
Chip ignores these bits when DI[15:12] is '0000'.
All '0'
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Programming
The GPIO functions and GPO status are set in GPIO
program registers, more details refer to Table 9.
Digital Output
Table 8 shows the theory output codes according to
different input ranges. The ADC codes are in straight binary
format.
The GPO refresh include two steps, first step setting in
operation frame N, second steps the chip refresh GPO data
on the nCS falling edge in frame N+1. More details refer to
Figure 10.
GPIO Registers
The GPIO pins can be used as GPO (general-purpose
output) or GPI (general-purpose input).
The chip samples the GPI input on the falling edge of nCS
in frame N, and outputs GPI data on SDO in the same
frame N.
Table 8. Ideal Input Voltages and Output Codes
Description
Analog Value
Full Scale Range
Range 1 → VREF
Range 2 → 2 × VREF
VREF/4096
2 × VREF/4096
Full Scale
VREF - 1LSB
Midscale
VREF/2
Least Significant Bit (LSB)
Midscale - 1LSB
Digital Output
Straight Binary
Binary Code
Hex Code
2 × VREF - 1LSB
1111 1111 1111
FFF
VREF
1000 0000 0000
800
VREF/2 - 1LSB
VREF - 1LSB
0111 1111 1111
7FF
0V
0V
0000 0000 0000
000
Zero
Frame N
Frame N+1
nCS
1
2
3
16
1
2
3
16
SCLK
GPOs are refreshed per previous frame SDI setting
SDI
DI[15:12] = 0100
Per Table 9 for detail setting
GPIs are sampled and output data on SDO
SDO
GPI Status Refreshed
Do Not Care
GPIs are sampled and output data on SDO
GPI Status Refreshed
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 10. GPIO Program Register Setting
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Table 9. GPIO Program Register Details
BITS
RESET
STATE
DESCRIPTION
DI[15:12] 0100 = Selects GPIO program registers for programming
NA
DI[11:10] 00 = Reserved bits, must be '00'
00
DI9
0 = Normal operation
1 = Resets all registers in the next nCS frame to default value (it also resets itself)
0
DI8
0 = GPIO3 is still as general-purpose I/O. Program 0 for TQFN packaged device
1 = Configures GPIO3 as the chip power-down input
0
DI7
0 = GPIO2 is still as general-purpose I/O. Program 0 for TQFN packaged device
1 = Configures GPIO2 as device range input
0
DI[6:4]
000 = GPIO1 and GPIO0 are still as general-purpose I/Os. Valid setting for TQFN packaged device
xx1 = Configures GPIO0 as 'high or low' alarm output. It is an active high output. GPIO1 is still as general-purpose
I/O. Valid setting for TQFN packaged device
010 = Configures GPIO0 as high alarm output. It is an active high output. GPIO1 is still as general-purpose I/O. Valid
setting for TQFN packaged device
100 = Configures GPIO1 as low alarm output. It is an active high output. GPIO0 is still as general-purpose I/O.
Configuration is not valid for TQFN packaged device
110 = Configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high outputs.
Configuration is not valid for TQFN packaged device
DI3 (1)
0 = GPIO3 pin is configured as GPI (general-purpose input). Setting is not valid for TQFN packaged device
1 = GPIO3 pin is configured as GPO (general-purpose output). Program '1' for TQFN packaged device
0
DI2 (1)
0 = GPIO2 pin is configured as GPI. Setting is not valid for TQFN packaged device
1 = GPIO2 pin is configured as GPO. Program '1' for TQFN packaged device
0
DI1 (1)
0 = GPIO1 pin is configured as GPI. Setting is not valid for TQFN packaged device
1 = GPIO1 pin is configured as GPO. Program '1' for TQFN packaged device
0
DI0 (1)
0 = GPIO0 pin is configured as GPI. Valid setting for TQFN packaged device
1 = GPIO0 pin is configured as GPO. Valid setting for TQFN packaged device
0
000
NOTE:
1. The bits are valid for GPIOs that are not assigned a specific function by bits DI[8:4].
Alarm Thresholds for GPIO Pins
Each channel has separate high alarm threshold and low
alarm threshold. To configure chip quickly, the input
channels are divided into 4 groups, each group can be
programmed consecutively (8 registers are programmed in
one sequence).
In Table 10, the chip has its input channels divide into 4
groups.
Once DI12 is enabled, the chip quits the configuration
sequence in the next frame.
Table 10. Alarm Program Registers Groups
Alarm
Program
Group
Register
DI[15:12]
Registers
0
1100
High and low alarm for CH0, CH1, CH2 and
CH3
Table 11 shows details of the alarm program register.
1
1101
High and low alarm for CH4, CH5, CH6 and
CH7
Each group needs 9 operation frames to complete the
alarm thresholds configuration. The chip supports quit the
configuration sequence in middle of progress (DI12 in alarm
program register is enabled, and < 8 registers is configured).
2
1110
High and low alarm for CH8, CH9, CH10
and CH11
3
1111
High and low alarm for CH12, CH13, CH14
and CH15
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12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Device in any operation mode
Program alarm thresholds?
Yes
Frame N
Enter alarm
program register
setting sequence
Frame N+1
Setting alarm
thresholds
SDI: DI[15:12] = 11xx
(xx indicates group of four channels; refer Table 10)
Device enters alarm register programming sequence
SDI: DI[15:0] as per Table 11
(program alarm thresholds)
DI12 is enabled?
No
Yes, quit current configuration group
Program another group of four channels?
Yes
No
End of alarm programming
NOTE: During the programming process, the chip continues to run in the selected mode. The SDO is valid, but it is impossible to
change the range or write GPIO data to the device during programming.
Figure 11. Alarm Program Register Programming Flowchart
Table 11. Alarm Program Register Details
DESCRIPTION
RESET
STATE
DI[15:12]
1100 = Alarm programming sequence for group 0
1101 = Alarm programming sequence for group 1
1110 = Alarm programming sequence for group 2
1111 = Alarm programming sequence for group 3
Note: DI[15:12] = 11AA is the alarm programming request for group AA. "AA" means the alarm programming
group number in binary format.
NA
DI[11:0]
Do not care.
NA
BITS
Frame 1
Frame 2 and Onwards
CC = "CC" means the channel number in binary format in group AA (each group has 4 channels)
The SGM5200 programs the alarm for the channel represented by the binary number "AACC". "AA" is
programmed in Frame 1.
NA
DI13
0 = Configure low alarm register
1 = Configure high alarm register
NA
DI12
0 = Continue alarm programming sequence in the next frame
1 = Exit alarm programming in the next frame
Note: To quit the threshold configure sequence if all threshold registers have been configured, DI12 must be set
to '1' to quit.
NA
DI[15:14]
DI[11:10]
DI[9:0]
Do not care.
The 10-bit alarm threshold is compared with the upper 10-bit of the 12-bit conversion result.
SG Micro Corp
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NA
'1111111111'
for high alarm
register
and
'0000000000'
for low alarm
register
SEPTEMBER 2022
24
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
SGM5200
DETAILED DESCRIPTION (continued)
Analog Input
Figure 12 shows the equivalent circuit model for the MUX and ADC.
MXO
CH0
6pF
CH15
6pF
150Ω
12pF
AINP
6pF
80Ω
7pF
80MΩ
NOTE: CH0 is assumed to be on, and CH15 is assumed to be off.
Figure 12. Equivalent Circuit for ADC and MUX
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SEPTEMBER 2022 ‒ REV.A to REV.A.1
Page
Update Electrical Characteristics section ............................................................................................................................................................. 5
Changes from Original (SEPTEMBER 2021) to REV.A
Page
Changed from product preview to production data ............................................................................................................................................. All
SG Micro Corp
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SEPTEMBER 2022
25
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TSSOP-38
D
E1
5.94
E
1.78
b
e
0.30
0.50
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
θ
A1
H
A2
Symbol
Dimensions
In Millimeters
MIN
MAX
Dimensions
In Inches
MIN
MAX
1.200
0.047
A
A1
c
0.050
0.150
0.002
0.006
A2
0.800
1.000
0.031
0.039
b
0.170
0.270
0.007
0.011
c
0.090
0.200
0.004
0.008
D
9.600
9.800
0.378
0.386
E
4.300
4.500
0.169
0.177
E1
6.250
6.550
0.246
0.258
e
0.500 BSC
0.020 BSC
H
0.250 TYP
0.010 TYP
L
0.450
0.750
0.018
0.030
θ
1°
7°
1°
7°
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
www.sg-micro.com
TX00183.001
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-5×5-32L
D
e
N17
L
D1
E
E1
N32
k
N1
b
TOP VIEW
BOTTOM VIEW
3.4
3.4
A
4.1
5.5
A1
A2
SIDE VIEW
0.7
0.24
0.5
RECOMMENDED LAND PATTERN (Unit: mm)
Symbol
Dimensions
In Millimeters
MIN
MAX
A
0.700
A1
0.000
A2
Dimensions
In Inches
MIN
MAX
0.800
0.028
0.050
0.000
0.203 REF
0.031
0.002
0.008 REF
D
4.924
5.076
0.194
0.200
D1
3.300
3.500
0.130
0.138
E
4.924
5.076
0.194
0.200
E1
3.300
3.500
0.130
0.138
0.300
0.007
k
b
0.200 MIN
0.180
e
L
0.008 MIN
0.500 TYP
0.324
0.012
0.020 TYP
0.476
0.013
0.019
NOTE: This drawing is subject to change without notice.
SG Micro Corp
www.sg-micro.com
TX00089.000
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
W
P0
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
B0
Reel Diameter
A0
P1
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel
Diameter
Reel Width
W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
P1
(mm)
P2
(mm)
W
(mm)
Pin1
Quadrant
TSSOP-38
13″
16.4
6.80
10.20
1.60
4.0
8.0
2.0
16.0
Q1
TQFN-5×5-32L
13″
12.4
5.30
5.30
1.10
4.0
8.0
2.0
12.0
Q2
SG Micro Corp
www.sg-micro.com
TX10000.000
DD0001
Package Type
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
DD0002
Reel Type
TX20000.000
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