C8051F022-GQR

C8051F020/1/2/3 8K ISP FLASH MCU Family ANALOG PERIPHERALS - SAR ADC • 12-Bit (C8051F020/1) • 10-Bit (C8051F022/3) • ± 1 LSB INL • Programmable Throughput up to 100 ksps • Up to 8 External Inputs; Programmable as Single-Ended or Programmable Throughput up to 500 ksps 8 External Inputs Programmable Amplifier Gain: 4, 2, 1, 0.5 Two 12-bit DACs • - Can Synchronize Outputs to Timers for Jitter-Free Waveform Generation - Two Analog Comparators - Voltage Reference - Precision VDD Monitor/Brown-Out Detector ON-CHIP JTAG DEBUG & BOUNDARY SCAN - On-Chip Debug Circuitry Facilitates Full- Speed, Non- Intrusive In-Circuit/In-System Debugging Provides Breakpoints, Single-Stepping, Watchpoints, Stack Monitor; Inspect/Modify Memory and Registers Superior Performance to Emulation Systems Using ICEChips, Target Pods, and Sockets IEEE1149.1 Compliant Boundary Scan Low-Cost, Complete Development Kit TEMP SENSOR Two UART Serial Ports Available Concurrently Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules 5 General Purpose 16-bit Counter/Timers Dedicated Watch-Dog Timer; Bi-directional Reset Pin CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16 MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE .......................... 2.7V TO 3.6V - Typical Operating Current: 10 mA @ 20 MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP and 64-Pin TQFP Packages Available Temperature Range: -40°C to +85°C ANALOG PERIPHERALS AMUX Sectors External 64k Byte Data Memory Interface (programmable multiplexed or non-multiplexed modes) DIGITAL PERIPHERALS - 8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant - 4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant - Hardware SMBus™ (I2C™ Compatible), SPI™, and 8-bit ADC • • • - - DIGITAL I/O UART0 PGA 10/12-bit 100ksps UART1 ADC SPI Bus VREF SMBus PCA 12-Bit DAC 12-Bit DAC AMUX Timer 0 8-bit 500ksps ADC PGA + + - - VOLTAGE COMPARATORS Timer 1 Timer 2 Timer 3 Port 0 External Memory Interface - Differential Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5 Data-Dependent Windowed Interrupt Generator Built-in Temperature Sensor (± 3°C) Instruction Set in 1 or 2 System Clocks - Up to 25 MIPS Throughput with 25 MHz Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (4k + 256) - 64k Bytes FLASH; In-System programmable in 512-byte CROSSBAR • • • HIGH SPEED 8051 μC CORE - Pipelined Instruction Architecture; Executes 70% of Timer 4 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 64 pin 100 pin HIGH-SPEED CONTROLLER CORE 8051 CPU (25MIPS) 22 INTERRUPTS Rev. 1.4 12/03 64KB ISP FLASH DEBUG CIRCUITRY 4352 B JTAG SRAM CLOCK SANITY CIRCUIT CONTROL Copyright © 2003 by Silicon Laboratories C8051F020/1/2/3 C8051F020/1/2/3 Notes 2 Rev. 1.4 C8051F020/1/2/3 TABLE OF CONTENTS 1. SYSTEM OVERVIEW .........................................................................................................17 1.1. CIP-51™ Microcontroller Core ......................................................................................22 1.1.1. Fully 8051 Compatible ..........................................................................................22 1.1.2. Improved Throughput ............................................................................................22 1.1.3. Additional Features................................................................................................23 1.2. On-Chip Memory ............................................................................................................24 1.3. JTAG Debug and Boundary Scan ...................................................................................25 1.4. Programmable Digital I/O and Crossbar .........................................................................26 1.5. Programmable Counter Array .........................................................................................27 1.6. Serial Ports.......................................................................................................................27 1.7. 12-Bit Analog to Digital Converter.................................................................................28 1.8. 8-Bit Analog to Digital Converter...................................................................................29 1.9. Comparators and DACs...................................................................................................30 2. ABSOLUTE MAXIMUM RATINGS ..................................................................................31 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................32 4. PINOUT AND PACKAGE DEFINITIONS........................................................................33 5. ADC0 (12-BIT ADC, C8051F020/1 ONLY) ........................................................................43 5.1. Analog Multiplexer and PGA..........................................................................................43 5.2. ADC Modes of Operation ...............................................................................................44 5.2.1. Starting a Conversion.............................................................................................44 5.2.2. Tracking Modes .....................................................................................................45 5.2.3. Settling Time Requirements ..................................................................................46 5.3. ADC0 Programmable Window Detector.........................................................................53 6. ADC0 (10-BIT ADC, C8051F022/3 ONLY) ........................................................................59 6.1. Analog Multiplexer and PGA..........................................................................................59 6.2. ADC Modes of Operation ...............................................................................................60 6.2.1. Starting a Conversion.............................................................................................60 6.2.2. Tracking Modes .....................................................................................................61 6.2.3. Settling Time Requirements ..................................................................................62 6.3. ADC0 Programmable Window Detector.........................................................................69 7. ADC1 (8-BIT ADC) ...............................................................................................................75 7.1. Analog Multiplexer and PGA..........................................................................................75 7.2. ADC1 Modes of Operation .............................................................................................76 7.2.1. Starting a Conversion.............................................................................................76 7.2.2. Tracking Modes .....................................................................................................76 7.2.3. Settling Time Requirements ..................................................................................78 8. DACS, 12-BIT VOLTAGE MODE ......................................................................................83 8.1. DAC Output Scheduling..................................................................................................83 8.1.1. Update Output On-Demand ...................................................................................84 8.1.2. Update Output Based on Timer Overflow .............................................................84 8.2. DAC Output Scaling/Justification...................................................................................84 9. VOLTAGE REFERENCE (C8051F020/2)..........................................................................91 Rev. 1.4 3 C8051F020/1/2/3 10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93 11. COMPARATORS..................................................................................................................95 12. CIP-51 MICROCONTROLLER........................................................................................101 12.1. Instruction Set................................................................................................................102 12.1.1. Instruction and CPU Timing................................................................................102 12.1.2. MOVX Instruction and Program Memory...........................................................102 12.2. Memory Organization ...................................................................................................107 12.2.1. Program Memory .................................................................................................107 12.2.2. Data Memory .......................................................................................................108 12.2.3. General Purpose Registers ...................................................................................108 12.2.4. Bit Addressable Locations ...................................................................................108 12.2.5. Stack .................................................................................................................108 12.2.6. Special Function Registers...................................................................................109 12.2.7. Register Descriptions ...........................................................................................113 12.3. Interrupt Handler ...........................................................................................................116 12.3.1. MCU Interrupt Sources and Vectors ...................................................................116 12.3.2. External Interrupts ...............................................................................................116 12.3.3. Interrupt Priorities................................................................................................118 12.3.4. Interrupt Latency..................................................................................................118 12.3.5. Interrupt Register Descriptions ............................................................................119 12.4. Power Management Modes ...........................................................................................125 12.4.1. Idle Mode .............................................................................................................125 12.4.2. Stop Mode............................................................................................................125 13. RESET SOURCES ..............................................................................................................127 13.1. Power-on Reset..............................................................................................................128 13.2. Power-fail Reset ............................................................................................................128 13.3. External Reset................................................................................................................129 13.4. Software Forced Reset...................................................................................................129 13.5. Missing Clock Detector Reset .......................................................................................129 13.6.Comparator0 Reset ........................................................................................................129 13.7. External CNVSTR Pin Reset.........................................................................................129 13.8. Watchdog Timer Reset ..................................................................................................129 13.8.1. Enable/Reset WDT ..............................................................................................130 13.8.2. Disable WDT .......................................................................................................130 13.8.3. Disable WDT Lockout.........................................................................................130 13.8.4. Setting WDT Interval...........................................................................................130 14. OSCILLATORS...................................................................................................................135 14.1. External Crystal Example..............................................................................................138 14.2. External RC Example ....................................................................................................138 14.3. External Capacitor Example..........................................................................................138 15. FLASH MEMORY ..............................................................................................................139 15.1. Programming The FLASH Memory .............................................................................139 15.2. Non-volatile Data Storage .............................................................................................140 15.3. Security Options ............................................................................................................140 16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145 4 Rev. 1.4 C8051F020/1/2/3 16.1. Accessing XRAM..........................................................................................................145 16.1.1. 16-Bit MOVX Example.......................................................................................145 16.1.2. 8-Bit MOVX Example.........................................................................................145 16.2. Configuring the External Memory Interface .................................................................146 16.3. Port Selection and Configuration ..................................................................................146 16.4. Multiplexed and Non-multiplexed Selection.................................................................148 16.4.1. Multiplexed Configuration ..................................................................................148 16.4.2. Non-multiplexed Configuration...........................................................................149 16.5. Memory Mode Selection ...............................................................................................150 16.5.1. Internal XRAM Only ...........................................................................................150 16.5.2. Split Mode without Bank Select ..........................................................................150 16.5.3. Split Mode with Bank Select ...............................................................................151 16.5.4. External Only .......................................................................................................151 16.6. Timing .......................................................................................................................151 16.6.1. Non-multiplexed Mode........................................................................................153 16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’................................153 16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’............154 16.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ..............................155 16.6.2. Multiplexed Mode................................................................................................156 16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’................................156 16.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’............157 16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ..............................158 17. PORT INPUT/OUTPUT .....................................................................................................161 17.1. Ports 0 through 3 and the Priority Crossbar Decoder....................................................163 17.1.1. Crossbar Pin Assignment and Allocation ............................................................163 17.1.2. Configuring the Output Modes of the Port Pins ..................................................164 17.1.3. Configuring Port Pins as Digital Inputs ...............................................................165 17.1.4. External Interrupts (IE6 and IE7) ........................................................................165 17.1.5. Weak Pull-ups......................................................................................................165 17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])......................................165 17.1.7. External Memory Interface Pin Assignments ......................................................166 17.1.8. Crossbar Pin Assignment Example......................................................................168 17.2. Ports 4 through 7 (C8051F020/2 only)..........................................................................177 17.2.1. Configuring Ports which are not Pinned Out.......................................................177 17.2.2. Configuring the Output Modes of the Port Pins ..................................................177 17.2.3. Configuring Port Pins as Digital Inputs ...............................................................178 17.2.4. Weak Pull-ups......................................................................................................178 17.2.5. External Memory Interface ..................................................................................178 18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183 18.1. Supporting Documents ..................................................................................................184 18.2. SMBus Protocol.............................................................................................................185 18.2.1. Arbitration............................................................................................................185 18.2.2. Clock Low Extension...........................................................................................185 18.2.3. SCL Low Timeout ...............................................................................................186 18.2.4. SCL High (SMBus Free) Timeout.......................................................................186 Rev. 1.4 5 C8051F020/1/2/3 18.3. SMBus Transfer Modes.................................................................................................187 18.3.1. Master Transmitter Mode ....................................................................................187 18.3.2. Master Receiver Mode.........................................................................................187 18.3.3. Slave Transmitter Mode.......................................................................................188 18.3.4. Slave Receiver Mode ...........................................................................................188 18.4. SMBus Special Function Registers ...............................................................................189 18.4.1. Control Register ...................................................................................................189 18.4.2. Clock Rate Register .............................................................................................192 18.4.3. Data Register........................................................................................................193 18.4.4. Address Register ..................................................................................................193 18.4.5. Status Register .....................................................................................................194 19. SERIAL PERIPHERAL INTERFACE BUS (SPI0) ........................................................197 19.1. Signal Descriptions........................................................................................................198 19.1.1. Master Out, Slave In (MOSI) ..............................................................................198 19.1.2. Master In, Slave Out (MISO) ..............................................................................198 19.1.3. Serial Clock (SCK) ..............................................................................................198 19.1.4. Slave Select (NSS)...............................................................................................198 19.2. SPI0 Operation ..............................................................................................................199 19.3. Serial Clock Timing ......................................................................................................200 19.4. SPI Special Function Registers .....................................................................................201 20. UART0 ..................................................................................................................................205 20.1.UART0 Operational Modes ..........................................................................................206 20.1.1. Mode 0: Synchronous Mode................................................................................206 20.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................207 20.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................208 20.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................209 20.2. Multiprocessor Communications...................................................................................210 20.3. Frame and Transmission Error Detection......................................................................211 21. UART1 ..................................................................................................................................215 21.1.UART1 Operational Modes ..........................................................................................216 21.1.1. Mode 0: Synchronous Mode................................................................................216 21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................217 21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................218 21.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................219 21.2. Multiprocessor Communications...................................................................................220 21.3. Frame and Transmission Error Detection......................................................................221 22. TIMERS................................................................................................................................225 22.1. Timer 0 and Timer 1......................................................................................................227 22.1.1. Mode 0: 13-bit Counter/Timer.............................................................................227 22.1.2. Mode 1: 16-bit Counter/Timer.............................................................................228 22.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload .................................................229 22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................230 22.2. Timer 2 .......................................................................................................................234 22.2.1. Mode 0: 16-bit Counter/Timer with Capture .......................................................235 22.2.2. Mode 1: 16-bit Counter/Timer with Auto-Reload ...............................................236 6 Rev. 1.4 C8051F020/1/2/3 22.2.3. Mode 2: Baud Rate Generator .............................................................................237 22.3. Timer 3 .......................................................................................................................240 22.4. Timer 4 .......................................................................................................................243 22.4.1. Mode 0: 16-bit Counter/Timer with Capture .......................................................244 22.4.2. Mode 1: 16-bit Counter/Timer with Auto-Reload ...............................................245 22.4.3. Mode 2: Baud Rate Generator .............................................................................246 23. PROGRAMMABLE COUNTER ARRAY .......................................................................249 23.1.PCA Counter/Timer.......................................................................................................250 23.2. Capture/Compare Modules............................................................................................252 23.2.1. Edge-triggered Capture Mode .............................................................................253 23.2.2. Software Timer (Compare) Mode........................................................................254 23.2.3. High Speed Output Mode ....................................................................................255 23.2.4. Frequency Output Mode ......................................................................................256 23.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................257 23.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................258 23.3. Register Descriptions for PCA0 ....................................................................................259 24. JTAG (IEEE 1149.1)............................................................................................................265 24.1. Boundary Scan...............................................................................................................266 24.1.1. EXTEST Instruction ............................................................................................267 24.1.2. SAMPLE Instruction ...........................................................................................267 24.1.3. BYPASS Instruction ............................................................................................267 24.1.4. IDCODE Instruction ............................................................................................267 24.2.Flash Programming Commands ....................................................................................268 24.3. Debug Support...............................................................................................................271 Rev. 1.4 7 C8051F020/1/2/3 Notes 8 Rev. 1.4 C8051F020/1/2/3 LIST OF FIGURES AND TABLES 1. SYSTEM OVERVIEW .........................................................................................................17 Table 1.1. Product Selection Guide ......................................................................................17 Figure 1.1. C8051F020 Block Diagram.................................................................................18 Figure 1.2. C8051F021 Block Diagram.................................................................................19 Figure 1.3. C8051F022 Block Diagram.................................................................................20 Figure 1.4. C8051F023 Block Diagram.................................................................................21 Figure 1.5. Comparison of Peak MCU Execution Speeds.....................................................22 Figure 1.6. On-Board Clock and Reset..................................................................................23 Figure 1.7. On-Chip Memory Map ........................................................................................24 Figure 1.8. Development/In-System Debug Diagram ...........................................................25 Figure 1.9. Digital Crossbar Diagram....................................................................................26 Figure 1.10. PCA Block Diagram............................................................................................27 Figure 1.11. 12-Bit ADC Block Diagram................................................................................28 Figure 1.12. 8-Bit ADC Diagram ............................................................................................29 Figure 1.13. Comparator and DAC Diagram...........................................................................30 2. ABSOLUTE MAXIMUM RATINGS ..................................................................................31 Table 2.1. Absolute Maximum Ratings*..............................................................................31 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................32 Table 3.1. Global DC Electrical Characteristics...................................................................32 4. PINOUT AND PACKAGE DEFINITIONS........................................................................33 Table 4.1. Pin Definitions.....................................................................................................33 Figure 4.1. TQFP-100 Pinout Diagram..................................................................................38 Figure 4.2. TQFP-100 Package Drawing...............................................................................39 Figure 4.3. TQFP-64 Pinout Diagram....................................................................................40 Figure 4.4. TQFP-64 Package Drawing.................................................................................41 5. ADC0 (12-BIT ADC, C8051F020/1 ONLY) ........................................................................43 Figure 5.1. 12-Bit ADC0 Functional Block Diagram............................................................43 Figure 5.2. Temperature Sensor Transfer Function ...............................................................44 Figure 5.3. 12-Bit ADC Track and Conversion Example Timing.........................................45 Figure 5.4. ADC0 Equivalent Input Circuits .........................................................................46 Figure 5.5. AMX0CF: AMUX0 Configuration Register (C8051F020/1) .............................47 Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F020/1)............................48 Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F020/1)..................................49 Figure 5.8. ADC0CN: ADC0 Control Register (C8051F020/1) ...........................................50 Figure 5.9. ADC0H: ADC0 Data Word MSB Register (C8051F020/1) ...............................51 Figure 5.10. ADC0L: ADC0 Data Word LSB Register (C8051F020/1).................................51 Figure 5.11. ADC0 Data Word Example (C8051F020/1) .......................................................52 Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F020/1) .....53 Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F020/1) ......53 Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F020/1) ..........53 Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F020/1) ...........53 Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data .54 Rev. 1.4 9 C8051F020/1/2/3 6. 7. 8. 9. 10 Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....55 Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data....56 Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data.......57 Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F020/1).....................................58 ADC0 (10-BIT ADC, C8051F022/3 ONLY) ........................................................................59 Figure 6.1. 10-Bit ADC0 Functional Block Diagram............................................................59 Figure 6.2. Temperature Sensor Transfer Function ...............................................................60 Figure 6.3. 10-Bit ADC Track and Conversion Example Timing.........................................61 Figure 6.4. ADC0 Equivalent Input Circuits .........................................................................62 Figure 6.5. AMX0CF: AMUX0 Configuration Register (C8051F022/3) .............................63 Figure 6.6. AMX0SL: AMUX0 Channel Select Register (C8051F022/3)............................64 Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3)..................................65 Figure 6.8. ADC0CN: ADC0 Control Register (C8051F022/3) ...........................................66 Figure 6.9. ADC0H: ADC0 Data Word MSB Register (C8051F022/3) ...............................67 Figure 6.10. ADC0L: ADC0 Data Word LSB Register (C8051F022/3).................................67 Figure 6.11. ADC0 Data Word Example (C8051F022/3) .......................................................68 Figure 6.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F022/3) .....69 Figure 6.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F022/3) ......69 Figure 6.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F022/3) ..........69 Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F022/3) ...........69 Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data .70 Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....71 Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data....72 Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data.......73 Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F022/3).....................................74 ADC1 (8-BIT ADC) ...............................................................................................................75 Figure 7.1. ADC1 Functional Block Diagram .......................................................................75 Figure 7.2. ADC1 Track and Conversion Example Timing ..................................................77 Figure 7.3. ADC1 Equivalent Input Circuit...........................................................................78 Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3)............................79 Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3) .....................79 Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3) .....................................80 Figure 7.7. ADC1: ADC1 Data Word Register .....................................................................81 Figure 7.8. ADC1 Data Word Example.................................................................................81 Table 7.1. ADC1 Electrical Characteristics..........................................................................82 DACS, 12-BIT VOLTAGE MODE ......................................................................................83 Figure 8.1. DAC Functional Block Diagram .........................................................................83 Figure 8.2. DAC0H: DAC0 High Byte Register ...................................................................85 Figure 8.3. DAC0L: DAC0 Low Byte Register ....................................................................85 Figure 8.4. DAC0CN: DAC0 Control Register .....................................................................86 Figure 8.5. DAC1H: DAC1 High Byte Register ...................................................................87 Figure 8.6. DAC1L: DAC1 Low Byte Register ....................................................................87 Figure 8.7. DAC1CN: DAC1 Control Register .....................................................................88 Table 8.1. DAC Electrical Characteristics............................................................................89 VOLTAGE REFERENCE (C8051F020/2)..........................................................................91 Rev. 1.4 C8051F020/1/2/3 Figure 9.1. Voltage Reference Functional Block Diagram....................................................91 Figure 9.2. REF0CN: Reference Control Register ................................................................92 Table 9.1. Voltage Reference Electrical Characteristics ......................................................92 10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93 Figure 10.1. Voltage Reference Functional Block Diagram ...................................................93 Figure 10.2. REF0CN: Reference Control Register ................................................................94 Table 10.1. Voltage Reference Electrical Characteristics ......................................................94 11. COMPARATORS..................................................................................................................95 Figure 11.1. Comparator Functional Block Diagram ..............................................................95 Figure 11.2. Comparator Hysteresis Plot.................................................................................96 Figure 11.3. CPT0CN: Comparator0 Control Register ...........................................................97 Figure 11.4. CPT1CN: Comparator1 Control Register ...........................................................98 Table 11.1. Comparator Electrical Characteristics.................................................................99 12. CIP-51 MICROCONTROLLER........................................................................................101 Figure 12.1. CIP-51 Block Diagram ......................................................................................101 Table 12.1. CIP-51 Instruction Set Summary.......................................................................103 Figure 12.2. Memory Map .....................................................................................................107 Table 12.2. Special Function Register (SFR) Memory Map................................................109 Table 12.3. Special Function Registers ................................................................................109 Figure 12.3. SP: Stack Pointer ...............................................................................................113 Figure 12.4. DPL: Data Pointer Low Byte ............................................................................113 Figure 12.5. DPH: Data Pointer High Byte ...........................................................................113 Figure 12.6. PSW: Program Status Word ..............................................................................114 Figure 12.7. ACC: Accumulator............................................................................................115 Figure 12.8. B: B Register .....................................................................................................115 Table 12.4. Interrupt Summary.............................................................................................117 Figure 12.9. IE: Interrupt Enable ...........................................................................................119 Figure 12.10. IP: Interrupt Priority ........................................................................................120 Figure 12.11. EIE1: Extended Interrupt Enable 1 .................................................................121 Figure 12.12. EIE2: Extended Interrupt Enable 2 .................................................................122 Figure 12.13. EIP1: Extended Interrupt Priority 1.................................................................123 Figure 12.14. EIP2: Extended Interrupt Priority 2.................................................................124 Figure 12.15. PCON: Power Control.....................................................................................126 13. RESET SOURCES ..............................................................................................................127 Figure 13.1. Reset Sources ....................................................................................................127 Figure 13.2. Reset Timing .....................................................................................................128 Figure 13.3. WDTCN: Watchdog Timer Control Register ...................................................131 Figure 13.4. RSTSRC: Reset Source Register.......................................................................132 Table 13.1. Reset Electrical Characteristics .........................................................................133 14. OSCILLATORS...................................................................................................................135 Figure 14.1. Oscillator Diagram ............................................................................................135 Figure 14.2. OSCICN: Internal Oscillator Control Register .................................................136 Table 14.1. Internal Oscillator Electrical Characteristics.....................................................136 Figure 14.3. OSCXCN: External Oscillator Control Register...............................................137 15. FLASH MEMORY ..............................................................................................................139 Rev. 1.4 11 C8051F020/1/2/3 Table 15.1. FLASH Electrical Characteristics .....................................................................140 Figure 15.1. FLASH Program Memory Map and Security Bytes .........................................141 Figure 15.2. FLACL: FLASH Access Limit .........................................................................142 Figure 15.3. FLSCL: FLASH Memory Control ....................................................................143 Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................144 16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145 Figure 16.1. EMI0CN: External Memory Interface Control .................................................147 Figure 16.2. EMI0CF: External Memory Configuration .......................................................147 Figure 16.3. Multiplexed Configuration Example.................................................................148 Figure 16.4. Non-multiplexed Configuration Example .........................................................149 Figure 16.5. EMIF Operating Modes.....................................................................................150 Figure 16.6. EMI0TC: External Memory Timing Control ....................................................152 Figure 16.7. Non-multiplexed 16-bit MOVX Timing ...........................................................153 Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................154 Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................155 Figure 16.10. Multiplexed 16-bit MOVX Timing .................................................................156 Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................157 Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................158 Table 16.1. AC Parameters for External Memory Interface.................................................159 17. PORT INPUT/OUTPUT .....................................................................................................161 Figure 17.1. Port I/O Cell Block Diagram.............................................................................161 Table 17.1. Port I/O DC Electrical Characteristics ..............................................................161 Figure 17.2. Lower Port I/O Functional Block Diagram .......................................................162 Figure 17.3. Priority Crossbar Decode Table ........................................................................163 Figure 17.4. Priority Crossbar Decode Table ........................................................................166 Figure 17.5. Priority Crossbar Decode Table ........................................................................167 Figure 17.6. Crossbar Example: ............................................................................................169 Figure 17.7. XBR0: Port I/O Crossbar Register 0 .................................................................170 Figure 17.8. XBR1: Port I/O Crossbar Register 1 .................................................................171 Figure 17.9. XBR2: Port I/O Crossbar Register 2 .................................................................172 Figure 17.10. P0: Port0 Data Register ...................................................................................173 Figure 17.11. P0MDOUT: Port0 Output Mode Register.......................................................173 Figure 17.12. P1: Port1 Data Register ...................................................................................174 Figure 17.13. P1MDIN: Port1 Input Mode Register .............................................................174 Figure 17.14. P1MDOUT: Port1 Output Mode Register.......................................................175 Figure 17.15. P2: Port2 Data Register ...................................................................................175 Figure 17.16. P2MDOUT: Port2 Output Mode Register.......................................................175 Figure 17.17. P3: Port3 Data Register ...................................................................................176 Figure 17.18. P3MDOUT: Port3 Output Mode Register.......................................................176 Figure 17.19. P3IF: Port3 Interrupt Flag Register .................................................................177 Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register ...................................................179 Figure 17.21. P4: Port4 Data Register ...................................................................................180 Figure 17.22. P5: Port5 Data Register ...................................................................................180 Figure 17.23. P6: Port6 Data Register ...................................................................................181 Figure 17.24. P7: Port7 Data Register ...................................................................................181 12 Rev. 1.4 C8051F020/1/2/3 18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183 Figure 18.1. SMBus0 Block Diagram ...................................................................................183 Figure 18.2. Typical SMBus Configuration ..........................................................................184 Figure 18.3. SMBus Transaction ...........................................................................................185 Figure 18.4. Typical Master Transmitter Sequence...............................................................187 Figure 18.5. Typical Master Receiver Sequence ...................................................................187 Figure 18.6. Typical Slave Transmitter Sequence .................................................................188 Figure 18.7. Typical Slave Receiver Sequence .....................................................................188 Figure 18.8. SMB0CN: SMBus0 Control Register ...............................................................191 Figure 18.9. SMB0CR: SMBus0 Clock Rate Register ..........................................................192 Figure 18.10. SMB0DAT: SMBus0 Data Register ...............................................................193 Figure 18.11. SMB0ADR: SMBus0 Address Register..........................................................193 Figure 18.12. SMB0STA: SMBus0 Status Register..............................................................194 Table 18.1. SMB0STA Status Codes and States ..................................................................195 19. SERIAL PERIPHERAL INTERFACE BUS (SPI0) ........................................................197 Figure 19.1. SPI Block Diagram............................................................................................197 Figure 19.2. Typical SPI Interconnection..............................................................................198 Figure 19.3. Full Duplex Operation.......................................................................................199 Figure 19.4. Data/Clock Timing Diagram .............................................................................200 Figure 19.5. SPI0CFG: SPI0 Configuration Register............................................................201 Figure 19.6. SPI0CN: SPI0 Control Register ........................................................................202 Figure 19.7. SPI0CKR: SPI0 Clock Rate Register ................................................................203 Figure 19.8. SPI0DAT: SPI0 Data Register ..........................................................................203 20. UART0 ..................................................................................................................................205 Figure 20.1. UART0 Block Diagram.....................................................................................205 Table 20.1. UART0 Modes ..................................................................................................206 Figure 20.2. UART0 Mode 0 Interconnect............................................................................206 Figure 20.3. UART0 Mode 0 Timing Diagram .....................................................................206 Figure 20.4. UART0 Mode 1 Timing Diagram .....................................................................207 Figure 20.5. UART Modes 2 and 3 Timing Diagram............................................................208 Figure 20.6. UART Modes 1, 2, and 3 Interconnect Diagram ..............................................209 Figure 20.7. UART Multi-Processor Mode Interconnect Diagram .......................................210 Table 20.2. Oscillator Frequencies for Standard Baud Rates...............................................212 Figure 20.8. SCON0: UART0 Control Register....................................................................213 Figure 20.9. SBUF0: UART0 Data Buffer Register..............................................................214 Figure 20.10. SADDR0: UART0 Slave Address Register ....................................................214 Figure 20.11. SADEN0: UART0 Slave Address Enable Register ........................................214 21. UART1 ..................................................................................................................................215 Figure 21.1. UART1 Block Diagram.....................................................................................215 Table 21.1. UART1 Modes ..................................................................................................216 Figure 21.2. UART1 Mode 0 Interconnect............................................................................216 Figure 21.3. UART1 Mode 0 Timing Diagram .....................................................................216 Figure 21.4. UART1 Mode 1 Timing Diagram .....................................................................217 Figure 21.5. UART Modes 2 and 3 Timing Diagram............................................................218 Figure 21.6. UART Modes 1, 2, and 3 Interconnect Diagram ..............................................219 Rev. 1.4 13 C8051F020/1/2/3 Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................................220 Table 21.2. Oscillator Frequencies for Standard Baud Rates...............................................222 Figure 21.8. SCON1: UART1 Control Register....................................................................223 Figure 21.9. SBUF1: UART1 Data Buffer Register..............................................................224 Figure 21.10. SADDR1: UART1 Slave Address Register ....................................................224 Figure 21.11. SADEN1: UART1 Slave Address Enable Register ........................................224 22. TIMERS................................................................................................................................225 Figure 22.1. CKCON: Clock Control Register......................................................................226 Figure 22.2. T0 Mode 0 Block Diagram................................................................................228 Figure 22.3. T0 Mode 2 (8-bit Auto-Reload) Block Diagram...............................................229 Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram................................................230 Figure 22.5. TCON: Timer Control Register.........................................................................231 Figure 22.6. TMOD: Timer Mode Register...........................................................................232 Figure 22.7. TL0: Timer 0 Low Byte ....................................................................................233 Figure 22.8. TL1: Timer 1 Low Byte ....................................................................................233 Figure 22.9. TH0 Timer 0 High Byte ....................................................................................233 Figure 22.10. TH1: Timer 1 High Byte .................................................................................233 Figure 22.11. T2 Mode 0 Block Diagram..............................................................................235 Figure 22.12. T2 Mode 1 Block Diagram..............................................................................236 Figure 22.13. T2 Mode 2 Block Diagram..............................................................................237 Figure 22.14. T2CON: Timer 2 Control Register..................................................................238 Figure 22.15. RCAP2L: Timer 2 Capture Register Low Byte ..............................................239 Figure 22.16. RCAP2H: Timer 2 Capture Register High Byte .............................................239 Figure 22.17. TL2: Timer 2 Low Byte ..................................................................................239 Figure 22.18. TH2 Timer 2 High Byte ..................................................................................239 Figure 22.19. Timer 3 Block Diagram...................................................................................240 Figure 22.20. TMR3CN: Timer 3 Control Register ..............................................................241 Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte ............................................241 Figure 22.22. TMR3RLH: Timer 3 Reload Register High Byte ...........................................242 Figure 22.23. TMR3L: Timer 3 Low Byte ............................................................................242 Figure 22.24. TMR3H: Timer 3 High Byte ...........................................................................242 Figure 22.25. T4 Mode 0 Block Diagram..............................................................................244 Figure 22.26. T4 Mode 1 Block Diagram..............................................................................245 Figure 22.27. T4 Mode 2 Block Diagram..............................................................................246 Figure 22.28. T4CON: Timer 4 Control Register..................................................................247 Figure 22.29. RCAP4L: Timer 4 Capture Register Low Byte ..............................................248 Figure 22.30. RCAP4H: Timer 4 Capture Register High Byte .............................................248 Figure 22.31. TL4: Timer 4 Low Byte ..................................................................................248 Figure 22.32. TH4 Timer 4 High Byte ..................................................................................248 23. PROGRAMMABLE COUNTER ARRAY .......................................................................249 Figure 23.1. PCA Block Diagram..........................................................................................249 Figure 23.2. PCA Counter/Timer Block Diagram .................................................................250 Table 23.1. PCA Timebase Input Options............................................................................250 Figure 23.3. PCA Interrupt Block Diagram...........................................................................252 Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..................252 14 Rev. 1.4 C8051F020/1/2/3 Figure 23.4. PCA Capture Mode Diagram ............................................................................253 Figure 23.5. PCA Software Timer Mode Diagram................................................................254 Figure 23.6. PCA High Speed Output Mode Diagram ..........................................................255 Figure 23.7. PCA Frequency Output Mode ...........................................................................256 Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................................257 Figure 23.9. PCA 16-Bit PWM Mode ...................................................................................258 Figure 23.10. PCA0CN: PCA Control Register ....................................................................259 Figure 23.11. PCA0MD: PCA0 Mode Register ....................................................................260 Figure 23.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers .................................261 Figure 23.13. PCA0L: PCA0 Counter/Timer Low Byte .......................................................262 Figure 23.14. PCA0H: PCA0 Counter/Timer High Byte ......................................................262 Figure 23.15. PCA0CPLn: PCA0 Capture Module Low Byte ..............................................263 Figure 23.16. PCA0CPHn: PCA0 Capture Module High Byte .............................................263 24. JTAG (IEEE 1149.1)............................................................................................................265 Figure 24.1. IR: JTAG Instruction Register ..........................................................................265 Table 24.1. Boundary Data Register Bit Definitions............................................................266 Figure 24.2. DEVICEID: JTAG Device ID Register ............................................................267 Figure 24.3. FLASHCON: JTAG Flash Control Register.....................................................269 Figure 24.4. FLASHADR: JTAG Flash Address Register ....................................................270 Figure 24.5. FLASHDAT: JTAG Flash Data Register..........................................................270 Rev. 1.4 15 C8051F020/1/2/3 Notes 16 Rev. 1.4 C8051F020/1/2/3 1. SYSTEM OVERVIEW The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 12-bit (C8051F020/1) or 10-bit (C8051F022/3) 100 ksps 8-channel ADC with PGA and analog multiplexer True 8-bit ADC 500 ksps 8-channel ADC with PGA and analog multiplexer Two 12-bit DACs with programmable update scheduling 64k bytes of in-system programmable FLASH memory 4352 (4096 + 256) bytes of on-chip RAM External Data Memory Interface with 64k byte address space SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware Five general purpose 16-bit Timers Programmable Counter/Timer Array with five capture/compare modules On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F020/1/2/3 devices are truly standalone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user firmware. The FLASH memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug system supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using JTAG. Each MCU is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-45° C to +85° C). The Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F020/2 are available in a 100-pin TQFP package (see block diagrams in Figure 1.1 and Figure 1.3). The C8051F021/3 are available in a 64-pin TQFP package (see block diagrams in Figure 1.2 and Figure 1.4). Programmable Counter Array Digital Port I/O’s 12-bit 100ksps ADC Inputs 10-bit 100ksps ADC Inputs 8-bit 500ksps ADC Inputs Voltage Reference Temperature Sensor DAC Resolution (bits) DAC Outputs Analog Comparators  64 8 - 8   12 2 2 100TQFP C8051F021 25 64k 4352    2 5  32 8 - 8   12 2 2 C8051F022 25 64k 4352    2 5  64 - 8 8   12 2 2 100TQFP C8051F023 25 64k 4352    2 5  32 - 8 8   12 2 2 Rev. 1.4 Package Timers (16-bit) 5 SPI 2 SMBus/I2C   External Memory Interface 64k 4352  RAM 25 FLASH Memory C8051F020 MIPS (Peak) UARTS Table 1.1. Product Selection Guide 64TQFP 64TQFP 17 C8051F020/1/2/3 Figure 1.1. C8051F020 Block Diagram VDD VDD VDD DGND DGND DGND Digital Power AV+ AV+ AGND AGND Analog Power TCK TMS TDI TDO Port I/O Config. 8 0 5 1 Boundary Scan JTAG Logic Debug HW Reset /RST MONEN VDD Monitor XTAL1 XTAL2 External Oscillator Circuit System Clock Internal Oscillator UART1 SPI Bus PCA SFR Bus Timers 0, 1, 2, 4 64kbyte FLASH 256 byte RAM P0, P1, P2, P3 Latches 4kbyte RAM DAC0 (12-Bit) A M U X Prog Gain Address Bus ADC 100ksps (12-Bit) TEMP SENSOR CP0+ Data Bus CP0 CP0CP1+ CP1 CP1- 18 P1.0/AIN1.0 P2 Drv P2.0 P3 Drv P3.0 P1.7/AIN1.7 P2.7 P3.7 Prog Gain A M U X 8:1 P4.0 Bus Control C T L VREF0 AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 P1 Drv P0.7 External Data Memory Bus DAC1 (12-Bit) DAC0 P0.0 VREF1 ADC 500ksps (8-Bit) VREFD DAC1 P0 Drv Crossbar Config. VREF VREF C R O S S B A R SMBus Timer 3/ RTC C o r e WDT UART0 Rev. 1.4 A d d r D a t a P4 Latch P4 DRV P4.4 P4.5/ALE P4.6/RD P4.7/WR P5 Latch P5 DRV P5.0/A8 P6 Latch P6 DRV P6.0/A0 P7 DRV P7.0/D0 P7 Latch P5.7/A15 P6.7/A7 P7.7/D7 C8051F020/1/2/3 Figure 1.2. C8051F021 Block Diagram VDD VDD VDD DGND DGND DGND Port I/O Config. Digital Power 8 0 5 1 AV+ AGND Analog Power TCK TMS TDI TDO Boundary Scan JTAG Logic Debug HW Reset /RST MONEN VDD Monitor XTAL1 XTAL2 External Oscillator Circuit System Clock Internal Oscillator VREF VREF DAC1 DAC1 (12-Bit) DAC0 DAC0 (12-Bit) UART1 C R O S S B A R SMBus SPI Bus PCA Timers 0, 1, 2, 4 SFR Bus Timer 3/ RTC C o r e WDT UART0 64kbyte FLASH P0, P1, P2, P3 Latches 256 byte RAM A M U X Prog Gain 4kbyte RAM ADC 500ksps (8-Bit) Bus Control Address Bus ADC 100ksps (12-Bit) Data Bus CP0 CP0CP1+ P1 Drv P1.0/AIN1.0 P2 Drv P2.0 P3 Drv P3.0 P0.7 P1.7/AIN1.7 P2.7 P3.7 Prog Gain A M 8:1 U X AV+ VREFA External Data Memory Bus TEMP SENSOR CP0+ P0.0 Crossbar Config. C T L VREFA AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 P0 Drv A d d r D a t a P4 Latch P4 DRV P5 Latch P5 DRV P6 Latch P6 DRV P7 Latch P7 DRV CP1 CP1- Rev. 1.4 19 C8051F020/1/2/3 Figure 1.3. C8051F022 Block Diagram VDD VDD VDD DGND DGND DGND Digital Power AV+ AV+ AGND AGND Analog Power TCK TMS TDI TDO JTAG Logic Port I/O Config. 8 0 5 1 Boundary Scan Debug HW Reset /RST MONEN VDD Monitor XTAL1 XTAL2 External Oscillator Circuit System Clock Internal Oscillator UART1 SPI Bus PCA SFR Bus Timers 0, 1, 2, 4 64kbyte FLASH 256 byte RAM P0, P1, P2, P3 Latches 4kbyte RAM DAC0 (12-Bit) A M U X Prog Gain Address Bus ADC 100ksps (10-Bit) TEMP SENSOR CP0+ Data Bus CP0 CP0CP1+ CP1 CP1- 20 P1.0/AIN1.0 P2 Drv P2.0 P3 Drv P3.0 P1.7/AIN1.7 P2.7 P3.7 Prog Gain A M U X 8:1 P4.0 Bus Control C T L VREF0 AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 P1 Drv P0.7 External Data Memory Bus DAC1 (12-Bit) DAC0 P0.0 VREF1 ADC 500ksps (8-Bit) VREFD DAC1 P0 Drv Crossbar Config. VREF VREF C R O S S B A R SMBus Timer 3/ RTC C o r e WDT UART0 Rev. 1.4 A d d r D a t a P4 Latch P4 DRV P4.4 P4.5/ALE P4.6/RD P4.7/WR P5 Latch P5 DRV P5.0/A8 P6 Latch P6 DRV P6.0/A0 P7 DRV P7.0/D0 P7 Latch P5.7/A15 P6.7/A7 P7.7/D7 C8051F020/1/2/3 Figure 1.4. C8051F023 Block Diagram VDD VDD VDD DGND DGND DGND Port I/O Config. Digital Power 8 0 5 1 AV+ AGND Analog Power TCK TMS TDI TDO Boundary Scan JTAG Logic Debug HW Reset /RST MONEN VDD Monitor XTAL1 XTAL2 External Oscillator Circuit System Clock Internal Oscillator VREF VREF DAC1 DAC1 (12-Bit) DAC0 DAC0 (12-Bit) UART1 C R O S S B A R SMBus SPI Bus PCA Timers 0, 1, 2, 4 SFR Bus Timer 3/ RTC C o r e WDT UART0 64kbyte FLASH P0, P1, P2, P3 Latches 256 byte RAM A M U X Prog Gain 4kbyte RAM ADC 500ksps (8-Bit) Bus Control Address Bus ADC 100ksps (10-Bit) Data Bus CP0 CP0CP1+ P1 Drv P1.0/AIN1.0 P2 Drv P2.0 P3 Drv P3.0 P0.7 P1.7/AIN1.7 P2.7 P3.7 Prog Gain A M 8:1 U X AV+ VREFA External Data Memory Bus TEMP SENSOR CP0+ P0.0 Crossbar Config. C T L VREFA AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 P0 Drv A d d r D a t a P4 Latch P4 DRV P5 Latch P5 DRV P6 Latch P6 DRV P7 Latch P7 DRV CP1 CP1- Rev. 1.4 21 C8051F020/1/2/3 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F020 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two fullduplex UARTs, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 8/4 bytewide I/O Ports. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5 shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks. Figure 1.5. Comparison of Peak MCU Execution Speeds 25 MIPS 20 15 10 5 Silicon Labs Microchip Philips ADuC812 CIP-51 PIC17C75x 80C51 8051 (25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk) 22 Rev. 1.4 C8051F020/1/2/3 1.1.3. Additional Features The C8051F020 MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR input pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be output on the /RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the user in software; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU initialization. The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the fast (up to 16 MHz) internal oscillator as needed. Figure 1.6. On-Board Clock and Reset VDD (Port I/O) CNVSTR Supply Monitor Crossbar (CNVSTR reset enable) (wired-OR) /RST Comparator0 CP0+ + - CP0- (CP0 reset enable) Missing Clock Detector (oneshot) EN System Clock XTAL1 OSC Clock Select Reset Funnel WDT PRE WDT Strobe WDT Enable EN MCD Enable Internal Clock Generator XTAL2 Supply Reset Timeout + - Software Reset CIP-51 Microcontroller Core System Reset Extended Interrupt Handler Rev. 1.4 23 C8051F020/1/2/3 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The CIP-51 in the C8051F020/1/2/3 MCUs additionally has an on-chip 4k byte RAM block and an external memory interface (EMIF) for accessing off-chip data memory. The on-chip 4k byte block can be addressed over the entire 64k external data memory address range (overlapping 4k boundaries). External data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4k directed to on-chip, above 4k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. The MCU’s program memory consists of 64k bytes of FLASH. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0xFE00 to 0xFFFF are reserved for factory use. There is also a single 128 byte sector at address 0x10000 to 0x1007F, which may be useful as a small table for software constants. See Figure 1.7 for the MCU system memory map. Figure 1.7. On-Chip Memory Map DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (FLASH) 0x1007F 0x10000 0xFFFF 0xFE00 Scrachpad Memory (DATA only) RESERVED 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) 0xFDFF FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Off-chip XRAM space 0x1000 0x0FFF 0x0000 24 XRAM - 4096 Bytes (accessable using MOVX instruction) Rev. 1.4 C8051F020/1/2/3 1.3. JTAG Debug and Boundary Scan The C8051F020 family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F020DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F020/1/2/3 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and an RS-232 to JTAG serial adapter. It also has a target application board with the associated MCU installed, plus the RS-232 and JTAG cables, and wall-mount power supply. The Development Kit requires a Windows 95/98/NT/ME/2000 computer with one available RS-232 serial port. As shown in Figure 1.8, the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the Serial Adapter to the user's application board, picking up the four JTAG pins and VDD and GND. The Serial Adapter takes its power from the application board; it requires roughly 20 mA at 2.7-3.6 V. For applications where there is not sufficient power available from the target system, the provided power supply can be connected directly to the Serial Adapter. Silicon Labs’ debug environment is a vastly superior configuration for developing and debugging embedded applications compared to standard MCU emulators, which use on-board "ICE Chips" and target cables and require the MCU in the application board to be socketed. Silicon Labs' debug environment both increases ease of use and preserves the performance of the precision analog peripherals. Figure 1.8. Development/In-System Debug Diagram Silicon Labs Integrated Development Environment WINDOWS 95/98/NT/ME/2000 RS-232 Serial Adapter JTAG (x4), VDD, GND VDD TARGET PCB GND C8051 F020 Rev. 1.4 25 C8051F020/1/2/3 1.4. Programmable Digital I/O and Crossbar The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F020/2 have 4 additional ports (4, 5, 6, and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the standard 8051 with a few enhancements. Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low-power applications. Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See Figure 1.9) Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported. The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. Figure 1.9. Digital Crossbar Diagram Highest Priority 2 UART0 4 SPI 2 UART1 (Internal Digital Signals) P0MDOUT, P1MDOUT, P2MDOUT, P3MDOUT Registers External Pins 2 SMBus Lowest Priority XBR0, XBR1, XBR2, P1MDIN Registers Priority Decoder 8 6 PCA P0 I/O Cells P0.0 P1 I/O Cells P1.0 P2 I/O Cells P2.0 P3 I/O Cells P3.0 P0.7 2 Comptr. Outputs Digital Crossbar T0, T1, T2, T2EX, T4,T4EX /INT0, /INT1 8 P1.7 8 8 /SYSCLK P2.7 CNVSTR 8 8 P0 (P0.0-P0.7) 8 P1 Port Latches (P1.0-P1.7) 8 P2 To External Memory Interface (EMIF) (P2.0-P2.7) 8 P3 26 Highest Priority (P3.0-P3.7) Rev. 1.4 To ADC1 Input P3.7 Lowest Priority C8051F020/1/2/3 1.5. Programmable Counter Array The C8051F020 MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 5 programmable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. The PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port I/O via the Digital Crossbar. Figure 1.10. PCA Block Diagram SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI PCA CLOCK MUX 16-Bit Counter/Timer SYSCLK External Clock/8 Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 Capture/Compare Module 3 Capture/Compare Module 4 CEX4 CEX3 CEX2 CEX1 CEX0 ECI Crossbar Port I/O 1.6. Serial Ports The C8051F020 MCU Family includes two Enhanced Full-Duplex UARTs, SPI Bus, and SMBus/I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share" resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together with any other. Rev. 1.4 27 C8051F020/1/2/3 1.7. 12-Bit Analog to Digital Converter The C8051F020/1 has an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer and programmable gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit accuracy with an INL of ±1LSB. C8051F022/3 devices include a 10-bit SAR ADC with similar specifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output and an external VREF pin. On C8051F020/2 devices, ADC0 has its own dedicated VREF0 input pin; on C8051F021/3 devices, the ADC0 shares the VREFA input pin with the 8bit ADC1. The on-chip 15 ppm/°C voltage reference may generate the voltage reference for other system components or the on-chip ADCs via the VREF output pin. The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers. One input channel is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the eight external input channels can be configured as either two single-ended inputs or a single differential input. The system controller can also put the ADC into shutdown mode to save power. A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software events, external HW signals, or a periodic timer overflow signal. Conversion completions are indicated by a status bit and an interrupt (if enabled). The resulting 10 or 12-bit data word is latched into two SFRs upon completion of a conversion. The data can be right or left justified in these registers under software control. Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within the specified window. Figure 1.11. 12-Bit ADC Block Diagram Analog Multiplexer Configuration, Control, and Data Registers Window Compare Interrupt Window Compare Logic + AIN0.0 AIN0.1 - AIN0.2 + AIN0.3 - AIN0.5 9-to-1 AMUX + (SE or - DIFF) AIN0.6 + AIN0.7 - AIN0.4 Programmable Gain Amplifier AV+ X + - 12-Bit SAR 12 ADC Data Registers ADC Conversion Complete Interrupt TEMP SENSOR External VREF Pin AGND DAC0 Output VREF Start Conversion Write to AD0BUSY Timer 3 Overflow CNVSTR Timer 2 Overflow 28 Rev. 1.4 C8051F020/1/2/3 1.8. 8-Bit Analog to Digital Converter The C8051F020/1/2/3 has an on-board 8-bit SAR ADC (ADC1) with an 8-channel input multiplexer and programmable gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit accuracy with an INL of ±1LSB. Eight input pins are available for measurement. The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. The ADC1 voltage reference is selected between the analog power supply (AV+) and an external VREF pin. On C8051F020/2 devices, ADC1 has its own dedicated VREF1 input pin; on C8051F021/3 devices, ADC1 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC1 into shutdown mode to save power. A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful when different ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). The PGA gain can be set in software to 0.5, 1, 2, or 4. A flexible conversion scheduling system allows ADC1 conversions to be initiated by software commands, timer overflows, or an external input signal. ADC1 conversions may also be synchronized with ADC0 software-commanded conversions. Conversion completions are indicated by a status bit and an interrupt (if enabled), and the resulting 8-bit data word is latched into an SFR upon completion. Figure 1.12. 8-Bit ADC Diagram Analog Multiplexer Configuration, Control, and Data Registers AIN1.0 AIN1.1 Programmable Gain Amplifier AIN1.2 AIN1.3 AIN1.4 AIN1.5 8-to-1 AMUX AV+ X + - 8-Bit SAR Conversion Complete Interrupt 8 ADC Data Register ADC AIN1.6 AIN1.7 Write to AD1BUSY External VREF Pin Timer 3 Overflow VREF Start Conversion CNVSTR Input AV+ Timer 2 Overflow Write to AD0BUSY (synchronized with ADC0) Rev. 1.4 29 C8051F020/1/2/3 1.9. Comparators and DACs Each C8051F020/1/2/3 MCU has two 12-bit DACs and two comparators on chip. The MCU data and control interface to each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown mode. The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the MCU from sleep mode. The comparators' output state can also be polled in software. The comparator outputs can be programmed to appear on the Port I/O pins via the Crossbar. The DACs are voltage output mode, and include a flexible output scheduling mechanism. This scheduling mechanism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F020/2 devices or via the internal voltage reference on C8051F021/3 devices. The DACs are especially useful as references for the comparators or offsets for the differential inputs of the ADC. Figure 1.13. ComparatorandDACDiagram CP0 (Port I/O) CP1 CROSSBAR (Port I/O) CP0+ + CP0- - CP1+ + CP0 CP0 CP1 CP1- CP1 SFR's - (Data and Cntrl) REF DAC0 DAC0 REF DAC1 30 DAC1 Rev. 1.4 CIP-51 and Interrupt Handler C8051F020/1/2/3 2. ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings* PARAMETER CONDITIONS MIN TYP MAX UNITS Ambient temperature under bias -55 125 °C Storage Temperature -65 150 °C Voltage on any Pin (except VDD and Port I/O) with respect to DGND -0.3 VDD + 0.3 V Voltage on any Port I/O Pin or /RST with respect to DGND -0.3 5.8 V Voltage on VDD with respect to DGND -0.3 4.2 V Maximum Total current through VDD, AV+, DGND, and AGND 800 mA Maximum output current sunk by any Port pin 100 mA Maximum output current sunk by any other I/O pin 50 mA Maximum output current sourced by any Port pin 100 mA Maximum output current sourced by any other I/O pin 50 mA * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.4 31 C8051F020/1/2/3 3. GLOBAL DC ELECTRICAL CHARACTERISTICS Table 1.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER CONDITIONS Analog Supply Voltage MIN TYP MAX UNITS 2.7† 3.0 3.6 V Analog Supply Current AV+=2.7 V, Internal REF, ADC, DAC, Comparators all active 1.7 mA Analog Supply Current with analog sub-systems inactive AV+=2.7 V, Internal REF, ADC, DAC, Comparators all disabled, oscillator disabled, VDD Monitor disabled 0.2 µA Analog-to-Digital Supply Delta (|VDD - AV+|) Digital Supply Voltage 2.7 3.0 0.5 V 3.6 V Digital Supply Current with CPU active VDD=2.7 V, Clock=25 MHz VDD=2.7 V, Clock=1 MHz VDD=2.7 V, Clock=32 kHz 10 0.5 20 mA mA µA Digital Supply Current with CPU inactive (not accessing FLASH) VDD=2.7 V, Clock=25 MHz VDD=2.7 V, Clock=1 MHz VDD=2.7 V, Clock=32 kHz 5 0.2 10 mA mA µA Digital Supply Current (shutdown) VDD=2.7 V, Oscillator not running, VDD Monitor disabled 0.2 µA 1.5 V Digital Supply RAM Data Retention Voltage Specified Operating Temperature Range -40 +85 °C SYSCLK (system clock frequency) 0‡ 25 MHz Tsysl (SYSCLK low time) 18 ns Tsysh (SYSCLK high time) 18 ns † ‡ Analog Supply AV+ must be greater than 1 V for VDD monitor to operate. SYSCLK must be at least 32 kHz to enable debugging. 32 Rev. 1.4 C8051F020/1/2/3 4. PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions Pin Numbers Name F020 F021 F022 F023 Type Description VDD 37, 64, 24, 41, 90 57 Digital Supply Voltage. Must be tied to +2.7 to +3.6 V. DGND 38, 63, 25, 40, 89 56 Digital Ground. Must be tied to Ground. AV+ 11, 14 6 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. AGND 10, 13 5 Analog Ground. Must be tied to Ground. TMS 1 58 D In JTAG Test Mode Select with internal pull-up. TCK 2 59 D In JTAG Test Clock with internal pull-up. TDI 3 60 D In JTAG Test Data Input with internal pull-up. TDI is latched on the rising edge of TCK. TDO 4 61 D Out JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on the falling edge of TCK. TDO output is a tri-state driver. /RST 5 62 D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven low when VDD is 0x0100. 54 AD0WINT not affected 0x00FF AD0WINT not affected 0 ADC0GTH:ADC0GTL 0x0000 Given: AMX0SL = 0x00, AMX0CF = 0x00, AD0LJST = ‘0’, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0x0200. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is > 0x0200 or < 0x0100. Rev. 1.4 C8051F020/1 Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage (AD0 - AD1) ADC Data Word Input Voltage (AD0 - AD1) ADC Data Word REF x (2047/2048) 0x07FF REF x (2047/2048) 0x07FF AD0WINT not affected AD0WINT=1 0x0101 REF x (256/2048) 0x0100 0x0101 ADC0LTH:ADC0LTL REF x (256/2048) 0x00FF 0x0100 0x00FF AD0WINT=1 0x0000 REF x (-1/2048) 0xFFFF 0x0000 ADC0GTH:ADC0GTL REF x (-1/2048) 0xFFFE 0xFFFF AD0WINT not affected ADC0LTH:ADC0LTL 0xFFFE AD0WINT=1 AD0WINT not affected -REF ADC0GTH:ADC0GTL 0xF800 Given: AMX0SL = 0x00, AMX0CF = 0x01, AD0LJST = ‘0’, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x0100 and > 0xFFFF. (In two’s-complement math, 0xFFFF = -1.) -REF 0xF800 Given: AMX0SL = 0x00, AMX0CF = 0x01, AD0LJST = ‘0’, ADC0LTH:ADC0LTL = 0xFFFF, ADC0GTH:ADC0GTL = 0x0100. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0xFFFF or > 0x0100. (In two’s-complement math, 0xFFFF = -1.) Rev. 1.4 55 C8051F020/1 Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage (AD0 - AGND) REF x (4095/4096) Input Voltage (AD0 - AGND) ADC Data Word 0xFFF0 REF x (4095/4096) ADC Data Word 0xFFF0 AD0WINT not affected AD0WINT=1 0x2010 REF x (512/4096) 0x2000 0x2010 ADC0LTH:ADC0LTL REF x (512/4096) 0x1FF0 0x2000 0x1FF0 AD0WINT=1 0x1010 REF x (256/4096) 0x1000 0x1010 ADC0GTH:ADC0GTL REF x (256/4096) 0x0FF0 0x1000 ADC0LTH:ADC0LTL AD0WINT=1 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00, AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0x1000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x2000 and > 0x1000. 56 AD0WINT not affected 0x0FF0 AD0WINT not affected 0 ADC0GTH:ADC0GTL 0x0000 Given: AMX0SL = 0x00, AMX0CF = 0x00, AD0LJST = ‘1’ ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0x2000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x1000 or > 0x2000. Rev. 1.4 C8051F020/1 Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage (AD0 - AD1) ADC Data Word Input Voltage (AD0 - AD1) ADC Data Word REF x (2047/2048) 0x7FF0 REF x (2047/2048) 0x7FF0 AD0WINT not affected AD0WINT=1 0x1010 REF x (256/2048) 0x1000 0x1010 ADC0LTH:ADC0LTL REF x (256/2048) 0x0FF0 0x1000 0x0FF0 AD0WINT=1 0x0000 REF x (-1/2048) 0xFFF0 0x0000 ADC0GTH:ADC0GTL REF x (-1/2048) 0xFFE0 0xFFF0 AD0WINT not affected ADC0LTH:ADC0LTL 0xFFE0 AD0WINT=1 AD0WINT not affected -REF ADC0GTH:ADC0GTL 0x8000 Given: AMX0SL = 0x00, AMX0CF = 0x01, AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0xFFF0. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x1000 and > 0xFFF0. (Two’s-complement math.) -REF 0x8000 Given: AMX0SL = 0x00, AMX0CF = 0x01, AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0xFFF0, ADC0GTH:ADC0GTL = 0x1000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0xFFF0 or > 0x1000. (Two’s-complement math.) Rev. 1.4 57 C8051F020/1 Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F020/1) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient bits ±1 LSB ±1 LSB -3±1 LSB -7±3 LSB ±0.25 ppm/°C DYNAMIC PERFORMANCE (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps Signal-to-Noise Plus Distortion Total Harmonic Distortion 66 Up to the 5th harmonic Spurious-Free Dynamic Range dB -75 dB 80 dB CONVERSION RATE SAR Clock Frequency 2.5 MHz Conversion Time in SAR Clocks 16 clocks Track/Hold Acquisition Time 1.5 µs Throughput Rate 100 ksps 0 VREF V AGND AV+ V ANALOG INPUTS Input Voltage Range Single-ended operation *Common-mode Voltage Range Differential operation Input Capacitance 10 pF TEMPERATURE SENSOR Nonlinearity -1.0 Absolute Accuracy +1.0 °C ±3 °C Gain PGA Gain = 1 2.86 mV/°C Offset PGA Gain = 1, Temp = 0°C 0.776 V Operating Mode, 100 ksps 450 POWER SPECIFICATIONS Power Supply Current (AV+ supplied to ADC) Power Supply Rejection 58 ±0.3 Rev. 1.4 900 µA mV/V C8051F022/3 6. ADC0 (10-BIT ADC, C8051F022/3 ONLY) The ADC0 subsystem for the C8051F022/3 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Registers shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91 for C8051F020/2 devices, or Section “10. VOLTAGE REFERENCE (C8051F021/3)” on page 93 for C8051F021/3 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. Figure 6.1. 10-Bit ADC0 Functional Block Diagram ADC0GTL ADC0LTH ADC0LTL 20 - AIN2 + AIN3 - AIN4 + AIN5 9-to-1 AMUX (SE or - DIFF) AIN6 + AIN7 - AD0EN AV+ X 10-Bit SAR + - ADC AGND AD0CM TEMP SENSOR 6.1. AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST AMX0SL AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 AIN67IC AIN45IC AIN23IC AIN01IC AGND AMX0CF 10 ADC0H AIN1 AV+ ADC0CF ADC0CN AD0WINT 10 ADC0L + SYSCLK REF AIN0 Comb. Logic 00 Start Conversion 01 AD0BUSY (W) Timer 3 Overflow 10 CNVSTR 11 Timer 2 Overflow AD0CM ADC0GTH Analog Multiplexer and PGA Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX input pairs can be programmed to operate in either differential or single-ended mode. This allows the user to select the best measurement technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 6.6), and the Configuration register AMX0CF (Figure 6.7). The table in Figure 6.6 shows AMUX functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 6.7). The PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset. Rev. 1.4 59 C8051F022/3 The Temperature Sensor transfer function is shown in Figure 6.2. The output voltage (VTEMP) is the PGA input when the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. Figure 6.2. Temperature Sensor Transfer Function (Volts) 1.000 0.900 0.800 VTEMP = 0.00286(TEMPC) + 0.776 0.700 for PGA Gain = 1 0.600 0.500 -50 6.2. 0 50 100 (Celsius) ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock divided by the value held in the ADCSC bits of register ADC0CF. 6.2.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by: 1. 2. 3. 4. Writing a ‘1’ to the AD0BUSY bit of ADC0CN; A Timer 3 overflow (i.e. timed continuous conversions); A rising edge detected on the external ADC convert start signal, CNVSTR; A Timer 2 overflow (i.e. timed continuous conversions). The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag (ADC0CN.5). Converted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in Figure 6.11) depending on the programmed state of the AD0LJST bit in the ADC0CN register. When initiating conversions by writing a ‘1’ to AD0BUSY, the AD0INT bit should be polled to determine when a conversion has completed (ADC0 interrupts may also be used). The recommended polling procedure is shown below. Step 1. Step 2. Step 3. Step 4. 60 Write a ‘0’ to AD0INT; Write a ‘1’ to AD0BUSY; Poll AD0INT for ‘1’; Process ADC0 data. Rev. 1.4 C8051F022/3 6.2.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in lowpower track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 6.3). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power trackand-hold mode is also useful when AMUX or PGA settings are frequently changed, to ensure that settling time requirements are met (see Section “6.2.3. Settling Time Requirements” on page 62). Figure 6.3. 10-Bit ADC Track and Conversion Example Timing A. ADC Timing for External Trigger Source CNVSTR (AD0STM[1:0]=10 ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SAR Clocks ADC0TM=1 ADC0TM=0 Low Power or Convert Track Track Or Convert Convert Low Power Mode Convert Track B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to AD0BUSY (AD0STM[1:0]=00, 01, 11) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SAR Clocks ADC0TM=1 Low Power or Convert Track 1 2 3 Convert 4 5 6 7 8 9 Low Power Mode 10 11 12 13 14 15 16 SAR Clocks ADC0TM=0 Track or Convert Convert Rev. 1.4 Track 61 C8051F022/3 6.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 6.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required settling time for a given settling accuracy (SA) may be approximated by Equation 6.1. When measuring the Temperature Sensor output, RTOTAL reduces to RMUX. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these three SAR clocks will meet the settling time requirements. See Table 6.1 on page 74 for minimum settling/tracking time requirements. Equation 6.1. ADC0 Settling Time Requirements n 2 t = ln  ------- × R TOTAL C SAMPLE  SA Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the ADC0 MUX resistance and any external source resistance. n is the ADC resolution in bits (10). Figure 6.4. ADC0 Equivalent Input Circuits Differential Mode Single-Ended Mode MUX Select MUX Select AIN0.x AIN0.x RMUX = 5k RMUX = 5k CSAMPLE = 10pF CSAMPLE = 10pF RCInput= RMUX * CSAMPLE RCInput= RMUX * CSAMPLE CSAMPLE = 10pF AIN0.y RMUX = 5k MUX Select 62 Rev. 1.4 C8051F022/3 Figure 6.5. AMX0CF: AMUX0 Configuration Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - AIN67IC AIN45IC AIN23IC AIN01IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBA Bits7-4: Bit3: Bit2: Bit1: Bit0: NOTE: UNUSED. Read = 0000b; Write = don’t care AIN67IC: AIN6, AIN7 Input Pair Configuration Bit 0: AIN6 and AIN7 are independent single-ended inputs 1: AIN6, AIN7 are (respectively) +, - differential input pair AIN45IC: AIN4, AIN5 Input Pair Configuration Bit 0: AIN4 and AIN5 are independent single-ended inputs 1: AIN4, AIN5 are (respectively) +, - differential input pair AIN23IC: AIN2, AIN3 Input Pair Configuration Bit 0: AIN2 and AIN3 are independent single-ended inputs 1: AIN2, AIN3 are (respectively) +, - differential input pair AIN01IC: AIN0, AIN1 Input Pair Configuration Bit 0: AIN0 and AIN1 are independent single-ended inputs 1: AIN0, AIN1 are (respectively) +, - differential input pair The ADC0 Data Word is in 2’s complement format for channels configured as differential. Rev. 1.4 63 C8051F022/3 Figure 6.6. AMX0SL: AMUX0 Channel Select Register (C8051F022/3) R/W R/W R/W R/W - - - - Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBB Bits7-4: Bits3-0: UNUSED. Read = 0000b; Write = don’t care AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per chart below AMX0AD3-0 AMX0CF Bits 3-0 0000 64 0000 AIN0 0001 +(AIN0) -(AIN1) 0010 AIN0 0011 +(AIN0) -(AIN1) 0100 AIN0 0101 +(AIN0) -(AIN1) 0110 AIN0 0111 +(AIN0) -(AIN1) 1000 AIN0 1001 +(AIN0) -(AIN1) 1010 AIN0 1011 +(AIN0) -(AIN1) 1100 AIN0 1101 +(AIN0) -(AIN1) 1110 AIN0 1111 +(AIN0) -(AIN1) 0001 AIN1 AIN1 AIN1 AIN1 AIN1 AIN1 AIN1 AIN1 0010 0011 0100 0101 0110 0111 1xxx AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 TEMP SENSOR AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 TEMP SENSOR +(AIN2) -(AIN3) AIN4 AIN5 AIN6 AIN7 TEMP SENSOR +(AIN2) -(AIN3) AIN4 AIN5 AIN6 AIN7 TEMP SENSOR AIN2 AIN3 +(AIN4) -(AIN5) AIN6 AIN7 TEMP SENSOR AIN2 AIN3 +(AIN4) -(AIN5) AIN6 AIN7 TEMP SENSOR +(AIN2) -(AIN3) +(AIN4) -(AIN5) AIN6 AIN7 TEMP SENSOR +(AIN2) -(AIN3) +(AIN4) -(AIN5) AIN6 AIN7 TEMP SENSOR AIN2 AIN3 AIN4 AIN5 +(AIN6) -(AIN7) TEMP SENSOR AIN2 AIN3 AIN4 AIN5 +(AIN6) -(AIN7) TEMP SENSOR +(AIN2) -(AIN3) AIN4 AIN5 +(AIN6) -(AIN7) TEMP SENSOR +(AIN2) -(AIN3) AIN4 AIN5 +(AIN6) -(AIN7) TEMP SENSOR AIN2 AIN3 +(AIN4) -(AIN5) +(AIN6) -(AIN7) TEMP SENSOR AIN2 AIN3 +(AIN4) -(AIN5) +(AIN6) -(AIN7) TEMP SENSOR +(AIN2) -(AIN3) +(AIN4) -(AIN5) +(AIN6) -(AIN7) TEMP SENSOR +(AIN2) -(AIN3) +(AIN4) -(AIN5) +(AIN6) -(AIN7) TEMP SENSOR Rev. 1.4 C8051F022/3 Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3) R/W R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBC Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in AD0SC4-0, and CLKSAR0 refers to the desired ADC0 SAR clock. See Table 6.1 on page 74 for SAR clock setting requirements. SYSCLK AD0SC = ----------------------- – 1 CLK SAR0 Bits2-0: AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA) 000: Gain = 1 001: Gain = 2 010: Gain = 4 011: Gain = 8 10x: Gain = 16 11x: Gain = 0.5 Rev. 1.4 65 C8051F022/3 Figure 6.8. ADC0CN: ADC0 Control Register (C8051F022/3) R/W R/W AD0EN AD0TM Bit7 Bit6 R/W R/W R/W AD0INT AD0BUSY AD0CM1 Bit5 Bit4 Bit3 R/W R/W AD0CM0 AD0WINT Bit2 Bit1 R/W Bit0 (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3-2: Bit1: Bit0: 66 Reset Value AD0LJST 00000000 SFR Address: 0xE8 AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. AD0TM: ADC Track Mode Bit 0: When the ADC is enabled, tracking is continuous unless a conversion is in process 1: Tracking Defined by ADSTM1-0 bits AD0INT: ADC0 Conversion Complete Interrupt Flag. This flag must be cleared by software. 0: ADC0 has not completed a data conversion since the last time this flag was cleared. 1: ADC0 has completed a data conversion. AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY. 1: ADC0 Conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0STM1-0 = 00b AD0CM1-0: ADC0 Start of Conversion Mode Select. If AD0TM = 0: 00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY. 01: ADC0 conversion initiated on overflow of Timer 3. 10: ADC0 conversion initiated on rising edge of external CNVSTR. 11: ADC0 conversion initiated on overflow of Timer 2. If AD0TM = 1: 00: Tracking starts with the write of ‘1’ to AD0BUSY and lasts for 3 SAR clocks, followed by conversion. 01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks, followed by conversion. 10: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks, followed by conversion. AD0WINT: ADC0 Window Compare Interrupt Flag. This bit must be cleared by software. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. Rev. 1.4 C8051F022/3 Figure 6.9. ADC0H: ADC0 Data Word MSB Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBF Bits7-0: ADC Data Word High-Order Bits. For ADLJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the 10-bit ADC Data Word. For ADLJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC Data Word. Figure 6.10. ADC0L: ADC0 Data Word LSB Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBE Bits7-0: ADC Data Word Low-Order Bits. For ADLJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit ADC Data Word. For ADLJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit ADC Data Word. Bits 5-0 will always read ‘0’. Rev. 1.4 67 C8051F022/3 Figure 6.11. ADC0 Data Word Example (C8051F022/3) 10-bit ADC Data Word appears in the ADC Data Word Registers as follows: ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0 (ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise = 000000b). ADC0H[7:0]:ADC0L[7:6], if ADLJST = 1 (ADC0L[5:0] = 000000b). Example: ADC Data Word Conversion Map, AIN0 Input in Single-Ended Mode (AMX0CF = 0x00, AMX0SL = 0x00) ADC0H:ADC0L ADC0H:ADC0L AIN0-AGND (Volts) (ADLJST = 0) (ADLJST = 1) VREF * (1023/1024) 0x03FF 0xFFC0 VREF / 2 0x0200 0x8000 VREF * (511/1024) 0x01FF 0x7FC0 0 0x0000 0x0000 Example: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair (AMX0CF = 0x01, AMX0SL = 0x00) ADC0H:ADC0L ADC0H:ADC0L AIN0-AGND (Volts) (ADLJST = 0) (ADLJST = 1) VREF * (511/512) 0x01FF 0x7FC0 VREF / 2 0x0100 0x4000 VREF * (1/512) 0x0001 0x0040 0 0x0000 0x0000 -VREF * (1/512) 0xFFFF (-1) 0xFFC0 -VREF / 2 0xFF00 (-256) 0xC000 -VREF 0xFE00 (-512) 0x8000 ADLJST = 0: Gain Code = Vin × --------------- × 2 n ; ‘n’ = 10 for Single-Ended; ‘n’=9 for Differential. VREF 68 Rev. 1.4 C8051F022/3 6.3. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. The high and low bytes of the reference words are loaded into the ADC0 Greater-Than and ADC0 Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Reference comparisons are shown starting on page 70. Notice that the window detector flag can be asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers. Figure 6.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xC5 Bits7-0: High byte of ADC0 Greater-Than Data Word. Figure 6.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xC4 Bits7-0: Low byte of ADC0 Greater-Than Data Word. Figure 6.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC7 Bits7-0: High byte of ADC0 Less-Than Data Word. Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F022/3) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xC6 Bits7-0: Low byte of ADC0 Less-Than Data Word. Rev. 1.4 69 C8051F022/3 Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage (AD0 - AGND) REF x (1023/1024) Input Voltage (AD0 - AGND) ADC Data Word 0x03FF REF x (1023/1024) ADC Data Word 0x03FF ADWINT not affected ADWINT=1 0x0201 REF x (512/1024) 0x0200 0x0201 ADC0LTH:ADC0LTL REF x (512/1024) 0x01FF 0x0200 0x01FF ADWINT=1 0x0101 REF x (256/1024) 0x0100 0x0101 ADC0GTH:ADC0GTL REF x (256/1024) 0x00FF 0x0100 ADC0LTH:ADC0LTL ADWINT=1 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0200 and > 0x0100. 70 ADWINT not affected 0x00FF ADWINT not affected 0 ADC0GTH:ADC0GTL 0x0000 Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0x0200. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is > 0x0200 or < 0x0100. Rev. 1.4 C8051F022/3 Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage (AD0 - AD1) ADC Data Word Input Voltage (AD0 - AD1) ADC Data Word REF x (511/512) 0x01FF REF x (511/512) 0x01FF ADWINT not affected ADWINT=1 0x0101 REF x (256/512) 0x0100 0x0101 ADC0LTH:ADC0LTL REF x (256/512) 0x00FF 0x0100 0x00FF ADWINT=1 0x0000 REF x (-1/512) 0xFFFF 0x0000 ADC0GTH:ADC0GTL REF x (-1/512) 0xFFFE 0xFFFF ADWINT not affected ADC0LTH:ADC0LTL 0xFFFE ADWINT=1 ADWINT not affected -REF ADC0GTH:ADC0GTL 0xFE00 Given: AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0100 and > 0xFFFF. (In two’s-complement math, 0xFFFF = -1.) -REF 0xFE00 Given: AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTL = 0xFFFF, ADC0GTH:ADC0GTL = 0x0100. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0xFFFF or > 0x0100. (In two’s-complement math, 0xFFFF = -1.) Rev. 1.4 71 C8051F022/3 Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage (AD0 - AGND) REF x (1023/1024) Input Voltage (AD0 - AGND) ADC Data Word REF x (1023/1024) 0xFFC0 ADC Data Word 0xFFC0 ADWINT not affected ADWINT=1 0x8040 REF x (512/1024) 0x8000 0x8040 REF x (512/1024) ADC0LTH:ADC0LTL 0x7FC0 0x8000 0x7FC0 ADWINT=1 0x4040 REF x (256/1024) 0x4000 0x4040 REF x (256/1024) ADC0GTH:ADC0GTL 0x3FC0 0x4000 ADC0LTH:ADC0LTL ADWINT=1 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1, ADC0LTH:ADC0LTL = 0x8000, ADC0GTH:ADC0GTL = 0x4000. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x8000 and > 0x4000. 72 ADWINT not affected 0x3FC0 ADWINT not affected 0 ADC0GTH:ADC0GTL 0x0000 Given: AMX0SL = 0x00, AMX0CF = 0x00, ADLJST = 1, ADC0LTH:ADC0LTL = 0x4000, ADC0GTH:ADC0GTL = 0x8000. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x4000 or > 0x8000. Rev. 1.4 C8051F022/3 Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage (AD0 - AD1) ADC Data Word Input Voltage (AD0 - AD1) ADC Data Word REF x (511/512) 0x7FC0 REF x (511/512) 0x7FC0 ADWINT not affected ADWINT=1 0x2040 REF x (128/512) 0x2000 0x2040 ADC0LTH:ADC0LTL REF x (128/512) 0x1FC0 0x2000 0x1FC0 ADWINT=1 0x0000 REF x (-1/512) 0xFFC0 0x0000 ADC0GTH:ADC0GTL REF x (-1/512) 0xFF80 0xFFC0 ADWINT not affected ADC0LTH:ADC0LTL 0xFF80 ADWINT=1 ADWINT not affected -REF ADC0GTH:ADC0GTL 0x8000 Given: AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0xFFC0. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x2000 and > 0xFFC0. (Two’s-complement math.) -REF 0x8000 Given: AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTL = 0xFFC0, ADC0GTH:ADC0GTL = 0x2000. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0xFFC0 or > 0x2000. (Two’s-complement math.) Rev. 1.4 73 C8051F022/3 Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F022/3) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient bits ±1 LSB ±1 LSB ±0.5 LSB -1.5±0.5 LSB ±0.25 ppm/°C DYNAMIC PERFORMANCE (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps Signal-to-Noise Plus Distortion Total Harmonic Distortion 59 Up to the 5th harmonic Spurious-Free Dynamic Range dB -70 dB 80 dB CONVERSION RATE SAR Clock Frequency 2.5 MHz Conversion Time in SAR Clocks 16 clocks Track/Hold Acquisition Time 1.5 µs Throughput Rate 100 ksps 0 VREF V AGND AV+ V ANALOG INPUTS Input Voltage Range Single-ended operation *Common-mode Voltage Range Differential operation Input Capacitance 10 pF TEMPERATURE SENSOR Nonlinearity -1.0 Absolute Accuracy +1.0 °C ±3 °C Gain PGA Gain = 1 2.86 mV/°C Offset PGA Gain = 1, Temp = 0°C 0.776 V Operating Mode, 100 ksps 450 POWER SPECIFICATIONS Power Supply Current (AV+ supplied to ADC) Power Supply Rejection 74 ±0.3 Rev. 1.4 900 µA mV/V C8051F020/1/2/3 7. ADC1 (8-BIT ADC) The ADC1 subsystem for the C8051F020/1/2/3 consists of an 8-channel, configurable analog multiplexer (AMUX1), a programmable gain amplifier (PGA1), and a 500 ksps, 8-bit successive-approximation-register ADC with integrated track-and-hold (see block diagram in Figure 7.1). The AMUX1, PGA1, and Data Conversion Modes, are all configurable under software control via the Special Function Registers shown in Figure 7.1. The ADC1 subsystem (8-bit ADC, track-and-hold and PGA) is enabled only when the AD1EN bit in the ADC1 Control register (ADC1CN) is set to logic 1. The ADC1 subsystem is in low power shutdown when this bit is logic 0. The voltage reference used by ADC1 is selected as described in Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91 for C8051F020/2 devices, or Section “10. VOLTAGE REFERENCE (C8051F021/3)” on page 93 for C8051F021/3 devices. SYSCLK REF Figure 7.1. ADC1 Functional Block Diagram AV+ AD1EN AIN1.0 (P1.0) AIN1.2 (P1.2) AIN1.3 (P1.3) AIN1.4 (P1.4) 8-to-1 AMUX X 8-Bit SAR + - AIN1.5 (P1.5) 8 ADC AGND ADC1 AV+ AIN1.1 (P1.1) AIN1.6 (P1.6) AMX1SL 7.1. ADC1CF 000 Write to AD1BUSY 001 Timer 3 Overflow 010 CNVSTR 011 Timer 2 Overflow 1xx Write to AD0BUSY (synchronized with ADC0) AD1CM Start Conversion AD1EN AD1TM AD1INT AD1BUSY AD1CM2 AD1CM1 AD1CM0 AMP1GN1 AMP1GN0 AD1SC4 AD1SC3 AD1SC2 AD1SC1 AD1SC0 AMX1AD2 AMX1AD1 AMX1AD0 AD1CM AIN1.7 (P1.7) ADC1CN Analog Multiplexer and PGA Eight ADC1 channels are available for measurement, as selected by the AMX1SL register (see Figure 7.5). The PGA amplifies the ADC1 output signal by an amount determined by the states of the AMP1GN2-0 bits in the ADC1 Configuration register, ADC1CF (Figure 7.4). The PGA can be software-programmed for gains of 0.5, 1, 2, or 4. Gain defaults to 0.5 on reset. Important Note: AIN1 pins also function as Port 1 I/O pins, and must be configured as analog inputs when used as ADC1 inputs. To configure an AIN1 pin for analog input, set to ‘0’ the corresponding bit in register P1MDIN. Port 1 pins selected as analog inputs are skipped by the Digital I/O Crossbar. See Section “17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])” on page 165 for more information on configuring the AIN1 pins. Rev. 1.4 75 C8051F020/1/2/3 7.2. ADC1 Modes of Operation ADC1 has a maximum conversion speed of 500 ksps. The ADC1 conversion clock (SAR1 clock) is a divided version of the system clock, determined by the AD1SC bits in the ADC1CF register (system clock divided by (AD1SC + 1) for 0 ≤ AD1SC ≤ 31). The maximum ADC1 conversion clock is 6 MHz. 7.2.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC1 Start of Conversion Mode bits (AD1CM2-0) in register ADC1CN. Conversions may be initiated by: 1. Writing a ‘1’ to the AD1BUSY bit of ADC1CN; 2. A Timer 3 overflow (i.e. timed continuous conversions); 3. A rising edge detected on the external ADC convert start signal, CNVSTR; 4. A Timer 2 overflow (i.e. timed continuous conversions); 5. Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC1 and ADC0 with a single software command). During conversion, the AD1BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The falling edge of AD1BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC1CN. Converted data is available in the ADC1 data word, ADC1. When a conversion is initiated by writing a ‘1’ to AD1BUSY, it is recommended to poll AD1INT to determine when the conversion is complete. The recommended procedure is: Step 1. Step 2. Step 3. Step 4. 7.2.2. Write a ‘0’ to AD1INT; Write a ‘1’ to AD1BUSY; Poll AD1INT for ‘1’; Process ADC1 data. Tracking Modes The AD1TM bit in register ADC1CN controls the ADC1 track-and-hold mode. In its default state, the ADC1 input is continuously tracked, except when a conversion is in progress. When the AD1TM bit is logic 1, ADC1 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC1 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 7.2). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power Track-and-Hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time requirements described in Section “7.2.3. Settling Time Requirements” on page 78. 76 Rev. 1.4 C8051F020/1/2/3 Figure 7.2. ADC1 Track and Conversion Example Timing A. ADC Timing for External Trigger Source CNVSTR (AD1CM[2:0]=010) 1 2 3 4 5 6 7 8 9 SAR1 Clocks AD1TM=1 AD1TM=0 Low Power or Convert Track Track or Convert Convert Low Power Mode Convert Track B. ADC Timing for Internal Trigger Source Write '1' to AD1BUSY, Timer 3 Overflow, Timer 2 Overflow, Write '1' to AD0BUSY (AD1CM[2:0]=000, 001, 011, 1xx) 1 2 3 4 5 6 7 8 9 10 11 12 SAR1 Clocks AD1TM=1 Low Power or Convert Track 1 2 3 Convert 4 5 6 7 8 Low Power Mode 9 SAR1 Clocks AD1TM=0 Track or Convert Convert Rev. 1.4 Track 77 C8051F020/1/2/3 7.2.3. Settling Time Requirements When the ADC1 input configuration is changed (i.e., a different MUX or PGA selection), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is determined by the ADC1 MUX resistance, the ADC1 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC1 input circuit. The required ADC1 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1. Note that in low-power tracking mode, three SAR1 clocks are used for tracking at the start of every conversion. For most applications, these three SAR1 clocks will meet the tracking requirements. See Table 7.1 for absolute minimum settling time requirements. Equation 7.1. ADC1 Settling Time Requirements n 2 t = ln  ------- × R TOTAL C SAMPLE  SA Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required tracking time in seconds RTOTAL is the sum of the ADC1 MUX resistance and any external source resistance. n is the ADC resolution in bits (8). Figure 7.3. ADC1 Equivalent Input Circuit MUX Select AIN1.x RMUX = 5k CSAMPLE = 10pF RCInput= RMUX * CSAMPLE 78 Rev. 1.4 C8051F020/1/2/3 Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3) R/W R/W R/W R/W R/W R/W AD1SC4 AD1SC3 AD1SC2 AD1SC1 AD1SC0 - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W Reset Value AMP1GN1 AMP1GN0 11111000 Bit1 Bit0 SFR Address: 0xAB Bits7-3: AD1SC4-0: ADC1 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD1SC refers to the 5-bit value held in AD1SC4-0. SAR conversion clock requirements are given in Table 7.1. SYSCLK AD1SC = ----------------------- – 1 CLK SAR1 Bit2: Bits1-0: UNUSED. Read = 0b. Write = don’t care. AMP1GN1-0: ADC1 Internal Amplifier Gain (PGA) 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3) R/W R/W R/W R/W R/W - - - - - Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value AMX1AD2 AMX1AD1 AMX1AD0 00000000 Bit2 Bit1 Bit0 SFR Address: 0xAC Bits7-3: Bits2-0: UNUSED. Read = 00000b; Write = don’t care AMX1AD2-0: AMX1 Address Bits 000-111b: ADC1 Inputs selected as follows: 000: AIN1.0 selected 001: AIN1.1 selected 010: AIN1.2 selected 011: AIN1.3 selected 100: AIN1.4 selected 101: AIN1.5 selected 110: AIN1.6 selected 111: AIN1.7 selected Rev. 1.4 79 C8051F020/1/2/3 Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3) R/W R/W AD1EN AD1TM Bit7 Bit6 R/W R/W R/W AD1INT AD1BUSY AD1CM2 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value AD1CM1 AD1CM0 - 00000000 Bit2 Bit1 Bit0 SFR Address: 0xAA Bit7: Bit6: Bit5: Bit4: Bit3-1: Bit0: 80 AD1EN: ADC1 Enable Bit. 0: ADC1 Disabled. ADC1 is in low-power shutdown. 1: ADC1 Enabled. ADC1 is active and ready for data conversions. AD1TM: ADC1 Track Mode Bit. 0: Normal Track Mode: When ADC1 is enabled, tracking is continuous unless a conversion is in process. 1: Low-power Track Mode: Tracking Defined by AD1STM2-0 bits (see below). AD1INT: ADC1 Conversion Complete Interrupt Flag. This flag must be cleared by software. 0: ADC1 has not completed a data conversion since the last time this flag was cleared. 1: ADC1 has completed a data conversion. AD1BUSY: ADC1 Busy Bit. Read: 0: ADC1 Conversion is complete or a conversion is not currently in progress. AD1INT is set to logic 1 on the falling edge of AD1BUSY. 1: ADC1 Conversion is in progress. Write: 0: No Effect. 1: Initiates ADC1 Conversion if AD1STM2-0 = 000b AD1CM2-0: ADC1 Start of Conversion Mode Select. AD1TM = 0: 000: ADC1 conversion initiated on every write of ‘1’ to AD1BUSY. 001: ADC1 conversion initiated on overflow of Timer 3. 010: ADC1 conversion initiated on rising edge of external CNVSTR. 011: ADC1 conversion initiated on overflow of Timer 2. 1xx: ADC1 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 softwarecommanded conversions). AD1TM = 1: 000: Tracking initiated on write of ‘1’ to AD1BUSY and lasts 3 SAR1 clocks, followed by conversion. 001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR1 clocks, followed by conversion. 010: ADC1 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR1 clocks, followed by conversion. 1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR1 clocks, followed by conversion. UNUSED. Read = 0b. Write = don’t care. Rev. 1.4 C8051F020/1/2/3 Figure 7.7. ADC1: ADC1 Data Word Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9C Bits7-0: ADC1 Data Word. Figure 7.8. ADC1 Data Word Example 8-bit ADC Data Word appears in the ADC1 Data Word Register as follows: Example: ADC1 Data Word Conversion Map, AIN1.0 Input (AMX1SL = 0x00) AIN1.0-AGND ADC1 (Volts) VREF * (255/256) 0xFF VREF / 2 0x80 VREF * (127/256) 0x7F 0 0x00 Gain Code = Vin × --------------- × 256 VREF Rev. 1.4 81 C8051F020/1/2/3 Table 7.1. ADC1 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF1 = 2.40 V (REFBE=0), PGA1 = 1, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient bits ±1 LSB ±1 LSB 0.5±0.3 LSB -1±0.2 LSB TBD ppm/°C DYNAMIC PERFORMANCE (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 500 ksps Signal-to-Noise Plus Distortion Total Harmonic Distortion 45 Up to the 5th harmonic Spurious-Free Dynamic Range 47 dB -51 dB 52 dB CONVERSION RATE SAR Conversion Clock 6 Conversion Time in SAR Clocks Track/Hold Acquisition Time MHz 8 clocks 300 ns Throughput Rate 500 ksps VREF V ANALOG INPUTS Input Voltage Range 0 Input Capacitance 10 pF POWER SPECIFICATIONS Power Supply Current (AV+ supplied to ADC1) Operating Mode, 500 ksps Power Supply Rejection 82 420 ±0.3 Rev. 1.4 900 µA mV/V C8051F020/1/2/3 8. DACS, 12-BIT VOLTAGE MODE Each C8051F020/1/2/3 device includes two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each DAC has an output swing of 0V to (VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The DACs may be enabled/disabled via their corresponding control registers, DAC0CN and DAC1CN. While disabled, the DAC output is maintained in a high-impedance state, and the DAC supply current falls to 1 µA or less. The voltage reference for each DAC is supplied at the VREFD pin (C8051F020/2 devices) or the VREF pin (C8051F021/3 devices). Note that the VREF pin on C8051F021/3 devices may be driven by the internal voltage reference or an external source. If the internal voltage reference is used it must be enabled in order for the DAC outputs to be valid. See Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91 or Section “10. VOLTAGE REFERENCE (C8051F021/3)” on page 93 for more information on configuring the voltage reference for the DACs. 8.1. DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 operation is identical. Note that reads from DAC0L return pre-latch data, meaning the value read is the same as the last value written to this register, not the value at the DAC0L latch. Reads from DAC0H always return the value at the DAC0H latch. Timer 2 REF Dig. MUX 8 12 DAC0 DAC0 8 AGND Timer 2 Timer 3 8 Timer 4 Latch 8 DAC1H DAC0L Latch AV+ DAC1EN DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 REF 8 8 Dig. MUX Latch 8 Latch DAC1H AV+ DAC1L DAC1CN Timer 4 DAC0H DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 DAC0H DAC0CN DAC0EN Timer 3 Figure 8.1. DAC Functional Block Diagram 12 DAC1 DAC1 8 AGND Rev. 1.4 83 C8051F020/1/2/3 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” on a write to the high-byte of the DAC0 data register (DAC0H). It’s important to note that writes to DAC0L are held, and have no effect on the DAC0 output until a write to DAC0H takes place. If writing a full 12-bit word to the DAC data registers, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers. Data is latched into DAC0 after a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-bit mode by initializing DAC0L to the desired value (typically 0x00), and writing data to only DAC0H (also see Section 8.2 for information on formatting the 12-bit DAC data word within the 16-bit SFR space). 8.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow independently of the processor, the DAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the DAC output. When the DAC0MD bits (DAC0CN.[4:3]) are set to ‘01’, ‘10’, or ‘11’, writes to both DAC data registers (DAC0L and DAC0H) are held until an associated Timer overflow event (Timer 3, Timer 4, or Timer 2, respectively) occurs, at which time the DAC0H:DAC0L contents are copied to the DAC input latches allowing the DAC output to change to the new value. 8.2. DAC Output Scaling/Justification In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data within the DAC input registers. This action would typically require one or more load and shift operations, adding software overhead and slowing DAC throughput. To alleviate this problem, the data-formatting feature provides a means for the user to program the orientation of the DAC0 data word within data registers DAC0H and DAC0L. The three DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data word orientations as shown in the DAC0CN register definition. DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and DAC1 are given in Table 8.1. 84 Rev. 1.4 C8051F020/1/2/3 Figure 8.2. DAC0H: DAC0 High Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xD3 Bits7-0: DAC0 Data Word Most Significant Byte. Figure 8.3. DAC0L: DAC0 Low Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD2 Bits7-0: DAC0 Data Word Least Significant Byte. Rev. 1.4 85 C8051F020/1/2/3 Figure 8.4. DAC0CN: DAC0 Control Register R/W R/W R/W DAC0EN - - Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 Bit7: Bits6-5: Bits4-3: Bits2-0: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational. UNUSED. Read = 00b; Write = don’t care. DAC0MD1-0: DAC0 Mode Bits. 00: DAC output updates occur on a write to DAC0H. 01: DAC output updates occur on Timer 3 overflow. 10: DAC output updates occur on Timer 4 overflow. 11: DAC output updates occur on Timer 2 overflow. DAC0DF2-0: DAC0 Data Format Bits: 000: The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least significant byte is in DAC0L. DAC0H DAC0L MSB 001: LSB The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least significant 7-bits are in DAC0L[7:1]. DAC0H DAC0L MSB 010: LSB The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least significant 6-bits are in DAC0L[7:2]. DAC0H DAC0L MSB 011: LSB The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least significant 5-bits are in DAC0L[7:3]. DAC0H DAC0L MSB 1xx: LSB The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least significant 4-bits are in DAC0L[7:4]. DAC0H DAC0L MSB 86 LSB Rev. 1.4 C8051F020/1/2/3 Figure 8.5. DAC1H: DAC1 High Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xD6 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 8.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xD5 Bits7-0: DAC1 Data Word Least Significant Byte. Rev. 1.4 87 C8051F020/1/2/3 Figure 8.7. DAC1CN: DAC1 Control Register R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD7 Bit7: Bits6-5: Bits4-3: Bits2-0: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational. UNUSED. Read = 00b; Write = don’t care. DAC1MD1-0: DAC1 Mode Bits: 00: DAC output updates occur on a write to DAC1H. 01: DAC output updates occur on Timer 3 overflow. 10: DAC output updates occur on Timer 4 overflow. 11: DAC output updates occur on Timer 2 overflow. DAC1DF2: DAC1 Data Format Bits: 000: The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least significant byte is in DAC1L. DAC1H DAC1L MSB 001: LSB The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least significant 7-bits are in DAC1L[7:1]. DAC1H DAC1L MSB 010: LSB The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least significant 6-bits are in DAC1L[7:2]. DAC1H DAC1L MSB 011: LSB The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least significant 5-bits are in DAC1L[7:3]. DAC1H DAC1L MSB 1xx: LSB The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least significant 4-bits are in DAC1L[7:4]. DAC1H DAC1L MSB 88 LSB Rev. 1.4 C8051F020/1/2/3 Table 8.1. DAC Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 bits Integral Nonlinearity ±2 LSB Differential Nonlinearity ±1 Output Noise No Output Filter 100 kHz Output Filter 10 kHz Output Filter 250 128 41 Offset Error Data Word = 0x014 ±3 Offset Tempco LSB µVrms ±30 6 mV ppm/°C Gain Error ±20 Gain-Error Tempco 10 ppm/°C VDD Power Supply Rejection Ratio -60 dB 100 kΩ 300 µA 15 mA 0.44 V/µs 10 µs Output Impedance in Shutdown Mode DACnEN = 0 Output Sink Current Output Short-Circuit Current Data Word = 0xFFF ±60 mV DYNAMIC PERFORMANCE Voltage Output Slew Rate Load = 40pF Output Settling Time to 1/2 LSB Load = 40pF, Output swing from code 0xFFF to 0x014 Output Voltage Swing 0 Startup Time VREF1LSB V 10 µs 60 ppm ANALOG OUTPUTS Load Regulation IL = 0.01mA to 0.3mA at code 0xFFF POWER CONSUMPTION (each DAC) Power Supply Current (AV+ supplied to DAC) Data Word = 0x7FF 110 Rev. 1.4 400 µA 89 C8051F020/1/2/3 Notes 90 Rev. 1.4 C8051F020/1/2/3 9. VOLTAGE REFERENCE (C8051F020/2) The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage reference output. ADC0 may also reference the DAC0 output internally, and ADC1 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure 9.1. The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system components or to the voltage reference input pins shown in Figure 9.1. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to AGND, as shown in Figure 9.1. See Table 9.1 for voltage reference specifications. The Reference Control Register, REF0CN (defined in Figure 9.2) enables/disables the internal reference generator and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the on-board reference generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether the voltage reference is derived from the on-chip reference or supplied by an off-chip source. If neither the ADC nor the DAC are being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD1VRS select the ADC0 and ADC1 voltage reference sources, respectively. The electrical specifications for the Voltage Reference circuit are given in Table 9.1. Figure 9.1. Voltage Reference Functional Block Diagram AD0VRS AD1VRS TEMPE BIASE REFBE REF0CN ADC1 AV+ 1 Ref VREF1 0 VDD External Voltage Reference Circuit R1 ADC0 VREF0 DGND 0 Ref 1 DAC0 VREFD Ref DAC1 BIASE EN VREF x2 4.7μF 0.1μF Bias to ADCs, DACs 1.2V Band-Gap REFBE Recommended Bypass Capacitors Rev. 1.4 91 C8051F020/1/2/3 The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 43 for C8051F020/1 devices, or Section “6.1. Analog Multiplexer and PGA” on page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in undefined data. Figure 9.2. REF0CN: Reference Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - AD0VRS AD1VRS TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7-5: Bit4: Bit3: Bit2: Bit1: Bit0: UNUSED. Read = 000b; Write = don’t care. AD0VRS: ADC0 Voltage Reference Select 0: ADC0 voltage reference from VREF0 pin. 1: ADC0 voltage reference from DAC0 output. AD1VRS: ADC1 Voltage Reference Select 0: ADC1 voltage reference from VREF1 pin. 1: ADC1 voltage reference from AV+. TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor Off. 1: Internal Temperature Sensor On. BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC or DAC). 0: Internal Bias Generator Off. 1: Internal Bias Generator On. REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer Off. 1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin. Table 9.1. Voltage Reference Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS 2.36 2.43 2.48 V 30 mA INTERNAL REFERENCE (REFBE = 1) Output Voltage 25°C ambient VREF Short-Circuit Current VREF Temperature Coefficient 15 ppm/°C 0.5 ppm/µA Load Regulation Load = 0 to 200 µA to AGND VREF Turn-on Time 1 4.7µF tantalum, 0.1µF ceramic bypass 2 ms VREF Turn-on Time 2 0.1µF ceramic bypass 20 µs VREF Turn-on Time 3 no bypass cap 10 µs EXTERNAL REFERENCE (REFBE = 0) Input Voltage Range 1.00 Input Current 92 0 Rev. 1.4 (AV+) 0.3 V 1 µA C8051F020/1/2/3 10. VOLTAGE REFERENCE (C8051F021/3) The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system components or to the VREFA input pin shown in Figure 10.1. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to AGND, as shown in Figure 10.1. See Table 10.1 for voltage reference specifications. The VREFA pin provides a voltage reference input for ADC0 and ADC1. ADC0 may also reference the DAC0 output internally, and ADC1 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure 10.1. The Reference Control Register, REF0CN (defined in Figure 10.2) enables/disables the internal reference generator and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the on-board reference generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to 1 (this includes any time a DAC is used). If the internal reference is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if either ADC is used, regardless of whether the voltage reference is derived from the on-chip reference or supplied by an off-chip source. If neither the ADC nor the DAC are being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD1VRS select the ADC0 and ADC1 voltage reference sources, respectively. The electrical specifications for the Voltage Reference are given in Table 10.1. Figure 10.1. Voltage Reference Functional Block Diagram AD0VRS AD1VRS TEMPE BIASE REFBE REF0CN ADC1 AV+ VDD 1 External Voltage Reference Circuit Ref R1 0 VREFA DGND ADC0 0 Ref 1 DAC0 Ref DAC1 BIASE EN VREF x2 4.7μF 0.1μF Bias to ADCs, DACs 1.2V Band-Gap REFBE Recommended Bypass Capacitors Rev. 1.4 93 C8051F020/1/2/3 The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 43 for C8051F020/1 devices, or Section “6.1. Analog Multiplexer and PGA” on page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in undefined data. Figure 10.2. REF0CN: Reference Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - AD0VRS AD1VRS TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7-5: Bit4: Bit3: Bit2: Bit1: Bit0: UNUSED. Read = 000b; Write = don’t care. AD0VRS: ADC0 Voltage Reference Select 0: ADC0 voltage reference from VREFA pin. 1: ADC0 voltage reference from DAC0 output. AD1VRS: ADC1 Voltage Reference Select 0: ADC1 voltage reference from VREFA pin. 1: ADC1 voltage reference from AV+. TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor Off. 1: Internal Temperature Sensor On. BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC or DAC). 0: Internal Bias Generator Off. 1: Internal Bias Generator On. REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer Off. 1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin. Table 10.1. Voltage Reference Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS 2.36 2.43 2.48 V 30 mA INTERNAL REFERENCE (REFBE = 1) Output Voltage 25°C ambient VREF Short-Circuit Current VREF Temperature Coefficient 15 ppm/°C 0.5 ppm/µA Load Regulation Load = 0 to 200 µA to AGND VREF Turn-on Time 1 4.7µF tantalum, 0.1µF ceramic bypass 2 ms VREF Turn-on Time 2 0.1µF ceramic bypass 20 µs VREF Turn-on Time 3 no bypass cap 10 µs EXTERNAL REFERENCE (REFBE = 0) Input Voltage Range 1.00 Input Current 94 0 Rev. 1.4 (AV+) 0.3 V 1 µA C8051F020/1/2/3 11. COMPARATORS Each MCU includes two on-board voltage comparators as shown in Figure 11.1. The inputs of each Comparator are available at the package pins. The output of each comparator is optionally available at the package pins via the I/O crossbar. When assigned to package pins, each comparator output can be programmed to operate in open drain or push-pull modes. See Section “17. PORT INPUT/OUTPUT” on page 161 for Crossbar and port initialization details. The hysteresis of each comparator is software-programmable via its respective Comparator control register (CPT0CN and CPT1CN for Comparator0 and Comparator1, respectively). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The output of the comparator can be polled in software, or can be used as an interrupt source. Each comparator can be individually enabled or disabled (shutdown). When disabled, the comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, its interrupt capability is suspended and its supply current falls to less than 1 µA. Comparator inputs can be externally driven from -0.25 V to (AV+) + 0.25 V without damage or upset. The Comparator0 hysteresis is programmed using bits 3-0 in the Comparator0 Control Register CPT0CN (shown in Figure 11.1). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits; In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits. See Table 11.1 on page 99 for hysteresis level specifications. Comparator interrupts can be generated on rising-edge and/or falling-edge output transitions. (For interrupt enable and priority control, see Section “12.3. Interrupt Handler” on page 116). The CP0FIF flag is set upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set upon the Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software. The Output State of Comparator0 can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic Figure 11.1. Comparator Functional Block Diagram CP0EN CPT0CN CP0OUT CP0RIF CP0FIF AV+ CP0HYP1 CP0HYP0 Reset Decision Tree CP0HYN1 CP0HYN0 CP0+ + CP0- - D CLR AGND CPT1CN CP1EN CP1OUT CP1RIF SET Q D Q SET CLR Q Q (SYNCHRONIZER) Crossbar Interrupt Handler AV+ CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 CP1+ + CP1- - D AGND Rev. 1.4 SET CLR Q Q D SET CLR Q Q (SYNCHRONIZER) Crossbar Interrupt Handler 95 C8051F020/1/2/3 Figure 11.2. Comparator Hysteresis Plot VIN+ VIN- CP0+ CP0- + CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VIN+ VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Negative Hysteresis Maximum Positive Hysteresis 0. Comparator0 can also be programmed as a reset source; for details, see Section “13.6. Comparator0 Reset” on page 129. The operation of Comparator1 is identical to that of Comparator0, though Comparator1 may not be configured as a reset source. Comparator1 is controlled by the CPT1CN Register (Figure 11.4). The complete electrical specifications for the Comparators are given in Table 11.1. 96 Rev. 1.4 C8051F020/1/2/3 Figure 11.3. CPT0CN: Comparator0 Control Register R/W R/W R/W R/W CP0EN CP0OUT CP0RIF CP0FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9E Bit7: Bit6: Bit5: Bit4: Bits3-2: Bits1-0: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage on CP0+ > CP0-. CP0RIF: Comparator0 Rising-Edge Interrupt Flag. 0: No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared. 1: Comparator0 Rising Edge Interrupt has occurred. CP0FIF: Comparator0 Falling-Edge Interrupt Flag. 0: No Comparator0 Falling-Edge Interrupt has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge Interrupt has occurred. CP0HYP1-0: Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 2 mV. 10: Positive Hysteresis = 4 mV. 11: Positive Hysteresis = 10 mV. CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 2 mV. 10: Negative Hysteresis = 4 mV. 11: Negative Hysteresis = 10 mV. Rev. 1.4 97 C8051F020/1/2/3 Figure 11.4. CPT1CN: Comparator1 Control Register R/W R/W R/W R/W CP1EN CP1OUT CP1RIF CP1FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9F Bit7: Bit6: Bit5: Bit4: Bits3-2: Bits1-0: 98 CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: Voltage on CP1+ > CP1-. CP1RIF: Comparator1 Rising-Edge Interrupt Flag. 0: No Comparator1 Rising Edge Interrupt has occurred since this flag was last cleared. 1: Comparator1 Rising Edge Interrupt has occurred. CP1FIF: Comparator1 Falling-Edge Interrupt Flag. 0: No Comparator1 Falling-Edge Interrupt has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge Interrupt has occurred. CP1HYP1-0: Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 2 mV. 10: Positive Hysteresis = 4 mV. 11: Positive Hysteresis = 10 mV. CP1HYN1-0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 2 mV. 10: Negative Hysteresis = 4 mV. 11: Negative Hysteresis = 10 mV. Rev. 1.4 C8051F020/1/2/3 Table 11.1. Comparator Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS Response Time 1 CP+ - CP- = 100 mV 4 µs Response Time 2 CP+ - CP- = 10 mV 12 µs Common-Mode Rejection Ratio 1.5 4 mV/V 0 1 mV Positive Hysteresis 1 CPnHYP1-0 = 00 Positive Hysteresis 2 CPnHYP1-0 = 01 2 4.5 7 mV Positive Hysteresis 3 CPnHYP1-0 = 10 4 9 13 mV Positive Hysteresis 4 CPnHYP1-0 = 11 10 17 25 mV Negative Hysteresis 1 CPnHYN1-0 = 00 0 1 mV Negative Hysteresis 2 CPnHYN1-0 = 01 2 4.5 7 mV Negative Hysteresis 3 CPnHYN1-0 = 10 4 9 13 mV Negative Hysteresis 4 CPnHYN1-0 = 11 10 17 25 mV (AV+) + 0.25 V Inverting or Non-Inverting Input Voltage Range -0.25 Input Capacitance 7 Input Bias Current -5 Input Offset Voltage -10 0.001 pF +5 nA +10 mV POWER SUPPLY Power-up Time CPnEN from 0 to 1 20 Power Supply Rejection Supply Current Operating Mode (each comparator) at DC Rev. 1.4 µs 0.1 1 mV/V 1.5 10 µA 99 C8051F020/1/2/3 Notes 100 Rev. 1.4 C8051F020/1/2/3 12. CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see description in Section 22), two full-duplex UARTs (see description in Section 20 and Section 21), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 12.2.6), and 8/4 byte-wide I/O Ports (see description in Section 17). The CIP-51 also includes on-chip debug hardware (see description in Section 24), and interfaces directly with the MCUs' analog and digital subsystems providing a complete data acquisition or controlsystem solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes the following features: Fully Compatible with MCS-51 Instruction Set 25 MIPS Peak Throughput with 25 MHz Clock 0 to 25 MHz Clock Frequency 256 Bytes of Internal RAM 8/4 Byte-Wide I/O Ports - Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security Figure 12.1. CIP-51 Block Diagram D8 D8 B REGISTER STACK POINTER D8 D8 D8 DATA BUS ACCUMULATOR TMP1 TMP2 SRAM ADDRESS REGISTER PSW D8 D8 D8 ALU SRAM (256 X 8) D8 DATA BUS DATA BUS SFR_ADDRESS BUFFER D8 DATA POINTER D8 D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER DATA BUS - PROGRAM COUNTER (PC) PRGM. ADDRESS REG. MEM_ADDRESS D8 MEM_CONTROL A16 MEMORY INTERFACE MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET D8 CONTROL LOGIC SYSTEM_IRQs CLOCK D8 STOP IDLE POWER CONTROL REGISTER INTERRUPT INTERFACE EMULATION_IRQ D8 Rev. 1.4 101 C8051F020/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 Programming and Debugging Support A JTAG-based serial interface is provided for in-system programming of the FLASH program memory and communication with on-chip debug support logic. The re-programmable FLASH can also be read and changed a single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers, or other on-chip resources. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. 12.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 12.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 12.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 12.1.2. MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip XRAM, and accessing on-chip program FLASH memory. The FLASH access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data storage (see Section “15. FLASH 102 Rev. 1.4 C8051F020/1/2/3 MEMORY” on page 139). The External Memory Interface provides a fast access to off-chip XRAM (or memorymapped peripherals) via the MOVX instruction. Refer to Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for details. Table 12.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri Description ARITHMETIC OPERATIONS Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust A LOGICAL OPERATIONS AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Rev. 1.4 Bytes Clock Cycles 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 4 8 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 103 C8051F020/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A DATA TRANSFER Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A BOOLEAN MANIPULATION Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C 104 2 2 3 1 1 1 1 1 1 1 Clock Cycles 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 3 3 3 3 3 3 3 2 2 1 2 2 2 1 2 1 2 1 1 2 1 2 1 Bytes Rev. 1.4 C8051F020/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit PROGRAM BRANCHING Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP 2 2 2 2 2 2 2 2 2 3 3 3 Clock Cycles 2 2 2 2 2 2 2 2/3 2/3 3/4 3/4 3/4 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 3 4 5 5 3 4 3 3 2/3 2/3 3/4 3/4 3/4 4/5 2/3 3/4 1 Bytes Rev. 1.4 105 C8051F020/1/2/3 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 64Kbyte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. 106 Rev. 1.4 C8051F020/1/2/3 12.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. There are 256 bytes of internal data memory and 64k bytes of internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in Figure 12.2. Figure 12.2. Memory Map DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (FLASH) 0x1007F 0x10000 0xFFFF 0xFE00 0xFDFF Scrachpad Memory (DATA only) RESERVED 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Off-chip XRAM space 0x1000 0x0FFF 0x0000 XRAM - 4096 Bytes (accessable using MOVX instruction) 12.2.1. Program Memory The CIP-51 has a 64k byte program memory space. The MCU implements 65536 bytes of this program memory space as in-system re-programmed FLASH memory, organized in a contiguous block from addresses 0x0000 to 0xFFFF. Note: 512 bytes (0xEE00 to 0xFFFF) of this memory are reserved for factory use and are not available for user program storage. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “15. FLASH MEMORY” on page 139 for further details. Rev. 1.4 107 C8051F020/1/2/3 12.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 12.2 illustrates the data memory organization of the CIP-51. 12.2.3. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in Figure 12.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 12.2.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 12.2.5. Stack A programmer's stack can be located anywhere in the 256 byte data memory. The stack area is designated using the Stack Pointer (SP, address 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07; therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. The MCUs also have built-in hardware for a stack record. The stack record is a 32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register, and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. 108 Rev. 1.4 C8051F020/1/2/3 12.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 12.2 lists the SFRs implemented in the CIP-51 System Controller. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 12.3, for a detailed description of each register. Table 12.2. Special Function Register (SFR) Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 SPI0CN B ADC0CN ACC PCA0CN PSW T2CON SMB0CN IP P3 IE P2 SCON0 P1 TCON P0 0(8) PCA0H PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPH3 PCA0CPH4 SCON1 SBUF1 SADDR1 TL4 TH4 EIP1 PCA0L PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4 XBR0 XBR1 XBR2 RCAP4L RCAP4H EIE1 PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 REF0CN DAC0L DAC0H DAC0CN DAC1L DAC1H T4CON RCAP2L RCAP2H TL2 TH2 SMB0STA SMB0DAT SMB0ADR ADC0GTL ADC0GTH ADC0LTL SADEN0 AMX0CF AMX0SL ADC0CF P1MDIN ADC0L OSCXCN OSCICN P74OUT† FLSCL SADDR0 ADC1CN ADC1CF AMX1SL P3IF SADEN1 EMI0TC EMI0CF P0MDOUT P1MDOUT P2MDOUT SBUF0 SPI0CFG SPI0DAT ADC1 SPI0CKR CPT0CN TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H P7† TMOD TL0 TL1 TH0 TH1 CKCON SP DPL DPH P4† P5† P6† 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) WDTCN EIP2 RSTSRC EIE2 DAC1CN SMB0CR ADC0LTH ADC0H FLACL EMI0CN P3MDOUT CPT1CN PSCTL PCON 7(F) (bit addressable) Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC5 ADC0 Greater-Than High ADC0GTL 0xC4 ADC0 Greater-Than Low ADC0H 0xBF ADC0 Data Word High ADC0L 0xBE ADC0 Data Word Low Rev. 1.4 Page No. page 115 page 49*, page 65** page 50*, page 66** page 53*, page 69** page 53*, page 69** page 51*, page 67** page 51*, page 67** 109 C8051F020/1/2/3 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description ADC0LTH 0xC7 ADC0 Less-Than High ADC0LTL 0xC6 ADC0 Less-Than Low ADC1CF 0xAB ADC1 Analog Multiplexer Configuration ADC1CN 0xAA ADC1 Control ADC1 0x9C ADC1 Data Word AMX0CF 0xBA ADC0 Multiplexer Configuration AMX0SL 0xBB ADC0 Multiplexer Channel Select AMX1SL 0xAC ADC1 Analog Multiplexer Channel Select B 0xF0 B Register CKCON 0x8E Clock Control CPT0CN 0x9E Comparator 0 Control CPT1CN 0x9F Comparator 1 Control DAC0CN 0xD4 DAC0 Control DAC0H 0xD3 DAC0 High DAC0L 0xD2 DAC0 Low DAC1CN 0xD7 DAC1 Control DAC1H 0xD6 DAC1 High Byte DAC1L 0xD5 DAC1 Low Byte DPH 0x83 Data Pointer High DPL 0x82 Data Pointer Low EIE1 0xE6 Extended Interrupt Enable 1 EIE2 0xE7 Extended Interrupt Enable 2 EIP1 0xF6 External Interrupt Priority 1 EIP2 0xF7 External Interrupt Priority 2 EMI0CN 0xAF External Memory Interface Control EMI0CF 0xA3 EMIF Configuration EMI0TC 0xA1 EMIF Timing Control FLACL 0xB7 FLASH Access Limit FLSCL 0xB6 FLASH Scale IE 0xA8 Interrupt Enable IP 0xB8 Interrupt Priority OSCICN 0xB2 Internal Oscillator Control OSCXCN 0xB1 External Oscillator Control P0 0x80 Port 0 Latch P0MDOUT 0xA4 Port 0 Output Mode Configuration P1 0x90 Port 1 Latch P1MDIN 0xBD Port 1 Input Mode P1MDOUT 0xA5 Port 1 Output Mode Configuration P2 0xA0 Port 2 Latch P2MDOUT 0xA6 Port 2 Output Mode Configuration P3 0xB0 Port 3 Latch P3IF 0xAD Port 3 Interrupt Flags P3MDOUT 0xA7 Port 3 Output Mode Configuration †P4 0x84 Port 4 Latch †P5 0x85 Port 5 Latch 110 Rev. 1.4 Page No. page 53*, page 69** page 53*, page 69** page 79 page 80 page 81 page 47*, page 63** page 48*, page 64** page 79 page 115 page 226 page 97 page 98 page 86 page 85 page 85 page 88 page 87 page 87 page 113 page 113 page 121 page 122 page 123 page 124 page 147 page 147 page 152 page 142 page 143 page 119 page 120 page 136 page 137 page 173 page 173 page 174 page 174 page 175 page 175 page 175 page 176 page 177 page 176 page 180† page 180† C8051F020/1/2/3 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description †P6 0x86 Port 6 Latch †P7 0x96 Port 7 Latch †P74OUT 0xB5 Port 4 through 7 Output Mode PCA0CN 0xD8 PCA Control PCA0CPH0 0xFA PCA Capture 0 High PCA0CPH1 0xFB PCA Capture 1 High PCA0CPH2 0xFC PCA Capture 2 High PCA0CPH3 0xFD PCA Capture 3 High PCA0CPH4 0xFE PCA Capture 4 High PCA0CPL0 0xEA PCA Capture 0 Low PCA0CPL1 0xEB PCA Capture 1 Low PCA0CPL2 0xEC PCA Capture 2 Low PCA0CPL3 0xED PCA Capture 3 Low PCA0CPL4 0xEE PCA Capture 4 Low PCA0CPM0 0xDA PCA Module 0 Mode Register PCA0CPM1 0xDB PCA Module 1 Mode Register PCA0CPM2 0xDC PCA Module 2 Mode Register PCA0CPM3 0xDD PCA Module 3 Mode Register PCA0CPM4 0xDE PCA Module 4 Mode Register PCA0H 0xF9 PCA Counter High PCA0L 0xE9 PCA Counter Low PCA0MD 0xD9 PCA Mode PCON 0x87 Power Control PSCTL 0x8F Program Store R/W Control PSW 0xD0 Program Status Word RCAP2H 0xCB Timer/Counter 2 Capture High RCAP2L 0xCA Timer/Counter 2 Capture Low RCAP4H 0xE5 Timer/Counter 4 Capture High RCAP4L 0xE4 Timer/Counter 4 Capture Low REF0CN 0xD1 Programmable Voltage Reference Control RSTSRC 0xEF Reset Source Register SADDR0 0xA9 UART0 Slave Address SADDR1 0xF3 UART1 Slave Address SADEN0 0xB9 UART0 Slave Address Enable SADEN1 0xAE UART1 Slave Address Enable SBUF0 0x99 UART0 Data Buffer SBUF1 0xF2 UART1 Data Buffer SCON0 0x98 UART0 Control SCON1 0xF1 UART1 Control SMB0ADR 0xC3 SMBus Slave Address SMB0CN 0xC0 SMBus Control SMB0CR 0xCF SMBus Clock Rate SMB0DAT 0xC2 SMBus Data SMB0STA 0xC1 SMBus Status SP 0x81 Stack Pointer Rev. 1.4 Page No. page 181† page 181† page 179† page 259 page 263 page 263 page 263 page 263 page 263 page 263 page 263 page 263 page 263 page 263 page 261 page 261 page 261 page 261 page 261 page 262 page 262 page 260 page 126 page 144 page 114 page 239 page 239 page 248 page 248 page 92†, page 94†† page 132 page 214 page 224 page 214 page 224 page 214 page 224 page 213 page 223 page 193 page 191 page 192 page 193 page 194 page 113 111 C8051F020/1/2/3 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description SPI0CFG 0x9A SPI Configuration SPI0CKR 0x9D SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT 0x9B SPI Data T2CON 0xC8 Timer/Counter 2 Control T4CON 0xC9 Timer/Counter 4 Control TCON 0x88 Timer/Counter Control TH0 0x8C Timer/Counter 0 High TH1 0x8D Timer/Counter 1 High TH2 0xCD Timer/Counter 2 High TH4 0xF5 Timer/Counter 4 High TL0 0x8A Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TL2 0xCC Timer/Counter 2 Low TL4 0xF4 Timer/Counter 4 Low TMOD 0x89 Timer/Counter Mode TMR3CN 0x91 Timer 3 Control TMR3H 0x95 Timer 3 High TMR3L 0x94 Timer 3 Low TMR3RLH 0x93 Timer 3 Reload High TMR3RLL 0x92 Timer 3 Reload Low WDTCN 0xFF Watchdog Timer Control XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xE3 Port I/O Crossbar Control 2 0x97, 0xA2, 0xB3, 0xB4, Reserved 0xCE, 0xDF * Refers to a register in the C8051F020/1 only. ** Refers to a register in the C8051F022/3 only. † Refers to a register in the C8051F020/2 only. †† Refers to a register in the C8051F021/3 only. 112 Rev. 1.4 Page No. page 201 page 203 page 202 page 203 page 238 page 247 page 231 page 233 page 233 page 239 page 248 page 233 page 233 page 239 page 248 page 232 page 241 page 242 page 242 page 242 page 241 page 131 page 170 page 171 page 172 C8051F020/1/2/3 12.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. Figure 12.3. SP: Stack Pointer R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x81 Bits7-0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. Figure 12.4. DPL: Data Pointer Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0x82 Bits7-0: DPL: Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and FLASH memory. Figure 12.5. DPH: Data Pointer High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x83 Bits7-0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and FLASH memory. Rev. 1.4 113 C8051F020/1/2/3 Figure 12.6. PSW: Program Status Word R/W R/W R/W R/W R/W R/W CY Bit7 R/W R AC F0 RS1 RS0 Bit6 Bit5 Bit4 Bit3 OV F1 PARITY 00000000 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bits4-3: Bit1: Bit0: 114 0xD0 CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to 0 by all other arithmetic operations. AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations. F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. RS1-RS0: Register Bank Select. These bits select which register bank is used during register accesses. RS1 0 0 1 1 Bit2: Reset Value RS0 0 1 0 1 Register Bank 0 1 2 3 Address 0x00 - 0x07 0x08 - 0x0F 0x10 - 0x17 0x18 - 0x1F OV: Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). It is cleared to 0 by all other arithmetic operations. F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. PARITY: Parity Flag. This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. Rev. 1.4 C8051F020/1/2/3 Figure 12.7. ACC: Accumulator R/W R/W R/W R/W R/W R/W R/W R/W ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0xE0 ACC: Accumulator. This register is the accumulator for arithmetic operations. Figure 12.8. B: B Register R/W R/W R/W R/W R/W R/W R/W R/W B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0xF0 B: B Register. This register serves as a second accumulator for certain arithmetic operations. Rev. 1.4 115 C8051F020/1/2/3 12.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interruptpending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 12.3.1. MCU Interrupt Sources and Vectors The MCUs support 22 interrupt sources. Software can simulate an interrupt event by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 12.4. Refer to the datasheet section associated with a particular onchip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 12.3.2. External Interrupts Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. The remaining 2 external interrupts (External Interrupts 6-7) are edge-sensitive inputs configurable as active-low or active-high. The interrupt-pending flags and configuration bits for these interrupts are in the Port 3 Interrupt Flag Register shown in Figure “17.19 P3IF: Port3 Interrupt Flag Register” on page 177. 116 Rev. 1.4 C8051F020/1/2/3 Interrupt Vector Priority Pending Flag Order Reset 0x0000 Top External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow 0x0003 0x000B 0x0013 0x001B 0 1 2 3 UART0 0x0023 4 Timer 2 Overflow (or EXF2) 0x002B Serial Peripheral Interface None Cleared by HW? Interrupt Source Bit addressable? Table 12.4. Interrupt Summary N/A N/A Always Enabled EX0 (IE.0) ET0 (IE.1) EX1 (IE.2) ET1 (IE.3) Always Highest PX0 (IP.0) PT0 (IP.1) PX1 (IP.2) PT1 (IP.3) Y ES0 (IE.4) PS0 (IP.4) 5 Y 0x0033 6 SPIF (SPI0CN.7) Y SMBus Interface 0x003B 7 SI (SMB0CN.3) Y ADC0 Window Comparator 0x0043 8 ET2 (IE.5) ESPI0 (EIE1.0) ESMB0 (EIE1.1) EWADC0 (EIE1.2) PT2 (IP.5) PSPI0 (EIP1.0) PSMB0 (EIP1.1) PWADC0 (EIP1.2) Programmable Counter Array 0x004B 9 EPCA0 (EIE1.3) PPCA0 (EIP1.3) Comparator 0 Falling Edge 0x0053 10 Comparator 0 Rising Edge 0x005B 11 Comparator 1 Falling Edge 0x0063 12 Comparator 1 Rising Edge 0x006B 13 Timer 3 Overflow 0x0073 14 TF3 (TMR3CN.7) ADC0 End of Conversion 0x007B 15 AD0INT (ADC0CN.5) Timer 4 Overflow 0x0083 16 TF4 (T4CON.7) ADC1 End of Conversion 0x008B 17 AD1INT (ADC1CN.5) External Interrupt 6 0x0093 18 IE6 (P3IF.5) External Interrupt 7 0x009B 19 IE7 (P3IF.6) ECP0F (EIE1.4) ECP0R (EIE1.5) ECP1F (EIE1.6) ECP1R (EIE1.7) ET3 (EIE2.0) EADC0 (EIE2.1) ET4 (EIE2.2) EADC1 (EIE2.3) EX6 (EIE2.4) EX7 (EIE2.5) PCP0F (EIP1.4) PCP0R (EIP1.5) PCP1F (EIP1.6) PCP1F (EIP1.7) PT3 (EIP2.0) PADC0 (EIP2.1) PT4 (EIP2.2) PADC1 (EIP2.3) PX6 (EIP2.4) PX7 (EIP2.5) UART1 0x00A3 20 ES1 PS1 External Crystal OSC Ready 0x00AB 21 EXVLD (EIE2.7) PXVLD (EIP2.7) RI1 (SCON1.0) TI1 (SCON1.1) XTLVLD (OSCXCN.7) Rev. 1.4 Y Y Y Y Y Y Y Priority Control IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3) TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2 (T2CON.7) AD0WINT (ADC0CN.2) CF (PCA0CN.7) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) CP0RIF (CPT0CN.5) CP1FIF (CPT1CN.4) CP1RIF (CPT1CN.5) Y Y Y Y Enable Flag 117 C8051F020/1/2/3 12.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 12.4. 12.3.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. 118 Rev. 1.4 C8051F020/1/2/3 12.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Figure 12.9. IE: Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 0xA8 EA: Enable All Interrupts. This bit globally enables/disables all interrupts. When set to ‘0’, individual interrupt mask settings are overridden. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. IEGF0: General Purpose Flag 0. This is a general purpose flag for use under software control. ET2: Enabler Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2 flag (T2CON.7). ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7). EX1: Enable External Interrupt 1. This bit sets the masking of external interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 pin. ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag (TCON.5). EX0: Enable External Interrupt 0. This bit sets the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 pin. Rev. 1.4 119 C8051F020/1/2/3 Figure 12.10. IP: Interrupt Priority R/W R/W R/W R/W R/W R/W R/W R/W - - PT2 PS0 PT1 PX1 PT0 PX0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 120 UNUSED. Read = 11b, Write = don't care. PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt priority determined by default priority order. 1: Timer 2 interrupts set to high priority level. PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt priority determined by default priority order. 1: UART0 interrupts set to high priority level. PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt priority determined by default priority order. 1: Timer 1 interrupts set to high priority level. PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 priority determined by default priority order. 1: External Interrupt 1 set to high priority level. PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt priority determined by default priority order. 1: Timer 0 interrupt set to high priority level. PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 priority determined by default priority order. 1: External Interrupt 0 set to high priority level. Rev. 1.4 Reset Value 0xB8 C8051F020/1/2/3 Figure 12.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ECP1R ECP1F ECP0R ECP0F EPCA0 EWADC0 ESMB0 ESPI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 Rising Edge interrupt. 1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.5). ECP1F: Enable Comparator (CP1) Falling Edge Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 Falling Edge interrupt. 1: Enable interrupt requests generated by the CP1FIF flag (CPT1CN.4). ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 Rising Edge interrupt. 1: Enable interrupt requests generated by the CP0RIF flag (CPT0CN.5). ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 Falling Edge interrupt. 1: Enable interrupt requests generated by the CP0FIF flag (CPT0CN.4). EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. EWADC0: Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison Interrupt. 1: Enable Interrupt requests generated by ADC0 Window Comparisons. ESMB0: Enable System Management Bus (SMBus0) Interrupt. This bit sets the masking of the SMBus interrupt. 0: Disable all SMBus interrupts. 1: Enable interrupt requests generated by the SI flag (SMB0CN.3). ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of SPI0 interrupt. 0: Disable all SPI0 interrupts. 1: Enable Interrupt requests generated by the SPIF flag (SPI0CN.7). Rev. 1.4 121 C8051F020/1/2/3 Figure 12.12. EIE2: Extended Interrupt Enable 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EXVLD ES1 EX7 EX6 EADC1 ET4 EADC0 ET3 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE7 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 122 EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt. This bit sets the masking of the XTLVLD interrupt. 0: Disable XTLVLD interrupt. 1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7) ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. EX7: Enable External Interrupt 7. This bit sets the masking of External Interrupt 7. 0: Disable External Interrupt 7. 1: Enable interrupt requests generated by the External Interrupt 7 input pin. EX6: Enable External Interrupt 6. This bit sets the masking of External Interrupt 6. 0: Disable External Interrupt 6. 1: Enable interrupt requests generated by the External Interrupt 6 input pin. EADC1: Enable ADC1 End Of Conversion Interrupt. This bit sets the masking of the ADC1 End of Conversion interrupt. 0: Disable ADC1 End of Conversion interrupt. 1: Enable interrupt requests generated by the ADC1 End of Conversion Interrupt. ET4: Enable Timer 4 Interrupt This bit sets the masking of the Timer 4 interrupt. 0: Disable Timer 4 interrupt. 1: Enable interrupt requests generated by the TF4 flag (T4CON.7). EADC0: Enable ADC0 End of Conversion Interrupt. This bit sets the masking of the ADC0 End of Conversion Interrupt. 0: Disable ADC0 Conversion Interrupt. 1: Enable interrupt requests generated by the ADC0 Conversion Interrupt. ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable all Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7). Rev. 1.4 C8051F020/1/2/3 Figure 12.13. EIP1: Extended Interrupt Priority 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PCP1R PCP1F PCP0R PCP0F PPCA0 PWADC0 PSMB0 PSPI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: PCP1R: Comparator1 (CP1) Rising Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 rising interrupt set to low priority level. 1: CP1 rising interrupt set to high priority level. PCP1F: Comparator1 (CP1) Falling Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 falling interrupt set to low priority level. 1: CP1 falling interrupt set to high priority level. PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 rising interrupt set to low priority level. 1: CP0 rising interrupt set to high priority level. PCP0F: Comparator0 (CP0) Falling Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 falling interrupt set to low priority level. 1: CP0 falling interrupt set to high priority level. PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. PWADC0: ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. PSMB0: System Management Bus (SMBus0) Interrupt Priority Control. This bit sets the priority of the SMBus0 interrupt. 0: SMBus interrupt set to low priority level. 1: SMBus interrupt set to high priority level. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. Rev. 1.4 123 C8051F020/1/2/3 Figure 12.14. EIP2: Extended Interrupt Priority 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PXVLD EP1 PX7 PX6 PADC1 PT4 PADC0 PT3 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF7 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 124 PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control. This bit sets the priority of the XTLVLD interrupt. 0: XTLVLD interrupt set to low priority level. 1: XTLVLD interrupt set to high priority level. EP1: UART1 Interrupt Priority Control. This bit sets the priority of the UART1 interrupt. 0: UART1 interrupt set to low priority. 1: UART1 interrupt set to high priority. PX7: External Interrupt 7 Priority Control. This bit sets the priority of the External Interrupt 7. 0: External Interrupt 7 set to low priority level. 1: External Interrupt 7 set to high priority level. PX6: External Interrupt 6 Priority Control. This bit sets the priority of the External Interrupt 6. 0: External Interrupt 6 set to low priority level. 1: External Interrupt 6 set to high priority level. PADC1: ADC1 End Of Conversion Interrupt Priority Control. This bit sets the priority of the ADC1 End of Conversion interrupt. 0: ADC1 End of Conversion interrupt set to low priority. 1: ADC1 End of Conversion interrupt set to low priority. PT4: Timer 4 Interrupt Priority Control. This bit sets the priority of the Timer 4 interrupt. 0: Timer 4 interrupt set to low priority. 1: Timer 4 interrupt set to low priority. PADC0: ADC End of Conversion Interrupt Priority Control. This bit sets the priority of the ADC0 End of Conversion Interrupt. 0: ADC0 End of Conversion interrupt set to low priority level. 1: ADC0 End of Conversion interrupt set to high priority level. PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupts. 0: Timer 3 interrupt priority determined by default priority order. 1: Timer 3 interrupt set to high priority level. Rev. 1.4 C8051F020/1/2/3 12.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 12.15 describes the Power Control Register (PCON) used to control the CIP-51's power management modes. Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or serial buses, draw little power whenever they are not in use. Turning off the Flash memory saves power, similar to entering Idle mode. Turning off the oscillator saves even more power, but requires a reset to restart the MCU. 12.4.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “13.8. Watchdog Timer Reset” on page 129 for more information on the use and configuration of the WDT. 12.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes. In Stop mode, the CPU and internal oscillator are stopped, effectively shutting down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 µs. Rev. 1.4 125 C8051F020/1/2/3 Figure 12.15. PCON: Power Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SMOD0 SSTAT0 Reserved SMOD1 SSTAT1 Reserved STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x87 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 126 SMOD0: UART0 Baud Rate Doubler Enable. This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations described in the UART0 section. 0: UART0 baud rate divide-by-two enabled. 1: UART0 baud rate divide-by-two disabled. SSTAT0: UART0 Enhanced Status Mode Select. This bit controls the access mode of the SM20-SM00 bits in register SCON0. 0: Reads/writes of SM20-SM00 access the SM20-SM00 UART0 mode setting. 1: Reads/writes of SM20-SM00 access the Framing Error (FE0), RX Overrun (RXOV0), and TX Collision (TXCOL0) status bits. Reserved. Read is undefined. Must write 0. SMOD1: UART1 Baud Rate Doubler Enable. This bit enables/disables the divide-by-two function of the UART1 baud rate logic for configurations described in the UART1 section. 0: UART1 baud rate divide-by-two enabled. 1: UART1 baud rate divide-by-two disabled. SSTAT1: UART1 Enhanced Status Mode Select. This bit controls the access mode of the SM21-SM01 bits in SCON1. 0: Reads/writes of SM21-SM01 access the SM21-SM01 UART1 mode setting. 1: Reads/writes of SM21-SM01 access the Framing Error (FE1), RX Overrun (RXOV1), and TX Collision (TXCOL1) status bits. Reserved. Read is undefined. Must write 0. STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. 1: CIP-51 forced into power-down mode. (Turns off internal oscillator). IDLE: IDLE Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’. 1: CIP-51 forced into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) Rev. 1.4 C8051F020/1/2/3 13. RESET SOURCES Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • • • • CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External port pins are forced to a known state Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered. The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins to a high state. Note that weak pull-ups are disabled during the reset, and enabled when the device exits the reset state. This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST pin is driven low until the end of the VDD reset timeout. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator running at 2 MHz. Refer to Section “14. OSCILLATORS” on page 135 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Section “13.8. Watchdog Timer Reset” on page 129). Once the system clock source is stable, program execution begins at location 0x0000. There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external CNVSTR signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset source is described in the following sections. Figure 13.1. Reset Sources VDD CNVSTR Supply Monitor Crossbar (CNVSTR reset enable) (wired-OR) /RST Comparator0 CP0+ + - CP0- (CP0 reset enable) Missing Clock Detector (oneshot) System Clock XTAL1 OSC Clock Select PRE WDT Enable MCD Enable Internal Clock Generator Reset Funnel WDT EN EN XTAL2 Supply Reset Timeout + - WDT Strobe (Port I/O) Software Reset CIP-51 Microcontroller Core System Reset Extended Interrupt Handler Rev. 1.4 127 C8051F020/1/2/3 13.1. Power-on Reset The C8051F020/1/2/3 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the VRST level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for the Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the 100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor function is enabled by tying the MONEN pin directly to VDD. This is the recommended configuration for the MONEN pin. . volts Figure 13.2. Reset Timing 2.70 VRST 2.55 VD D 2.0 1.0 t Logic HIGH /RST 100ms 100ms Logic LOW Power-On Reset 13.2. VDD Monitor Reset Power-fail Reset When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset (see Figure 13.2). Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag is set to logic 1, the data may no longer be valid. 128 Rev. 1.4 C8051F020/1/2/3 13.3. External Reset The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting the /RST pin low will cause the MCU to enter the reset state. It may be desirable to provide an external pull-up and/or decoupling of the /RST pin to avoid erroneous noise-induced resets. The MCU will remain in reset until at least 12 clock cycles after the active-low /RST signal is removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 13.4. Software Forced Reset Writing a ‘1’ to the SWRSEF bit forces a Software Reset as described in Section 13.1. 13.5. Missing Clock Detector Reset The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the system clock goes away for more than 100 µs, the one-shot will time out and generate a reset. After a Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. Setting the MSCLKE bit in the OSCICN register (see Section “14. OSCILLATORS” on page 135) enables the Missing Clock Detector. 13.6. Comparator0 Reset Comparator0 can be configured as a reset input by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled using CPT0CN.7 (see Section “11. COMPARATORS” on page 95) prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (CP0+ pin) is less than the inverting input voltage (CP0- pin), the MCU is put into the reset state. After a Comparator0 Reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. 13.7. External CNVSTR Pin Reset The external CNVSTR signal can be configured as a reset input by writing a ‘1’ to the CNVRSEF flag (RSTSRC.6). The CNVSTR signal can appear on any of the P0, P1, P2 or P3 I/O pins as described in Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 163. Note that the Crossbar must be configured for the CNVSTR signal to be routed to the appropriate Port I/O. The Crossbar should be configured and enabled before the CNVRSEF is set. When configured as a reset, CNVSTR is active-low and level sensitive. After a CNVSTR reset, the CNVRSEF flag (RSTSRC.6) will read ‘1’ signifying CNVSTR as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. 13.8. Watchdog Timer Reset The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences a software/hardware malfunction preventing the software from restarting the WDT, the WDT will overflow and cause a reset. This should prevent the system from running out of control. Following a reset the WDT is automatically enabled and running with the default maximum time interval. If desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset. The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 13.3. Rev. 1.4 129 C8051F020/1/2/3 13.8.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's application software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT is enabled and reset as a result of any system reset. 13.8.2. Disable WDT Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates disabling the WDT: CLR MOV MOV SETB EA WDTCN,#0DEh WDTCN,#0ADh EA ; disable all interrupts ; disable software watchdog timer ; re-enable interrupts The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes. 13.8.3. Disable WDT Lockout Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use the watchdog should write 0xFF to WDTCN in the initialization code. 13.8.4. Setting WDT Interval WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation: 4 3 + WDTCN [ 2 – 0 ] × T sysclk ; where Tsysclk is the system clock period. For a 2 MHz system clock, this provides an interval range of 0.032 ms to 524 ms. WDTCN.7 must be logic 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b after a system reset. 130 Rev. 1.4 C8051F020/1/2/3 Figure 13.3. WDTCN: Watchdog Timer Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: xxxxx111 0xFF Bits7-0: Bit4: Bits2-0: WDT Control Writing 0xA5 both enables and reloads the WDT. Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT. Writing 0xFF locks out the disable feature. Watchdog Status Bit (when Read) Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. Rev. 1.4 131 C8051F020/1/2/3 Figure 13.4. RSTSRC: Reset Source Register R Bit7 R/W R/W CNVRSEF C0RSEF Bit6 Bit5 R/W SWRSEF Bit4 R R WDTRSF MCDRSF Bit3 Bit2 R/W R PORSF PINRSF Reset Value Variable Bit1 Bit0 SFR Address: 0xEF (Note: Do not use read-modify-write operations on this register.) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 132 Reserved. CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR is not a reset source. 1: CNVSTR is a reset source (active low). Read: 0: Source of prior reset was not CNVSTR. 1: Source of prior reset was CNVSTR. C0RSEF: Comparator0 Reset Enable and Flag Write: 0: Comparator0 is not a reset source. 1: Comparator0 is a reset source (active low). Read: 0: Source of prior reset was not Comparator0. 1: Source of prior reset was Comparator0. SWRSF: Software Reset Force and Flag Write: 0: No Effect. 1: Forces an internal reset. /RST pin is not affected. Read: 0: Prior reset source was not a write to the SWRSF bit. 1: Prior reset source was a write to the SWRSF bit. WDTRSF: Watchdog Timer Reset Flag 0: Source of prior reset was not WDT timeout. 1: Source of prior reset was WDT timeout. MCDRSF: Missing Clock Detector Flag 0: Source of prior reset was not Missing Clock Detector timeout. 1: Source of prior reset was Missing Clock Detector timeout. PORSF: Power-On Reset Force and Flag Write: 0: No effect. 1: Forces a Power-On Reset. /RST is driven low. Read: 0: Source of prior reset was not POR. 1: Source of prior reset was POR. PINRSF: HW Pin Reset Flag 0: Source of prior reset was not /RST pin. 1: Source of prior reset was /RST pin. Rev. 1.4 C8051F020/1/2/3 Table 13.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. PARAMETER CONDITIONS /RST Output High Voltage IOH = -3 mA /RST Output Low Voltage IOL = 8.5 mA, VDD = 2.7 V to 3.6 V MIN VDD 0.7 TYP 0.6 Missing Clock Detector Timeout V V 0.3 x VDD /RST Input Low Voltage Reset Time Delay UNITS V 0.7 x VDD /RST Input High Voltage /RST Input Leakage Current VDD for /RST Output Valid AV+ for /RST Output Valid VDD POR Threshold (VRST) Minimum /RST Low Time to Generate a System Reset MAX /RST = 0.0 V 50 1.0 1.0 2.40 2.55 2.70 10 /RST rising edge after VDD crosses VRST threshold Time from last system clock to reset initiation Rev. 1.4 µA V V V ns 80 100 120 ms 100 220 500 µs 133 C8051F020/1/2/3 Notes 134 Rev. 1.4 C8051F020/1/2/3 14. OSCILLATORS Each MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the system clock. The MCUs operate from the internal oscillator after any reset. This internal oscillator can be enabled/disabled and its frequency can be set using the Internal Oscillator Control Register (OSCICN) as shown in Figure 14.1. The internal oscillator's electrical specifications are given in Table 14.1. Both oscillators are disabled when the /RST pin is held low. The MCUs can run from the internal oscillator permanently, or can switch to the external oscillator if desired using CLKSL bit in the OSCICN Register. The external oscillator requires an external resonator, crystal, capacitor, or RC network connected to the XTAL1/XTAL2 pins (see Table 14.1). The oscillator circuit must be configured for one of these sources in the OSCXCN register. An external CMOS clock can also provide the system clock; in this configuration, the XTAL1 pin is used as the CMOS clock input. The XTAL1 and XTAL2 pins are NOT 5V tolerant. Figure 14.1. Oscillator Diagram IFRDY CLKSL IOSCEN IFCN1 IFCN0 MSCLKE OSCICN VDD EN Internal Clock Generator opt. 2 AV+ SYSCLK AV+ opt. 1 opt. 3 XTAL1 XTAL2 XTAL1 XTAL1 Input Circuit XTAL2 OSC AGND XFCN2 XFCN1 XFCN0 XTAL1 XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 opt. 4 OSCXCN Rev. 1.4 135 C8051F020/1/2/3 Figure 14.2. OSCICN: Internal Oscillator Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value MSCLKE - - IFRDY CLKSL IOSCEN IFCN1 IFCN0 00010100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB2 Bit7: Bits6-5: Bit4: Bit3: Bit2: Bits1-0: MSCLKE: Missing Clock Enable Bit 0: Missing Clock Detector Disabled 1: Missing Clock Detector Enabled; reset triggered if clock is missing for more than 100 µs UNUSED. Read = 00b, Write = don't care IFRDY: Internal Oscillator Frequency Ready Flag 0: Internal Oscillator Frequency not running at speed specified by the IFCN bits. 1: Internal Oscillator Frequency running at speed specified by the IFCN bits. CLKSL: System Clock Source Select Bit 0: Uses Internal Oscillator as System Clock. 1: Uses External Oscillator as System Clock. IOSCEN: Internal Oscillator Enable Bit 0: Internal Oscillator Disabled 1: Internal Oscillator Enabled IFCN1-0: Internal Oscillator Frequency Control Bits 00: Internal Oscillator typical frequency is 2 MHz. 01: Internal Oscillator typical frequency is 4 MHz. 10: Internal Oscillator typical frequency is 8 MHz. 11: Internal Oscillator typical frequency is 16 MHz. Table 14.1. Internal Oscillator Electrical Characteristics VDD = 2.7V to 3.6V; Ta = -40°C to +85°C PARAMETER CONDITIONS OSCICN.[1:0] = 00 Internal Oscillator Frequency Internal Oscillator Current Consumption (from VDD) 136 MIN 1.5 TYP 2 OSCICN.[1:0] = 01 3.1 4 4.8 OSCICN.[1:0] = 10 6.2 8 9.6 OSCICN.[1:0] = 11 12.3 16 19.2 OSCICN.2 = 1 Rev. 1.4 200 MAX 2.4 UNITS MHz µA C8051F020/1/2/3 Figure 14.3. OSCXCN: External Oscillator Control Register R/W R/W R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value - XFCN2 XFCN1 XFCN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 Bit7: Bits6-4: Bit3: Bits2-0: XTLVLD: Crystal Oscillator Valid Flag (Valid only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable 1: Crystal Oscillator is running and stable XOSCMD2-0: External Oscillator Mode Bits 00x: Off. XTAL1 pin is grounded internally. 010: System Clock from External CMOS Clock on XTAL1 pin. 011: System Clock from External CMOS Clock on XTAL1 pin divided by 2. 10x: RC/C Oscillator Mode with divide by 2 stage. 110: Crystal Oscillator Mode 111: Crystal Oscillator Mode with divide by 2 stage. RESERVED. Read = undefined, Write = don't care XFCN2-0: External Oscillator Frequency Control Bits 000-111: XFCN Crystal (XOSCMD = 11x) RC (XOSCMD = 10x) C (XOSCMD = 10x) 000 f < 12 kHz f < 25 kHz K Factor = 0.44 001 12 kHz < f ≤ 30 kHz 25 kHz < f ≤ 50 kHz K Factor = 1.4 010 30 kHz < f ≤ 95 kHz 50 kHz < f ≤ 100 kHz K Factor = 4.4 011 95 kHz < f ≤ 270 kHz 100 kHz < f ≤ 200 kHz K Factor = 13 100 270 kHz < f ≤ 720 kHz 200 kHz < f ≤ 400 kHz K Factor = 38 101 720 kHz < f ≤ 2.2 MHz 400 kHz < f ≤ 800 kHz K Factor = 100 110 2.2 MHz < f ≤ 6.7 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 420 111 f > 6.7 MHz 1.6 MHz < f ≤ 3.2 MHz K Factor = 1400 CRYSTAL MODE (Circuit from Figure 14.1, Option 1; XOSCMD = 11x) Choose XFCN value to match the crystal or ceramic resonator frequency. RC MODE (Circuit from Figure 14.1, Option 2; XOSCMD = 10x) Choose oscillation frequency range where: f = 1.23(103) / (R * C), where f = frequency of oscillation in MHz C = capacitor value in pF R = Pull-up resistor value in kΩ C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired: f = KF / (C * AV+), where f = frequency of oscillation in MHz C = capacitor value on XTAL1, XTAL2 pins in pF AV+ = Analog Power Supply on MCU in volts Rev. 1.4 137 C8051F020/1/2/3 14.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in Figure 14.3 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b. The Crystal Oscillator Valid Flag (XTLVLD in register OSCXCN) is set to logic 1 by hardware when the external crystal oscillator is running and stable. The XTLVLD detection circuit requires a startup time of at least 1 ms between enabling the oscillator and checking the XTLVLD bit. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Step 2. Step 3. Step 4. Enable the external oscillator. Wait at least 1 ms. Poll for XTLVLD => ‘1’. Switch the system clock to the external oscillator. Important Note: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device, as should the loading capacitors on the crystal pins. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. 14.2. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be as shown in Figure 14.1, Option 2. The capacitor must be no greater than 100 pF; however for small capacitors (less than ~20 pF), the total capacitance may be dominated by PWB parasitic capacitance. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF: f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 * 50 ] = 0.1 MHz = 100 kHz XFCN ≥ log2 ( f / 25 kHz ) XFCN ≥ log2 ( 100 kHz / 25 kHz ) = log2 ( 4 ) XFCN ≥ 2, or code 010b 14.3. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be as shown in Figure 14.1, Option 3. The capacitor must be no greater than 100 pF; however for small capacitors (less than ~20 pF), the total capacitance may be dominated by PWB parasitic capacitance. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF: f = KF / ( C * VDD ) = KF / ( 50 * 3 ) f = KF / 150 If a frequency of roughly 90 kHz is desired, select the K Factor from the table in Figure 14.3 as KF = 13: f = 13 / 150 = 0.087 MHz, or 87 kHz Therefore, the XFCN value to use in this example is 011b. 138 Rev. 1.4 C8051F020/1/2/3 15. FLASH MEMORY The C8051F020/1/2/3 family includes 64k + 128 bytes of on-chip, reprogrammable FLASH memory for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the JTAG interface or by software. Once cleared to logic 0, a FLASH bit must be erased to set it back to logic 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. FLASH write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Refer to Table 15.1 for the electrical characteristics of the FLASH memory. 15.1. Programming The FLASH Memory The simplest means of programming the FLASH memory is through the JTAG interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the JTAG commands to program FLASH memory, see Section “24.2. Flash Programming Commands” on page 268. The FLASH memory can be programmed by software using a MOVX write instruction, with the address and data byte to be programmed provided as normal operands. Before writing to FLASH memory using a MOVX write, FLASH write operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. This directs the MOVX writes to FLASH memory instead of XRAM. The PSWE bit remains set until cleared by software. To avoid errant FLASH writes, it is recommended that interrupts be disabled while the PSWE bit is logic 1. FLASH memory is read using the MOVC read instruction. MOVX reads are always directed to XRAM, regardless of the state of PSWE. To ensure the integrity of FLASH contents, it is strongly recommended that the on-chip VDD monitor be enabled by tying the MONEN pin to VDD in any system which includes code that writes to or erases FLASH memory from software. A write to FLASH memory can clear bits but cannot set them; only an erase operation can set bits in FLASH. A byte location to be programmed must be erased before a new value can be written. The 64k byte FLASH memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). The following steps illustrate the algorithm for programming FLASH by user software. Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. Disable interrupts. Set FLWE (FLSCL.0) to enable FLASH writes/erases via user software. Set PSEE (PSCTL.1) to enable FLASH erases. Set PSWE (PSCTL.0) to redirect MOVX commands to write to FLASH. Use the MOVX command to write a data byte to any location within the 512-byte page to be erased. Clear PSEE to disable FLASH erases Use the MOVX command to write a data byte to the desired byte location within the erased 512-byte page. Repeat this step until all desired bytes are written (within the target page). Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 9. Re-enable interrupts. Rev. 1.4 139 C8051F020/1/2/3 Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the FLASH is being programmed or erased. Interrupts that are posted during a FLASH write or erase operation are held pending until the FLASH operation has completed, at which time they are serviced by the CPU in priority order. Table 15.1. FLASH Electrical Characteristics VDD = 2.7V to 3.6V; Ta = -40°C to +85°C PARAMETER CONDITIONS Endurance Erase Cycle Time Write Cycle Time 15.2. MIN 20k 10 40 TYP 100k 12 50 MAX 14 60 UNITS Erase/Write ms µs Non-volatile Data Storage The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction (as described in the previous section) and read using the MOVC read instruction. An additional 128-byte sector of FLASH memory is included for non-volatile data storage. Its smaller sector size makes it particularly well suited as general purpose, non-volatile scratchpad memory. Even though FLASH memory can be written a single byte at a time, an entire sector must be erased first. In order to change a single byte of a multibyte data set, the data must be moved to temporary storage. The 128-byte sector-size facilitates updating data without wasting program memory or RAM space. The 128-byte sector is double-mapped over the 64k byte FLASH memory; its address ranges from 0x00 to 0x7F (see Figure 15.1). To access this 128-byte sector, the SFLE bit in PSCTL must be set to logic 1. Code execution from this 128-byte scratchpad sector is not permitted. 15.3. Security Options The CIP-51 provides security options to protect the FLASH memory from inadvertent modification by software as well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the FLASH memory from accidental modification by software. These bits must be explicitly set to logic 1 before software can modify the FLASH memory. Additional security features prevent proprietary program code and data constants from being read or altered across the JTAG interface or by software running on the system controller. A set of security lock bytes stored at 0xFDFE and 0xFDFF protect the FLASH program memory from being read or altered across the JTAG interface. Each bit in a security lock-byte protects one 8k-byte block of memory. Clearing a bit to logic 0 in a Read Lock Byte prevents the corresponding block of FLASH memory from being read across the JTAG interface. Clearing a bit in the Write/Erase Lock Byte protects the block from JTAG erasures and/or writes. The 128-byte scratchpad sector is locked only when all other sectors are locked. The Read Lock Byte is at location 0xFDFF. The Write/Erase Lock Byte is located at 0xFDFE. Figure 15.1 shows the location and bit definitions of the security bytes. The 512-byte sector containing the lock bytes can be written to, but not erased by software. An attempted read of a read-locked byte returns undefined data. Debugging code in a readlocked sector is not possible through the JTAG port. 140 Rev. 1.4 C8051F020/1/2/3 Figure 15.1. FLASH Program Memory Map and Security Bytes Read and Write/Erase Security Bits. (Bit 7 is MSB.) Bit Memory Block 7 6 5 4 3 2 1 0 0xE000 - 0xFDFD 0xC000 - 0xDFFF 0xA000 - 0xBFFF 0x8000 - 0x9FFF 0x6000 - 0x7FFF 0x4000 - 0x5FFF 0x2000 - 0x3FFF 0x0000 - 0x1FFF SFLE = 0 SFLE = 1 0xFFFF Reserved Scratchpad Memory (Data only) 0xFE00 Read Lock Byte 0xFDFF Write/Erase Lock Byte 0xFDFE 0x007F 0x0000 0xFDFD Program/Data Memory Space Software Read Limit 0x0000 FLASH Read Lock Byte Bits7-0: Each bit locks a corresponding block of memory. (Bit7 is MSB). 0: Read operations are locked (disabled) for corresponding block across the JTAG interface. 1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface. FLASH Write/Erase Lock Byte Bits7-0: Each bit locks a corresponding block of memory. 0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface. 1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface. NOTE: When the highest block is locked, the security bytes may be written but not erased. FLASH access Limit Register (FLACL) The content of this register is used as the high byte of the 16-bit software read limit address. This 16bit read limit address value is calculated as 0xNN00 where NN is replaced by content of this register on reset. Software running at or above this address is prohibited from using the MOVX and MOVC instructions to read, write, or erase FLASH locations below this address. Any attempts to read locations below this limit will return the value 0x00. The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block containing the security bytes. This allows additional blocks to be protected after the block containing the security bytes has been locked. Important Note: The only means of removing a lock once set is to erase the entire program memory space by performing a JTAG erase operation (i.e. cannot be done in user firmware). Addressing either security byte while performing a JTAG erase operation will automatically initiate erasure of the entire program memory space (except for the reserved area). This erasure can only be performed via JTAG. If a nonsecurity byte in the 0xFBFF-0xFDFF page is addressed during the JTAG erasure, only that page (including the security bytes) will be erased. The FLASH Access Limit security feature (see Figure 15.1) protects proprietary program code and data from being read by software running on the C8051F020/1/2/3. This feature provides support for OEMs that wish to program the Rev. 1.4 141 C8051F020/1/2/3 MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later. The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory space. The first is an upper partition consisting of all the program memory locations at or above the SRL address, and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but excluding) the SRL address. Software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruction. (Executing a MOVC instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00.) Software running in the lower partition can access locations in both the upper and lower partition without restriction. The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a predetermined location in the upper partition. If entry points are published, software running in the upper partition may execute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition. The SRL address is specified using the contents of the FLASH Access Register. The 16-bit SRL address is calculated as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a 512 boundary be used. The contents of a non-initialized SRL security byte is 0x00, thereby setting the SRL address to 0x0000 and allowing read access to all locations in program memory space by default. Figure 15.2. FLACL: FLASH Access Limit R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB7 Bits 7-0: 142 FLACL: FLASH Access Limit. This register holds the high byte of the 16-bit program memory read/write/erase limit address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of FLACL. A write to this register sets the FLASH Access Limit. This register can only be written once after any reset. Any subsequent writes are ignored until the next reset. Rev. 1.4 C8051F020/1/2/3 Figure 15.3. FLSCL: FLASH Memory Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value FOSE FRAE Reserved Reserved Reserved Reserved Reserved FLWE 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB6 Bit7: Bit6: Bits5-1: Bit0: FOSE: FLASH One-Shot Timer Enable This is the timer that turns off the sense amps after a FLASH read. 0: FLASH One-Shot Timer disabled. 1: FLASH One-Shot Timer enabled. FRAE: FLASH Read Always Enable 0: FLASH reads per One-Shot Timer. 1: FLASH always in read mode. RESERVED. Read = 00000b. Must Write 00000b. FLWE: FLASH Read/Write Enable This bit must be set to allow FLASH writes from user software. 0: FLASH writes disabled. 1: FLASH writes enabled. Rev. 1.4 143 C8051F020/1/2/3 Figure 15.4. PSCTL: Program Store Read/Write Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - SFLE PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8F Bits7-3: Bit2: Bit1: Bit0: 144 UNUSED. Read = 00000b, Write = don't care. SFLE: Scratchpad FLASH Memory Access Enable. When this bit is set, FLASH reads and writes from user software are directed to the 128-byte Scratchpad FLASH sector. When SFLE is set to logic 1, FLASH accesses out of the address range 0x000x7F should not be attempted. Reads/Writes out of this range will yield unpredictable results. 0: FLASH access from user software directed to the 64k byte Program/Data FLASH sector. 1: FLASH access from user software directed to the 128 byte Scratchpad sector. PSEE: Program Store Erase Enable. Setting this bit allows an entire page of the FLASH program memory to be erased provided the PSWE bit is also set. After setting this bit, a write to FLASH memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. 0: FLASH program memory erasure disabled. 1: FLASH program memory erasure enabled. PSWE: Program Store Write Enable. Setting this bit allows writing a byte of data to the FLASH program memory using the MOVX instruction. The location must be erased before writing data. 0: Write to FLASH program memory disabled. 1: Write to FLASH program memory enabled. Rev. 1.4 C8051F020/1/2/3 16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM The C8051F020/1/2/3 MCUs include 4k bytes of on-chip RAM mapped into the external data memory space (XRAM), as well as an External Data Memory Interface which can be used to access off-chip memories and memorymapped devices connected to the GPIO ports. The external memory space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in Figure 16.1). Note: the MOVX instruction can also be used for writing to the FLASH memory. See Section “15. FLASH MEMORY” on page 139 for details. The MOVX instruction accesses XRAM by default. The EMIF can be configured to appear on the lower I/O ports (P0-P3) or the upper I/O ports (P4-P7). 16.1. Accessing XRAM The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms, both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which contains the effective address of the XRAM location to be read or written. The second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM address. Examples of both of these methods are given below. 16.1.1. 16-Bit MOVX Example The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A: MOV MOVX DPTR, #1234h A, @DPTR ; load DPTR with 16-bit address to read (0x1234) ; load contents of 0x1234 into accumulator A The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately, the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains the lower 8-bits of DPTR. 16.1.2. 8-Bit MOVX Example The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the effective address to be accessed. The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A. MOV MOV MOVX EMI0CN, #12h R0, #34h a, @R0 ; load high byte of address into EMI0CN ; load low byte of address into R0 (or R1) ; load contents of 0x1234 into accumulator A Rev. 1.4 145 C8051F020/1/2/3 16.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of four steps: 1. Select EMIF on Low Ports (P3, P2, P1, and P0) or High Ports (P7, P6, P5, and P4). 2. Select Multiplexed mode or Non-multiplexed mode. 3. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 4. Set up timing to interface with off-chip memory or peripherals. 5. Select the desired output mode for the associated Ports (registers PnMDOUT, P74OUT). Each of these four steps is explained in detail in the following sections. The Port selection, Multiplexed mode selection, and Mode bits are located in the EMI0CF register shown in Figure 16.2. 16.3. Port Selection and Configuration The External Memory Interface can appear on Ports 3, 2, 1, and 0 (C8051F020/1/2/3 devices) or on Ports 7, 6, 5, and 4 (C8051F020/2 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are selected, the EMIFLE bit (XBR2.1) must be set to a ‘1’ so that the Crossbar will skip over P0.7 (/WR), P0.6 (/RD), and if multiplexed mode is selected P0.5 (ALE). For more information about the configuring the Crossbar, see Section “17. PORT INPUT/OUTPUT” on page 161. The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port latches or to the Crossbar (on Ports 3, 2, 1, and 0). See Section “17. PORT INPUT/OUTPUT” on page 161 for more information about the Crossbar and Port operation and configuration. The Port latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant state, most commonly by setting them to a logic 1. During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface operation, and remains controlled by the PnMDOUT registers. See Section “17. PORT INPUT/OUTPUT” on page 161 for more information about Port output mode configuration. 146 Rev. 1.4 C8051F020/1/2/3 Figure 16.1. EMI0CN: External Memory Interface Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xAF Bits7-0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. 0x00: 0x0000 to 0x00FF 0x01: 0x0100 to 0x01FF ... 0xFE: 0xFE00 to 0xFEFF 0xFF: 0xFF00 to 0xFFFF Figure 16.2. EMI0CF: External Memory Configuration R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - PRTSEL EMD2 EMD1 EMD0 EALE1 EALE0 00000011 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA3 Bits7-6: Bit5: Bit4: Bits3-2: Bits1-0: Unused. Read = 00b. Write = don’t care. PRTSEL: EMIF Port Select. 0: EMIF active on P0-P3. 1: EMIF active on P4-P7. EMD2: EMIF Multiplex Mode Select. 0: EMIF operates in multiplexed address/data mode. 1: EMIF operates in non-multiplexed mode (separate address and data pins). EMD1-0: EMIF Operating Mode Select. These bits control the operating mode of the External Memory Interface. 00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip memory space. 01: Split Mode without Bank Select: Accesses below the 4k boundary are directed on-chip. Accesses above the 4k boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte. Note that in order to access off-chip space, EMI0CN must be set to a page that is not contained in the on-chip address space. 10: Split Mode with Bank Select: Accesses below the 4k boundary are directed on-chip. Accesses above the 4k boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine the high-byte of the address. 11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU. EALE1-0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0). 00: ALE high and ALE low pulse width = 1 SYSCLK cycle. 01: ALE high and ALE low pulse width = 2 SYSCLK cycles. 10: ALE high and ALE low pulse width = 3 SYSCLK cycles. 11: ALE high and ALE low pulse width = 4 SYSCLK cycles. Rev. 1.4 147 C8051F020/1/2/3 16.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 16.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in Figure 16.3. In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data Bus controls the state of the AD[7:0] port at the time /RD or /WR is asserted. See Section “16.6.2. Multiplexed Mode” on page 156 for more information. Figure 16.3. Multiplexed Configuration Example A[15:8] A[15:8] ADDRESS BUS 74HC373 E M I F ALE AD[7:0] G ADDRESS/DATA BUS D A[7:0] VDD 64K X 8 SRAM 8 I/O[7:0] CE WE OE /WR /RD 148 Q Rev. 1.4 C8051F020/1/2/3 16.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 16.4. See Section “16.6.1. Non-multiplexed Mode” on page 153 for more information about Non-multiplexed operation. Figure 16.4. Non-multiplexed Configuration Example E M I F A[15:0] ADDRESS BUS A[15:0] VDD 8 D[7:0] DATA BUS 64K X 8 SRAM I/O[7:0] CE WE OE /WR /RD Rev. 1.4 149 C8051F020/1/2/3 16.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 16.5, based on the EMIF Mode bits in the EMI0CF register (Figure 16.2). These modes are summarized below. More information about the different modes can be found in Section “ .” on page 152. 16.5.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 4k boundaries. As an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space. 8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0 or R1 to determine the low-byte of the effective address. 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address. • • 16.5.2. Split Mode without Bank Select When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and off-chip space. Effective addresses below the 4k boundary will access on-chip XRAM space. Effective addresses beyond the 4k boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or offchip. The lower 8-bits of the Address Bus A[7:0] are driven as defined by R0 or R1. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate the upper address bits at will by setting the Port state directly. This behavior is in contrast with “Split Mode with Bank Select” described below. 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or offchip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the offchip transaction. • • • • Figure 16.5. EMIF Operating Modes EMI0CF[3:2] = 00 EMI0CF[3:2] = 01 0xFFFF EMI0CF[3:2] = 11 EMI0CF[3:2] = 10 0xFFFF 0xFFFF 0xFFFF On-Chip XRAM On-Chip XRAM Off-Chip Memory (No Bank Select) Off-Chip Memory (Bank Select) On-Chip XRAM Off-Chip Memory On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM 0x0000 150 0x0000 Rev. 1.4 0x0000 0x0000 C8051F020/1/2/3 16.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • • • • Effective addresses below the 4k boundary will access on-chip XRAM space. Effective addresses beyond the 4k boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or offchip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank Select” mode. 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or offchip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. 16.5.4. External Only When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the 4k boundary. • • 8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective address A[7:0] are determined by the contents of R0 or R1. 16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. 16.6. Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time, /RD and /WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through EMI0TC, shown in Figure 16.6, and EMI0CF[1:0]. The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the minimum execution time of an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 SYSCLKs for /ALE, 1 for /RD or /WR + 4 SYSCLKs). The programmable setup and hold times default to the maximum delay settings after a reset. Table 16.1 lists the AC parameters for the External Memory Interface, and Figure 16.7 through Figure 16.11 show the timing diagrams for the different External Memory Interface modes and MOVX operations Rev. 1.4 151 C8051F020/1/2/3 . Figure 16.6. EMI0TC: External Memory Timing Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EAS1 EAS0 EWR3 EWR2 EWR1 EWR0 EAH1 EAH0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA1 Bits7-6: Bits5-2: Bits1-0: 152 EAS1-0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles. EWR3-0: EMIF /WR and /RD Pulse-Width Control Bits. 0000: /WR and /RD pulse width = 1 SYSCLK cycle. 0001: /WR and /RD pulse width = 2 SYSCLK cycles. 0010: /WR and /RD pulse width = 3 SYSCLK cycles. 0011: /WR and /RD pulse width = 4 SYSCLK cycles. 0100: /WR and /RD pulse width = 5 SYSCLK cycles. 0101: /WR and /RD pulse width = 6 SYSCLK cycles. 0110: /WR and /RD pulse width = 7 SYSCLK cycles. 0111: /WR and /RD pulse width = 8 SYSCLK cycles. 1000: /WR and /RD pulse width = 9 SYSCLK cycles. 1001: /WR and /RD pulse width = 10 SYSCLK cycles. 1010: /WR and /RD pulse width = 11 SYSCLK cycles. 1011: /WR and /RD pulse width = 12 SYSCLK cycles. 1100: /WR and /RD pulse width = 13 SYSCLK cycles. 1101: /WR and /RD pulse width = 14 SYSCLK cycles. 1110: /WR and /RD pulse width = 15 SYSCLK cycles. 1111: /WR and /RD pulse width = 16 SYSCLK cycles. EAH1-0: EMIF Address Hold Time Bits. 00: Address hold time = 0 SYSCLK cycles. 01: Address hold time = 1 SYSCLK cycle. 10: Address hold time = 2 SYSCLK cycles. 11: Address hold time = 3 SYSCLK cycles. Rev. 1.4 C8051F020/1/2/3 16.6.1. Non-multiplexed Mode 16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Figure 16.7. Non-multiplexed 16-bit MOVX Timing Nonmuxed 16-bit WRITE ADDR[15:8] P1/P5 EMIF ADDRESS (8 MSBs) from DPH P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from DPL P2/P6 DATA[7:0] P3/P7 EMIF WRITE DATA P3/P7 T T WDS T ACS WDH T T ACW ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Nonmuxed 16-bit READ ADDR[15:8] P1/P5 EMIF ADDRESS (8 MSBs) from DPH P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from DPL P2/P6 DATA[7:0] P3/P7 EMIF READ DATA P3/P7 T RDS T ACS T ACW T RDH T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Rev. 1.4 153 C8051F020/1/2/3 16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing Nonmuxed 8-bit WRITE without Bank Select ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from R0 or R1 P2/P6 DATA[7:0] P3/P7 EMIF WRITE DATA P3/P7 T T WDS T WDH T ACS T ACW ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Nonmuxed 8-bit READ without Bank Select ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF READ DATA T RDS T T ACS 154 ACW P2/P6 P3/P7 T RDH T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Rev. 1.4 C8051F020/1/2/3 16.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing Nonmuxed 8-bit WRITE with Bank Select ADDR[15:8] P1/P5 EMIF ADDRESS (8 MSBs) from EMI0CN P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from R0 or R1 P2/P6 DATA[7:0] P3/P7 EMIF WRITE DATA P3/P7 T T WDS T ACS WDH T T ACW ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Nonmuxed 8-bit READ with Bank Select ADDR[15:8] P1/P5 EMIF ADDRESS (8 MSBs) from EMI0CN P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from R0 or R1 P2/P6 DATA[7:0] P3/P7 EMIF READ DATA T RDS T ACS T ACW P3/P7 T RDH T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Rev. 1.4 155 C8051F020/1/2/3 16.6.2. Multiplexed Mode 16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Figure 16.10. Multiplexed 16-bit MOVX Timing Muxed 16-bit WRITE ADDR[15:8] P2/P6 AD[7:0] P3/P7 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH ALE P2/P6 EMIF WRITE DATA P3/P7 T ALEL P0.5/P4.5 P0.5/P4.5 T T WDS T ACS WDH T T ACW ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Muxed 16-bit READ ADDR[15:8] P2/P6 AD[7:0] P3/P7 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH ALE EMIF READ DATA T T ALEL RDS P3/P7 T RDH P0.5/P4.5 P0.5/P4.5 T ACS 156 P2/P6 T ACW T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Rev. 1.4 C8051F020/1/2/3 16.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing Muxed 8-bit WRITE Without Bank Select ADDR[15:8] AD[7:0] P2/P6 P3/P7 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF WRITE DATA P3/P7 T ALEL P0.5/P4.5 P0.5/P4.5 T T WDS T ACS WDH T T ACW ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Muxed 8-bit READ Without Bank Select ADDR[15:8] AD[7:0] P2/P6 P3/P7 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF READ DATA T T ALEL RDS P3/P7 T RDH P0.5/P4.5 P0.5/P4.5 T ACS T ACW T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Rev. 1.4 157 C8051F020/1/2/3 16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing Muxed 8-bit WRITE with Bank Select ADDR[15:8] P2/P6 AD[7:0] P3/P7 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P2/P6 EMIF WRITE DATA P3/P7 T ALEL P0.5/P4.5 P0.5/P4.5 T T WDS T ACS WDH T T ACW ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Muxed 8-bit READ with Bank Select ADDR[15:8] P2/P6 AD[7:0] P3/P7 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF READ DATA T T ALEL RDS P3/P7 T RDH P0.5/P4.5 P0.5/P4.5 T ACS 158 P2/P6 T ACW T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Rev. 1.4 C8051F020/1/2/3 Table 16.1. AC Parameters for External Memory Interface PARAMETER DESCRIPTION MIN MAX UNITS TSYSCLK System Clock Period 40 TACS Address / Control Setup Time 0 3*TSYSCLK ns TACW Address / Control Pulse Width 1*TSYSCLK 16*TSYSCLK ns TACH Address / Control Hold Time 0 3*TSYSCLK ns TALEH Address Latch Enable High Time 1*TSYSCLK 4*TSYSCLK ns TALEL Address Latch Enable Low Time 1*TSYSCLK 4*TSYSCLK ns TWDS Write Data Setup Time 1*TSYSCLK 19*TSYSCLK ns TWDH Write Data Hold Time 0 3*TSYSCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns Rev. 1.4 ns 159 C8051F020/1/2/3 Notes 160 Rev. 1.4 C8051F020/1/2/3 17. PORT INPUT/OUTPUT The C8051F020/1/2/3 are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3), organized as 8-bit Ports. The lower ports: P0, P1, P2, and P3, are both bit- and byte-addressable through their corresponding Port Data registers. The upper ports: P4, P5, P6, and P7 are byte-addressable. All Port pins are 5 V-tolerant, and all support configurable Open-Drain or Push-Pull output modes and weak pull-ups. A block diagram of the Port I/O cell is shown in Figure 17.1. Complete Electrical Specifications for the Port I/O pins are given in Table 16.1. Figure 17.1. Port I/O Cell Block Diagram /WEAK-PULLUP VDD PUSH-PULL VDD /PORT-OUTENABLE (WEAK) PORT PAD PORT-OUTPUT DGND Analog Select (Port 1 Only) ANALOG INPUT PORT-INPUT Table 17.1. Port I/O DC Electrical Characteristics VDD = 2.7 V to 3.6 V, -40°C to +85°C unless otherwise specified. PARAMETER CONDITIONS MIN Output High Voltage (VOH) IOH = -10 µA, Port I/O Push-Pull IOH = -3 mA, Port I/O Push-Pull IOH = -10 mA, Port I/O Push-Pull TYP VDD - 0.1 VDD - 0.7 UNITS V VDD - 0.8 Output Low Voltage (VOL) IOL = 10 µA IOL = 8.5 mA IOL = 25 mA 0.1 0.6 V 1.0 Input High Voltage (VIH) 0.7 x VDD V Input Low Voltage (VIL) Input Leakage Current MAX 0.3 x VDD DGND < Port Pin < VDD, Pin Tri-state Weak Pull-up Off Weak Pull-up On Input Capacitance µA ±1 10 5 Rev. 1.4 V pF 161 C8051F020/1/2/3 The C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 17.2. The system designer controls which digital functions are assigned pins, limited only by the number of pins available. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read from its associated Data register regardless of whether that pin has been assigned to a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as Analog Inputs to ADC1. An External Memory Interface which is active during the execution of a MOVX instruction whose target address resides in off-chip memory can be active on either the lower Ports or the upper Ports. See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. The upper Ports (available on C8051F020/2) can be byte-accessed as GPIO pins. Figure 17.2. Lower Port I/O Functional Block Diagram Highest Priority 2 UART0 4 SPI 2 UART1 (Internal Digital Signals) P0MDOUT, P1MDOUT, P2MDOUT, P3MDOUT Registers External Pins 2 SMBus Lowest Priority XBR0, XBR1, XBR2, P1MDIN Registers Priority Decoder 8 6 PCA P0 I/O Cells P0.0 P1 I/O Cells P1.0 Digital Crossbar T0, T1, T2, T2EX, T4,T4EX /INT0, /INT1 8 8 8 8 P2 I/O Cells P2.0 P3 I/O Cells P3.0 (P0.0-P0.7) 8 P1 (P1.0-P1.7) 8 P2 To External Memory Interface (EMIF) (P2.0-P2.7) 8 P3 162 P1.7 8 /SYSCLK CNVSTR Port Latches P0.7 2 Comptr. Outputs P0 Highest Priority (P3.0-P3.7) Rev. 1.4 To ADC1 Input P2.7 P3.7 Lowest Priority C8051F020/1/2/3 17.1. Ports 0 through 3 and the Priority Crossbar Decoder The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port pins are allocated in order starting with P0.0 and continue through P3.7 if necessary. The digital peripherals are assigned Port pins in a priority order which is listed in Figure 17.3, with UART0 having the highest priority and CNVSTR having the lowest priority. 17.1.1. Crossbar Pin Assignment and Allocation The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in the Crossbar configuration registers XBR0, XBR1, and XBR2, shown in Figure 17.7, Figure 17.8, and Figure 17.9. For example, if the UART0EN bit (XBR0.2) is set to a logic 1, the TX0 and RX0 pins will be mapped to P0.0 and P0.1 respectively. Because UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when UART0EN is set to a logic 1. If a digital peripheral’s enable bits are not set to a logic 1, then its ports are not accessible at the Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when a serial communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to assign TX0 Figure 17.3. Priority Crossbar Decode Table (EMIFLE = 0; P1MDIN = 0xFF) P0 PIN I/O 0 TX0 2  CEX3 CEX4 0 1 2 3 P2 4 5 6 7 0 1 2 3 P3 4 5 6 7 0 1 2 3 Crossbar Register Bits 4 5 6 7                SPI0EN: XBR0.1    RX1 CEX2 7   SCL CEX1 6  NSS CEX0 5 UART0EN: XBR0.2  MOSI TX1 P1 4  MISO SDA 3  RX0 SCK 1                    UART1EN: XBR2.2      SMB0EN: XBR0.0       PCA0ME: XBR0.[5:3]                ECI                 ECI0E: XBR0.6 CP0                  CP0E: XBR0.7 CP1                   CP1E: XBR1.0 T0                    /INT0                     T0E: XBR1.1 INT0E: XBR1.2 T1                      /INT1                       T1E: XBR1.3 INT1E: XBR1.4 T2                        T2EX                         T2E: XBR1.5 T2EXE: XBR1.6 AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Rev. 1.4 T4E: XBR2.3 AD7/D7 AD6/D6 AD5/D5 AD4/D4 AD3/D3 T4EXE: XBR2.4 AD2/D2 AD1/D1 AD0/D0 A15m/A7 A14m/A6 A13m/A5 A12m/A4 A11m/A3 A10m/A2 A9m/A1 A8m/A0 AIN1.7/A1 AIN1.6/A1 AIN1.5/A1 AIN1.4/A1 AIN1.3/A1 CNVSTE: XBR2.0 AIN1.2/A1 SYSCKE: XBR1.7                             AIN1.1/A9                            AIN1.0/A8 /SYSCLK CNVSTR /WR                           /RD                          ALE T4 T4EX Muxed Data/Non-muxed Data 163 C8051F020/1/2/3 to a Port pin without assigning RX0 as well. Each combination of enabled peripherals results in a unique device pinout. All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 17.10, Figure 17.12, Figure 17.15, and Figure 17.17), a set of SFRs which are both byte- and bit-addressable. The output states of Port pins that are allocated by the Crossbar are controlled by the digital peripheral that is mapped to those pins. Writes to the Port Data registers (or associated Port bits) will have no effect on the states of these pins. A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV operation). During the read cycle of the read-modify-write instruction, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read. Because the Crossbar registers affect the pinout of the peripherals of the device, they are typically configured in the initialization code of the system before the peripherals themselves are configured. Once configured, the Crossbar registers are typically left alone. Once the Crossbar registers have been properly configured, the Crossbar is enabled by setting XBARE (XBR2.6) to a logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar registers and other registers which can affect the device pinout are being written. The output drivers on Crossbar-assigned input signals (like RX0, for example) are explicitly disabled; thus the values of the Port Data registers and the PnMDOUT registers have no effect on the states of these pins. 17.1.2. Configuring the Output Modes of the Port Pins The output drivers on Ports 0 through 3 remain disabled until the Crossbar is enabled by setting XBARE (XBR2.6) to a logic 1. The output mode of each port pin can be configured as either Open-Drain or Push-Pull; the default state is OpenDrain. In the Push-Pull configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and writing a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high-impedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire (like the SDA signal on an SMBus connection). The output modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated PnMDOUT registers (See Figure 17.11, Figure 17.14, Figure 17.16, and Figure 17.18). For example, a logic 1 in P3MDOUT.7 will configure the output mode of P3.7 to Push-Pull; a logic 0 in P3MDOUT.7 will configure the output mode of P3.7 to Open-Drain. All Port pins default to Open-Drain output. The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has allocated the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected to SDA, SCL, RX0 (if UART0 is in Mode 0), and RX1 (if UART1 is in Mode 0) are always configured as Open-Drain outputs, regardless of the settings of the associated bits in the PnMDOUT registers. 164 Rev. 1.4 C8051F020/1/2/3 17.1.3. Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For example, P3.7 is configured as a digital input by setting P3MDOUT.7 to a logic 0 and P3.7 to a logic 1. If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input (for example RX0, the UART0 receive pin), then the output drivers on that pin are automatically disabled. 17.1.4. External Interrupts (IE6 and IE7) In addition to the external interrupts /INT0 and /INT1, whose Port pins are allocated and assigned by the Crossbar, P3.6 and P3.7 can be configured to generate edge sensitive interrupts; these interrupts are configurable as falling- or rising-edge sensitive using the IE6CF (P3IF.2) and IE7CF (P3IF.3) bits. When an active edge is detected on P3.6 or P3.7, a corresponding External Interrupt flag (IE6 or IE7) will be set to a logic 1 in the P3IF register (See Figure 17.19). If the associated interrupt is enabled, an interrupt will be generated and the CPU will vector to the associated interrupt vector location. See Section “12.3. Interrupt Handler” on page 116 for more information about interrupts. 17.1.5. Weak Pull-ups By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about 100 kΩ) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is driving a logic 0; that is, an output pin will not contend with its own pull-up device. The weak pull-up device can also be explicitly disabled on a Port 1 pin by configuring the pin as an Analog Input, as described below. 17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0]) The pins on Port 1 can serve as analog inputs to the ADC1 analog MUX. A Port pin is configured as an Analog Input by writing a logic 0 to the associated bit in the P1MDIN register (see Figure 17.13). All Port pins default to a Digital Input mode. Configuring a Port pin as an analog input: 1. 2. 3. Disables the digital input path from the pin. This prevents additional power supply current from being drawn when the voltage at the pin is near VDD / 2. A read of the Port Data bit will return a logic 0 regardless of the voltage at the Port pin. Disables the weak pull-up device on the pin. Causes the Crossbar to “skip over” the pin when allocating Port pins for digital peripherals. Note that the output drivers on a pin configured as an Analog Input are not explicitly disabled. Therefore, the associated P1MDOUT bits of pins configured as Analog Inputs should explicitly be set to logic 0 (Open-Drain output mode), and the associated Port Data bits should be set to logic 1 (high-impedance). Also note that it is not required to configure a Port pin as an Analog Input in order to use it as an input to the ADC1 MUX; however, it is strongly recommended. See Section “7. ADC1 (8-Bit ADC)” on page 75 for more information about ADC1. Rev. 1.4 165 C8051F020/1/2/3 17.1.7. External Memory Interface Pin Assignments If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.1) should be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Memory Interface is in Multiplexed mode, P0.5 (ALE). Figure 17.4 shows an example Crossbar Decode Table with EMIFLE=1 and the EMIF in Multiplexed mode. Figure 17.5 shows an example Crossbar Decode Table with EMIFLE=1 and the EMIF in Non-multiplexed mode. If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the External Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX instruction, regardless of the settings of the Crossbar registers or the Port Data registers. The output configuration of the Port pins is not affected by the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus. See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. Figure 17.4. Priority Crossbar Decode Table EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF) P0 PIN I/O 0 TX0 2  CEX3 CEX4 0 1 2 3 P2 4 5 6 7 0 1 2 3 P3 4 5 6 7 0 1 2 3 Crossbar Register Bits 4 5 6 7 SPI0EN: XBR0.1              RX1 CEX2 7   SCL CEX1 6  NSS CEX0 5 UART0EN: XBR0.2  MOSI TX1 P1 4  MISO SDA 3  RX0 SCK 1                         UART1EN: XBR2.2      SMB0EN: XBR0.0       PCA0ME: XBR0.[5:3]                ECI                 ECI0E: XBR0.6 CP0                  CP0E: XBR0.7 CP1                   CP1E: XBR1.0 T0                    /INT0                     T0E: XBR1.1 INT0E: XBR1.2 T1                      /INT1                       T2                        T2EX                         T1E: XBR1.3 INT1E: XBR1.4 T2E: XBR1.5 T2EXE: XBR1.6 AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L 166 Rev. 1.4 T4E: XBR2.3 AD7/D7 AD6/D6 T4EXE: XBR2.4 AD5/D5 AD4/D4 AD3/D3 AD2/D2 AD1/D1 AD0/D0 A15m/A7 A14m/A6 A13m/A5 A12m/A4 A11m/A3 A10m/A2 A9m/A1 A8m/A0 AIN1.7/A1 AIN1.6/A1 AIN1.5/A1 CNVSTE: XBR2.0 AIN1.4/A1 SYSCKE: XBR1.7                        AIN1.3/A1                            AIN1.2/A1      AIN1.1/A9 /SYSCLK CNVSTR AIN1.0/A8                      /WR                          /RD      ALE T4 T4EX Muxed Data/Non-muxed Data C8051F020/1/2/3 Figure 17.5. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Non-multiplexed Mode; P1MDIN = 0xFF) P0 PIN I/O 0 TX0 2  CEX3 CEX4 0 1 2 3 P2 4 5 6 7 0 1 2 3 P3 4 5 6 7 0 1 2 3 Crossbar Register Bits 4 5 6 7                  UART1EN: XBR2.2                 SMB0EN: XBR0.0     SPI0EN: XBR0.1    RX1 CEX2 7   SCL CEX1 6  NSS CEX0 5 UART0EN: XBR0.2  MOSI TX1 P1 4  MISO SDA 3  RX0 SCK 1        PCA0ME: XBR0.[5:3]                 ECI                 ECI0E: XBR0.6 CP0                  CP0E: XBR0.7 CP1                   CP1E: XBR1.0 T0                    /INT0                     T0E: XBR1.1 INT0E: XBR1.2 T1                      /INT1                       T2                        T2EX                         T1E: XBR1.3 INT1E: XBR1.4 T2E: XBR1.5 T2EXE: XBR1.6 AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Rev. 1.4 T4E: XBR2.3 AD7/D7 AD6/D6 AD5/D5 T4EXE: XBR2.4 AD4/D4 AD3/D3 AD2/D2 AD1/D1 AD0/D0 A15m/A7 A14m/A6 A13m/A5 A12m/A4 A11m/A3 A10m/A2 A9m/A1 A8m/A0 AIN1.7/A1 AIN1.6/A1 AIN1.5/A1 CNVSTE: XBR2.0 AIN1.4/A1 SYSCKE: XBR1.7                       AIN1.3/A1                            AIN1.2/A1       AIN1.1/A9 /SYSCLK CNVSTR AIN1.0/A8                     /WR                          /RD       ALE T4 T4EX Muxed Data/Non-muxed Data 167 C8051F020/1/2/3 17.1.8. Crossbar Pin Assignment Example In this example (Figure 17.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1, /INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to operate in Multiplexed mode and to appear on the Low ports. Further, we configure P1.2, P1.3, and P1.4 for Analog Input mode so that the voltages at these pins can be measured by ADC1. The configuration steps are as follows: 1. 2. 3. 4. 5. 6. 7. 168 XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, INT0E = 1, INT1E = 1, and EMIFLE = 1. Thus: XBR0 = 0x05, XBR1 = 0x14, and XBR2 = 0x02. We configure the External Memory Interface to use Multiplexed mode and to appear on the Low ports. PRTSEL = 0, EMD2 = 0. We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0xE3 (P1.4, P1.3, and P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0). We enable the Crossbar by setting XBARE = 1: XBR2 = 0x46. - UART0 has the highest priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0. - The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to SCL. - UART1 is next in priority order, so P0.4 is assigned to TX1. Because the External Memory Interface is selected on the lower Ports, EMIFLE = 1, which causes the Crossbar to skip P0.6 (/RD) and P0.7 (/WR). Because the External Memory Interface is configured in Multiplexed mode, the Crossbar will also skip P0.5 (ALE). RX1 is assigned to the next non-skipped pin, which in this case is P1.0. - /INT0 is next in priority order, so it is assigned to P1.1. - P1MDIN is set to 0xE3, which configures P1.2, P1.3, and P1.4 as Analog Inputs, causing the Crossbar to skip these pins. - /INT1 is next in priority order, so it is assigned to the next non-skipped pin, which is P1.5. - The External Memory Interface will drive Ports 2 and 3 (denoted by red dots in Figure 17.6) during the execution of an off-chip MOVX instruction. We set the UART0 TX pin (TX0, P0.0), UART1 TX pin (TX1, P0.4), ALE, /RD, /WR (P0.[7:3]) outputs to Push-Pull by setting P0MDOUT = 0xF1. We configure the output modes of the EMIF Ports (P2, P3) to Push-Pull by setting P2MDOUT = 0xFF and P3MDOUT = 0xFF. We explicitly disable the output drivers on the 3 Analog Input pins by setting P1MDOUT = 0x00 (configure outputs to Open-Drain) and P1 = 0xFF (a logic 1 selects the high-impedance state). Rev. 1.4 C8051F020/1/2/3 Figure 17.6. Crossbar Example: (EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xE3; XBR0 = 0x05; XBR1 = 0x14; XBR2 = 0x46) P0 PIN I/O 0 TX0 2  CEX3 CEX4 0 1 2 3 P2 4 5 6 7 0 1 2 3 P3 4 5 6 7 0 1 2 3 Crossbar Register Bits 4 5 6 7 SPI0EN: XBR0.1              RX1 CEX2 7   SCL CEX1 6  NSS CEX0 5 UART0EN: XBR0.2  MOSI TX1 P1 4  MISO SDA 3  RX0 SCK 1                    UART1EN: XBR2.2         SMB0EN: XBR0.0          PCA0ME: XBR0.[5:3]                                  T2EXE: XBR1.6 T4 T4EX                                                    T4EXE: XBR2.4 /SYSCLK                           SYSCKE: XBR1.7 CNVSTR                           CNVSTE: XBR2.0 AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Rev. 1.4 T4E: XBR2.3 AD7/D7 AD6/D6 T2E: XBR1.5 AD5/D5 AD4/D4 T1E: XBR1.3 AD3/D3 AD2/D2 T0E: XBR1.1 AD1/D1 AD0/D0      A15m/A7 T2EX A14m/A6 INT1E: XBR1.4 T2                                A13m/A5                   A12m/A4             A11m/A3      /INT1 A10m/A2 T1 A9m/A1 INT0E: XBR1.2 A8m/A0              AIN1.7/A1   AIN1.6/A1      AIN1.5/A1 /INT0 AIN1.4/A1                        AIN1.3/A1     CP1E: XBR1.0 T0           AIN1.2/A1 CP0E: XBR0.7 CP1 AIN1.1/A9 ECI0E: XBR0.6           AIN1.0/A8            /WR        /RD      ALE ECI CP0 Muxed Data/Non-muxed Data 169 C8051F020/1/2/3 Figure 17.7. XBR0: Port I/O Crossbar Register 0 R/W R/W CP0E ECI0E Bit7 Bit6 R/W R/W R/W PCA0ME Bit5 Bit4 Bit3 R/W R/W R/W Reset Value UART0EN SPI0EN SMB0EN 00000000 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bit7: Bit6: Bits5-3: Bit2: Bit1: Bit0: 170 CP0E: Comparator 0 Output Enable Bit. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. ECI0E: PCA0 External Counter Input Enable Bit. 0: PCA0 External Counter Input unavailable at Port pin. 1: PCA0 External Counter Input (ECI0) routed to Port pin. PCA0ME: PCA0 Module I/O Enable Bits. 000: All PCA0 I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to 2 Port pins. 011: CEX0, CEX1, and CEX2 routed to 3 Port pins. 100: CEX0, CEX1, CEX2, and CEX3 routed to 4 Port pins. 101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 Port pins. 110: RESERVED 111: RESERVED UART0EN: UART0 I/O Enable Bit. 0: UART0 I/O unavailable at Port pins. 1: UART0 TX routed to P0.0, and RX routed to P0.1. SPI0EN: SPI0 Bus I/O Enable Bit. 0: SPI0 I/O unavailable at Port pins. 1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins. SMB0EN: SMBus0 Bus I/O Enable Bit. 0: SMBus0 I/O unavailable at Port pins. 1: SMBus0 SDA and SCL routed to 2 Port pins. Rev. 1.4 C8051F020/1/2/3 Figure 17.8. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SYSCKE T2EXE T2E INT1E T1E INT0E T0E CP1E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE2 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: SYSCKE: /SYSCLK Output Enable Bit. 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK routed to Port pin. T2EXE: T2EX Input Enable Bit. 0: T2EX unavailable at Port pin. 1: T2EX routed to Port pin. T2E: T2 Input Enable Bit. 0: T2 unavailable at Port pin. 1: T2 routed to Port pin. INT1E: /INT1 Input Enable Bit. 0: /INT1 unavailable at Port pin. 1: /INT1 routed to Port pin. T1E: T1 Input Enable Bit. 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. INT0E: /INT0 Input Enable Bit. 0: /INT0 unavailable at Port pin. 1: /INT1 routed to Port pin. T0E: T0 Input Enable Bit. 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. CP1E: CP1 Output Enable Bit. 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. Rev. 1.4 171 C8051F020/1/2/3 Figure 17.9. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W R/W R/W R/W R/W R/W WEAKPUD Bit7 Reset Value XBARE - T4EXE T4E UART1E EMIFLE CNVSTE 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE3 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 172 WEAKPUD: Weak Pull-Up Disable Bit. 0: Weak pull-ups globally enabled. 1: Weak pull-ups globally disabled. XBARE: Crossbar Enable Bit. 0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode. 1: Crossbar enabled. UNUSED. Read = 0, Write = don't care. T4EXE: T4EX Input Enable Bit. 0: T4EX unavailable at Port pin. 1: T4EX routed to Port pin. T4E: T4 Input Enable Bit. 0: T4 unavailable at Port pin. 1: T4 routed to Port pin. UART1E: UART1 I/O Enable Bit. 0: UART1 I/O unavailable at Port pins. 1: UART1 TX and RX routed to 2 Port pins. EMIFLE: External Memory Interface Low-Port Enable Bit. 0: P0.7, P0.6, and P0.5 functions are determined by the Crossbar or the Port latches. 1: If EMI0CF.4 = ‘0’ (External Memory Interface is in Multiplexed mode) P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) are ‘skipped’ by the Crossbar and their output states are determined by the Port latches and the External Memory Interface. 1: If EMI0CF.4 = ‘1’ (External Memory Interface is in Non-multiplexed mode) P0.7 (/WR) and P0.6 (/RD) are ‘skipped’ by the Crossbar and their output states are determined by the Port latches and the External Memory Interface. CNVSTE: External Convert Start Input Enable Bit. 0: CNVSTR unavailable at Port pin. 1: CNVSTR routed to Port pin. Rev. 1.4 C8051F020/1/2/3 Figure 17.10. P0: Port0 Data Register R/W R/W R/W R/W R/W R/W R/W R/W P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0x80 P0.[7:0]: Port0 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P0MDOUT.n bit = 0). (Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings). 0: P0.n pin is logic low. 1: P0.n pin is logic high. Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory Interface. See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information. See also Figure 17.9 for information about configuring the Crossbar for External Memory accesses. Figure 17.11. P0MDOUT: Port0 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7-0: P0MDOUT.[7:0]: Port0 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. Rev. 1.4 173 C8051F020/1/2/3 Figure 17.12. P1: Port1 Data Register R/W R/W R/W R/W R/W R/W R/W R/W P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Notes: 1. 2. Reset Value 0x90 P1.[7:0]: Port1 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P1MDOUT.n bit = 0). (Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings). 0: P1.n pin is logic low. 1: P1.n pin is logic high. P1.[7:0] can be configured as inputs to ADC1 as AIN1.[7:0], in which case they are ‘skipped’ by the Crossbar assignment process and their digital input paths are disabled, depending on P1MDIN (See Figure 17.13). Note that in analog mode, the output mode of the pin is determined by the Port 1 latch and P1MDOUT (Figure 17.14). See Section “7. ADC1 (8-Bit ADC)” on page 75 for more information about ADC1. P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. Figure 17.13. P1MDIN: Port1 Input Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBD Bits7-0: 174 P1MDIN.[7:0]: Port 1 Input Mode Bits. 0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from the Port bit will always return ‘0’). The weak pull-up on the pin is disabled. 1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic level at the Pin. The state of the weak pull-up is determined by the WEAKPUD bit (XBR2.7, see Figure 17.9). Rev. 1.4 C8051F020/1/2/3 Figure 17.14. P1MDOUT: Port1 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xA5 Bits7-0: P1MDOUT.[7:0]: Port1 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. Figure 17.15. P2: Port2 Data Register R/W R/W R/W R/W R/W R/W R/W R/W P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xA0 Bits7-0: P2.[7:0]: Port2 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P2MDOUT.n bit = 0). (Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings). 0: P2.n pin is logic low. 1: P2.n pin is logic high. Note: P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed mode, or as Address[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. Figure 17.16. P2MDOUT: Port2 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA6 Bits7-0: P2MDOUT.[7:0]: Port2 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. Rev. 1.4 175 C8051F020/1/2/3 Figure 17.17. P3: Port3 Data Register R/W R/W R/W R/W R/W R/W R/W R/W P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xB0 Bits7-0: P3.[7:0]: Port3 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P3MDOUT.n bit = 0). (Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings). 0: P3.n pin is logic low. 1: P3.n pin is logic high. Note: P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or as D[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. Figure 17.18. P3MDOUT: Port3 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA7 Bits7-0: P3MDOUT.[7:0]: Port3 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. 176 Rev. 1.4 C8051F020/1/2/3 Figure 17.19. P3IF: Port3 Interrupt Flag Register R/W R/W IE7 IE6 Bit7 Bit6 R R R/W R/W R/W R/W Reset Value - - IE7CF IE6CF - - 00000000 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xAD Bit7: Bit6: Bits5-4: Bit3: Bit2: Bits1-0: 17.2. IE7: External Interrupt 7 Pending Flag 0: No falling edge has been detected on P3.7 since this bit was last cleared. 1: This flag is set by hardware when a falling edge on P3.7 is detected. IE6: External Interrupt 6 Pending Flag 0: No falling edge has been detected on P3.6 since this bit was last cleared. 1: This flag is set by hardware when a falling edge on P3.6 is detected. UNUSED. Read = 00b, Write = don’t care. IE7CF: External Interrupt 7 Edge Configuration 0: External Interrupt 7 triggered by a falling edge on the IE7 input. 1: External Interrupt 7 triggered by a rising edge on the IE7 input. IE6CF: External Interrupt 6 Edge Configuration 0: External Interrupt 6 triggered by a falling edge on the IE6 input. 1: External Interrupt 6 triggered by a rising edge on the IE6 input. UNUSED. Read = 00b, Write = don’t care. Ports 4 through 7 (C8051F020/2 only) All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 17.21, Figure 17.22, Figure 17.23, and Figure 17.24), a set of SFRs which are byte-addressable. A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV operation). During the read cycle of the read-modify-write instruction, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read. 17.2.1. Configuring Ports which are not Pinned Out Although P4, P5, P6, and P7 are not brought out to pins on the C8051F021/3 devices, the Port Data registers are still present and can be used by software. Because the digital input paths also remain active, it is recommended that these pins not be left in a ‘floating’ state in order to avoid unnecessary power dissipation arising from the inputs floating to non-valid logic levels. This condition can be prevented by any of the following: 1. 2. 3. Leave the weak pull-up devices enabled by setting WEAKPUD (XBR2.7) to a logic 0. Configure the output modes of P4, P5, P6, and P7 to “Push-Pull” by writing P74OUT = 0xFF. Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data registers: P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00. 17.2.2. Configuring the Output Modes of the Port Pins The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in the associated bit in the Rev. 1.4 177 C8051F020/1/2/3 Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a highimpedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire. The output modes of the Port pins on Ports 4 through 7 are determined by the bits in the P74OUT register (see Figure 17.20). Each bit in P74OUT controls the output mode of a 4-bit bank of Port pins on Ports 4, 5, 6, and 7. A logic 1 in P74OUT.7 will configure the output modes of 4 most-significant bits of Port 7, P7.[7:4], to Push-Pull; a logic 0 in P74OUT.7 will configure the output modes of P7.[7:4] to Open-Drain. 17.2.3. Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting P74OUT.7 to a logic 0 and P7.7 to a logic 1. 17.2.4. Weak Pull-ups By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about 100 kΩ) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is driving a logic 0; that is, an output pin will not contend with its own pull-up device. 17.2.5. External Memory Interface If the External Memory Interface (EMIF) is enabled on the High ports (Ports 4 through 7), EMIFLE (XBR2.1) should be set to a logic 0. If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the External Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX instruction, regardless of the settings of the Port Data registers. The output configuration of the Port pins is not affected by the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus during the MOVX execution. See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. 178 Rev. 1.4 C8051F020/1/2/3 Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P7H P7L P6H P6L P5H P5L P4H P4L 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB5 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: P7H: Port7 Output Mode High Nibble Bit. 0: P7.[7:4] configured as Open-Drain. 1: P7.[7:4] configured as Push-Pull. P7L: Port7 Output Mode Low Nibble Bit. 0: P7.[3:0] configured as Open-Drain. 1: P7.[3:0] configured as Push-Pull. P6H: Port6 Output Mode High Nibble Bit. 0: P6.[7:4] configured as Open-Drain. 1: P6.[7:4] configured as Push-Pull. P6L: Port6 Output Mode Low Nibble Bit. 0: P6.[3:0] configured as Open-Drain. 1: P6.[3:0] configured as Push-Pull. P5H: Port5 Output Mode High Nibble Bit. 0: P5.[7:4] configured as Open-Drain. 1: P5.[7:4] configured as Push-Pull. P5L: Port5 Output Mode Low Nibble Bit. 0: P5.[3:0] configured as Open-Drain. 1: P5.[3:0] configured as Push-Pull. P4H: Port4 Output Mode High Nibble Bit. 0: P4.[7:4] configured as Open-Drain. 1: P4.[7:4] configured as Push-Pull. P4L: Port4 Output Mode Low Nibble Bit. 0: P4.[3:0] configured as Open-Drain. 1: P4.[3:0] configured as Push-Pull. Rev. 1.4 179 C8051F020/1/2/3 Figure 17.21. P4: Port4 Data Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x84 Bits7-0: P4.[7:0]: Port4 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20. Read - Returns states of I/O pins. 0: P4.n pin is logic low. 1: P4.n pin is logic high. Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface. See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information. Figure 17.22. P5: Port5 Data Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x85 Bits7-0: P5.[7:0]: Port5 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20. Read - Returns states of I/O pins. 0: P5.n pin is logic low. 1: P5.n pin is logic high. Note: P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. 180 Rev. 1.4 C8051F020/1/2/3 Figure 17.23. P6: Port6 Data Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x86 Bits7-0: P6.[7:0]: Port6 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20. Read - Returns states of I/O pins. 0: P6.n pin is logic low. 1: P6.n pin is logic high. Note: P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed mode, or as Address[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. Figure 17.24. P7: Port7 Data Register R/W R/W R/W R/W R/W R/W R/W R/W P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x96 Bits7-0: P7.[7:0]: Port7 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20. Read - Returns states of I/O pins. 0: P7.n pin is logic low. 1: P7.n pin is logic high. Note: P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or as D[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory Interface. Rev. 1.4 181 C8051F020/1/2/3 Notes 182 Rev. 1.4 C8051F020/1/2/3 18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. SMBus0 is controlled by SFRs as described in Section 18.4 on page 189. Figure 18.1. SMBus0 Block Diagram SFR Bus SMB0CN B U S Y SMB0STA E S S S A F T N T T I A T O S A O E E M B S T A 7 S T A 6 S T A 5 S T A 4 S T A 3 S T A 2 SMB0CR S T A 1 S T A 0 C C C C C C C C R R R R R R R R 7 6 5 4 3 2 1 0 Clock Divide Logic SYSCLK SCL FILTER SMBUS CONTROL LOGIC SMBUS IRQ Arbitration SCL Synchronization Status Generation SCL Generation (Master Mode) IRQ Generation Interrupt Request SCL Control SDA Control C R O S S B A R A=B A=B Data Path Control B N A B A Port I/O 0000000b 7 MSBs 8 7 SMB0DAT 7 6 5 4 3 2 1 0 8 S L V 6 S L V 5 S L V 4 S L V 3 S L V 2 S L V 1 SDA FILTER 8 1 S L V G 0 C N 0 Read SMB0DAT SMB0ADR Write to SMB0DAT SFR Bus Rev. 1.4 183 C8051F020/1/2/3 Figure 18.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between 3.0 V and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus will not exceed 300 ns and 1000 ns, respectively. Figure 18.2. Typical SMBus Configuration VDD = 5V VDD = 3V VDD = 5V VDD = 3V Master Device Slave Device 1 Slave Device 2 SDA SCL 18.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. 2. 3. 184 The I2C-bus and how to use it (including specifications), Philips Semiconductor. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. Rev. 1.4 C8051F020/1/2/3 18.2. SMBus Protocol Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. Note: multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the master in a system; any device who transmits a START and a slave address becomes the master for that transfer. A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 18.3). If the receiving device does not ACK, the transmitting device will read a “not acknowledge” (NACK), which is a high SDA during a high SCL. The direction bit (R/W) occupies the least-significant bit position of the address. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 18.3 illustrates a typical SMBus transaction. Figure 18.3. SMBus Transaction SCL SDA SLA6 START SLA5-0 Slave Address + R/W R/W D7 ACK D6-0 Data Byte NACK STOP 18.2.1. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section 18.2.4). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is opendrain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and give up the bus. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer. This arbitration scheme is non-destructive: one device always wins, and no data is lost. 18.2.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. Rev. 1.4 185 C8051F020/1/2/3 18.2.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. 18.2.4. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. If an SMBus device is waiting to generate a Master START, the START will be generated following a bus free timeout. 186 Rev. 1.4 C8051F020/1/2/3 18.3. SMBus Transfer Modes The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the interface will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. See Table 18.1 for transfer mode status decoding using the SMB0STA status register. The following mode descriptions illustrate an interrupt-driven SMBus0 application; SMBus0 may alternatively be operated in polled mode. 18.3.1. Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output on SCL. SMBus0 generates a START condition and then transmits the first byte containing the address of the target slave device and the data direction bit. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface transmits one or more bytes of serial data, waiting for an acknowledge (ACK) from the slave after each byte. To indicate the end of the serial transfer, SMBus0 generates a STOP condition. Figure 18.4. Typical Master Transmitter Sequence S SLA W Interrupt A Data Byte Interrupt A Data Byte Interrupt A P Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface 18.3.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus0 interface generates a START followed by the first data byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives serial data from the slave and generates the clock on SCL. After each byte is received, SMBus0 generates an ACK or NACK depending on the state of the AA bit in register SMB0CN. SMBus0 generates a STOP condition to indicate the end of the serial transfer. Figure 18.5. Typical Master Receiver Sequence S SLA R Interrupt A Interrupt Data Byte A Data Byte Interrupt N P Interrupt S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Rev. 1.4 187 C8051F020/1/2/3 18.3.3. Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit. If the received slave address matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will also ACK if the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial data, waiting for an ACK from the master after each byte. SMBus0 exits slave mode after receiving a STOP condition from the master. Figure 18.6. Typical Slave Transmitter Sequence Interrupt S SLA R A Data Byte Interrupt A Data Byte Interrupt N P Interrupt S = START P = STOP N = NACK W = WRITE SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface 18.3.4. Slave Receiver Mode Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit. If the received slave address matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface receives one or more bytes of serial data; after each byte is received, the interface transmits an ACK or NACK depending on the state of the AA bit in SMB0CN. SMBus0 exits Slave Receiver Mode after receiving a STOP condition from the master. Figure 18.7. Typical Slave Receiver Sequence Interrupt S SLA W A Interrupt Data Byte A Interrupt A Transmitted by SMBus Interface Rev. 1.4 P Interrupt S = START P = STOP A = ACK R = READ SLA = Slave Address Received by SMBus Interface 188 Data Byte C8051F020/1/2/3 18.4. SMBus Special Function Registers The SMBus0 serial interface is accessed and controlled through five SFRs: SMB0CN Control Register, SMB0CR Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The five special function registers related to the operation of the SMBus0 interface are described in the following sections. 18.4.1. Control Register The SMBus0 Control register SMB0CN is used to configure and control the SMBus0 interface. All of the bits in the register can be read or written by software. Two of the control bits are also affected by the SMBus0 hardware. The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs. It can only be cleared by software. The Stop flag (STO, SMB0CN.4) is cleared to logic 0 by hardware when a STOP condition is detected on the bus. Setting the ENSMS flag to logic 1 enables the SMBus0 interface. Clearing the ENSMB flag to logic 0 disables the SMBus0 interface and removes it from the bus. Momentarily clearing the ENSMB flag and then resetting it to logic 1 will reset SMBus0 communication. However, ENSMB should not be used to temporarily remove a device from the bus since the bus state information will be lost. Instead, the Assert Acknowledge (AA) flag should be used to temporarily remove the device from the bus (see description of AA flag below). Setting the Start flag (STA, SMB0CN.5) to logic 1 will put SMBus0 in a master mode. If the bus is free, SMBus0 will generate a START condition. If the bus is not free, SMBus0 waits for a STOP condition to free the bus and then generates a START condition after a 5 µs delay per the SMB0CR value (In accordance with the SMBus protocol, the SMBus0 interface also considers the bus free if the bus is idle for 50 µs and no STOP condition was recognized). If STA is set to logic 1 while SMBus0 is in master mode and one or more bytes have been transferred, a repeated START condition will be generated. To ensure proper operation, the STO bit should be explicitly cleared to ‘0’ before setting the STA bit to ‘1’. When the Stop flag (STO, SMB0CN.4) is set to logic 1 while the SMBus0 interface is in master mode, the interface generates a STOP condition. In a slave mode, the STO flag may be used to recover from an error condition. In this case, a STOP condition is not generated on the bus, but the SMBus hardware behaves as if a STOP condition has been received and enters the "not addressed" slave receiver mode. Note that this simulated STOP will not cause the bus to appear free to SMBus0. The bus will remain occupied until a STOP appears on the bus or a Bus Free Timeout occurs. Hardware automatically clears the STO flag to logic 0 when a STOP condition is detected on the bus. The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by hardware when the SMBus0 interface enters one of 27 possible states. If interrupts are enabled for the SMBus0 interface, an interrupt request is generated when the SI flag is set. The SI flag must be cleared by software. Important Note: If SI is set to logic 1 while the SCL line is low, the clock-low period of the serial clock will be stretched and the serial transfer is suspended until SI is cleared to logic 0. A high level on SCL is not affected by the setting of the SI flag. The Assert Acknowledge flag (AA, SMB0CN.2) is used to set the level of the SDA line during the acknowledge clock cycle on the SCL line. Setting the AA flag to logic 1 will cause an ACK (low level on SDA) to be sent during the acknowledge cycle if the device has been addressed. Setting the AA flag to logic 0 will cause a NACK (high level on SDA) to be sent during acknowledge cycle. After the transmission of a byte in slave mode, the slave can be temporarily removed from the bus by clearing the AA flag. The slave's own address and general call address will be ignored. To resume operation on the bus, the AA flag must be reset to logic 1 to allow the slave's address to be recognized. Rev. 1.4 189 C8051F020/1/2/3 Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR. When SCL goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if SMBus0 is waiting to generate a START, it will do so after this timeout. The bus free period should be less than 50 µs (see Figure 18.9, SMBus0 Clock Rate Register). When the TOE bit in SMB0CN is set to logic 1, Timer 3 is used to detect SCL low timeouts. If Timer 3 is enabled (see Section “22.2. Timer 3” on page 240), Timer 3 is forced to reload when SCL is high, and forced to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and TOE set), a Timer 3 overflow indicates a SCL low timeout; the Timer 3 interrupt service routine can then be used to reset SMBus0 communication in the event of an SCL low timeout. 190 Rev. 1.4 C8051F020/1/2/3 Figure 18.8. SMB0CN: SMBus0 Control Register R R/W R/W R/W R/W R/W R/W R/W Reset Value BUSY ENSMB STA STO SI AA FTE TOE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 0xC0 BUSY: Busy Status Flag. 0: SMBus0 is free 1: SMBus0 is busy ENSMB: SMBus Enable. This bit enables/disables the SMBus serial interface. 0: SMBus0 disabled. 1: SMBus0 enabled. STA: SMBus Start Flag. 0: No START condition is transmitted. 1: When operating as a master, a START condition is transmitted if the bus is free. (If the bus is not free, the START is transmitted after a STOP is received.) If STA is set after one or more bytes have been transmitted or received and before a STOP is received, a repeated START condition is transmitted. To ensure proper operation, the STO bit should be explicitly cleared to ‘0’ before setting the STA bit to ‘1’. STO: SMBus Stop Flag. 0: No STOP condition is transmitted. 1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP condition is received, hardware clears STO to logic 0. If both STA and STO are set, a STOP condition is transmitted followed by a START condition. In slave mode, setting the STO flag causes SMBus to behave as if a STOP condition was received. SI: SMBus Serial Interrupt Flag. This bit is set by hardware when one of 27 possible SMBus0 states is entered. (Status code 0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes the CPU to vector to the SMBus interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. AA: SMBus Assert Acknowledge Flag. This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL line. 0: A "not acknowledge" (high level on SDA) is returned during the acknowledge cycle. 1: An "acknowledge" (low level on SDA) is returned during the acknowledge cycle. FTE: SMBus Free Timer Enable Bit 0: No timeout when SCL is high 1: Timeout when SCL high time exceeds limit specified by the SMB0CR value. TOE: SMBus Timeout Enable Bit 0: No timeout when SCL is low. Rev. 1.4 191 C8051F020/1/2/3 18.4.2. Clock Rate Register Figure 18.9. SMB0CR: SMBus0 Clock Rate Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xCF Bits7-0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles. The SMB0CR setting should be bounded by the following equation , where SMB0CR is the unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in Hz: SMB0CR < ( ( 288 – 0.85 ⋅ SYSCLK ) ⁄ 1.125 ) The resulting SCL signal high and low times are given by the following equations: T LOW = ( 256 – SMB0CR ) ⁄ SYSCLK T HIGH ≅ ( 258 – SMB0CR ) ⁄ SYSCLK + 625ns Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the following equation: ( 256 – SMB0CR ) + 1 T BFT ≅ 10 × ----------------------------------------------------SYSCLK 192 Rev. 1.4 C8051F020/1/2/3 18.4.3. Data Register The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software can read or write to this register while the SI flag is set to logic 1; software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0 since the hardware may be in the process of shifting a byte of data in or out of the register. Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. Therefore, SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in SMB0DAT. Figure 18.10. SMB0DAT: SMBus0 Data Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC2 Bits7-0: SMB0DAT: SMBus0 Data. The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial interface or a byte that has just been received on the SMBus0 serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set to logic 1. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. 18.4.4. Address Register The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the seven mostsignificant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the recognition of the general call address (0x00). If Bit0 is set to logic 1, the general call address will be recognized. Otherwise, the general call address is ignored. The contents of this register are ignored when SMBus0 is operating in master mode. Figure 18.11. SMB0ADR: SMBus0 Address Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SLV6 SLV5 SLV4 SLV3 SLV2 SLV1 SLV0 GC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC3 Bits7-1: SLV6-SLV0: SMBus0 Slave Address. These bits are loaded with the 7-bit slave address to which SMBus0 will respond when operating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address and corresponds to the first bit of the address byte received. Bit0: GC: General Call Address Enable. This bit is used to enable general call address (0x00) recognition. 0: General call address is ignored. 1: General call address is recognized. Rev. 1.4 193 C8051F020/1/2/3 18.4.5. Status Register The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 interface. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight. This facilitates the use of status codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive service routine). For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is logic 1. Software should never write to the SMB0STA register; doing so will yield indeterminate results. The 28 SMBus0 states, along with their corresponding status codes, are given in Table 1.1. Figure 18.12. SMB0STA: SMBus0 Status Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value STA7 STA6 STA5 STA4 STA3 STA2 STA1 STA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC1 Bits7-3: STA7-STA3: SMBus0 Status Code. These bits contain the SMBus0 Status Code. There are 28 possible status codes; each status code corresponds to a single SMBus state. A valid status code is present in SMB0STA when the SI flag (SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when the SI flag is logic 0. Writing to the SMB0STA register at any time will yield indeterminate results. Bits2-0: STA2-STA0: The three least significant bits of SMB0STA are always read as logic 0 when the SI flag is logic 1. 194 Rev. 1.4 C8051F020/1/2/3 Table 18.1. SMB0STA Status Codes and States Master Receiver Master Transmitter MT/ MR Mode Status Code SMBus State Typical Action 0x08 START condition transmitted. Load SMB0DAT with Slave Address + R/W. Clear STA. 0x10 Repeated START condition transmitted. Load SMB0DAT with Slave Address + R/W. Clear STA. 0x18 Slave Address + W transmitted. ACK received. Load SMB0DAT with data to be transmitted. 0x20 Slave Address + W transmitted. NACK received. Acknowledge poll to retry. Set STO + STA. 0x28 Data byte transmitted. ACK received. 0x30 Data byte transmitted. NACK received. 1) Retry transfer OR 2) Set STO. 0x38 Arbitration Lost. Save current data. 0x40 Slave Address + R transmitted. ACK received. If only receiving one byte, clear AA (send NACK after received byte). Wait for received data. 0x48 Slave Address + R transmitted. NACK received. Acknowledge poll to retry. Set STO + STA. 0x50 Data byte received. ACK transmitted. Read SMB0DAT. Wait for next byte. If next byte is last byte, clear AA. 0x58 Data byte received. NACK transmitted. Set STO. Rev. 1.4 1) Load SMB0DAT with next byte, OR 2) Set STO, OR 3) Clear STO then set STA for repeated START. 195 C8051F020/1/2/3 Table 18.1. SMB0STA Status Codes and States All Slave Slave Transmitter Slave Receiver Mode 196 Status Code SMBus State Typical Action 0x60 Own slave address + W received. ACK transmitted. Wait for data. 0x68 Arbitration lost in sending SLA + R/W as master. Own address + W received. ACK transmitted. Save current data for retry when bus is free. Wait for data. 0x70 General call address received. ACK transmitted. Wait for data. 0x78 Arbitration lost in sending SLA + R/W as master. General call address received. ACK transmitted. Save current data for retry when bus is free. 0x80 Data byte received. ACK transmitted. Read SMB0DAT. Wait for next byte or STOP. 0x88 Data byte received. NACK transmitted. Set STO to reset SMBus. 0x90 Data byte received after general call address. ACK transmitted. Read SMB0DAT. Wait for next byte or STOP. 0x98 Data byte received after general call address. NACK transmitted. Set STO to reset SMBus. 0xA0 STOP or repeated START received. No action necessary. 0xA8 Own address + R received. ACK transmitted. Load SMB0DAT with data to transmit. 0xB0 Arbitration lost in transmitting SLA + R/W as master. Own address + R received. ACK transmitted. Save current data for retry when bus is free. Load SMB0DAT with data to transmit. 0xB8 Data byte transmitted. ACK received. Load SMB0DAT with data to transmit. 0xC0 Data byte transmitted. NACK received. Wait for STOP. 0xC8 Last data byte transmitted (AA=0). ACK received. Set STO to reset SMBus. 0xD0 SCL Clock High Timer per SMB0CR timed out Set STO to reset SMBus. 0x00 Bus Error (illegal START or STOP) Set STO to reset SMBus. 0xF8 Idle State does not set SI. Rev. 1.4 C8051F020/1/2/3 19. SERIAL PERIPHERAL INTERFACE BUS (SPI0) The Serial Peripheral Interface (SPI0) provides access to a four-wire, full-duplex, serial bus. SPI0 may operate as a master or a slave, and supports the connection of multiple slaves and masters on the same bus. A slave-select input (NSS) is included in the SPI0 interface to select SPI0 as a slave; additional general purpose port I/O can be used as slave-select outputs when SPI0 is operating as a master. Collision detection is provided when two or more masters attempt a data transfer at the same time. When the SPI is configured as a master, the maximum data transfer rate (bits/ sec) is one-half the system clock frequency. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS, and the serial input data synchronously with the system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less that 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the system clock. Figure 19.1. SPI Block Diagram SFR Bus SPI0CKR S C R 7 SYSCLK S C R 6 S C R 5 S C R 4 S C R 3 S C R 2 SPI0CFG S C R 1 S C R 0 C K P H A C B B B F K C C C R P 2 1 0 S O 2 L Clock Divide Logic SPI0CN F R S 1 F R S 0 S P I F W C O L M O D F R X O V R N T X B S Y S L V S E L M S T E N S P I E N Bit Count Logic SPI CONTROL LOGIC Data Path Control SPI Clock (Master Mode) SPI IRQ Pin Control Interface SCK MOSI Tx Data SPI0DAT Shift Register 7 6 5 4 3 2 1 0 Rx Data Pin Control Logic Receive Data Register Write to SPI0DAT MISO C R O S S B A R Port I/O NSS Read SPI0DAT SFR Bus Rev. 1.4 197 C8051F020/1/2/3 19.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 19.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master, and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. 19.1.2. Master In, Slave Out (MISO) The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master, and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. A SPI slave places the MISO pin in a high-impedance state when the slave is not selected. 19.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. 19.1.4. Slave Select (NSS) The slave select (NSS) signal is an input used to select SPI0 as a slave, or to disable SPI0 as a master. Note that the NSS signal is always an input to SPI0; with SPI0 operating as a master, slave select signals must be output via general purpose port I/O pins. See Figure 19.2 for a typical configuration; see Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 163 for general purpose port configuration. The NSS signal must be low to initiate a transfer with SPI0 as a slave; SPI0 will exit slave mode when NSS is released high. Note that received data is not latched into the receive buffer until NSS is high. For multiple-byte transfers, NSS must be released high for at least 4 system clocks following each byte that is received by the SPI0 slave. Figure 19.2. Typical SPI Interconnection NSS NSS NSS Slave Device Slave Device Slave Device VDD GPIO Master Device 198 MISO MISO MOSI MOSI SCK SCK Rev. 1.4 C8051F020/1/2/3 19.2. SPI0 Operation Only a SPI master device can initiate a data transfer. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.1). Writing a byte of data to the SPI0 data register (SPI0DAT) when in Master Mode starts a data transfer. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. The SPI0 master can be configured to shift in/out from one to eight bits in a transfer operation in order to accommodate slave devices with different word lengths. The SPIFRS bits in the SP0I Configuration Register (SPI0CFG.[2:0]) are used to select the number of bits to shift in/out in a transfer operation. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. The data byte received from the slave replaces the data in the master's data register. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data transfer in both directions is synchronized with the serial clock generated by the master. Figure 19.3 illustrates the full-duplex operation of an SPI master and an addressed slave. MASTER DEVICE SPI SHIFT REGISTER 7 6 5 4 3 2 1 0 Figure 19.3. Full Duplex Operation MOSI MOSI MISO MISO SLAVE DEVICE SPI SHIFT REGISTER 7 6 5 4 3 2 1 0 VDD Receive Buffer NSS NSS Baud Rate Generator SCK SCK Receive Buffer Px.y When SPI0 is enabled and not configured as a master, it will operate as an SPI slave. Another SPI device acting as a master will initiate a transfer by driving the NSS input signal low. The master then shifts data out of the shift register on the MOSI pin using the its serial clock. The SPIF flag is set to logic 1 when the NSS signal goes high, indicating the end of a data transfer. Note that following a rising edge on NSS, the receive buffer will always contain the last 8 bits of data in the slave shift register. The slave can load its shift register for the next data transfer by writing to the SPI0 data register. The slave must make the write to the data register at least one SPI serial clock cycle before the master starts the next transmission. Otherwise, the byte of data already in the slave's shift register will be transferred. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. The SPI0 data register is double buffered on reads, but not on writes. If a write to SPI0DAT is attempted during a data transfer, the WCOL flag (SPI0CN.6) will be set to logic 1 and the write will be ignored. The current data transfer will continue uninterrupted. A read of the SPI0 data register by the system controller actually reads the receive buffer. The receive overrun flag (RXOVRN in register SPI0CN) is set anytime a SPI0 slave detects a rising edge on NSS while the receive buffer still holds unread data from a previous transfer. The new data is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte causing the overrun is lost. Rev. 1.4 199 C8051F020/1/2/3 Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when SPI0 is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the Mode Fault flag is set, the MSTEN and SPIEN bits of the SPI control register are cleared by hardware, thereby placing the SPI0 module in an "off-line" state. In a multiple-master environment, the system controller should check the state of the SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the MSTEN bit and initiating a data transfer. 19.3. Serial Clock Timing As shown in Figure 19.4, four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. Note: SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) while changing the clock phase and polarity. The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 19.7 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. Figure 19.4. Data/Clock Timing Diagram SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB Bit 6 Bit 5 Bit 4 NSS 200 Rev. 1.4 Bit 3 Bit 2 Bit 1 Bit 0 C8051F020/1/2/3 19.4. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following section. Figure 19.5. SPI0CFG: SPI0 Configuration Register R/W R/W R R R R/W R/W R/W Reset Value CKPHA CKPOL BC2 BC1 BC0 SPIFRS2 SPIFRS1 SPIFRS0 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A Bit7: Bit6: Bits5-3: CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data sampled on first edge of SCK period. 1: Data sampled on second edge of SCK period. CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. BC2-BC0: SPI0 Bit Count. Indicates which of the up to 8 bits of the SPI0 word have been transmitted. 0 0 0 0 1 1 1 1 Bits2-0: BC2-BC0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 BIT Transmitted Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB) SPIFRS2-SPIFRS0: SPI0 Frame Size. These three bits determine the number of bits to shift in/out of the SPI0 shift register during a data transfer in master mode. They are ignored in slave mode. 0 0 0 0 1 1 1 1 SPIFRS 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bits Shifted 1 2 3 4 5 6 7 8 Rev. 1.4 201 C8051F020/1/2/3 Figure 19.6. SPI0CN: SPI0 Control Register R/W R/W R/W R/W R R R/W R/W SPIF WCOL MODF RXOVRN TXBSY SLVSEL MSTEN SPIEN 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 202 Reset Value 0xF8 SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. WCOL: Write Collision Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. MODF: Mode Fault Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low and MSTEN = 1). If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. RXOVRN: Receive Overrun Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. TXBSY: Transmit Busy Flag. This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is cleared by hardware at the end of the transfer. SLVSEL: Slave Selected Flag. This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It is cleared to logic 0 when NSS is high (slave disabled). MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. Rev. 1.4 C8051F020/1/2/3 Figure 19.7. SPI0CKR: SPI0 Clock Rate Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9D Bits7-0: SCR7-SCR0: SPI0 Clock Rate These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided down version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CR is the 8bit value held in the SPI0CR register. SYSCLK f SCK = ------------------------------------------------2 × ( SPI0CKR + 1 ) for 0