C8051F320R

C8051F320/1 Full Speed USB, 16k ISP FLASH MCU Family ANALOG PERIPHERALS - 10-Bit ADC • Up to 200 ksps • Up to 17 or 13 External Single-Ended or Differential Instructions in 1 or 2 System Clocks - Up to 25 MIPS Throughput with 25 MHz Clock - Expanded Interrupt Handler MEMORY - 2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO) - 16k Bytes FLASH; In-system programmable in 512-byte Inputs VREF from External Pin, Internal Reference, or VDD Built-in Temperature Sensor External Conversion Start Input - Two Comparators - Internal Voltage Reference - POR/Brown-Out Detector USB FUNCTION CONTROLLER - USB Specification 2.0 Compliant - Full Speed (12 Mbps) or Low Speed (1.5 Mbps) - Sectors DIGITAL PERIPHERALS - 25/21 Port I/O; All 5 V tolerant with High Sink Current - Hardware Enhanced SPI™, Enhanced UART, and Operation Integrated Clock Recovery; No External Crystal Required for Full Speed or Low Speed Supports Eight Flexible Endpoints 1k Byte USB Buffer Memory Integrated Transceiver; No External Resistors Required ON-CHIP DEBUG - On-Chip Debug Circuitry Facilitates Full Speed, - ANALOG PERIPHERALS TEMP SENSOR VREF + - + - VREG PRECISION INTERNAL OSCILLATOR SMBus™ Serial Ports Four General Purpose 16-Bit Counter/Timers 16-Bit Programmable Counter Array (PCA) with Five Capture/Compare Modules Real Time Clock Mode using External Clock Source and PCA or Timer CLOCK SOURCES - Internal Oscillator: 0.25% Accuracy with Clock - VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V 10-bit 200ksps ADC - - Non-Intrusive In-System Debug (No Emulator Required!) Provides Breakpoints, Single Stepping, Inspect/Modify Memory and Registers Superior Performance to Emulation Systems Using ICE-Chips, Target Pods, and Sockets A M U X - Recovery enabled. Supports all USB and UART Modes External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin Modes) Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Strategies PACKAGES - 32-pin LQFP (C8051F320) - 28-pin MLP (C8051F321) TEMPERATURE RANGE: -40°C TO +85°C DIGITAL I/O UART SPI SMBus PCA Timer 0 Timer 1 Timer 2 Timer 3 CROSSBAR • • • HIGH SPEED 8051 µC Core - Pipelined Instruction Architecture; Executes 70% of Port 0 Port 1 Port 2 Port 3 USB Controller / Transceiver HIGH-SPEED CONTROLLER CORE 16KB ISP FLASH 16 INTERRUPTS Preliminary Rev. 1.1 12/03 8051 CPU (25MIPS) DEBUG CIRCUITRY 2304 B SRAM POR Copyright © 2003 by Silicon Laboratories WDT C8051F320/1-DS11 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. C8051F320/1 Notes 2 Rev. 1.1 C8051F320/1 TABLE OF CONTENTS 1. SYSTEM OVERVIEW .........................................................................................................17 1.1. CIP-51™ Microcontroller Core ......................................................................................20 1.1.1. Fully 8051 Compatible ..........................................................................................20 1.1.2. Improved Throughput ............................................................................................20 1.1.3. Additional Features................................................................................................21 1.2. On-Chip Memory ............................................................................................................22 1.3. Universal Serial Bus Controller.......................................................................................23 1.4. Voltage Regulator............................................................................................................23 1.5. On-Chip Debug Circuitry ................................................................................................24 1.6. Programmable Digital I/O and Crossbar .........................................................................25 1.7. Serial Ports.......................................................................................................................25 1.8. Programmable Counter Array .........................................................................................26 1.9. 10-Bit Analog to Digital Converter.................................................................................27 1.10. Comparators ....................................................................................................................28 2. ABSOLUTE MAXIMUM RATINGS ..................................................................................29 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................30 4. PINOUT AND PACKAGE DEFINITIONS........................................................................31 5. 10-BIT ADC (ADC0) .............................................................................................................39 5.1. Analog Multiplexer .........................................................................................................40 5.2. Temperature Sensor.........................................................................................................41 5.3. Modes of Operation.........................................................................................................42 5.3.1. Starting a Conversion.............................................................................................42 5.3.2. Tracking Modes .....................................................................................................43 5.3.3. Settling Time Requirements ..................................................................................44 5.4. Programmable Window Detector ....................................................................................50 5.4.1. Window Detector In Single-Ended Mode .............................................................52 5.4.2. Window Detector In Differential Mode.................................................................53 6. VOLTAGE REFERENCE....................................................................................................55 7. COMPARATORS ................................................................................................................57 8. VOLTAGE REGULATOR (REG0) ....................................................................................67 8.1. Regulator Mode Selection ...............................................................................................68 8.2. VBUS Detection..............................................................................................................69 9. CIP-51 MICROCONTROLLER .........................................................................................73 9.1. Instruction Set..................................................................................................................75 9.1.1. Instruction and CPU Timing..................................................................................75 9.1.2. MOVX Instruction and Program Memory.............................................................75 9.2. Memory Organization .....................................................................................................79 9.2.1. Program Memory ...................................................................................................79 9.2.2. Data Memory .........................................................................................................80 9.2.3. General Purpose Registers .....................................................................................80 9.2.4. Bit Addressable Locations .....................................................................................80 9.2.5. Stack ...................................................................................................................80 9.2.6. Special Function Registers.....................................................................................81 Rev. 1.1 3 C8051F320/1 9.2.7. Register Descriptions .............................................................................................84 9.3. Interrupt Handler .............................................................................................................87 9.3.1. MCU Interrupt Sources and Vectors .....................................................................87 9.3.2. External Interrupts .................................................................................................88 9.3.3. Interrupt Priorities..................................................................................................88 9.3.4. Interrupt Latency....................................................................................................88 9.3.5. Interrupt Register Descriptions ..............................................................................90 9.4. Power Management Modes .............................................................................................96 9.4.1. Idle Mode ...............................................................................................................96 9.4.2. Stop Mode..............................................................................................................96 10. RESET SOURCES ..............................................................................................................99 10.1. Power-On Reset.............................................................................................................100 10.2. Power-Fail Reset / VDD Monitor..................................................................................101 10.3. External Reset................................................................................................................102 10.4. Missing Clock Detector Reset .......................................................................................102 10.5.Comparator0 Reset ........................................................................................................102 10.6. PCA Watchdog Timer Reset .........................................................................................102 10.7. FLASH Error Reset .......................................................................................................102 10.8. Software Reset...............................................................................................................103 10.9. USB Reset .....................................................................................................................103 11. FLASH MEMORY ............................................................................................................107 11.1. Programming The FLASH Memory .............................................................................107 11.1.1. FLASH Lock and Key Functions ........................................................................107 11.1.2. FLASH Erase Procedure......................................................................................107 11.1.3. FLASH Write Procedure .....................................................................................108 11.2. Non-volatile Data Storage .............................................................................................109 11.3. Security Options ............................................................................................................109 12. EXTERNAL RAM .............................................................................................................113 12.1. Accessing User XRAM .................................................................................................113 12.2. Accessing USB FIFO Space..........................................................................................114 13. OSCILLATORS...................................................................................................................117 13.1. Programmable Internal Oscillator .................................................................................117 13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices .........................118 13.1.2. Internal Oscillator Suspend Mode .......................................................................118 13.2.External Oscillator Drive Circuit...................................................................................120 13.2.1. Clocking Timers Directly Through the External Oscillator ................................120 13.2.2. External Crystal Example ....................................................................................120 13.2.3. External RC Example ..........................................................................................121 13.2.4. External Capacitor Example ................................................................................121 13.3.4x Clock Multiplier .......................................................................................................123 13.4. System and USB Clock Selection .................................................................................124 13.4.1. System Clock Selection .......................................................................................124 13.4.2. USB Clock Selection ...........................................................................................124 14. PORT INPUT/OUTPUT ...................................................................................................127 14.1. Priority Crossbar Decoder .............................................................................................129 4 Rev. 1.1 C8051F320/1 14.2. Port I/O Initialization.....................................................................................................131 14.3.General Purpose Port I/O...............................................................................................134 15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ....................................................143 15.1.Endpoint Addressing .....................................................................................................144 15.2. USB Transceiver ...........................................................................................................144 15.3. USB Register Access.....................................................................................................146 15.4.USB Clock Configuration .............................................................................................150 15.5. FIFO Management.........................................................................................................151 15.5.1. FIFO Split Mode ..................................................................................................151 15.5.2. FIFO Double Buffering .......................................................................................151 15.5.3. FIFO Access ........................................................................................................152 15.6. Function Addressing......................................................................................................153 15.7. Function Configuration and Control .............................................................................154 15.8. Interrupts .......................................................................................................................157 15.9.The Serial Interface Engine ...........................................................................................161 15.10.Endpoint0.....................................................................................................................161 15.10.1.Endpoint0 SETUP Transactions .........................................................................162 15.10.2.Endpoint0 IN Transactions .................................................................................162 15.10.3.Endpoint0 OUT Transactions .............................................................................163 15.11.Configuring Endpoints1-3 ...........................................................................................166 15.12.Controlling Endpoints1-3 IN .......................................................................................166 15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode ...........................................................166 15.12.2.Endpoints1-3 IN Isochronous Mode...................................................................167 15.13.Controlling Endpoints1-3 OUT ...................................................................................170 15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode .......................................................170 15.13.2.Endpoints1-3 OUT Isochronous Mode...............................................................170 16. SMBUS..................................................................................................................................175 16.1. Supporting Documents ..................................................................................................176 16.2. SMBus Configuration....................................................................................................176 16.3. SMBus Operation ..........................................................................................................177 16.3.1. Arbitration............................................................................................................177 16.3.2. Clock Low Extension...........................................................................................178 16.3.3. SCL Low Timeout ...............................................................................................178 16.3.4. SCL High (SMBus Free) Timeout.......................................................................178 16.4. Using the SMBus...........................................................................................................179 16.4.1. SMBus Configuration Register............................................................................180 16.4.2. SMB0CN Control Register ..................................................................................183 16.4.3. Data Register........................................................................................................186 16.5. SMBus Transfer Modes.................................................................................................187 16.5.1. Master Transmitter Mode ....................................................................................187 16.5.2. Master Receiver Mode.........................................................................................188 16.5.3. Slave Receiver Mode ...........................................................................................189 16.5.4. Slave Transmitter Mode.......................................................................................190 16.6. SMBus Status Decoding................................................................................................191 17. UART0 ..................................................................................................................................193 Rev. 1.1 5 C8051F320/1 17.1. Enhanced Baud Rate Generation...................................................................................194 17.2. Operational Modes ........................................................................................................195 17.2.1. 8-Bit UART .........................................................................................................195 17.2.2. 9-Bit UART .........................................................................................................196 17.3. Multiprocessor Communications...................................................................................197 18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................203 18.1. Signal Descriptions........................................................................................................204 18.1.1. Master Out, Slave In (MOSI) ..............................................................................204 18.1.2. Master In, Slave Out (MISO) ..............................................................................204 18.1.3. Serial Clock (SCK) ..............................................................................................204 18.1.4. Slave Select (NSS)...............................................................................................204 18.2. SPI0 Master Mode Operation........................................................................................205 18.3. SPI0 Slave Mode Operation ..........................................................................................207 18.4. SPI0 Interrupt Sources...................................................................................................207 18.5. Serial Clock Timing ......................................................................................................208 18.6. SPI Special Function Registers .....................................................................................210 19. TIMERS ...............................................................................................................................217 19.1. Timer 0 and Timer 1......................................................................................................217 19.1.1. Mode 0: 13-bit Counter/Timer.............................................................................217 19.1.2. Mode 1: 16-bit Counter/Timer.............................................................................218 19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload .................................................219 19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................220 19.2. Timer 2 .......................................................................................................................225 19.2.1. 16-bit Timer with Auto-Reload ...........................................................................225 19.2.2. 8-bit Timers with Auto-Reload............................................................................226 19.2.3. USB Start-of-Frame Capture ...............................................................................227 19.3. Timer 3 .......................................................................................................................230 19.3.1. 16-bit Timer with Auto-Reload ...........................................................................230 19.3.2. 8-bit Timers with Auto-Reload............................................................................231 19.3.3. USB Start-of-Frame Capture ...............................................................................232 20. PROGRAMMABLE COUNTER ARRAY (PCA0) .........................................................235 20.1.PCA Counter/Timer.......................................................................................................236 20.2. Capture/Compare Modules............................................................................................237 20.2.1. Edge-triggered Capture Mode .............................................................................238 20.2.2. Software Timer (Compare) Mode........................................................................239 20.2.3. High Speed Output Mode ....................................................................................240 20.2.4. Frequency Output Mode ......................................................................................241 20.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................242 20.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................244 20.3. Watchdog Timer Mode..................................................................................................246 20.3.1. Watchdog Timer Operation .................................................................................246 20.3.2. Watchdog Timer Usage .......................................................................................247 20.4. Register Descriptions for PCA ......................................................................................248 21. C2 INTERFACE ..................................................................................................................253 21.1. C2 Interface Registers ...................................................................................................253 6 Rev. 1.1 C8051F320/1 21.2. C2 Pin Sharing...............................................................................................................255 Rev. 1.1 7 C8051F320/1 Notes 8 Rev. 1.1 C8051F320/1 LIST OF FIGURES AND TABLES 1. SYSTEM OVERVIEW ........................................................................................................17 Table 1.1. Product Selection Guide ......................................................................................17 Figure 1.1. C8051F320 Block Diagram.................................................................................18 Figure 1.2. C8051F321 Block Diagram.................................................................................19 Figure 1.3. Comparison of Peak MCU Execution Speeds.....................................................20 Figure 1.4. On-Chip Clock and Reset....................................................................................21 Figure 1.5. On-Board Memory Map ......................................................................................22 Figure 1.6. USB Controller Block Diagram ..........................................................................23 Figure 1.7. Development/In-System Debug Diagram ...........................................................24 Figure 1.8. Digital Crossbar Diagram....................................................................................25 Figure 1.9. PCA Block Diagram............................................................................................26 Figure 1.10. PCA Block Diagram............................................................................................26 Figure 1.11. 10-Bit ADC Block Diagram................................................................................27 Figure 1.12. Comparator0 Block Diagram ..............................................................................28 2. ABSOLUTE MAXIMUM RATINGS .................................................................................29 Table 2.1. Absolute Maximum Ratings*..............................................................................29 3. GLOBAL DC ELECTRICAL CHARACTERISTICS .....................................................30 Table 3.1. Global DC Electrical Characteristics...................................................................30 4. PINOUT AND PACKAGE DEFINITIONS .......................................................................31 Table 4.1. Pin Definitions for the C8051F320/1 ..................................................................31 Figure 4.1. LQFP-32 Pinout Diagram (Top View)................................................................33 Figure 4.2. LQFP-32 Package Diagram.................................................................................34 Table 4.2. LQFP-32 Package Dimensions............................................................................34 Figure 4.3. MLP-28 Pinout Diagram (Top View) .................................................................35 Figure 4.4. MLP-28 Package Drawing ..................................................................................36 Table 4.3. MLP-28 Package Dimensions .............................................................................36 Figure 4.5. Typical MLP-28 Landing Diagram .....................................................................37 Figure 4.6. Typical MLP-28 Solder Mask .............................................................................38 5. 10-BIT ADC (ADC0) ............................................................................................................39 Figure 5.1. ADC0 Functional Block Diagram .......................................................................39 Figure 5.2. Typical Temperature Sensor Transfer Function..................................................41 Figure 5.3. 10-Bit ADC Track and Conversion Example Timing.........................................43 Figure 5.4. ADC0 Equivalent Input Circuits .........................................................................44 Figure 5.5. AMX0P: AMUX0 Positive Channel Select Register..........................................45 Figure 5.6. AMX0N: AMUX0 Negative Channel Select Register........................................46 Figure 5.7. ADC0CF: ADC0 Configuration Register ...........................................................47 Figure 5.8. ADC0H: ADC0 Data Word MSB Register.........................................................47 Figure 5.9. ADC0L: ADC0 Data Word LSB Register ..........................................................48 Figure 5.10. ADC0CN: ADC0 Control Register .....................................................................49 Figure 5.11. ADC0GTH: ADC0 Greater-Than Data High Byte Register...............................50 Figure 5.12. ADC0GTL: ADC0 Greater-Than Data Low Byte Register ................................50 Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register ....................................51 Figure 5.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register .....................................51 Rev. 1.1 9 C8051F320/1 6. 7. 8. 9. 10 Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data..............52 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data ................52 Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data.................53 Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ...................53 Table 5.1. ADC0 Electrical Characteristics..........................................................................54 VOLTAGE REFERENCE ...................................................................................................55 Figure 6.1. Voltage Reference Functional Block Diagram....................................................55 Figure 6.2. REF0CN: Reference Control Register ................................................................56 Table 6.1. Voltage Reference Electrical Characteristics ......................................................56 COMPARATORS ...............................................................................................................57 Figure 7.1. Comparator0 Functional Block Diagram ............................................................57 Figure 7.2. Comparator1 Functional Block Diagram ............................................................58 Figure 7.3. Comparator Hysteresis Plot.................................................................................59 Figure 7.4. CPT0CN: Comparator0 Control Register ...........................................................60 Figure 7.5. CPT0MX: Comparator0 MUX Selection Register..............................................61 Figure 7.6. CPT0MD: Comparator0 Mode Selection Register..............................................62 Figure 7.7. CPT1CN: Comparator1 Control Register ...........................................................63 Figure 7.8. CPT1MX: Comparator1 MUX Selection Register..............................................64 Figure 7.9. CPT1MD: Comparator1 Mode Selection Register..............................................65 Table 7.1. Comparator Electrical Characteristics.................................................................66 VOLTAGE REGULATOR (REG0) ...................................................................................67 Table 8.1. Voltage Regulator Electrical Specifications........................................................69 Figure 8.1. REG0 Configuration: USB Bus-Powered ...........................................................70 Figure 8.2. REG0 Configuration: USB Self-Powered ...........................................................70 Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled ..........................71 Figure 8.4. REG0 Configuration: No USB Connection ........................................................71 Figure 8.5. REG0CN: Voltage Regulator Control.................................................................72 CIP-51 MICROCONTROLLER ........................................................................................73 Figure 9.1. CIP-51 Block Diagram ........................................................................................73 Table 9.1. CIP-51 Instruction Set Summary.........................................................................75 Figure 9.2. Memory Map .......................................................................................................79 Table 9.2. Special Function Register (SFR) Memory Map..................................................81 Table 9.3. Special Function Registers ..................................................................................81 Figure 9.3. DPL: Data Pointer Low Byte ..............................................................................84 Figure 9.4. DPH: Data Pointer High Byte .............................................................................84 Figure 9.5. SP: Stack Pointer .................................................................................................85 Figure 9.6. PSW: Program Status Word ................................................................................85 Figure 9.7. ACC: Accumulator..............................................................................................86 Figure 9.8. B: B Register .......................................................................................................86 Table 9.4. Interrupt Summary...............................................................................................89 Figure 9.9. IE: Interrupt Enable .............................................................................................90 Figure 9.10. IP: Interrupt Priority ............................................................................................91 Figure 9.11. EIE1: Extended Interrupt Enable 1 .....................................................................92 Figure 9.12. EIP1: Extended Interrupt Priority 1.....................................................................93 Figure 9.13. EIE2: Extended Interrupt Enable 2 .....................................................................94 Rev. 1.1 C8051F320/1 Figure 9.14. EIP2: Extended Interrupt Priority 2.....................................................................94 Figure 9.15. IT01CF: INT0/INT1 Configuration Register ......................................................95 Figure 9.16. PCON: Power Control Register ..........................................................................97 10. RESET SOURCES .............................................................................................................99 Figure 10.1. Reset Sources ......................................................................................................99 Figure 10.2. Power-On and VDD Monitor Reset Timing .....................................................100 Figure 10.3. VDM0CN: VDD Monitor Control ....................................................................101 Figure 10.4. RSTSRC: Reset Source Register.......................................................................104 Table 10.1. Reset Electrical Characteristics .........................................................................105 11. FLASH MEMORY ...........................................................................................................107 Table 11.1. FLASH Electrical Characteristics .....................................................................108 Figure 11.1. FLASH Program Memory Map and Security Byte...........................................110 Figure 11.2. PSCTL: Program Store R/W Control ................................................................110 Figure 11.3. FLKEY: FLASH Lock and Key Register .........................................................111 Figure 11.4. FLSCL: FLASH Scale Register ........................................................................111 12. EXTERNAL RAM ............................................................................................................113 Figure 12.1. External Ram Memory Map..............................................................................113 Figure 12.2. XRAM Memory Map Expanded View .............................................................114 Figure 12.3. EMI0CN: External Memory Interface Control .................................................115 13. OSCILLATORS ..................................................................................................................117 Figure 13.1. Oscillator Diagram ............................................................................................117 Figure 13.2. OSCICN: Internal Oscillator Control Register .................................................119 Figure 13.3. OSCICL: Internal Oscillator Calibration Register ............................................119 Figure 13.4. OSCXCN: External Oscillator Control Register...............................................122 Figure 13.5. CLKMUL: Clock Multiplier Control Register..................................................123 Table 13.1. Typical USB Full Speed Clock Settings ...........................................................124 Table 13.2. Typical USB Low Speed Clock Settings...........................................................124 Figure 13.6. CLKSEL: Clock Select Register .......................................................................125 Table 13.3. Internal Oscillator Electrical Characteristics.....................................................126 14. PORT INPUT/OUTPUT ..................................................................................................127 Figure 14.1. Port I/O Functional Block Diagram ..................................................................127 Figure 14.2. Port I/O Cell Block Diagram.............................................................................128 Figure 14.3. Crossbar Priority Decoder with No Pins Skipped .............................................129 Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ......................................130 Figure 14.5. XBR0: Port I/O Crossbar Register 0 .................................................................132 Figure 14.6. XBR1: Port I/O Crossbar Register 1 .................................................................133 Figure 14.7. P0: Port0 Register..............................................................................................135 Figure 14.8. P0MDIN: Port0 Input Mode Register ...............................................................135 Figure 14.9. P0MDOUT: Port0 Output Mode Register.........................................................136 Figure 14.10. P0SKIP: Port0 Skip Register...........................................................................136 Figure 14.11. P1: Port1 Register............................................................................................137 Figure 14.12. P1MDIN: Port1 Input Mode Register .............................................................137 Figure 14.13. P1MDOUT: Port1 Output Mode Register.......................................................138 Figure 14.14. P1SKIP: Port1 Skip Register...........................................................................138 Figure 14.15. P2: Port2 Register............................................................................................139 Rev. 1.1 11 C8051F320/1 Figure 14.16. P2MDIN: Port2 Input Mode Register .............................................................139 Figure 14.17. P2MDOUT: Port2 Output Mode Register.......................................................140 Figure 14.18. P2SKIP: Port2 Skip Register...........................................................................140 Figure 14.19. P3: Port3 Register............................................................................................141 Figure 14.20. P3MDIN: Port3 Input Mode Register .............................................................141 Figure 14.21. P3MDOUT: Port3 Output Mode Register.......................................................142 Table 14.1. Port I/O DC Electrical Characteristics ..............................................................142 15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ...................................................143 Figure 15.1. USB0 Block Diagram........................................................................................143 Table 15.1. Endpoint Addressing Scheme............................................................................144 Figure 15.2. USB0XCN: USB0 Transceiver Control............................................................145 Figure 15.3. USB0 Register Access Scheme .........................................................................146 Figure 15.4. USB0ADR: USB0 Indirect Address Register ...................................................147 Figure 15.5. USB0DAT: USB0 Data Register ......................................................................148 Figure 15.6. INDEX: USB0 Endpoint Index (USB Register) ...............................................148 Table 15.2. USB0 Controller Registers ................................................................................149 Figure 15.7. CLKREC: Clock Recovery Control (USB Register) ........................................150 Figure 15.8. USB FIFO Allocation........................................................................................151 Table 15.3. FIFO Configurations .........................................................................................152 Figure 15.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers) ...................................152 Figure 15.10. FADDR: USB0 Function Address (USB Register) ........................................153 Figure 15.11. POWER: USB0 Power (USB Register) ..........................................................155 Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register) .................................156 Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register) ................................156 Figure 15.14. IN1INT: USB0 IN Endpoint Interrupt (USB Register)...................................157 Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register).............................158 Figure 15.16. CMINT: USB0 Common Interrupt (USB Register)........................................159 Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) .........................160 Figure 15.18. OUT1IE: USB0 Out Endpoint Interrupt Enable (USB Register)....................160 Figure 15.19. CMIE: USB0 Common Interrupt Enable (USB Register) ..............................161 Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) ........................................164 Figure 15.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register) .................................165 Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register) ...............168 Figure 15.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) ...............169 Figure 15.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) .......171 Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) .......172 Figure 15.26. EOUTCNTL: USB0 OUT Endpoint Count Low (USB Register) ..................172 Figure 15.27. EOUTCNTH: USB0 OUT Endpoint Count High (USB Register) .................172 Table 15.4. USB Transceiver Electrical Characteristics ......................................................173 16. SMBUS .................................................................................................................................175 Figure 16.1. SMBus Block Diagram .....................................................................................175 Figure 16.2. Typical SMBus Configuration ..........................................................................176 Figure 16.3. SMBus Transaction ...........................................................................................177 Table 16.1. SMBus Clock Source Selection.........................................................................180 Figure 16.4. Typical SMBus SCL Generation.......................................................................181 12 Rev. 1.1 C8051F320/1 Table 16.2. Minimum SDA Setup and Hold Times .............................................................181 Figure 16.5. SMB0CF: SMBus Clock/Configuration Register .............................................182 Figure 16.6. SMB0CN: SMBus Control Register .................................................................184 Table 16.3. Sources for Hardware Changes to SMB0CN ....................................................185 Figure 16.7. SMB0DAT: SMBus Data Register ...................................................................186 Figure 16.8. Typical Master Transmitter Sequence...............................................................187 Figure 16.9. Typical Master Receiver Sequence ...................................................................188 Figure 16.10. Typical Slave Receiver Sequence ...................................................................189 Figure 16.11. Typical Slave Transmitter Sequence ...............................................................190 Table 16.4. SMBus Status Decoding....................................................................................191 17. UART0 .................................................................................................................................193 Figure 17.1. UART0 Block Diagram.....................................................................................193 Figure 17.2. UART0 Baud Rate Logic ..................................................................................194 Figure 17.3. UART Interconnect Diagram ............................................................................195 Figure 17.4. 8-Bit UART Timing Diagram ...........................................................................195 Figure 17.5. 9-Bit UART Timing Diagram ...........................................................................196 Figure 17.6. UART Multi-Processor Mode Interconnect Diagram .......................................197 Figure 17.7. SCON0: Serial Port 0 Control Register.............................................................198 Figure 17.8. SBUF0: Serial (UART0) Port Data Buffer Register .........................................199 Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ...........200 Table 17.2. Timer Settings for Standard Baud Rates Using an External Oscillator.............200 Table 17.3. Timer Settings for Standard Baud Rates Using an External Oscillator.............201 Table 17.4. Timer Settings for Standard Baud Rates Using an External Oscillator.............201 Table 17.5. Timer Settings for Standard Baud Rates Using an External Oscillator.............202 Table 17.6. Timer Settings for Standard Baud Rates Using an External Oscillator.............202 18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) ........................................203 Figure 18.1. SPI Block Diagram............................................................................................203 Figure 18.2. Multiple-Master Mode Connection Diagram ....................................................206 Figure 18.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ...206 Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....206 Figure 18.5. Master Mode Data/Clock Timing......................................................................208 Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................................209 Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................................209 Figure 18.8. SPI0CFG: SPI0 Configuration Register............................................................210 Figure 18.9. SPI0CN: SPI0 Control Register ........................................................................211 Figure 18.10. SPI0CKR: SPI0 Clock Rate Register ..............................................................212 Figure 18.11. SPI0DAT: SPI0 Data Register ........................................................................213 Figure 18.12. SPI Master Timing (CKPHA = 0)...................................................................214 Figure 18.13. SPI Master Timing (CKPHA = 1)...................................................................214 Figure 18.14. SPI Slave Timing (CKPHA = 0) .....................................................................215 Figure 18.15. SPI Slave Timing (CKPHA = 1) .....................................................................215 Table 18.1. SPI Slave Timing Parameters............................................................................216 19. TIMERS ..............................................................................................................................217 Figure 19.1. T0 Mode 0 Block Diagram................................................................................218 Figure 19.2. T0 Mode 2 Block Diagram................................................................................219 Rev. 1.1 13 C8051F320/1 Figure 19.3. T0 Mode 3 Block Diagram................................................................................220 Figure 19.4. TCON: Timer Control Register.........................................................................221 Figure 19.5. TMOD: Timer Mode Register...........................................................................222 Figure 19.6. CKCON: Clock Control Register......................................................................223 Figure 19.7. TL0: Timer 0 Low Byte ....................................................................................224 Figure 19.8. TL1: Timer 1 Low Byte ....................................................................................224 Figure 19.9. TH0: Timer 0 High Byte ...................................................................................224 Figure 19.10. TH1: Timer 1 High Byte .................................................................................224 Figure 19.11. Timer 2 16-Bit Mode Block Diagram .............................................................225 Figure 19.12. Timer 2 8-Bit Mode Block Diagram ...............................................................226 Figure 19.13. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’) ................................................227 Figure 19.14. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’) ................................................227 Figure 19.15. TMR2CN: Timer 2 Control Register ..............................................................228 Figure 19.16. TMR2RLL: Timer 2 Reload Register Low Byte ............................................229 Figure 19.17. TMR2RLH: Timer 2 Reload Register High Byte ...........................................229 Figure 19.18. TMR2L: Timer 2 Low Byte ............................................................................229 Figure 19.19. TMR2H Timer 2 High Byte ............................................................................229 Figure 19.20. Timer 3 16-Bit Mode Block Diagram .............................................................230 Figure 19.21. Timer 3 8-Bit Mode Block Diagram ...............................................................231 Figure 19.22. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’) ................................................232 Figure 19.23. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’) ................................................232 Figure 19.24. TMR3CN: Timer 3 Control Register ..............................................................233 Figure 19.25. TMR3RLL: Timer 3 Reload Register Low Byte ............................................234 Figure 19.26. TMR3RLH: Timer 3 Reload Register High Byte ...........................................234 Figure 19.27. TMR3L: Timer 3 Low Byte ............................................................................234 Figure 19.28. TMR3H Timer 3 High Byte ............................................................................234 20. PROGRAMMABLE COUNTER ARRAY (PCA0) ........................................................235 Figure 20.1. PCA Block Diagram..........................................................................................235 Figure 20.2. PCA Counter/Timer Block Diagram .................................................................236 Table 20.1. PCA Timebase Input Options............................................................................236 Figure 20.3. PCA Interrupt Block Diagram...........................................................................237 Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..................237 Figure 20.4. PCA Capture Mode Diagram ............................................................................238 Figure 20.5. PCA Software Timer Mode Diagram................................................................239 Figure 20.6. PCA High Speed Output Mode Diagram ..........................................................240 Figure 20.7. PCA Frequency Output Mode ...........................................................................241 Figure 20.8. PCA 8-Bit PWM Mode Diagram ......................................................................243 Figure 20.9. PCA 16-Bit PWM Mode ...................................................................................244 Figure 20.10. PCA Module 4 with Watchdog Timer Enabled ..............................................246 Table 20.3. Watchdog Timer Timeout Intervals† ................................................................247 Figure 20.11. PCA0CN: PCA Control Register ....................................................................248 Figure 20.12. PCA0MD: PCA Mode Register ......................................................................249 Figure 20.13. PCA0CPMn: PCA Capture/Compare Mode Registers ...................................250 Figure 20.14. PCA0L: PCA Counter/Timer Low Byte .........................................................251 Figure 20.15. PCA0H: PCA Counter/Timer High Byte ........................................................251 14 Rev. 1.1 C8051F320/1 Figure 20.16. PCA0CPLn: PCA Capture Module Low Byte ................................................252 Figure 20.17. PCA0CPHn: PCA Capture Module High Byte ...............................................252 21. C2 INTERFACE .................................................................................................................253 Figure 21.1. C2ADD: C2 Address Register ..........................................................................253 Figure 21.2. DEVICEID: C2 Device ID Register .................................................................253 Figure 21.3. REVID: C2 Revision ID Register .....................................................................254 Figure 21.4. FPCTL: C2 FLASH Programming Control Register ........................................254 Figure 21.5. FPDAT: C2 FLASH Programming Data Register ............................................254 Figure 21.6. Typical C2 Pin Sharing .....................................................................................255 Rev. 1.1 15 C8051F320/1 Notes 16 Rev. 1.1 C8051F320/1 1. SYSTEM OVERVIEW C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • • • • High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1k FIFO RAM Supply Voltage Regulator (5V-to-3V) True 10-bit 200 ksps 17-channel single-ended/differential ADC with analog multiplexer On-chip Voltage Reference and Temperature Sensor On-chip Voltage Comparators (2) Precision programmable 12 MHz internal oscillator and 4x clock multiplier 16k bytes of on-chip FLASH memory 2304 total bytes of on-chip RAM (256 + 1k + 1k USB FIFO) SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer function On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector 25/21 Port I/O (5V tolerant) With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator, C8051F320/1 devices are truly stand-alone System-on-a-Chip solutions. The FLASH memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-40°C to +85°C). (Note that 3.0 V-to-3.6 V is required for USB communication.) The Port I/O and /RST pins are tolerant of input signals up to 5 V. C8051F320/1 are available in a 32-pin LQFP or a 28-pin MLP package. MIPS (Peak) FLASH Memory RAM Calibrated Internal Oscillator USB Supply Voltage Regulator SMBus/I2C Enhanced SPI UART Timers (16-bit) Programmable Counter Array Digital Port I/Os 10-bit 200ksps ADC Temperature Sensor Voltage Reference Analog Comparators Package Table 1.1. Product Selection Guide C8051F320 25 16k 2304 3 3 3 3 3 3 4 3 25 3 3 3 2 LQFP-32 C8051F321 25 16k 2304 3 3 3 3 3 3 4 3 21 3 3 3 2 MLP-28 Rev. 1.1 17 C8051F320/1 Figure 1.1. C8051F320 Block Diagram 5.0V REGIN IN Voltage Regulator Enable OUT VDD Analog/Digital Power Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit System Clock x4 2 Clock Recovery D+ DVBUS 18 Port 1 Latch D r v 8 0 5 1 2 16kbyte FLASH PCA/ WDT 256 byte SRAM SMBus P 1 D r v P 2 SPI C o r SFR Bus e D r v Port 2 Latch P 3 Port 3 Latch D r v VREF USB Clock 1,2,3,4 USB Transceiver C R O S S B A R Timer 0,1,2,3 / RTC 1K byte XRAM XTAL1 XTAL2 12MHz Internal Oscillator P 0 UART GND C2D Port 0 Latch VREF USB Controller CP0 + - CP1 + - VDD Temp 10-bit 200ksps ADC 1K byte USB SRAM Rev. 1.1 A M U X AIN0-AIN16 VDD VREF P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D C8051F320/1 Figure 1.2. C8051F321 Block Diagram 5.0V REGIN Voltage IN Regulator Enable OUT VDD Analog/Digital Power Debug HW Reset /RST/C2CK POR BrownOut External Oscillator Circuit System Clock x4 2 Clock Recovery D+ DVBUS Port 1 Latch D r v 8 0 5 1 2 16kbyte FLASH PCA/ WDT 256 byte SRAM SMBus P 1 D r v P 2 SPI C o r SFR Bus e P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 D r v Port 2 Latch P 3 Port 3 Latch P3.0/C2D D r v VREF USB Clock 1,2,3,4 USB Transceiver C R O S S B A R Timer 0,1,2,3 / RTC 1K byte XRAM XTAL1 XTAL2 12MHz Internal Oscillator P 0 UART GND C2D Port 0 Latch VREF USB Controller CP0 + - CP1 + - VDD Temp 10-bit 200ksps ADC 1K byte USB SRAM Rev. 1.1 A M U X AIN0-AIN11 VDD VREF 19 C8051F320/1 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F320/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 2304 bytes of on-chip RAM, 128 byte Special Function Register (SFR) address space, and 25/21 I/O pins. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks. Figure 1.3. Comparison of Peak MCU Execution Speeds 25 MIPS 20 15 10 5 Silicon Labs Microchip Philips ADuC812 CIP-51 PIC17C75x 80C51 8051 (25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk) 20 Rev. 1.1 C8051F320/1 1.1.3. Additional Features The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below VRST as given in Table 10.1 on page 105), the USB controller (USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an errant FLASH read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or FLASH error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 12 MHz ±1.5%, and the internal oscillator period may be user programmed in ~0.25% increments. A clock recovery mechanism allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed mode; the internal oscillator can also be used as the USB clock source in Low Speed mode. External oscillators may also be used with the 4x Clock Multiplier. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. The system clock may be configured to use the internal oscillator, external oscillator, or the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly between oscillator sources. An external oscillator can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external clock source, while periodically switching to the internal oscillator as needed. Figure 1.4. On-Chip Clock and Reset VDD Supply Monitor + - + - EN XTAL2 External Oscillator Drive /RST Reset Funnel PCA WDT Software Reset (SWRSF) Errant FLASH Operation MCD Enable WDT Enable EN System Clock (wired-OR) C0RSEF Missing Clock Detector (oneshot) Internal Oscillator '0' CIP-51 Microcontroller Core System Reset Enable Px.x XTAL1 Power On Reset Comparator 0 Px.x Clock Multiplier Enable USB Controller VBUS Transition Clock Select Extended Interrupt Handler Rev. 1.1 21 C8051F320/1 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 16k bytes of FLASH. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. See Figure 1.5 for the MCU system memory map. Figure 1.5. On-Board Memory Map DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (FLASH) 0x3E00 0x3DFF RESERVED 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) 16K FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2K-byte boundaries 0x0800 0x07FF 0x0400 0x03FF 0x0000 22 Special Function Register's (Direct Addressing Only) USB FIFOs 1024 Bytes XRAM - 1024 Bytes (accessable using MOVX instruction) Rev. 1.1 C8051F320/1 1.3. Universal Serial Bus Controller The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT). A 1k block of XRAM is used as dedicated USB FIFO space. This FIFO space is distributed among Endpoints0-3; Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum FIFO size is 512 bytes (Endpoint3). USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate the USB clock. The CPU clock source is independent of the USB clock. The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the software-selected speed setting (Full or Low Speed). Figure 1.6. USB Controller Block Diagram Transceiver Serial Interface Engine (SIE) Endpoint0 VDD IN/OUT D+ Data Transfer Control D- Endpoint1 Endpoint2 Endpoint3 OUT IN IN USB Control, Status, and Interrupt Registers CIP-51 Core OUT IN OUT USB FIFOs (1k RAM) 1.4. Voltage Regulator C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software. Rev. 1.1 23 C8051F320/1 1.5. On-Chip Debug Circuitry The C8051F320/1 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the USB, ADC, and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F310DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F320/1 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and an RS-232 to C2 serial adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the RS-232 and C2 cables, and wall-mount power supply. The Development Kit requires a Windows 95/98/NT/ME/2000 computer with one available RS-232 serial port. As shown in Figure 1.7, the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the Serial Adapter to the user's application board, picking up the two C2 pins and VDD and GND. The Serial Adapter takes its power from the application board. For applications where there is not sufficient power available from the target board, the provided power supply can be connected directly to the Serial Adapter. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Figure 1.7. Development/In-System Debug Diagram Silicon Labs Integrated Development Environment WINDOWS 95/98/NT/ME/2000 RS-232 Serial Adapter C2 (x2), VDD, GND VDD TARGET PCB GND C8051F320 24 Rev. 1.1 C8051F320/1 1.6. Programmable Digital I/O and Crossbar C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.8). On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. Figure 1.8. Digital Crossbar Diagram XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder Highest Priority 2 UART (Internal Digital Signals) P0 I/O Cells P0.0 P1 I/O Cells P1.0 P2 I/O Cells P2.0 P3 I/O Cells P3.0 2 8 Note: P2.4-P2.7 only available on the C8051F320 4 SPI 8 SMBus CP0 Outputs 2 CP1 Outputs 2 Digital Crossbar 8 8 SYSCLK P1.7 P2.7 6 PCA 1 Lowest Priority P0.7 2 T0, T1 P0 (P0.0-P0.7) P1 (P1.0-P1.7) (Port Latches) 8 8 P2 (P2.0-P2.7) P3 (P3.0) 8 1.7. Serial Ports The C8051F320/1 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. Rev. 1.1 25 C8051F320/1 1.8. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally, Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. Figure 1.9. PCA Block Diagram SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK PCA CLOCK MUX 16-Bit Counter/Timer External Clock/8 Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 26 Rev. 1.1 Capture/Compare Module 4 / WDT CEX4 Port I/O CEX3 CEX2 CEX1 CEX0 ECI Crossbar Capture/Compare Module 3 C8051F320/1 1.9. 10-Bit Analog to Digital Converter The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as ADC inputs; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC to save power. Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data SFRs upon completion of a conversion. Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. Figure 1.10. 10-Bit ADC Block Diagram Analog Multiplexer P1.0 Configuration, Control, and Data Registers P1.7 P2.0 P2.4-2.7 available on C8051F320 Temp Sensor 19-to-1 AMUX Start Conversion P2.7 P3.0 VDD (+) (-) P1.0 P1.7 P2.0 P2.4-2.7 available on C8051F320 19-to-1 AMUX 10-Bit SAR ADC End of Conversion Interrupt 16 000 AD0BUSY (W) 001 Timer 0 Overflow 010 Timer 2 Overflow 011 100 Timer 1 Overflow CNVSTR Input 101 Timer 3 Overflow ADC Data Registers Window Compare Logic Window Compare Interrupt P2.7 P3.0 VREF GND Rev. 1.1 27 C8051F320/1 1.10. Comparators C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hysteresis are also configurable. Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source. Figure 1.11 shows the Comparator0 block diagram. Figure 1.11. Comparator0 Block Diagram CP0EN CPT0CN CPT0MX CP0OUT CMX0N1 CMX0N0 CP0RIF VDD CP0FIF CP0HYP1 CP0HYP0 CP0 Interrupt CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 CP0 Rising-edge P1.0 CP0 Falling-edge P1.4 P2.0 CP0 + Interrupt Logic P2.4 + D - CLR GND CP0 - SET CLR CP0 Q Q CP0A Reset Decision Tree CPT0MD P2.5 CP0RIE CP0FIE CP0MD1 CP0MD0 28 Q D (SYNCHRONIZER) P2.1 Note: P2.4 and P2.5 available only on C8051F320 Q Crossbar P1.1 P1.5 SET CP0RIE CP0FIE Rev. 1.1 C8051F320/1 2. ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings* PARAMETER CONDITIONS MIN TYP MAX UNITS Ambient temperature under bias -55 125 °C Storage Temperature -65 150 °C Voltage on any Port I/O Pin or /RST with respect to GND -0.3 5.8 V Voltage on VDD with respect to GND -0.3 4.2 V Maximum Total current through VDD and GND 500 mA Maximum output current sunk by /RST or any Port pin 100 mA *Note: stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.1 29 C8051F320/1 3. GLOBAL DC ELECTRICAL CHARACTERISTICS Table 3.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER CONDITIONS Digital Supply Voltage (Note 1) Digital Supply Current with CPU active MIN TYP MAX UNITS 2.7 3.3 3.6 V VDD=3.3V, Clock=24MHz VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz Digital Supply Current with CPU VDD=3.3V, Clock=24MHz active and USB active (Full or Low VDD=3.3V, Clock=6MHz Speed) Digital Supply Current with CPU inactive (not accessing FLASH) VDD=3.3V, Clock=24MHz VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz Digital Supply Current (suspend mode or shutdown mode) Oscillator not running Digital Supply RAM Data Retention Voltage 10 0.6 30 mA mA µA TBD TBD mA mA 5 0.3 14 mA mA µA < 0.1 µA 1.5 V SYSCLK (System Clock) (Note 2) 0 TSYSH (SYSCLK High Time) 18 ns TSYSL (SYSCLK Low Time) 18 ns Specified Operating Temperature Range -40 Note 1: USB Requires 3.0 V Minimum Supply Voltage. Note 2: SYSCLK must be at least 32 kHz to enable debugging. 30 Rev. 1.1 25 +85 MHz °C C8051F320/1 4. PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions for the C8051F320/1 Name Pin Numbers ‘F320 ‘F321 Type Description Power In 2.7-3.6 V Power Supply Voltage Input. VDD GND 6 3 6 3 /RST/ 9 P3.0/ D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. See Section 10. D I/O Clock signal for the C2 Debug Interface. D I/O Port 3.0. See Section 14 for a complete description. D I/O Bi-directional data signal for the C2 Debug Interface. 10 C2D REGIN 3.3 V Voltage Regulator Output. See Section 8. Ground. 9 C2CK 10 Power Out Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator. 7 7 VBUS 8 8 D In VBUS Sense Input. This pin should be connected to the VBUS signal of a USB network. A 5 V signal on this pin indicates a USB network connection. D+ 4 4 D I/O USB D+. D- 5 5 D I/O USB D-. P0.0 2 2 D I/O Port 0.0. See Section 14 for a complete description. P0.1 1 1 D I/O Port 0.1. See Section 14 for a complete description. D I/O Port 0.2. See Section 14 for a complete description. XTAL1 A In External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Section 13. P0.3/ D I/O Port 0.3. See Section 14 for a complete description. P0.2/ 32 28 31 27 P0.4 30 26 D I/O Port 0.4. See Section 14 for a complete description. P0.5 29 25 D I/O Port 0.5. See Section 14 for a complete description. XTAL2 External Clock Output. This pin is the excitation driver for an A I/O or external crystal or resonator, or an external clock input for CMOS, capacitor, or RC oscillator configurations. See Section 13. D In Rev. 1.1 31 C8051F320/1 Table 4.1. Pin Definitions for the C8051F320/1 Name Pin Numbers ‘F320 ‘F321 28 24 Type P0.6/ Port 0.6. See Section 14 for a complete description. CNVSTR ADC0 External Convert Start Input. See Section 5. P0.7/ 27 D I/O Port 0.7. See Section 14 for a complete description. A I/O External VREF input or output. See Section 6. 23 VREF 32 Description P1.0 26 22 D I/O or Port 1.0. See Section 14 for a complete description. A In P1.1 25 21 D I/O or Port 1.1. See Section 14 for a complete description. A In P1.2 24 20 D I/O or Port 1.2. See Section 14 for a complete description. A In P1.3 23 19 D I/O or Port 1.3. See Section 14 for a complete description. A In P1.4 22 18 D I/O or Port 1.4. See Section 14 for a complete description. A In P1.5 21 17 D I/O or Port 1.5. See Section 14 for a complete description. A In P1.6 20 16 D I/O or Port 1.6. See Section 14 for a complete description. A In P1.7 19 15 D I/O or Port 1.7. See Section 14 for a complete description. A In P2.0 18 14 D I/O or Port 2.0. See Section 14 for a complete description. A In P2.1 17 13 D I/O or Port 2.1. See Section 14 for a complete description. A In P2.2 16 12 D I/O or Port 2.2. See Section 14 for a complete description. A In P2.3 15 11 D I/O or Port 2.3. See Section 14 for a complete description. A In P2.4 14 D I/O or Port 2.4. See Section 14 for a complete description. A In P2.5 13 D I/O or Port 2.5. See Section 14 for a complete description. A In P2.6 12 D I/O or Port 2.6. See Section 14 for a complete description. A In Rev. 1.1 C8051F320/1 Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 P2.7 ‘F321 Type Description D I/O or Port 2.7. See Section 14 for a complete description. A In 11 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 32 31 30 29 28 27 26 25 Figure 4.1. LQFP-32 Pinout Diagram (Top View) P0.1 1 24 P1.2 P0.0 2 23 P1.3 GND 3 22 P1.4 D+ 4 21 P1.5 D- 5 20 P1.6 VDD 6 19 P1.7 REGIN 7 18 P2.0 VBUS 8 17 P2.1 14 15 16 P2.3 P2.2 12 P2.6 P2.4 11 P2.7 13 10 P3.0 / C2D P2.5 9 /RST / C2CK C8051F320 Top View Rev. 1.1 33 C8051F320/1 Figure 4.2. LQFP-32 Package Diagram D Table 4.2. LQFP-32 Package Dimensions D1 E1 E 32 PIN 1 IDENTIFIER 1 A2 A b 34 A1 e Rev. 1.1 A A1 A2 b D D1 e E E1 MIN 0.05 1.35 0.30 - MM TYP 1.40 0.37 9.00 7.00 0.80 9.00 7.00 MAX 1.60 0.15 1.45 0.45 - C8051F320/1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 27 26 25 24 23 22 GND 28 Figure 4.3. MLP-28 Pinout Diagram (Top View) P0.1 1 21 P1.1 P0.0 2 20 P1.2 GND 3 19 P1.3 D+ 4 18 P1.4 D- 5 17 P1.5 VDD 6 16 P1.6 REGIN 7 15 P1.7 C8051F321 Top View 8 9 10 11 12 13 14 VBUS /RST / C2CK P3.0 / C2D P2.3 P2.2 P2.1 P2.0 GND Rev. 1.1 35 C8051F320/1 Figure 4.4. MLP-28 Package Drawing L 7 15 16 D2 5 17 D2 2 e E2 4 18 19 E2 2 3 R 6xe E b 6 20 2 21 22 23 24 25 26 27 DETAIL 1 28 1 Table 4.2. MLP-28 Package Dimensions 14 13 12 11 10 9 8 Bottom View 6xe D A A2 Side View A1 A3 e DETAIL 1 CC 36 DD BB AA Rev. 1.1 A A1 A2 A3 b D D2 E E2 e L N ND NE R AA BB CC DD MIN 0.80 0 0 0.18 2.90 2.90 0.45 0.09 - MM TYP 0.90 0.02 0.65 0.25 0.23 5.00 3.15 5.00 3.15 0.5 0.55 28 7 7 0.435 0.435 0.18 0.18 MAX 1.00 0.05 1.00 0.30 3.35 3.35 0.65 - C8051F320/1 Figure 4.5. Typical MLP-28 Landing Diagram 0.50 mm 0.35 mm 0.50 mm 0.10 mm 0.85 mm 0.30 mm 0.20 mm 0.20 mm 0.50 mm Top View b 0.20 mm D D2 Optional GND Connection L e E2 0.20 mm 0.30 mm 0.50 mm 0.85 mm 0.35 mm 0.10 mm E Rev. 1.1 37 C8051F320/1 Figure 4.6. Typical MLP-28 Solder Mask 0.50 mm 0.35 mm 0.50 mm 0.60 mm 0.20 mm 0.10 mm 0.85 mm 0.30 mm 0.20 mm 0.20 mm 0.50 mm Top View 0.60 mm 0.30 mm 0.70 mm b 0.20 mm e L E2 0.20 mm 0.30 mm 0.50 mm 0.85 mm 0.35 mm 0.10 mm E 38 Rev. 1.1 D D2 0.40 mm C8051F320/1 5. 10-BIT ADC (ADC0) The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated trackand-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure P1.0-P3.0, the Temperature Sensor output, or VDD with respect to P1.0-P3.0, VREF, or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. Figure 5.1. ADC0 Functional Block Diagram P2.4-2.7 available on C8051F320 VDD AD0SC0 AD0LJST AD0SC1 ADC0CF Rev. 1.1 AD0CM1 AD0CM0 AD0BUSY (W) Timer 0 Overflow 010 011 100 101 Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow ADC0H 000 001 REF ADC SYSCLK (-) AD0SC2 AD0SC3 AD0SC4 AMX0N0 GND AMX0N1 VREF AMX0N2 P2.7 P3.0 AMX0N AMX0N3 P2.4-2.7 available on C8051F320 10-Bit SAR 19-to-1 AMUX AMX0N4 P1.7 P2.0 (+) ADC0L VDD P1.0 AD0CM2 Start Conversion P2.7 P3.0 Temp Sensor AD0WINT AD0INT AD0BUSY AD0EN 19-to-1 AMUX AD0TM AMX0P0 ADC0CN AMX0P1 AMX0P2 AMX0P4 P1.7 P2.0 AMX0P3 AMX0P P1.0 ADC0LTH ADC0LTL AD0WINT 32 Window Compare Logic ADC0GTH ADC0GTL 39 C8051F320/1 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be selected as the negative input: P1.0-P3.0, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in Figure 5.5 and Figure 5.6. The conversion code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage (Single-Ended) VREF * 1023/1024 VREF * 512/1024 VREF * 256/1024 0 Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x03FF 0x0200 0x0100 0x0000 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0xFFC0 0x8000 0x4000 0x0000 When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’. Input Voltage (Differential) VREF * 511/512 VREF * 256/512 0 -VREF * 256/512 - VREF Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x01FF 0x0100 0x0000 0xFF00 0xFE00 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0x7FC0 0x4000 0x0000 0xC000 0x8000 Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See Section “14. Port Input/Output” on page 127 for more Port I/O configuration details. 40 Rev. 1.1 C8051F320/1 5.2. Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Figure 5.2. Typical Temperature Sensor Transfer Function (mV) 1000 900 800 VTEMP = 2.86(TEMPC) + 776 mV 700 600 500 -50 0 50 100 (Celsius) Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. Rev. 1.1 41 C8051F320/1 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the following: 1. 2. 3. 4. 5. 6. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN A Timer 0 overflow (i.e., timed continuous conversions) A Timer 2 overflow A Timer 1 overflow A rising edge on the CNVSTR input signal (pin P0.6) A Timer 3 overflow Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section “19. Timers” on page 217 for timer configuration. Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “14. Port Input/Output” on page 127 for details on Port I/O configuration. 42 Rev. 1.1 C8051F320/1 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.3). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power trackand-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling Time Requirements” on page 44. Figure 5.3. 10-Bit ADC Track and Conversion Example Timing A. ADC0 Timing for External Trigger Source CNVSTR (AD0CM[2:0]=100) 1 2 3 4 5 6 7 8 9 10 11 SAR Clocks AD0TM=1 AD0TM=0 Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) Low Power or Convert Track Track or Convert Convert Low Power Mode Convert Track B. ADC0 Timing for Internal Trigger Source 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAR Clocks AD0TM=1 Low Power or Convert Track 1 2 3 Convert 4 5 6 7 8 9 Low Power Mode 10 11 SAR Clocks AD0TM=0 Track or Convert Convert Rev. 1.1 Track 43 C8051F320/1 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements. Figure 5.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum settling time requirements. Equation 5.1. ADC0 Settling Time Requirements n 2 t = ln  ------- × R TOTAL C SAMPLE  SA Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (10). Figure 5.4. ADC0 Equivalent Input Circuits Differential Mode Single-Ended Mode MUX Select MUX Select Px.x Px.x RMUX = 5k RMUX = 5k CSAMPLE = 5pF CSAMPLE = 5pF RCInput= RMUX * CSAMPLE RCInput= RMUX * CSAMPLE CSAMPLE = 5pF Px.x RMUX = 5k MUX Select 44 Rev. 1.1 C8051F320/1 Figure 5.5. AMX0P: AMUX0 Positive Channel Select Register R R R R/W R/W R/W R/W R/W Reset Value - - - AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBB Bits7-5: Bits4-0: UNUSED. Read = 000b; Write = don’t care. AMX0P4-0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100† 01101† 01110† 01111† 10000 10001 - 11101 11110 11111 ADC0 Positive Input P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4† P2.5† P2.6† P2.7† P3.0 RESERVED Temp Sensor VDD †Only applies to C8051F320; selection RESERVED on C8051F321 devices. Rev. 1.1 45 C8051F320/1 Figure 5.6. AMX0N: AMUX0 Negative Channel Select Register R R R - - - Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBA Bits7-5: Bits4-0: UNUSED. Read = 000b; Write = don’t care. AMX0N4-0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. AMX0N4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100† 01101† 01110† 01111† 10000 10001 - 11101 11110 11111 ADC0 Negative Input P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4† P2.5† P2.6† P2.7† P3.0 RESERVED VREF GND (ADC in Single-Ended Mode) †Only applies to C8051F320; selection RESERVED on C8051F321 devices. 46 Rev. 1.1 C8051F320/1 Figure 5.7. ADC0CF: ADC0 Configuration Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST - - 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBC Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.1. AD0SC = SYSCLK ---------------------- – 1 CLK SAR Bit2: Bits1-0: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. UNUSED. Read = 00b; Write = don’t care. Figure 5.8. ADC0H: ADC0 Data Word MSB Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xBE Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the 10-bit ADC0 Data Word. For AD0LJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC0 Data Word. Rev. 1.1 47 C8051F320/1 Figure 5.9. ADC0L: ADC0 Data Word LSB Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBD Bits7-0: 48 ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always read ‘0’. Rev. 1.1 C8051F320/1 Figure 5.10. ADC0CN: ADC0 Control Register R/W R/W AD0EN AD0TM Bit7 Bit6 R/W R/W R/W R/W AD0INT AD0BUSY AD0WINT AD0CM2 Bit5 Bit4 Bit3 Bit2 R/W R/W Reset Value AD0CM1 AD0CM0 00000000 Bit0 SFR Address: Bit1 (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bits2-0: 0xE8 AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. AD0TM: ADC0 Track Mode Bit. 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. 1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below). AD0INT: ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since the last time AD0INT was cleared. 1: ADC0 has completed a data conversion. AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY. 1: ADC0 conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM2-0 = 000b AD0WINT: ADC0 Window Compare Interrupt Flag. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. AD0CM2-0: ADC0 Start of Conversion Mode Select. When AD0TM = 0: 000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY. 001: ADC0 conversion initiated on overflow of Timer 0. 010: ADC0 conversion initiated on overflow of Timer 2. 011: ADC0 conversion initiated on overflow of Timer 1. 100: ADC0 conversion initiated on rising edge of external CNVSTR. 101: ADC0 conversion initiated on overflow of Timer 3. 11x: Reserved. When AD0TM = 1: 000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion. 001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion. 010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion. 011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. Rev. 1.1 49 C8051F320/1 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. The Window Detector registers must be written with the same format (left/right justified, signed/unsigned) as that of the current ADC configuration (left/right justified, single-ended/differential). Figure 5.11. ADC0GTH: ADC0 Greater-Than Data High Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xC4 Bits7-0: High byte of ADC0 Greater-Than Data Word. Figure 5.12. ADC0GTL: ADC0 Greater-Than Data Low Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xC3 Bits7-0: Low byte of ADC0 Greater-Than Data Word. 50 Rev. 1.1 C8051F320/1 Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC6 Bits7-0: High byte of ADC0 Less-Than Data Word. Figure 5.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xC5 Bits7-0: Low byte of ADC0 Less-Than Data Word. Rev. 1.1 51 C8051F320/1 5.4.1. Window Detector In Single-Ended Mode Figure 5.15 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF * (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.16 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.. Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) Input Voltage (Px.x - GND) 0x03FF VREF x (1023/1024) 0x03FF AD0WINT not affected AD0WINT=1 0x0081 VREF x (128/1024) 0x0080 0x0081 ADC0LTH:ADC0LTL VREF x (128/1024) 0x007F 0x0080 0x007F AD0WINT=1 VREF x (64/1024) 0x0041 0x0040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x003F 0x0041 0x0040 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL 0x003F AD0WINT=1 AD0WINT not affected 0 0x0000 0 0x0000 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) Input Voltage (Px.x - GND) 0xFFC0 VREF x (1023/1024) 0xFFC0 AD0WINT not affected AD0WINT=1 0x2040 VREF x (128/1024) 0x2000 0x2040 ADC0LTH:ADC0LTL VREF x (128/1024) 0x1FC0 0x2000 0x1FC0 AD0WINT=1 0x1040 VREF x (64/1024) 0x1000 0x1040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x0FC0 0x1000 52 AD0WINT not affected ADC0LTH:ADC0LTL 0x0FC0 AD0WINT=1 AD0WINT not affected 0 ADC0GTH:ADC0GTL 0x0000 0 Rev. 1.1 0x0000 C8051F320/1 5.4.2. Window Detector In Differential Mode Figure 5.17 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented as 10bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)). Figure 5.18 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.. Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) Input Voltage (Px.x - Px.x) 0x01FF VREF x (511/512) 0x01FF AD0WINT not affected AD0WINT=1 0x0041 VREF x (64/512) 0x0040 0x0041 ADC0LTH:ADC0LTL VREF x (64/512) 0x003F 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) 0xFFFF 0x0000 ADC0GTH:ADC0GTL VREF x (-1/512) 0xFFFE 0xFFFF ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL 0xFFFE AD0WINT=1 AD0WINT not affected -VREF 0x0200 -VREF 0x0200 Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ADC0H:ADC0L ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) Input Voltage (Px.x - Px.y) 0x7FC0 VREF x (511/512) 0x7FC0 AD0WINT not affected AD0WINT=1 0x1040 VREF x (64/512) 0x1000 0x1040 ADC0LTH:ADC0LTL VREF x (64/512) 0x0FC0 0x1000 0x0FC0 AD0WINT=1 0x0000 VREF x (-1/512) 0xFFC0 0x0000 ADC0GTH:ADC0GTL VREF x (-1/512) 0xFF80 0xFFC0 0x8000 AD0WINT not affected ADC0LTH:ADC0LTL 0xFF80 AD0WINT=1 AD0WINT not affected -VREF ADC0GTH:ADC0GTL -VREF Rev. 1.1 0x8000 53 C8051F320/1 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic bits ±0.5 ±1 LSB ±0.5 ±1 LSB Offset Error 0 LSB Full Scale Error -1 LSB Offset Temperature Coefficient 10 ppm/°C DYNAMIC PERFORMANCE (10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion 53 Up to the 5th harmonic Spurious-Free Dynamic Range 55.5 dB -67 dB 78 dB CONVERSION RATE SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track/Hold Acquisition Time 300 ns Throughput Rate 200 ksps 0 -VREF VREF VREF V V 0 VDD V ANALOG INPUTS ADC Input Voltage Range Single Ended (AIN+ - GND) Differential (AIN+ - AIN-) Absolute Pin Voltage with respect to Single Ended or Differential GND Input Capacitance 5 pF TEMPERATURE SENSOR Linearity Note 1 ±0.1 °C Gain Note 2 2.86 mV / °C Offset Notes 1, 2 (Temp = 0 °C) 0.776 ±8.5 mV Operating Mode, 200 ksps 400 POWER SPECIFICATIONS Power Supply Current (VDD supplied to ADC0) Power Supply Rejection ±0.3 Note 1: Includes ADC offset, gain, and linearity variations. Note 2: Represents one standard deviation from the mean. 54 Rev. 1.1 900 µA mV/V C8051F320/1 6. VOLTAGE REFERENCE The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to ‘0’; For VDD as the reference source, REFSL should be set to ‘1’. The BIASE bit enables the internal ADC bias generator, which is used by the ADC and Internal Oscillator. This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see Figure 6.2 for REF0CN register details. The Reference bias generator (see Figure 6.1) is used by the Internal Voltage Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically enabled when any of the aforementioned peripherals are enabled. The electrical specifications for the voltage reference and bias circuits are given in Table 6.1. Important Note About the VREF Input: Port pin P0.7 is used as the external VREF input. When using an external voltage reference, P0.7 should be configured as analog input and skipped by the Digital Crossbar. To configure P0.7 as analog input, set to ‘0’ Bit7 in register P0MDIN. To configure the Crossbar to skip P0.7, set to ‘1’ Bit7 in register P0SKIP. Refer to Section “14. Port Input/Output” on page 127 for complete Port I/O configuration details. The temperature sensor connects to the ADC0 positive input multiplexer (see Section “5.1. Analog Multiplexer” on page 40 for details). The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. Figure 6.1. Voltage Reference Functional Block Diagram REFSL TEMPE BIASE REFBE REF0CN AD0EN EN ADC Bias To ADC, Internal Oscillator IOSCEN VDD R1 External Voltage Reference Circuit EN VREF Temp Sensor To Analog Mux 0 VREF (to ADC) GND VDD 1 CLKMUL Enable EN TEMPE Reference Bias To Clock Multiplier, Temp Sensor REFBE EN Internal Reference Rev. 1.1 55 C8051F320/1 Figure 6.2. REF0CN: Reference Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - REFSL TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7-3: Bit3: Bit2: Bit1: Bit0: UNUSED. Read = 00000b; Write = don’t care. REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. BIASE: Internal Analog Bias Generator Enable Bit. 0: Internal Bias Generator off. 1: Internal Bias Generator on. REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer disabled. 1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin. Table 6.1. Voltage Reference Electrical Characteristics VDD = 3.0 V; -40°C TO +85°C UNLESS OTHERWISE SPECIFIED PARAMETER CONDITIONS MIN TYP MAX UNITS 2.38 2.44 2.50 V 10 mA INTERNAL REFERENCE (REFBE = 1) Output Voltage 25°C ambient VREF Short-Circuit Current VREF Temperature Coefficient 15 ppm/°C 1.5 ppm/µA Load Regulation Load = 0 to 200 µA to GND VREF Turn-on Time 1 4.7µF tantalum, 0.1µF ceramic bypass 2 ms VREF Turn-on Time 2 0.1µF ceramic bypass 20 µs VREF Turn-on Time 3 no bypass cap 10 µs 140 ppm/V Power Supply Rejection EXTERNAL REFERENCE (REFBE = 0) Input Voltage Range Input Current 0 VDD V Sample Rate = 200 ksps; VREF = 3.0 V 12 µA BIASE = ‘1’ 100 µA 40 µA BIAS GENERATORS ADC Bias Generator Reference Bias Generator 56 Rev. 1.1 C8051F320/1 7. COMPARATORS C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be used as a reset source. Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section “14.2. Port I/O Initialization” on page 131). Comparator0 may also be used as a reset source (see Section “10.5. Comparator0 Reset” on page 102). The Comparator0 inputs are selected in the CPT0MX register (Figure 7.5). The CMX0P1-CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. The Comparator1 inputs are selected in the CPT1MX register (Figure 7.8). The CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1 negative input. Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “14.3. General Purpose Port I/O” on page 134). CPT0CN CMX0N1 CMX0N0 CMX0P1 CMX0P0 CP0EN CP0OUT CP0RIF CP0FIF VDD CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 CP0 Interrupt CP0 Rising-edge P1.0 CP0 Falling-edge P1.4 P2.0 CP0 + Interrupt Logic P2.4 + D P1.5 Q Q D SET CLR CP0RIE CP0FIE CP0 Q Q Crossbar (SYNCHRONIZER) GND CP0 - P2.1 CP0A Reset Decision Tree P2.5 Note: P2.4 and P2.5 available only on C8051F320 SET CLR P1.1 CPT0MD CPT0MX Figure 7.1. Comparator0 Functional Block Diagram CP0RIE CP0FIE CP0MD1 CP0MD0 Rev. 1.1 57 C8051F320/1 Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and supply current falls to less than 100 nA. See Section “14.1. Priority Crossbar Decoder” on page 129 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 7.1. Comparator response time may be configured in software via the CPTnMD registers (see Figure 7.6 and Figure 7.9). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for complete timing and supply current specifications. CPT1CN CPT1MX Figure 7.2. Comparator1 Functional Block Diagram CMX1N1 CMX1N0 CMX1P1 CMX1P0 CP1EN CP1OUT CP1RIF CP1FIF VDD CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 CP1 Interrupt CP1 Rising-edge P1.2 CP1 Falling-edge P1.6 P2.2 CP1 + Interrupt Logic P2.6 CP1 + D - Q D SET CLR Q Q Crossbar CP1 - GND CPT1MD P2.7 CP1RIE CP1FIE CP1MD1 CP1MD0 58 Q (SYNCHRONIZER) P2.3 Note: P2.6 and P2.7 available only on C8051F320 SET CLR P1.3 P1.7 CP1RIE CP1FIE Rev. 1.1 CP1A C8051F320/1 Figure 7.3. Comparator Hysteresis Plot VIN+ VIN- CP0+ CP0- + CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VIN+ VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Negative Hysteresis Maximum Positive Hysteresis Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown in Figure 7.4 and Figure 7.7). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in Figure 7.3, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits. Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page 58.) The CPnFIF flag is set to ‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge. Once set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to ‘1’, and is disabled by clearing this bit to ‘0’. Rev. 1.1 59 C8051F320/1 Figure 7.4. CPT0CN: Comparator0 Control Register R/W R R/W R/W CP0EN CP0OUT CP0RIF CP0FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9B Bit7: Bit6: Bit5: Bit4: Bits3-2: Bits1-0: 60 CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage on CP0+ > CP0-. CP0RIF: Comparator0 Rising-Edge Flag. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. CP0FIF: Comparator0 Falling-Edge Flag. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge Interrupt has occurred. CP0HYP1-0: Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Rev. 1.1 C8051F320/1 Figure 7.5. CPT0MX: Comparator0 MUX Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - CMX0N1 CMX0N0 - - CMX0P1 CMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9F Bits7-6: Bits5-4: UNUSED. Read = 00b, Write = don’t care. CMX0N1-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N1 CMX0N0 0 0 0 1 1 0 1 1 Bits3-2: Bits1-0: Negative Input P1.1 P1.5 P2.1 P2.5† UNUSED. Read = 00b, Write = don’t care. CMX0P1-CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 0 0 0 1 1 0 1 1 Positive Input P1.0 P1.4 P2.0 P2.4† † Note: P2.4 and P2.5 available only on C8051F320 devices; selection reserved on C8051F321 devices. Rev. 1.1 61 C8051F320/1 Figure 7.6. CPT0MD: Comparator0 Mode Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - CP0RIE CP0FIE - - CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9D Bits7-6: Bit5: Bit4: Bits3-2: Bits1-0: UNUSED. Read = 00b. Write = don’t care. CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. CP0FIE: Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 falling-edge interrupt disabled. 1: Comparator0 falling-edge interrupt enabled. UNUSED. Read = 00b. Write = don’t care. CP0MD1-CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode 0 1 2 3 62 CP0MD1 0 0 1 1 CP0MD0 CP0 Response Time (TYP) 0 100 ns 1 175 ns 0 320 ns 1 1050 ns Rev. 1.1 C8051F320/1 Figure 7.7. CPT1CN: Comparator1 Control Register R/W R R/W R/W CP1EN CP1OUT CP1RIF CP1FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A Bit7: Bit6: Bit5: Bit4: Bits3-2: Bits1-0: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: Voltage on CP1+ > CP1-. CP1RIF: Comparator1 Rising-Edge Flag. 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. CP1FIF: Comparator1 Falling-Edge Flag. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. CP1HYP1-0: Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. CP1HYN1-0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Rev. 1.1 63 C8051F320/1 Figure 7.8. CPT1MX: Comparator1 MUX Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - CMX1N1 CMX1N0 - - CMX1P1 CMX1P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9E Bits7-6: Bits5-4: UNUSED. Read = 00b, Write = don’t care. CMX1N1-CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. CMX1N1 CMX1N0 0 0 0 1 1 0 1 1 Bits3-2: Bits1-0: Negative Input P1.3 P1.7 P2.3 P2.7† UNUSED. Read = 00b, Write = don’t care. CMX1P1-CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P1 CMX1P0 0 0 0 1 1 0 1 1 Positive Input P1.2 P1.6 P2.2 P2.6† † Note: P2.6 and P2.7 available only on C8051F320 devices; selection reserved on C8051F321 devices. 64 Rev. 1.1 C8051F320/1 Figure 7.9. CPT1MD: Comparator1 Mode Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - CP1RIE CP1FIE - - CP1MD1 CP1MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9C Bits7-6: Bit5: Bit4: Bits1-0: UNUSED. Read = 00b, Write = don’t care. CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge interrupt enabled. CP1FIE: Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 falling-edge interrupt disabled. 1: Comparator1 falling-edge interrupt enabled. CP1MD1-CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Mode 0 1 2 3 CP1MD1 0 0 1 1 CP1MD0 CP1 Response Time (TYP) 0 100 ns 1 175 ns 0 320 ns 1 1050 ns Rev. 1.1 65 C8051F320/1 Table 7.1. Comparator Electrical Characteristics VDD = 3.0 V, -40°C to +85°C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Response Time: Mode 0, Vcm† = 1.5 V CP0+ - CP0- = 100 mV 100 ns CP0+ - CP0- = -100 mV 250 ns Response Time: Mode 1, Vcm† = 1.5 V CP0+ - CP0- = 100 mV 175 ns CP0+ - CP0- = -100 mV 500 ns Response Time: Mode 2, Vcm† = 1.5 V CP0+ - CP0- = 100 mV 320 ns CP0+ - CP0- = -100 mV 1100 ns Response Time: Mode 3, Vcm† = 1.5 V CP0+ - CP0- = 100 mV 1050 ns CP0+ - CP0- = -100 mV 5200 ns Common-Mode Rejection Ratio 1.5 4 mV/V 0 1 mV Positive Hysteresis 1 CP0HYP1-0 = 00 Positive Hysteresis 2 CP0HYP1-0 = 01 2 5 10 mV Positive Hysteresis 3 CP0HYP1-0 = 10 7 10 20 mV Positive Hysteresis 4 CP0HYP1-0 = 11 15 20 30 mV Negative Hysteresis 1 CP0HYN1-0 = 00 0 1 mV Negative Hysteresis 2 CP0HYN1-0 = 01 2 5 10 mV Negative Hysteresis 3 CP0HYN1-0 = 10 7 10 20 mV Negative Hysteresis 4 CP0HYN1-0 = 11 15 20 30 mV VDD + 0.25 V Inverting or Non-Inverting Input Voltage Range -0.25 Input Capacitance 3 pF Input Bias Current 0.001 nA Input Offset Voltage -5 +5 mV POWER SUPPLY Power Supply Rejection 0.1 mV/V Power-up Time 10 µs Mode 0 7.6 µA Mode 1 3.2 µA Mode 2 1.3 µA Mode 3 0.4 µA Supply Current at DC † Vcm is the common-mode voltage on CP0+ and CP0-. 66 Rev. 1.1 C8051F320/1 8. VOLTAGE REGULATOR (REG0) C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network. The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered function. REG0 configuration options are shown in Figure 8.1 - Figure 8.4. Rev. 1.1 67 C8051F320/1 8.1. Regulator Mode Selection REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is degraded. See Table 8.1 for normal and low power mode supply current specifications. The REG0 mode selection is controlled via the REGMOD bit in register REG0CN. 68 Rev. 1.1 C8051F320/1 8.2. VBUS Detection When the USB Function Controller is used (see section Section “15. Universal Serial Bus Controller (USB0)” on page 143), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be active as long as the VBUS signal matches the polarity selected by VBPOL. See Table 8.1 for VBUS input parameters. Important Note: When USB is selected as a reset source, a system reset will be generated when the VBUS signal matches the polarity selected by the VBPOL bit. See Section “10. Reset Sources” on page 99 for details on selecting USB as a reset source. Table 8.1. Voltage Regulator Electrical Specifications VDD = 3.0 V; -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS Input Voltage Range Output Voltage TYP 4.0 Output Current = 1 to 100 mA VBUS Detection Input Threshold Bias Current MIN Normal Mode (REGMOD = ‘0’) Low Power Mode (REGMOD = ‘1’) Rev. 1.1 MAX UNITS 5.25 V 3.0 3.3 3.6 V 1.0 1.8 4.0 V 90 60 TBD TBD µA 69 C8051F320/1 Figure 8.1. REG0 Configuration: USB Bus-Powered C8051F320/1 VBUS VBUS Sense From VBUS REGIN 5V In Voltage Regulator (REG0) 3V Out To 3V Power Net Device Power Net VDD Figure 8.2. REG0 Configuration: USB Self-Powered C8051F320/1 From VBUS VBUS VBUS Sense From 5V Power Net REGIN 5V In Voltage Regulator (REG0) 3V Out To 3V Power Net 70 Device Power Net VDD Rev. 1.1 C8051F320/1 Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled C8051F320/1 From VBUS VBUS VBUS Sense REGIN 5V In Voltage Regulator (REG0) 3V Out From 3V Power Net Device Power Net VDD Figure 8.4. REG0 Configuration: No USB Connection C8051F320/1 VBUS VBUS Sense From 5V Power Net REGIN 5V In Voltage Regulator (REG0) 3V Out To 3V Power Net Device Power Net VDD Rev. 1.1 71 C8051F320/1 Figure 8.5. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 R/W R/W REGMOD Reserved Bit4 Bit3 R/W R/W R/W Reset Value Reserved Reserved Reserved 00000000 Bit2 Bit1 Bit0 SFR Address: 0xC9 Bit7: Bit6: Bit5: Bit4: Bits3-0: 72 REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). 1: VBUS signal currently preset (device attached to USB network). VBPOL: VBUS Interrupt Polarity Select. This bit selects the VBUS interrupt polarity. 0: VBUS interrupt active when VBUS is low. 1: VBUS interrupt active when VBUS is high. REGMOD: Voltage Regulator Mode Select. This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regulator operates in low power (suspend) mode. 0: USB0 Voltage Regulator in normal mode. 1: USB0 Voltage Regulator in low power mode. Reserved. Read = 0000b. Must Write = 0000b. Rev. 1.1 C8051F320/1 9. CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section 19), an enhanced full-duplex UART (see description in Section 17), an Enhanced SPI (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Section 14). The CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). The CIP-51 includes the following features: - Fully Compatible with MCS-51 Instruction Set 25 MIPS Peak Throughput with 25 MHz Clock 0 to 25 MHz Clock Frequency 256 Bytes of Internal RAM 25 Port I/O Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security Figure 9.1. CIP-51 Block Diagram D8 TMP2 B REGISTER STACK POINTER SRAM ADDRESS REGISTER PSW D8 D8 D8 ALU SRAM (256 X 8) D8 D8 TMP1 ACCUMULATOR D8 D8 D8 DATA BUS DATA BUS DATA BUS SFR_ADDRESS BUFFER D8 DATA POINTER D8 D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER DATA BUS - PROGRAM COUNTER (PC) PRGM. ADDRESS REG. PIPELINE RESET MEM_CONTROL A16 MEMORY INTERFACE MEM_READ_DATA CONTROL LOGIC SYSTEM_IRQs D8 STOP POWER CONTROL REGISTER MEM_WRITE_DATA D8 CLOCK IDLE MEM_ADDRESS D8 INTERRUPT INTERFACE EMULATION_IRQ D8 Rev. 1.1 73 C8051F320/1 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that for execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 Programming and Debugging Support In-system programming of the FLASH program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-programmable FLASH can also be read and changed a single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “21. C2 Interface” on page 253. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. 74 Rev. 1.1 C8051F320/1 9.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 9.1.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 9.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses external RAM (XRAM) and the on-chip program memory space implemented as re-programmable FLASH memory. The FLASH access feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “11. FLASH Memory” on page 107 for further details. Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR ARITHMETIC OPERATIONS Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Rev. 1.1 Bytes Clock Cycles 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 75 C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description MUL AB DIV AB DA A Multiply A and B Divide A by B Decimal adjust A LOGICAL OPERATIONS AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A DATA TRANSFER Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data 76 1 1 1 Clock Cycles 4 8 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 Bytes Rev. 1.1 C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A BOOLEAN MANIPULATION Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit PROGRAM BRANCHING Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel 3 1 1 1 1 1 1 2 2 1 2 1 1 Clock Cycles 3 3 3 3 3 3 3 2 2 1 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 1 2 1 2 1 2 2 2 2 2 2 2 2/3 2/3 3/4 3/4 3/4 2 3 1 1 2 3 2 1 2 2 3 3 3 3 4 5 5 3 4 3 3 2/3 2/3 3/4 3/4 3/4 Bytes Rev. 1.1 77 C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description Bytes CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation 3 2 3 1 Clock Cycles 4/5 2/3 3/4 1 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8Kbyte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. 78 Rev. 1.1 C8051F320/1 9.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The CIP-51 memory organization is shown in Figure 9.2. Figure 9.2. Memory Map DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE PROGRAM/DATA MEMORY (FLASH) 0x3E00 RESERVED 0x3DFF 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) 16K FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) General Purpose Registers EXTERNAL DATA ADDRESS SPACE 0x0000 0xFFFF Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2K-byte boundaries 0x0800 0x07FF 0x0400 0x03FF 0x0000 9.2.1. USB FIFOs 1024 Bytes XRAM - 1024 Bytes (accessable using MOVX instruction) Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F320/1 implements 16k bytes of this program memory space as in-system, re-programmable FLASH memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “11. FLASH Memory” on page 107 for further details. Rev. 1.1 79 C8051F320/1 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51. 9.2.3. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in Figure 9.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 9.2.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22h.3 moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 9.2.5. Stack A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. 80 Rev. 1.1 C8051F320/1 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 9.3, for a detailed description of each register. Table 9.2. Special Function Register (SFR) Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 SPI0CN B ADC0CN ACC PCA0CN PSW TMR2CN SMB0CN IP P3 IE P2 SCON0 P1 TCON P0 0(8) PCA0L P0MDIN PCA0CPL1 XBR0 PCA0MD REF0CN REG0CN SMB0CF CLKMUL OSCXCN CLKSEL SPI0CFG SBUF0 TMR3CN TMOD SP 1(9) PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 P1MDIN P2MDIN P3MDIN PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 XBR1 IT01CF PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 P0SKIP P1SKIP TMR2RLL TMR2RLH TMR2L TMR2H SMB0DAT ADC0GTL ADC0GTH ADC0LTL AMX0N AMX0P ADC0CF ADC0L OSCICN OSCICL EMI0CN SPI0CKR SPI0DAT P0MDOUT P1MDOUT CPT1CN CPT0CN CPT1MD CPT0MD TMR3RLL TMR3RLH TMR3L TMR3H TL0 TL1 TH0 TH1 DPL DPH 2(A) 3(B) 4(C) 5(D) PCA0CPH4 EIP1 PCA0CPH3 EIE1 PCA0CPM4 P2SKIP USB0XCN ADC0LTH ADC0H FLSCL FLKEY P2MDOUT CPT1MX USB0ADR CKCON 6(E) VDM0CN EIP2 RSTSRC EIE2 P3MDOUT CPT0MX USB0DAT PSCTL PCON 7(F) (bit addressable) Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High ADC0L 0xBD ADC0 Low ADC0LTH 0xC6 ADC0 Less-Than Compare Word High Rev. 1.1 Page 86 47 49 50 50 47 48 51 81 C8051F320/1 Table 9.3. Special Function Registers Register ADC0LTL AMX0N AMX0P B CKCON CLKSEL CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD CPT1MX DPH DPL EIE1 EIE2 EIP1 EIP2 EMI0CN FLKEY FLSCL IE IP IT01CF OSCICL OSCICN OSCXCN P0 P0MDIN P0MDOUT P0SKIP P1 P1MDIN P1MDOUT P1SKIP P2 P2MDIN P2MDOUT P2SKIP P3 P3MDIN P3MDOUT PCA0CN PCA0CPH0 PCA0CPH1 PCA0CPH2 82 Address 0xC5 0xBA 0xBB 0xF0 0x8E 0xA9 0x9B 0x9D 0x9F 0x9A 0x9C 0x9E 0x83 0x82 0xE6 0xE7 0xF6 0xF7 0xAA 0xB7 0xB6 0xA8 0xB8 0xE4 0xB3 0xB2 0xB1 0x80 0xF1 0xA4 0xD4 0x90 0xF2 0xA5 0xD5 0xA0 0xF3 0xA6 0xD6 0xB0 0xF4 0xA7 0xD8 0xFC 0xEA 0xEC Description ADC0 Less-Than Compare Word Low AMUX0 Negative Channel Select AMUX0 Positive Channel Select B Register Clock Control Clock Select Comparator0 Control Comparator0 Mode Selection Comparator0 MUX Selection Comparator1 Control Comparator1 Mode Selection Comparator1 MUX Selection Data Pointer High Data Pointer Low Extended Interrupt Enable 1 Extended Interrupt Enable 2 Extended Interrupt Priority 1 Extended Interrupt Priority 2 External Memory Interface Control FLASH Lock and Key FLASH Scale Interrupt Enable Interrupt Priority INT0/INT1 Configuration Internal Oscillator Calibration Internal Oscillator Control External Oscillator Control Port 0 Latch Port 0 Input Mode Configuration Port 0 Output Mode Configuration Port 0 Skip Port 1 Latch Port 1 Input Mode Configuration Port 1 Output Mode Configuration Port 1 Skip Port 2 Latch Port 2 Input Mode Configuration Port 2 Output Mode Configuration Port 2 Skip Port 3 Latch Port 3 Input Mode Configuration Port 3 Output Mode Configuration PCA Control PCA Capture 0 High PCA Capture 1 High PCA Capture 2 High Rev. 1.1 Page No. 51 46 45 86 223 125 60 62 61 63 65 64 84 84 92 94 93 94 115 111 111 90 91 95 119 119 122 135 135 136 136 137 137 138 138 139 139 140 140 141 141 142 248 252 252 252 C8051F320/1 Table 9.3. Special Function Registers Register PCA0CPH3 PCA0CPH4 PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0H PCA0L PCA0MD PCON PSCTL PSW REF0CN RSTSRC SBUF0 SCON0 SMB0CF SMB0CN SMB0DAT SP SPI0CFG SPI0CKR SPI0CN SPI0DAT TCON TH0 TH1 TL0 TL1 TMOD TMR2CN TMR2H TMR2L TMR2RLH TMR2RLL TMR3CN TMR3H TMR3L TMR3RLH TMR3RLL Address 0xEE 0xFE 0xFB 0xE9 0xEB 0xED 0xFD 0xDA 0xDB 0xDC 0xDD 0xDE 0xFA 0xF9 0xD9 0x87 0x8F 0xD0 0xD1 0xEF 0x99 0x98 0xC1 0xC0 0xC2 0x81 0xA1 0xA2 0xF8 0xA3 0x88 0x8C 0x8D 0x8A 0x8B 0x89 0xC8 0xCD 0xCC 0xCB 0xCA 0x91 0x95 0x94 0x93 0x92 Description PCA Capture 3High PCA Capture 4 High PCA Capture 0 Low PCA Capture 1 Low PCA Capture 2 Low PCA Capture 3Low PCA Capture 4 Low PCA Module 0 Mode Register PCA Module 1 Mode Register PCA Module 2 Mode Register PCA Module 3 Mode Register PCA Module 4 Mode Register PCA Counter High PCA Counter Low PCA Mode Power Control Program Store R/W Control Program Status Word Voltage Reference Control Reset Source Configuration/Status UART0 Data Buffer UART0 Control SMBus Configuration SMBus Control SMBus Data Stack Pointer SPI Configuration SPI Clock Rate Control SPI Control SPI Data Timer/Counter Control Timer/Counter 0 High Timer/Counter 1 High Timer/Counter 0 Low Timer/Counter 1 Low Timer/Counter Mode Timer/Counter 2 Control Timer/Counter 2 High Timer/Counter 2 Low Timer/Counter 2 Reload High Timer/Counter 2 Reload Low Timer/Counter 3Control Timer/Counter 3 High Timer/Counter 3Low Timer/Counter 3 Reload High Timer/Counter 3 Reload Low Rev. 1.1 Page No. 252 252 252 252 252 252 252 250 250 250 250 250 251 251 249 97 110 85 56 104 199 198 182 184 186 85 210 212 211 213 221 224 224 224 224 222 228 229 229 229 229 233 234 234 234 234 83 C8051F320/1 Table 9.3. Special Function Registers Register Address VDM0CN 0xFF XBR0 0xE1 XBR1 0xE2 0x84-0x86, 0xAB-0xAF, 0xB4, 0xB5, 0xBF, 0xC7, 0xCE, 0xCF, 0xD2, 0xD3, 0xDF, 0xE3, 0xE5, 0xF5 9.2.7. Description VDD Monitor Control Port I/O Crossbar Control 0 Port I/O Crossbar Control 1 Page No. 101 132 133 Reserved Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. Figure 9.3. DPL: Data Pointer Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0x82 Bits7-0: DPL: Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. Figure 9.4. DPH: Data Pointer High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x83 Bits7-0: 84 DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. Rev. 1.1 C8051F320/1 Figure 9.5. SP: Stack Pointer R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x81 Bits7-0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. Figure 9.6. PSW: Program Status Word R/W R/W R/W R/W R/W R/W R/W R Reset Value CY AC F0 RS1 RS0 OV F1 PARITY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bits4-3: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations. F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. RS1-RS0: Register Bank Select. These bits select which register bank is used during register accesses. RS1 0 0 1 1 Bit2: Bit1: Bit0: 0xD0 RS0 0 1 0 1 Register Bank 0 1 2 3 Address 0x00 - 0x07 0x08 - 0x0F 0x10 - 0x17 0x18 - 0x1F OV: Overflow Flag. This bit is set to 1 under the following circumstances: • An ADD, ADDC, or SUBB instruction causes a sign-change overflow. • A MUL instruction results in an overflow (result is greater than 255). • A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. PARITY: Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. Rev. 1.1 85 C8051F320/1 Figure 9.7. ACC: Accumulator R/W R/W R/W R/W R/W R/W R/W R/W ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0xE0 ACC: Accumulator. This register is the accumulator for arithmetic operations. Figure 9.8. B: B Register R/W R/W R/W R/W R/W R/W R/W R/W B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: 86 B: B Register. This register serves as a second accumulator for certain arithmetic operations. Rev. 1.1 Reset Value 0xF0 C8051F320/1 9.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interruptpending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 9.3.1. MCU Interrupt Sources and Vectors The MCU supports 16 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 89. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Rev. 1.1 87 C8051F320/1 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “19.1. Timer 0 and Timer 1” on page 217) select level or edge sensitive. The table below lists the possible configurations. IT0 1 1 0 0 IN0PL 0 1 0 1 /INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 /INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive /INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see Figure 9.15). Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “14.1. Priority Crossbar Decoder” on page 129 for complete details on configuring the Crossbar). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interruptpending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. 9.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 9.4. 9.3.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Note that the CPU is stalled during FLASH write/erase operations and USB FIFO MOVX accesses (see Section “12.2. Accessing USB FIFO Space” on page 114). Interrupt service latency will be increased for interrupts occuring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the CPU is stalled. 88 Rev. 1.1 C8051F320/1 Reset Interrupt Vector Priority Pending Flag Order Priority Control Always Enabled Always Highest Top 0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0) 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2) 0x001B 3 Y Y ET1 (IE.3) PT1 (IP.3) UART0 0x0023 4 Y N ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow 0x002B 5 Y N ET2 (IE.5) PT2 (IP.5) SPI0 0x0033 6 TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) Y N ESPI0 (IE.6) PSPI0 (IP.6) SMB0 0x003B 7 USB0 0x0043 8 ADC0 Window Compare 0x004B 9 0x0053 10 0x005B 11 Comparator0 0x0063 12 Comparator1 0x006B 13 Timer 3 Overflow 0x0073 14 VBUS Level 0x007B 15 ADC0 Conversion Complete Programmable Counter Array N/A N/A Enable Flag 0x0000 External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow None Cleared by HW? Interrupt Source Bit addressable? Table 9.4. Interrupt Summary ESMB0 (EIE1.0) EUSB0 Special N N (EIE1.1) AD0WINT EWADC0 Y N (ADC0CN.3) (EIE1.2) EADC0 AD0INT (ADC0CN.5) Y N (EIE1.3) CF (PCA0CN.7) EPCA0 Y N (EIE1.4) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) ECP0 N N CP0RIF (CPT0CN.5) (EIE1.5) CP1FIF (CPT1CN.4) ECP1 N N CP1RIF (CPT1CN.5) (EIE1.6) TF3H (TMR3CN.7) ET3 N N (EIE1.7) TF3L (TMR3CN.6) EVBUS N/A N/A N/A (EIE2.0) SI (SMB0CN.0) Rev. 1.1 Y N PT0 (IP.1) PSMB0 (EIP1.0) PUSB0 (EIP1.1) PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) PVBUS (EIP2.0) 89 C8051F320/1 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Figure 9.9. IE: Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 90 0xA8 EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. ET2: Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. EX1: Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 input. ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. Rev. 1.1 C8051F320/1 Figure 9.10. IP: Interrupt Priority R/W R/W R/W R/W R/W R/W R/W R/W - PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: Reset Value 0xB8 UNUSED. Read = 1, Write = don't care. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupts set to high priority level. PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupts set to high priority level. PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupts set to high priority level. PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Rev. 1.1 91 C8051F320/1 Figure 9.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 92 ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ECP1: Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. ECP0: Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. EADC0: Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. EWADC0: Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). EUSB0: Enable USB0 Interrupt. This bit sets the masking of the USB0 interrupt. 0: Disable all USB0 interrupts. 1: Enable interrupt requests generated by USB0. ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. Rev. 1.1 C8051F320/1 Figure 9.12. EIP1: Extended Interrupt Priority 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. PCP1: Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. PCP0: Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. PADC0 ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. PWADC0: ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. PUSB0: USB0 Interrupt Priority Control. This bit sets the priority of the USB0 interrupt. 0: USB0 interrupt set to low priority level. 1: USB0 interrupt set to high priority level. PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Rev. 1.1 93 C8051F320/1 Figure 9.13. EIE2: Extended Interrupt Enable 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - - - EVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE7 Bits7-1: Bit0: UNUSED. Read = 0000000b. Write = don’t care. EVBUS: Enable VBUS Level Interrupt. This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS interrupts. 1: Enable interrupt requests generated by VBUS level sense. Figure 9.14. EIP2: Extended Interrupt Priority 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - - - PVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF7 Bits7-1: Bit0: 94 UNUSED. Read = 0000000b. Write = don’t care. PVBUS: VBUS Level Interrupt Priority Control. This bit sets the priority of the VBUS interrupt. 0: VBUS interrupt set to low priority level. 1: VBUS interrupt set to high priority level. Rev. 1.1 C8051F320/1 Figure 9.15. IT01CF: INT0/INT1 Configuration Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE4 Note: Refer to Figure 19.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: Bits6-4: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. IN1SL2-0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN1SL2-0 000 001 010 011 100 101 110 111 Bit3: Bits2-0: /INT1 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 IN0PL: /INT0 Polarity 0: /INT0 interrupt is active low. 1: /INT0 interrupt is active high. INT0SL2-0: /INT0 Port Pin Selection Bits These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN0SL2-0 000 001 010 011 100 101 110 111 /INT0 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Rev. 1.1 95 C8051F320/1 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON) used to control the CIP-51's power management modes. Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished through system clock and individual peripheral management. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU. The internal oscillator can be placed in Suspend mode (see Section “13. Oscillators” on page 117). In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected, or the VBUS input signal matches the polarity selected by the VBPOL bit in register REG0CN (Figure 8.5 on Page 72). 9.4.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “10.6. PCA Watchdog Timer Reset” on page 102 for more information on the use and configuration of the WDT. 9.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 µsec. 96 Rev. 1.1 C8051F320/1 Figure 9.16. PCON: Power Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x87 Bits7-2: Bit1: Bit0: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control. STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: CPU goes into Stop mode (internal oscillator stopped). IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) Rev. 1.1 97 C8051F320/1 Notes 98 Rev. 1.1 C8051F320/1 10. RESET SOURCES Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • • • • CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered. The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled during and after the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “13. Oscillators” on page 117 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source (Section “20.3. Watchdog Timer Mode” on page 246 details the use of the Watchdog Timer). Program execution begins at location 0x0000. Figure 10.1. Reset Sources VDD Supply Monitor + - + - EN XTAL2 External Oscillator Drive Software Reset (SWRSF) Errant FLASH Operation WDT Enable MCD Enable Clock Select /RST Reset Funnel PCA WDT EN System Clock (wired-OR) C0RSEF Missing Clock Detector (oneshot) Internal Oscillator '0' CIP-51 Microcontroller Core System Reset Enable Px.x XTAL1 Power On Reset Comparator 0 Px.x Clock Multiplier Enable USB Controller VBUS Transition Extended Interrupt Handler Rev. 1.1 99 C8051F320/1 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above VRST. A Power-On Reset delay (TPORDelay) occurs before the device is released from reset; this delay is typically less than 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC. volts Figure 10.2. Power-On and VDD Monitor Reset Timing VDD 2.70 2.4 VRST VD D 2.0 1.0 t Logic HIGH Logic LOW /RST TPORDelay VDD Monitor Reset Power-On Reset 100 Rev. 1.1 C8051F320/1 10.2. Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the VDD monitor will still be enabled after the reset. Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized will cause a system reset. The procedure for configuring the VDD monitor as a reset source is shown below: Step 1. Enable the VDD monitor (VDM0CN.7 = ‘1’). Step 2. Wait for the VDD monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time). Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = ‘1’). See Figure 10.2 for VDD monitor timing. See Table 10.1 for complete electrical characteristics of the VDD monitor. Figure 10.3. VDM0CN: VDD Monitor Control R/W R R VDMEN VDDSTAT Reserved Bit7 Bit6 Bit5 R R R R R Reset Value Reserved Reserved Reserved Reserved Reserved Variable Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xFF Bit7: Bit6: Bits5-0: VDMEN: VDD Monitor Enable. This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (Figure 10.4). The VDD Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the VDD monitor as a reset source before it has stabilized will generate a system reset. See Table 10.1 for the minimum VDD Monitor turn-on time. The VDD Monitor is enabled following all POR resets. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. VDDSTAT: VDD Status. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. Reserved. Read = Variable. Write = don’t care. Rev. 1.1 101 C8051F320/1 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete /RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 10.4. Missing Clock Detector Reset The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If more than 100 µs pass between rising edges on the system clock, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise, this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables it. The state of the /RST pin is unaffected by this reset. 10.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), a system reset is generated. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. 10.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “20.3. Watchdog Timer Mode” on page 246; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to ‘1’. The state of the /RST pin is unaffected by this reset. 10.7. FLASH Error Reset If a FLASH read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • • • • A FLASH write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX write operation is attempted above address 0x3DFF. A FLASH read is attempted above user code space. This occurs when a MOVC operation is attempted above address 0x3DFF. A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above 0x3DFF. A FLASH read, write or erase attempt is restricted due to a FLASH security setting (see Section “11.3. Security Options” on page 109). The FERROR bit (RSTSRC.6) is set following a FLASH error reset. The state of the /RST pin is unaffected by this reset. 102 Rev. 1.1 C8051F320/1 10.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the /RST pin is unaffected by this reset. 10.9. USB Reset Writing ‘1’ to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as a reset source, a system reset will be generated when either of the following occur: 1. 2. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be enabled for RESET signaling to be detected. See Section “15. Universal Serial Bus Controller (USB0)” on page 143 for information on the USB Function Controller. The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register REG0CN. See Section “8. Voltage Regulator (REG0)” on page 67 for details on the VBUS detection circuit. The USBRSF bit will read ‘1’ following a USB reset. The state of the /RST pin is unaffected by this reset. Rev. 1.1 103 C8051F320/1 Figure 10.4. RSTSRC: Reset Source Register R/W R R/W R/W USBRSF FERROR C0RSEF SWRSF Bit7 Bit6 Bit5 Bit4 R R/W WDTRSF MCDRSF Bit3 Bit2 R/W R Reset Value PORSF PINRSF Variable Bit1 Bit0 SFR Address: 0xEF Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. FERROR: FLASH Error Indicator. 0: Source of last reset was not a FLASH read/write/erase error. 1: Source of last reset was a FLASH read/write/erase error. C0RSEF: Comparator0 Reset Enable and Flag. 0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset source. 1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source (active-low). SWRSF: Software Reset Force and Flag. 0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect. 1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset. WDTRSF: Watchdog Timer Reset Flag. 0: Source of last reset was not a WDT timeout. 1: Source of last reset was a WDT timeout. MCDRSF: Missing Clock Detector Flag. 0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing Clock Detector disabled. 1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected. PORSF: Power-On / VDD Monitor Reset Flag. This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled and stabilized can cause a system reset. See register VDM0CN (Figure 10.3). 0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a reset source. 1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate; Write: VDD monitor is a reset source. PINRSF: HW Pin Reset Flag. 0: Source of last reset was not /RST pin. 1: Source of last reset was /RST pin. Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), readmodify-write instructions read and modify the source enable only. This applies to bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF. 104 Rev. 1.1 C8051F320/1 Table 10.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. PARAMETER CONDITIONS IOL = 8.5 mA, VDD = 2.7 V to 3.6 V /RST Output Low Voltage MIN /RST Input High Voltage 0.7 x VDD TYP 2.40 25 2.55 0.3 x VDD 40 2.70 µA V Missing Clock Detector Timeout 100 220 500 µs Reset Time Delay /RST = 0.0 V Time from last system clock rising edge to reset initiation Delay between release of any reset source and code execution at location 0x0000 Minimum /RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply Current 5.0 µs 15 µs 100 20 Rev. 1.1 UNITS V V /RST Input Low Voltage /RST Input Pull-Up Current VDD POR Threshold (VRST) MAX 0.6 50 µs µA 105 C8051F320/1 Notes 106 Rev. 1.1 C8051F320/1 11. FLASH MEMORY On-chip, re-programmable FLASH memory is included for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a FLASH bit must be erased to set it back to logic 1. FLASH bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code execution is stalled during a FLASH write/erase operation. Refer to Table 11.1 for complete FLASH memory electrical characteristics. 11.1. Programming The FLASH Memory The simplest means of programming the FLASH memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program FLASH memory, see Section “21. C2 Interface” on page 253. To ensure the integrity of FLASH contents, it is strongly recommended that the on-chip VDD Monitor be enabled in any system that includes code that writes and/or erases FLASH memory from software. 11.1.1. FLASH Lock and Key Functions FLASH writes and erases by user software are protected with a lock and key function. The FLASH Lock and Key Register (FLKEY) must be written with the correct key codes, in sequence, before FLASH operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order, or the wrong codes are written, FLASH writes and erases will be disabled until the next system reset. FLASH writes and erases will also be disabled if a FLASH write or erase is attempted before the key codes have been written properly. The FLASH lock resets after each write or erase; the key codes must be written again before a following FLASH operation can be performed. The FLKEY register is detailed in Figure 11.3. 11.1.2. FLASH Erase Procedure The FLASH memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to FLASH memory using MOVX, FLASH write operations must be enabled by: (1) Writing the FLASH key codes in sequence to the FLASH Lock register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target FLASH memory). The PSWE bit remains set until cleared by software. A write to FLASH memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in FLASH. A byte location to be programmed must be erased before a new value is written. The FLASH memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps: Step 1. Disable interrupts (recommended). Step 2. Write the first key code to FLKEY: 0xA5. Step 3. Write the second key code to FLKEY: 0xF1. Step 4. Set the PSEE bit (register PSCTL). Step 5. Set the PSWE bit (register PSCTL). Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE bit (register PSCTL). Step 8. Clear the PSEE bit (register PSCTI). Rev. 1.1 107 C8051F320/1 11.1.3. FLASH Write Procedure FLASH bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte FLASH page containing the target location, as described in Section 11.1.2. Step 3. Write the first key code to FLKEY: 0xA5. Step 4. Write the second key code to FLKEY: 0xF1. Step 5. Set the PSWE bit (register PSCTL). Step 6. Clear the PSEE bit (register PSCTL). Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector. Step 8. Clear the PSWE bit (register PSCTL). Steps 3-8 must be repeated for each byte to be written. After FLASH writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. Table 11.1. FLASH Electrical Characteristics PARAMETER FLASH Size Endurance Erase Cycle Time Write Cycle Time CONDITIONS C8051F320/1 MIN 25 MHz System Clock 25 MHz System Clock † Note: 512 bytes at location 0x3E00 to 0x3FFF are reserved. 108 TYP MAX 100k 15 55 20 70 † Rev. 1.1 16384 20k 10 40 UNITS bytes Erase/Write ms µs C8051F320/1 11.2. Non-volatile Data Storage The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. 11.3. Security Options The CIP-51 provides security options to protect the FLASH memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the FLASH memory from accidental modification by software. PSWE must be explicitly set to ‘1’ before software can modify the FLASH memory; both PSWE and PSEE must be set to ‘1’ before software can erase FLASH memory. Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface. A Security Lock Byte located at the last byte of FLASH user space offers protection of the FLASH program memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The FLASH security mechanism allows the user to lock n 512-byte FLASH pages, starting at page 0 (addresses 0x0000 to 0x01FF), where n is the 1’s compliment number represented by the Security Lock Byte. See example below. Security Lock Byte: 1’s Compliment: FLASH pages locked: Addresses locked: 11111101b 00000010b 2 0x0000 to 0x03FF Important Notes About the FLASH Security: 1. Clearing any bit of the Lock Byte to ‘0’ will lock the FLASH page containing the Lock Byte (in addition to the selected pages). 2. Locked pages cannot be read, written, or erased via the C2 interface. 3. Locked pages cannot be read, written, or erased by user firmware executing from unlocked memory space. 4. User firmware executing in a locked page may read and write FLASH memory in any locked or unlocked page excluding the reserved area. 5. User firmware executing in a locked page may erase FLASH memory in any locked or unlocked page excluding the reserved area and the page containing the Lock Byte. 6. Locked pages can only be unlocked through the C2 interface with a C2 Device Erase command. 7. If a user firmware FLASH access attempt is denied (per restrictions #3, #4, and #5 above), a FLASH Error system reset will be generated. Rev. 1.1 109 C8051F320/1 Figure 11.1. FLASH Program Memory Map and Security Byte C8051F320/1 Reserved 0x3E00 Lock Byte Locked when any other FLASH pages are locked 0x3DFF 0x3DFE 0x3C00 FLASH memory organized in 512-byte pages Unlocked FLASH Pages Access limit set according to the FLASH security lock byte 0x0000 Figure 11.2. PSCTL: Program Store R/W Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - Reserved PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8F Bits7-3: Bit2: Bit1: Bit0: 110 Unused: Read = 00000b. Write = don’t care. Reserved. Read = 0b. Must Write = 0b. PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of FLASH program memory to be erased. If this bit is logic 1 and FLASH writes are enabled (PSWE is logic 1), a write to FLASH memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. 0: FLASH program memory erasure disabled. 1: FLASH program memory erasure enabled. PSWE: Program Store Write Enable Setting this bit allows writing a byte of data to the FLASH program memory using the MOVX write instruction. The FLASH location should be erased before writing data. 0: Writes to FLASH program memory disabled. 1: Writes to FLASH program memory enabled; the MOVX write instruction targets FLASH memory. Rev. 1.1 C8051F320/1 Figure 11.3. FLKEY: FLASH Lock and Key Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB7 Bits7-0: FLKEY: FLASH Lock and Key Register Write: This register must be written to before FLASH writes or erases can be performed. FLASH remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The timing of the writes does not matter, as long as the codes are written in order. The key codes must be written for each FLASH write or erase operation. FLASH will be locked until the next system reset if the wrong codes are written or if a FLASH operation is attempted before the codes have been written correctly. Read: When read, bits 1-0 indicate the current FLASH lock state. 00: FLASH is write/erase locked. 01: The first key code has been written (0xA5). 10: FLASH is unlocked (writes/erases allowed). 11: FLASH writes/erases disabled until the next reset. Figure 11.4. FLSCL: FLASH Scale Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB6 Bits7: Bits6-0: FOSE: FLASH One-shot Enable This bit enables the FLASH read one-shot. When the FLASH one-shot disabled, the FLASH sense amps are enabled for a full clock cycle during FLASH reads. At system clock frequencies below 10 MHz, disabling the FLASH one-shot will increase system power consumption. 0: FLASH one-shot disabled. 1: FLASH one-shot enabled. RESERVED. Read = 0. Must Write 0. Rev. 1.1 111 C8051F320/1 Notes 112 Rev. 1.1 C8051F320/1 12. EXTERNAL RAM The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF). Figure 12.1. External Ram Memory Map 0xFFFF Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2K-byte boundaries 0x0800 0x07FF 0x0400 0x03FF 0x0000 12.1. USB FIFOs 1024 Bytes Accessed through USB FIFO registers XRAM 1024 Bytes Accessed with the MOVX instruction Accessing User XRAM XRAM can be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in Figure 12.3). Note: the MOVX instruction is also used for writes to the FLASH memory. See Section “11. FLASH Memory” on page 107 for details. The MOVX instruction accesses XRAM by default. For any of the addressing modes the upper 5 bits of the 16-bit external data memory address word are "don't cares". As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external data memory address range. For example, the XRAM byte at address 0x0000 is also at address 0x0800, 0x1000, 0x1800, 0x2000, etc. Important Note: The upper 1k of the 2k XRAM functions as USB FIFO space. See Section 12.2 for details on accessing this memory space. Rev. 1.1 113 C8051F320/1 12.2. Accessing USB FIFO Space The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see Section “15.5. FIFO Management” on page 151 for more information on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space. Unused areas of the FIFO space may be used as general purpose XRAM, accessible as described in Section 12.1. The FIFO block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space. Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing USB FIFO space. Important Note: The USB clock must be active when accessing FIFO space. Figure 12.2. XRAM Memory Map Expanded View 0x03FF 0x07FF 0x07C0 Endpoint0 (64 bytes) 0x07BF 0x0740 Endpoint1 (128 bytes) 0x073F Endpoint2 (256 bytes) User XRAM Space User XRAM (1024 bytes) (System Clock Domain) USB FIFO Space 0x0640 (USB Clock Domain) 0x063F Endpoint3 (512 bytes) 0x0440 0x043F 0x0000 114 0x0400 Rev. 1.1 Free (64 bytes) C8051F320/1 Figure 12.3. EMI0CN: External Memory Interface Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - PGSEL2 PGSEL1 PGSEL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xAA Bits7-3: Bits2-0: Not Used - reads 00000b. PGSEL[2:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. The upper 5-bits are "don't cares", so the 2k address blocks are repeated modulo over the entire 64k external data memory address space. Rev. 1.1 115 C8051F320/1 Notes 116 Rev. 1.1 C8051F320/1 13. OSCILLATORS C8051F320/1 devices include a programmable internal oscillator, an external oscillator drive circuit, and a 4x Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 13.1. The system clock (SYSCLK) can be derived from the internal oscillator, external oscillator circuit, or the 4x Clock Multiplier divided by 2. The USB clock (USBCLK) can be derived from the internal oscillator, external oscillator, or 4x Clock Multiplier. Oscillator electrical specifications are given in Table 13.3 on page 126. Figure 13.1. Oscillator Diagram IFCN1 IFCN0 IOSCEN IFRDY SUSPEND Option 3 XTAL2 VDD CLKSEL CLKSL1 CLKSL0 OSCICN USBCLK2 USBCLK1 USBCLK0 OSCICL Option 2 XTAL2 EN Programmable Internal Clock Generator Option 1 IOSC n XTAL1 Input Circuit 10MΩ OSC EXOSC SYSCLK Option 4 XTAL2 XTLVLD XTAL2 IOSC EXOSC x2 EXOSC / 2 x2 Clock Multiplier IOSC / 2 EXOSC MULSEL1 MULSEL0 CLKMUL EXOSC / 3 EXOSC / 4 USBCLK2-0 OSCXCN MULEN MULINIT MULRDY XFCN2 XFCN1 XFCN0 XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 USBCLK EXOSC / 2 13.1. Programmable Internal Oscillator All C8051F320/1 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register as defined by Equation 13.1, where fBASE is the frequency of the internal oscillator following a reset, ∆T is the change in internal oscillator period, and ∆OSCICL is a change to the value held in register OSCICL. Equation 13.1. Typical Change in Internal Oscillator Period with OSCICL 1 ∆T ≅ 0.0025 × ------------- × ∆OSCICL f BASE Rev. 1.1 117 C8051F320/1 On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (fBASE). Section 13.1.1 details oscillator programming for C8051F320/1 devices. Electrical specifications for the precision internal oscillator are given in Table 13.3 on page 126. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. 13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices The OSCICL reset value is factory calibrated to result in a 12 MHz internal oscillator with a ±1.5% accuracy; this frequency is suitable for use as the USB clock (see Section 13.4). Software may modify the frequency of the internal oscillator as described below. Important Note: Once the internal oscillator frequency has been modified, the internal oscillator may not be used as the USB clock as described in Section 13.4. The internal oscillator frequency will reset to its original factory-calibrated frequency following any device reset, at which point the oscillator is suitable for use as the USB clock. Software should read and adjust the value of OSCICL according to Equation 13.1 to obtain the desired frequency. The example below shows how to obtain an 11.6 MHz internal oscillator frequency. fBASE is the internal oscillator reset frequency; TBASE is the reset oscillator period. fDES is the desired internal oscillator frequency; TDES is the desired oscillator period. f BASE = 12000000Hz 1 T BASE = ------------------------ s 12000000 f DES = 11600000Hz 1 T DES = ------------------------ s 11600000 The required change in period (∆TDES) is the difference between the base period and the desired period. 1 - – ----------------------1 - = 2.87 × 10 – 9 s ∆T DES = ----------------------11600000 12000000 Using Equation 13.1 and the above calculations, find ∆OSCICL: 2.87 × 10 –9 1 = 0.0025 × ------------- × ∆OSCICL f BASE ∆OSCICL = 13.79 ∆OSCICL is rounded to the nearest integer (14) and added to the reset value of register OSCICL. Important Note: If the sum of the reset value of OSCICL and ∆OSCICL is greater than 31 or less than 0, then the device will not be capable of producing the desired frequency. 13.1.2. Internal Oscillator Suspend Mode The internal oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register OSCICN. In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected (Section 15) or VBUS matches the polarity selected by the VBPOL bit in register REG0CN (Section 8.2). Note that the USB transceiver must be enabled for a USB event to be detected. 118 Rev. 1.1 C8051F320/1 Figure 13.2. OSCICN: Internal Oscillator Control Register R/W R R/W R R/W R/W R/W R/W Reset Value IOSCEN IFRDY SUSPEND - - - IFCN1 IFCN0 00010100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB2 Bit7: Bit6: Bit5: Bits4-2: Bits1-0: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator is not running at programmed frequency. 1: Internal Oscillator is running at programmed frequency. SUSPEND: Force Suspend Writing a ‘1’ to this bit will force the internal oscillator to be stopped. The oscillator will be re-started on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event (see Figure 8.5). UNUSED. Read = 000b, Write = don't care. IFCN1-0: Internal Oscillator Frequency Control Bits. 00: SYSCLK derived from Internal Oscillator divided by 8. 01: SYSCLK derived from Internal Oscillator divided by 4. 10: SYSCLK derived from Internal Oscillator divided by 2. 11: SYSCLK derived from Internal Oscillator divided by 1. Figure 13.3. OSCICL: Internal Oscillator Calibration Register R/W R/W R/W - - - Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value Bit1 Bit0 SFR Address: OSCCAL Bit4 Bit3 Bit2 Variable 0xB3 Bits4-0: OSCCAL: Oscillator Calibration Value These bits determine the internal oscillator period as per Equation 13.1. Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “15.4. USB Clock Configuration” on page 150 for details on Clock Recovery. Rev. 1.1 119 C8051F320/1 13.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13.1. A 10 MΩ resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as shown in Option 2, 3, or 4 of Figure 13.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see Figure 13.4) Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit; see Section “14.1. Priority Crossbar Decoder” on page 129 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section “14.2. Port I/O Initialization” on page 131 for details on Port input mode selection. 13.2.1. Clocking Timers Directly Through the External Oscillator The external oscillator source divided by eight is a clock option for the timers (Section “19. Timers” on page 217) and the Programmable Counter Array (PCA) (Section “20. Programmable Counter Array (PCA0)” on page 235). When the external oscillator is used to clock these peripherals, but is not used as the system clock, the external oscillator frequency must be less than or equal to the system clock frequency. In this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized with the system clock; the jitter associated with this synchronization is limited to ±0.5 system clock cycles. 13.2.2. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in Figure 13.4 (OSCXCN register). For example, a 12 MHz crystal requires an XFCN setting of 111b. When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Step 2. Step 3. Step 4. Enable the external oscillator. Wait at least 1 ms. Poll for XTLVLD => ‘1’. Switch the system clock to the external oscillator. Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. 120 Rev. 1.1 C8051F320/1 13.2.3. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF: f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 * 50 ] = 0.1 MHz = 100 kHz Referring to the table in Figure 13.4, the required XFCN setting is 010b. Programming XFCN to a higher setting in RC mode will improve frequency accuracy at an increased external oscillator supply current. 13.2.4. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 13.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF: f = KF / ( C * VDD ) = KF / ( 50 * 3 ) MHz f = KF / 150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in Figure 13.4 as KF = 22: f = 22 / 150 = 0.146 MHz, or 146 kHz Therefore, the XFCN value to use in this example is 011b. Rev. 1.1 121 C8051F320/1 Figure 13.4. OSCXCN: External Oscillator Control Register R R/W R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit4 R R/W R/W R/W Reset Value - XFCN2 XFCN1 XFCN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 Bit7: Bits6-4: Bit3: Bits2-0: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. XOSCMD2-0: External Oscillator Mode Bits. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode. 101: Capacitor Oscillator Mode. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. RESERVED. Read = 0, Write = don't care. XFCN2-0: External Oscillator Frequency Control Bits. 000-111: See table below: XFCN 000 001 010 011 100 101 110 111 Crystal (XOSCMD = 11x) f ≤ 32kHz 32kHz < f ≤ 84kHz 84kHz < f ≤ 225kHz 225kHz < f ≤ 590kHz 590kHz < f ≤ 1.5MHz 1.5MHz < f ≤ 4MHz 4MHz < f ≤ 10MHz 10MHz < f ≤ 30MHz RC (XOSCMD = 10x) f ≤ 25kHz 25kHz < f ≤ 50kHz 50kHz < f ≤ 100kHz 100kHz < f ≤ 200kHz 200kHz < f ≤ 400kHz 400kHz < f ≤ 800kHz 800kHz < f ≤ 1.6MHz 1.6MHz < f ≤ 3.2MHz CRYSTAL MODE (Circuit from Figure 13.1, Option 1; XOSCMD = 11x) Choose XFCN value to match crystal or resonator frequency. RC MODE (Circuit from Figure 13.1, Option 2; XOSCMD = 10x) Choose XFCN value to match frequency range: f = 1.23(103) / (R * C), where f = frequency of clock in MHz C = capacitor value in pF R = Pull-up resistor value in kΩ C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired: f = KF / (C * VDD), where f = frequency of clock in MHz C = capacitor value the XTAL2 pin in pF VDD = Power Supply on MCU in volts 122 Rev. 1.1 C (XOSCMD = 10x) K Factor = 0.87 K Factor = 2.6 K Factor = 7.7 K Factor = 22 K Factor = 65 K Factor = 180 K Factor = 664 K Factor = 1590 C8051F320/1 13.3. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “15.4. USB Clock Configuration” on page 150). A divided version of the Multiplier output can also be used as the system clock. See Section 13.4 for details on system clock and USB clock source selection. The 4x Clock Multiplier is configured via the CLKMUL register. The procedure for configuring and enabling the 4x Clock Multiplier is as follows: 1. 2. 3. 4. 5. 6. Reset the Multiplier by writing 0x00 to register CLKMUL. Select the Multiplier input source via the MULSEL bits. Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80). Delay for >5 µs. Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0). Poll for MULRDY => ‘1’. Important Note: When using an external oscillator as the input to the 4x Clock Multiplier, the external source must be enabled and stable before the Multiplier is initialized. See Section 13.4 for details on selecting an external oscillator source. Figure 13.5. CLKMUL: Clock Multiplier Control Register R/W MULEN Bit7 R/W R MULINIT MULRDY Bit6 Bit5 R/W R/W R/W - - - Bit4 Bit3 Bit2 R/W R/W MULSEL Bit1 Bit0 Reset Value 00000000 SFR Address 0xB9 Bit7: Bit6: Bit5: Bits4-2: Bits1-0: MULEN: Clock Multiplier Enable 0: Clock Multiplier disabled. 1: Clock Multiplier enabled. MULINIT: Clock Multiplier Initialize This bit should be a ‘0’ when the Clock Multiplier is enabled. Once enabled, writing a ‘1’ to this bit will initialize the Clock Multiplier. The MULRDY bit reads ‘1’ when the Clock Multiplier is stabilized. MULRDY: Clock Multiplier Ready This read-only bit indicates the status of the Clock Multiplier. 0: Clock Multiplier not ready. 1: Clock Multiplier ready (locked). Unused. Read = 000b; Write = don’t care. MULSEL: Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier. MULSEL 00 01 10 11 Selected Clock Internal Oscillator External Oscillator External Oscillator / 2 RESERVED Rev. 1.1 123 C8051F320/1 13.4. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. 13.4.1. System Clock Selection The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA, USB) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and 4x Clock Multiplier so long as the selected oscillator is enabled and has settled. 13.4.2. USB Clock Selection The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The USB clock may be derived from the 4x Clock Multiplier output, a divided version of the internal oscillator, or a divided version of the external oscillator. Note that the USB clock must be 48 MHz when operating USB0 as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low Speed Function. See Figure 13.6 for USB clock selection options. Some example USB clock configurations for Full and Low Speed mode are given below: Table 13.1. Typical USB Full Speed Clock Settings Clock Signal USB Clock Clock Multiplier Input Internal Oscillator Clock Signal USB Clock Clock Multiplier Input External Oscillator † Internal Oscillator Input Source Selection Clock Multiplier Internal Oscillator† Divide by 1 External Oscillator Input Source Selection Clock Multiplier External Oscillator Crystal Oscillator Mode 12 MHz Crystal Register Bit Settings USBCLK = 000b MULSEL = 00b IFCN = 11b Register Bit Settings USBCLK = 000b MULSEL = 01b XOSCMD = 110b XFCN = 111b Clock Recovery must be enabled for this configuration. Table 13.2. Typical USB Low Speed Clock Settings Clock Signal USB Clock Internal Oscillator Clock Signal USB Clock External Oscillator 124 Internal Oscillator Input Source Selection Internal Oscillator / 2 Divide by 1 External Oscillator Input Source Selection External Oscillator / 4 Crystal Oscillator Mode 24 MHz Crystal Rev. 1.1 Register Bit Settings USBCLK = 001b IFCN = 11b Register Bit Settings USBCLK = 101b XOSCMD = 110b XFCN = 111b C8051F320/1 Figure 13.6. CLKSEL: Clock Select Register R/W R/W Bit7 R/W R/W USBCLK Bit6 Bit5 Bit4 R/W R/W - - Bit3 Bit2 R/W R/W CLKSL Bit1 Reset Value 00000000 Bit0 SFR Address 0xA9 Bit 7: Bits6-4: Unused. Read = 0b; Write = don’t care. USBCLK2-0: USB Clock Select These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected clock should be 6 MHz. USBCLK 000 001 010 011 100 101 110 111 Bits3-2: Bits1-0: Selected Clock 4x Clock Multiplier Internal Oscillator / 2 External Oscillator External Oscillator / 2 External Oscillator / 3 External Oscillator / 4 RESERVED RESERVED Unused. Read = 00b; Write = don’t care. CLKSL1-0: System Clock Select These bits select the system clock source. CLKSL 00 01 10 11 Selected Clock Internal Oscillator (as determined by the IFCN bits in register OSCICN) External Oscillator 4x Clock Multiplier / 2 RESERVED Rev. 1.1 125 C8051F320/1 Table 13.3. Internal Oscillator Electrical Characteristics -40°C to +85°C unless otherwise specified PARAMETER Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) USB Clock Frequency† †Applies 126 CONDITIONS Reset Frequency MIN 11.82 OSCICN.7 = 1 TYP 12 MAX 12.18 450 µA Full Speed Mode 47.88 48 48.12 Low Speed Mode 5.91 6 6.09 only to external oscillator sources. Rev. 1.1 UNITS MHz MHz C8051F320/1 14. PORT INPUT/OUTPUT Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321). Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 14.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.5 and Figure 14.6, are used to select internal digital functions. All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Complete Electrical Specifications for Port I/O are given in Table 14.1 on page 142. Figure 14.1. Port I/O Functional Block Diagram XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder Highest Priority 2 UART (Internal Digital Signals) P0 I/O Cells P0.0 P1 I/O Cells P1.0 P2 I/O Cells P2.0 P3 I/O Cells P3.0 2 8 Note: P2.4-P2.7 only available on the C8051F320 4 SPI 8 CP0 Outputs 2 CP1 Outputs 2 Digital Crossbar 8 8 SYSCLK 1 T0, T1 P0 P1.7 P2.7 6 PCA Lowest Priority P0.7 2 SMBus (P0.0-P0.7) (Port Latches) 8 P1 (P1.0-P1.7) P2 (P2.0-P2.7) 8 8 P3 (P3.0) Rev. 1.1 127 C8051F320/1 Figure 14.2. Port I/O Cell Block Diagram /WEAK-PULLUP VDD PUSH-PULL /PORT-OUTENABLE (WEAK) PORT PAD PORT-OUTPUT GND Analog Select ANALOG INPUT PORT-INPUT 128 VDD Rev. 1.1 C8051F320/1 14.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.7 if VREF is used, P0.3 and/or P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 14.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP = 0x00); Figure 14.4 shows the Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C). Figure 14.3. Crossbar Priority Decoder with No Pins Skipped P1 1 2 3 4 5 VREF 0 CNVSTR PIN I/O XTAL2 SF Signals XTAL1 P0 6 7 0 1 2 3 P2 4 5 6 7 0 0 0 0 0 1 2 3 0 0 0 4 5 6 7 TX0 RX0 SCK MISO MOSI NSS* *NSS is only pinned out in 4-wire SPI mode SDA SCL CP0 Signals Unavailable CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 0 0 0 0 0 0 0 P0SKIP[0:7] 0 0 0 0 0 0 P1SKIP[0:7] P2SKIP[0:3] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. Rev. 1.1 129 C8051F320/1 Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped 1 2 3 4 5 VREF 0 P1 CNVSTR PIN I/O XTAL2 SF Signals XTAL1 P0 6 7 0 1 2 3 P2 4 5 6 7 0 1 2 3 0 0 0 4 5 6 7 TX0 RX0 SCK MISO MOSI *NSS is only pinned out in 4-wire SPI mode NSS* SDA SCL CP0 Signals Unavailable CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 0 0 1 1 0 0 0 P0SKIP[0:7] 0 0 0 0 0 0 P1SKIP[0:7] 0 0 0 0 P2SKIP[0:3] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. 130 Rev. 1.1 C8051F320/1 14.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals (XBR0, XBR1). Step 5. Enable the Crossbar (XBARE = ‘1’). All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. To configure a Port pin for digital input, write ‘0’ to the corresponding bit in register PnMDOUT, and write ‘1’ to the corresponding Port latch (register Pn). Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See Figure 14.8 for the PnMDIN register details. The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pull-up is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pull-up is turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation. Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. Important Note: The Crossbar must be enabled to use Ports P0, P1, and P2.0-P2.3 as standard Port I/O in output mode. These Port output drivers are disabled while the Crossbar is disabled. P2.4-P2.7 and P3.0 always function as standard GPIO. Rev. 1.1 131 C8051F320/1 Figure 14.5. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 132 CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. SYSCKE: /SYSCLK Output Enable 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. SMB0E: SMBus I/O Enable 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. SPI0E: SPI I/O Enable 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. Rev. 1.1 C8051F320/1 Figure 14.6. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W R/W R/W WEAKPUD XBARE T1E T0E ECIE Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value Bit0 SFR Address: PCA0ME Bit2 Bit1 00000000 0xE2 Bit7: Bit6: Bit5: Bit4: Bit3: Bits2-0: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull output). 1: Weak Pull-ups disabled. XBARE: Crossbar Enable. 0: Crossbar disabled; all Port drivers disabled. 1: Crossbar enabled. T1E: T1 Enable 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. T0E: T0 Enable 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. ECIE: PCA0 External Counter Input Enable 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. PCA0ME: PCA Module I/O Enable Bits. 000: All PCA I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110: Reserved. 111: Reserved. Rev. 1.1 133 C8051F320/1 14.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. 134 Rev. 1.1 C8051F320/1 Figure 14.7. P0: Port0 Register R/W R/W R/W R/W R/W R/W R/W R/W P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0x80 P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input. 0: P0.n pin is logic low. 1: P0.n pin is logic high. Figure 14.8. P0MDIN: Port0 Input Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF1 Bits7-0: Analog Input Configuration Bits for P0.7-P0.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is not configured as an analog input. Rev. 1.1 135 C8051F320/1 Figure 14.9. P0MDOUT: Port0 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT). Figure 14.10. P0SKIP: Port0 Skip Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 Bits7-0: 136 P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. Rev. 1.1 C8051F320/1 Figure 14.11. P1: Port1 Register R/W R/W R/W R/W R/W R/W R/W R/W P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0x90 P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. Figure 14.12. P1MDIN: Port1 Input Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF2 Bits7-0: Analog Input Configuration Bits for P1.7-P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. Rev. 1.1 137 C8051F320/1 Figure 14.13. P1MDOUT: Port1 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA5 Bits7-0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. Figure 14.14. P1SKIP: Port1 Skip Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xD5 Bits7-0: 138 P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. Rev. 1.1 C8051F320/1 Figure 14.15. P2: Port2 Register R/W R/W R/W R/W R/W R/W R/W R/W P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0xA0 P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. Note: P2.7-P2.4 only available on C8051F320 devices. Writes to these Ports do not require XBARE = ‘1’. Figure 14.16. P2MDIN: Port2 Input Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 11111111 0xF3 Bits7-0: Analog Input Configuration Bits for P2.7-P2.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured as an analog input. 1: Corresponding P2.n pin is not configured as an analog input. Note: P2.7-P2.4 only available on C8051F320 devices. Rev. 1.1 139 C8051F320/1 Figure 14.17. P2MDOUT: Port2 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA6 Bits7-0: Output Configuration Bits for P2.7-P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. Note: P2.7-P2.4 only available on C8051F320 devices. Figure 14.18. P2SKIP: Port2 Skip Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD6 Bits7-4: Bits3-0: 140 Unused. Read = 0000b. Write = don’t care. P2SKIP[3:0]: Port2 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. Rev. 1.1 C8051F320/1 Figure 14.19. P3: Port3 Register R/W R/W R/W R/W R/W R/W R/W R/W P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bits7-0: Reset Value 0xB0 P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. 0: P3.n pin is logic low. 1: P3.n pin is logic high. Figure 14.20. P3MDIN: Port3 Input Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000001 0xF4 Bits7-1: Bit0: UNUSED. Read = 0000000b; Write = don’t care. Analog Input Configuration Bit for P3.0. Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P3.n pin is configured as an analog input. 1: Corresponding P3.n pin is not configured as an analog input. Rev. 1.1 141 C8051F320/1 Figure 14.21. P3MDOUT: Port3 Output Mode Register R/W R/W R/W - - - Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA7 Bits7-1: Bit0: UNUSED. Read = 0000000b; Write = don’t care. Output Configuration Bit for P3.0; ignored if corresponding bit in register P3MDIN is logic 0. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. Table 14.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6V, -40°C to +85°C unless otherwise specified PARAMETERS CONDITIONS IOH = -3mA, Port I/O push-pull Output High Voltage IOH = -10µA, Port I/O push-pull MIN VDD-0.1 V 0.6 IOL = 10µA 0.1 V 1.0 Input High Voltage Input Low Voltage 142 UNITS VDD-0.8 IOL = 25mA Input Leakage Current MAX VDD-0.7 IOH = -10mA, Port I/O push-pull IOL = 8.5mA Output Low Voltage TYP 2.0 0.8 ±1 Weak Pull-up Off Weak Pull-up On, VIN = 0 V Rev. 1.1 25 50 V V µA C8051F320/1 15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) C8051F320/1 devices include a complete Full/Low Speed USB function for USB peripheral implementations†. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation. No external components are required. The USB Function Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant. Figure 15.1. USB0 Block Diagram Transceiver Serial Interface Engine (SIE) Endpoint0 VDD IN/OUT D+ Data Transfer Control D- Endpoint1 Endpoint2 Endpoint3 OUT IN IN USB Control, Status, and Interrupt Registers CIP-51 Core OUT IN OUT USB FIFOs (1k RAM) Important Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and abbreviations used in this document are defined in the USB Specification. We encourage you to review the latest version of the USB Specification before proceeding. † The C8051F320/1 cannot be used as a USB Host device. Rev. 1.1 143 C8051F320/1 15.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 15.1. Endpoint Addressing Scheme Endpoint Endpoint0 Endpoint1 Endpoint2 Endpoint3 15.2. Associated Pipes Endpoint0 IN Endpoint0 OUT Endpoint1 IN Endpoint1 OUT Endpoint2 IN Endpoint2 OUT Endpoint3 IN Endpoint3 OUT USB Protocol Address 0x00 0x00 0x81 0x01 0x82 0x02 0x83 0x03 USB Transceiver The USB Transceiver is configured via the USB0XCN register shown in Figure 15.2. This configuration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (Full or Low Speed). When bit SPEED = ‘1’, USB0 operates as a Full Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = ‘0’, USB0 operates as a Low Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register USB0XCN can be used for Transceiver testing as described in Figure 15.2. The pull-up resistor is enabled only when VBUS is present (see Section “8.2. VBUS Detection” on page 69 for details on VBUS detection). Important Note: The USB clock should be active before the Transceiver is enabled. 144 Rev. 1.1 C8051F320/1 Figure 15.2. USB0XCN: USB0 Transceiver Control R/W R/W R/W PREN PHYEN SPEED Bit7 Bit6 Bit5 R/W R/W PHYTST1 PHYTST0 Bit4 R R R Reset Value DFREC Dp Dn 00000000 Bit2 Bit1 Bit0 SFR Address: Bit3 0xD7 Bit7: Bit6: Bit5: Bits4-3: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from the USB network). 1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB network). PHYEN: Physical Layer Enable This bit enables/disables the USB0 physical layer transceiver. 0: Transceiver disabled (suspend). 1: Transceiver enabled (normal). SPEED: USB0 Speed Select This bit selects the USB0 speed. 0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the Dline. 1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+ line. PHYTST1-0: Physical Layer Test These bits can be used to test the USB0 transceiver. PHYTST[1:0] 00b 01b 10b 11b Bit2: Bit1: Bit0: Mode Mode 0: Normal (non-test mode) Mode 1: Differential ‘1’ Forced Mode 2: Differential ‘0’ Forced Mode 3: Single-Ended ‘0’ Forced D+ X 1 0 0 DX 0 1 0 DFREC: Differential Receiver The state of this bit indicates the current differential value present on the D+ and D- lines when PHYEN = ‘1’. 0: Differential ‘0’ signaling on the bus. 1: Differential ‘1’ signaling on the bus. Dp: D+ Signal Status This bit indicates the current logic level of the D+ pin. 0: D+ signal currently at logic 0. 1: D+ signal currently at logic 1. Dn: D- Signal Status This bit indicates the current logic level of the D- pin. 0: D- signal currently at logic 0. 1: D- signal currently at logic 1. Rev. 1.1 145 C8051F320/1 15.3. USB Register Access The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 15.3. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 15.2 for a list of endpoint control/status registers. Important Note: The USB clock must be active when accessing USB registers. Figure 15.3. USB0 Register Access Scheme 8051 SFRs USB Controller Interrupt Registers FIFO Access Common Registers Index Register USB0DAT Endpoint0 Control/ Status Registers Endpoint1 Control/ Status Registers Endpoint2 Control/ Status Registers USB0ADR 146 Endpoint3 Control/ Status Registers Rev. 1.1 C8051F320/1 Figure 15.4. USB0ADR: USB0 Indirect Address Register R/W R/W BUSY AUTORD Bit7 Bit6 R/W R/W R/W R/W R/W R/W USBADDR Bit5 Bit4 Bit3 Bit2 Reset Value 00000000 Bit1 Bit0 SFR Address: 0x96 Bits7: Bit6: Bits5-0: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is set to ‘1’, hardware will clear BUSY when the targeted register data is ready in the USB0DAT register. Software should check BUSY for ‘0’ before writing to USB0DAT. Write: 0: No effect. 1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits. Read: 0: USB0DAT register data is valid. 1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid. AUTORD: USB0 Register Auto-read Flag This bit is used for block FIFO reads. 0: BUSY must be written manually for each USB0 indirect register read. 1: The next indirect register read will automatically be initiated when software reads USB0DAT (USBADDR bits will not be changed). USBADDR: USB0 Indirect Register Address These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 15.2 lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. Rev. 1.1 147 C8051F320/1 Figure 15.5. USB0DAT: USB0 Data Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value USB0DAT Bit7 Bit6 Bit5 Bit4 Bit3 00000000 Bit2 Bit1 Bit0 SFR Address: 0x97 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write data to USB0DAT. 4. Repeat (Step 2 may be skipped when writing to the same USB0 register). Read Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write ‘1’ to the BUSY bit in register USB0ADR (steps 2 and 3 can be performed in the same write). 4. Poll for BUSY (USB0ADR.7) => ‘0’. 5. Read data from USB0DAT. 6. Repeat from Step 2 (Step 2 may be skipped when reading the same USB0 register; Step 3 may be skipped when the AUTORD bit (USB0ADR.6) is logic 1). Figure 15.6. INDEX: USB0 Endpoint Index (USB Register) R R R R - - - - Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W EPSEL Bit3 Bit2 Reset Value 00000000 Bit1 Bit0 USB Address: 0x0E Bits7-4: Bits3-0: Unused. Read = 0000b; Write = don’t care. EPSEL: Endpoint Select These bits select which endpoint is targeted when indexed USB0 registers are accessed. INDEX 0x0 0x1 0x2 0x3 0x4 - 0xF 148 Target Endpoint 0 1 2 3 Reserved Rev. 1.1 C8051F320/1 Table 15.2. USB0 Controller Registers USB Register Name USB Register Address IN1INT OUT1INT CMINT IN1IE OUT1IE CMIE 0x02 0x04 0x06 0x07 0x09 0x0B FADDR POWER FRAMEL FRAMEH INDEX CLKREC FIFOn 0x00 0x01 0x0C 0x0D 0x0E 0x0F 0x20-0x23 E0CSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH E0CNT EOUTCNTL EOUTCNTH 0x11 0x12 0x14 0x15 0x16 0x17 Description Page Number Interrupt Registers Endpoint0 and Endpoints1-3 IN Interrupt Flags Endpoints1-3 OUT Interrupt Flags Common USB Interrupt Flags Endpoint0 and Endpoints1-3 IN Interrupt Enables Endpoints1-3 OUT Interrupt Enables Common USB Interrupt Enables Common Registers Function Address Power Management Frame Number Low Byte Frame Number High Byte Endpoint Index Selection Clock Recovery Control Endpoints0-3 FIFOs Indexed Registers Endpoint0 Control / Status Endpoint IN Control / Status Low Byte Endpoint IN Control / Status High Byte Endpoint OUT Control / Status Low Byte Endpoint OUT Control / Status High Byte Number of Received Bytes in Endpoint0 FIFO Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte Rev. 1.1 157 158 159 160 160 161 153 155 156 156 148 150 152 164 168 169 171 172 165 172 172 149 C8051F320/1 15.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “13. Oscillators” on page 117. The USB0 clock is selected via SFR CLKSEL (see Figure 13.6 on Page 125). Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows the internal oscillator (and 4x Clock Multiplier) to meet the requirements for USB clock tolerance. Clock Recovery should be used in the following configurations: Communication Speed Full Speed Low Speed USB Clock 4x Clock Multiplier Internal Oscillator / 2 4x Clock Multiplier Input Internal Oscillator N/A When operating USB0 as a Low Speed function with Clock Recovery, software must write ‘1’ to the CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode. Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network. This mode is not required (or recommended) in typical USB environments. Figure 15.7. CLKREC: Clock Recovery Control (USB Register) R/W R/W R/W CRE CRSSEN CRLOW Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reserved Bit4 Bit3 Bit2 Reset Value 00001001 Bit1 Bit0 USB Address: 0x0F Bit7: Bit6: Bit5: Bits4-0: 150 CRE: Clock Recovery Enable. This bit enables/disables the USB clock recovery feature. 0: Clock recovery disabled. 1: Clock recovery enabled. CRSSEN: Clock Recovery Single Step. This bit forces the oscillator calibration into ‘single-step’ mode during clock recovery. 0: Normal calibration mode. 1: Single step mode. CRLOW: Low Speed Clock Recovery Mode. This bit must be set to ‘1’ if clock recovery is used when operating as a Low Speed USB device. 0: Full Speed Mode. 1: Low Speed Mode. Reserved. Read = Variable. Must Write = 1001b. Rev. 1.1 C8051F320/1 15.5. FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 15.8. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT). Figure 15.8. USB FIFO Allocation 0x07FF 0x07C0 0x07BF 0x0740 0x073F Endpoint0 (64 bytes) Endpoint1 (128 bytes) Configurable as IN, OUT, or both (Split Mode) Endpoint2 (256 bytes) 0x0640 0x063F Endpoint3 (512 bytes) 0x0440 0x043F 0x0400 Free (64 bytes) USB Clock Domain System Clock Domain 0x03FF User XRAM (1024 bytes) 0x0000 15.5.1. FIFO Split Mode The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes (0x0440 to 0x053F) are used by Endpoint3 OUT. If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see Figure 15.23). 15.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When Rev. 1.1 151 C8051F320/1 Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration. Table 15.3. FIFO Configurations Endpoint Number 0 Split Mode Enabled? Maximum IN Packet Size (Double Buffer Disabled / Enabled) N/A N Y N Y N Y 1 2 3 64 / 32 128 / 64 256 / 128 Maximum OUT Packet Size (Double Buffer Disabled / Enabled) 64 128 / 64 64 / 32 256 / 128 128 / 64 512 / 256 256 / 128 15.5.3. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the endpoint FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO. Figure 15.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers) R/W R/W R/W R/W R/W R/W R/W R/W FIFODATA Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x20 - 0x23 USB Addresses 0x20 - 0x23 provide access to the 4 pairs of endpoint FIFOs: IN/OUT Endpoint FIFO 0 1 2 3 USB Address 0x20 0x21 0x22 0x23 Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint. Reading from the FIFO address unloads data from the OUT FIFO for the corresponding endpoint. 152 Rev. 1.1 C8051F320/1 15.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The UPDATE bit (FADDR.7) is set to ‘1’ by hardware when software writes a new address to the FADDR register. Hardware clears the UPDATE bit when the new address takes effect as described above. Figure 15.10. FADDR: USB0 Function Address (USB Register) R R/W R/W R/W Bit6 Bit5 Bit4 Update Bit7 R/W R/W R/W R/W Reset Value Bit2 Bit1 Bit0 USB Address: Function Address Bit3 00000000 0x00 Bit7: Bits6-0: Update: Function Address Update Set to ‘1’ when software writes the FADDR register. USB0 clears this bit to ‘0’ when the new address takes effect. 0: The last address written to FADDR is in effect. 1: The last address written to FADDR is not yet in effect. Function Address Holds the 7-bit function address for USB0. This address should be written by software when the SET_ADDRESS standard device request is received on Endpoint0. The new address takes effect when the device request completes. Rev. 1.1 153 C8051F320/1 15.7. Function Configuration and Control The USB register POWER (Figure 15.11) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: 1. 2. 3. 4. 5. 6. The USB0 Address is reset (FADDR = 0x00). Endpoint FIFOs are flushed. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH). USB register INDEX is reset to 0x00. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared. A USB Reset interrupt is generated if enabled. Writing a ‘1’ to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to their default values following this asynchronous reset. Suspend Mode: With Suspend Detection enabled (SUSEN = ‘1’), USB0 will enter Suspend Mode when Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = ‘1’). The Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section “13. Oscillators” on page 117 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or generated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscillator will exit Suspend mode upon any of the above listed events. Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume interrupt will be generated upon detection if enabled (RESINTE = ‘1’). Software may force a Remote Wakeup by writing ‘1’ to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should write RESUME = ‘0’ to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME = ‘1’). ISO Update: When software writes ‘1’ to the ISOUP bit (POWER.7), the ISO Update function is enabled. With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will transmit a zero-length packet. When ISOUP = ‘1’, ISO Update is enabled for all ISO endpoints. USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the USBINH bit (POWER.4). Once written to ‘0’, the USBINH can only be set to ‘1’ by one of the following: (1) a Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing ‘1’ to the USBRST bit (POWER.3). Software should perform all USB0 configuration before enabling USB0. The configuration sequence should be performed as follows: Step 1. Step 2. Step 3. Step 4. Step 5. 154 Select and enable the USB clock source. Reset USB0 by writing USBRST= ‘1’. Configure and enable the USB Transceiver. Perform any USB0 function configuration (interrupts, Suspend detect). Enable USB0 by writing USBINH = ‘0’. Rev. 1.1 C8051F320/1 Figure 15.11. POWER: USB0 Power (USB Register) R/W R/W R/W R/W R/W R/W R R/W Reset Value ISOUD - - USBINH USBRST RESUME SUSMD SUSEN 00010000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x01 Bit7: Bits6-5: Bit4: Bit3: Bit2: Bit1: Bit0: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet when the next IN token is received. 1: When software writes INPRDY = ‘1’, USB0 will wait for a SOF token before sending the packet. If an IN token is received before a SOF token, USB0 will send a zero-length data packet. Unused. Read = 00b. Write = don’t care. USBINH: USB0 Inhibit This bit is set to ‘1’ following a power-on reset (POR) or an asynchronous USB0 reset (see Bit3: RESET). Software should clear this bit after all USB0 and transceiver initialization is complete. Software cannot set this bit to ‘1’. 0: USB0 enabled. 1: USB0 inhibited. All USB traffic is ignored. USBRST: Reset Detect Writing ‘1’ to this bit forces an asynchronous USB0 reset. Reading this bit provides bus reset status information. Read: 0: Reset signaling is not present on the bus. 1: Reset signaling detected on the bus. RESUME: Force Resume Software can force resume signaling on the bus to wake USB0 from suspend mode. Writing a ‘1’ to this bit while in Suspend mode (SUSMD = ‘1’) forces USB0 to generate Resume signaling on the bus (a remote Wakeup event). Software should write RESUME = ‘0’ after 10 ms to15 ms to end the Resume signaling. An interrupt is generated, and hardware clears SUSMD, when software writes RESUME = ‘0’. SUSMD: Suspend Mode Set to ‘1’ by hardware when USB0 enters suspend mode. Cleared by hardware when software writes RESUME = ‘0’ (following a remote wakeup) or reads the CMINT register after detection of Resume signaling on the bus. 0: USB0 not in suspend mode. 1: USB0 in suspend mode. SUSEN: Suspend Detection Enable 0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. Rev. 1.1 155 C8051F320/1 Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register) R R R R R R R R Frame Number Low Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x0C Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register) R R R R R - - - - - Bit7 Bit6 Bit5 Bit4 Bit3 R R R Reset Value Bit0 USB Address: Frame Number High Bit2 Bit1 00000000 0x0D Bits7-3: Bits2-0: 156 Unused. Read = 0. Write = don’t care. Frame Number High Byte This register contains bits10-8 of the last received frame number. Rev. 1.1 C8051F320/1 15.8. Interrupts The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.14 through Figure 15.16. The associated interrupt enable bits are located in the USB registers shown in Figure 15.17 through Figure 15.19. A USB0 interrupt is generated when any of the USB interrupt flags is set to ‘1’. The USB0 interrupt is enabled via the EIE1 SFR (see Section “9.3. Interrupt Handler” on page 87). Important Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’. Figure 15.14. IN1INT: USB0 IN Endpoint Interrupt (USB Register) R R R R R R R R Reset Value - - - - IN3 IN2 IN1 EP0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x02 Bits7-4: Bit3: Bit2: Bit1: Bit0: Unused. Read = 0000b. Write = don’t care. IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 3 interrupt inactive. 1: IN Endpoint 3 interrupt active. IN2: IN Endpoint 2 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 2 interrupt inactive. 1: IN Endpoint 2 interrupt active. IN1: IN Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 1 interrupt inactive. 1: IN Endpoint 1 interrupt active. EP0: Endpoint 0 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active. Rev. 1.1 157 C8051F320/1 Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register) R R R R R R R R Reset Value - - - - OUT3 OUT2 OUT1 - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x04 Bits7-4: Bit3: Bit2: Bit1: Bit0: 158 Unused. Read = 0000b. Write = don’t care. OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 3 interrupt inactive. 1: OUT Endpoint 3 interrupt active. OUT2: OUT Endpoint 2 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 2 interrupt inactive. 1: OUT Endpoint 2 interrupt active. OUT1: OUT Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 1 interrupt inactive. 1: OUT Endpoint 1 interrupt active. Unused. Read = 0; Write = don’t care. Rev. 1.1 C8051F320/1 Figure 15.16. CMINT: USB0 Common Interrupt (USB Register) R R R R R R R R Reset Value - - - - SOF RSTINT RSUINT SUSINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x06 Bits7-4: Bit3: Bit2: Bit1: Bit0: Unused. Read = 0000b; Write = don’t care. SOF: Start of Frame Interrupt Set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted. This bit is cleared when software reads the CMINT register. 0: SOF interrupt inactive. 1: SOF interrupt active. RSTINT: Reset Interrupt-pending Flag Set by hardware when Reset signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Reset interrupt inactive. 1: Reset interrupt active. RSUINT: Resume Interrupt-pending Flag Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend mode. This bit is cleared when software reads the CMINT register. 0: Resume interrupt inactive. 1: Resume interrupt active. SUSINT: Suspend Interrupt-pending Flag When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active. Rev. 1.1 159 C8051F320/1 Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - IN3E IN2E IN1E EP0E 00001111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x07 Bits7-4: Bit3: Bit2: Bit1: Bit0: Unused. Read = 0000b. Write = don’t care. IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled. 1: IN Endpoint 3 interrupt enabled. IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled. 1: IN Endpoint 2 interrupt enabled. IN1E: IN Endpoint 1 Interrupt Enable 0: IN Endpoint 1 interrupt disabled. 1: IN Endpoint 1 interrupt enabled. EP0E: Endpoint 0 Interrupt Enable 0: Endpoint 0 interrupt disabled. 1: Endpoint 0 interrupt enabled. Figure 15.18. OUT1IE: USB0 Out Endpoint Interrupt Enable (USB Register) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - OUT3E OUT2E OUT1E - 00001110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x09 Bits7-4: Bit3: Bit2: Bit1: Bit0: 160 Unused. Read = 0000b. Write = don’t care. OUT3E: OUT Endpoint 3 Interrupt Enable 0: OUT Endpoint 3 interrupt disabled. 1: OUT Endpoint 3 interrupt enabled. OUT2E: OUT Endpoint 2 Interrupt Enable 0: OUT Endpoint 2 interrupt disabled. 1: OUT Endpoint 2 interrupt enabled. OUT1E: OUT Endpoint 1 Interrupt Enable 0: OUT Endpoint 1 interrupt disabled. 1: OUT Endpoint 1 interrupt enabled. Unused. Read = 0; Write = don’t’ care. Rev. 1.1 C8051F320/1 Figure 15.19. CMIE: USB0 Common Interrupt Enable (USB Register) R/W R/W R/W R/W R/W - - - - SOFE Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value RSTINTE RSUINTE SUSINTE 00000110 Bit2 Bit1 Bit0 USB Address: 0x0B Bits7-4: Bit3: Bit2: Bit1: Bit0: 15.9. Unused. Read = 0000b; Write = don’t care. SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF interrupt enabled. RSTINTE: Reset Interrupt Enable 0: Reset interrupt disabled. 1: Reset interrupt enabled. RSUINTE: Resume Interrupt Enable 0: Resume interrupt disabled. 1: Resume interrupt enabled. SUSINTE: Suspend Interrupt Enable 0: Suspend interrupt disabled. 1: Suspend interrupt enabled. The Serial Interface Engine The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automatically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. The SIE will not interrupt the processor when corrupted/erroneous packets are received. 15.10. Endpoint0 Endpoint0 is managed through the USB register E0CSR (Figure 15.20). The INDEX register must be loaded with 0x00 to access the E0CSR register. An Endpoint0 interrupt is generated when: 1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY bit (E0CSR.0) is set to ‘1’ by hardware. 2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host; INPRDY is reset to ‘0’ by hardware. 3. An IN transaction is completed (this interrupt generated during the status stage of the transaction). 4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation. 5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). The E0CNT register (Figure 15.21) holds the number of received data bytes in the Endpoint0 FIFO. Rev. 1.1 161 C8051F320/1 Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’ and an interrupt generated. The following conditions will cause hardware to generate a STALL condition: 1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to ‘1’. 2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to ‘1’. 3. The host sends a packet that exceeds the maximum packet size for Endpoint0. 4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction. Firmware sets the SDSTL bit (E0CSR.5) to ‘1’. 15.10.1.Endpoint0 SETUP Transactions All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, containing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate that it has serviced the OUT packet. 15.10.2.Endpoint0 IN Transactions When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is transmitted successfully. Note that no interrupt will be generated if an IN request is received before firmware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. If the requested data is an integer multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet signaling the end of the transfer. Firmware should set the DATAEND bit to ‘1’ after loading into the Endpoint0 FIFO the last data packet for a transfer. Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to ‘1’ if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode. Endpoint0 will remain in Transmit Mode until any of the following occur: 1. 2. 3. USB0 receives an Endpoint0 SETUP or OUT token. Firmware sends a packet less than the maximum Endpoint0 packet size. Firmware sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when performing (2) and (3) above. The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY = ‘0’). 162 Rev. 1.1 C8051F320/1 15.10.3.Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘1’. If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to ‘1’ if a SETUP or IN token is received while Endpoint0 is in Receive Mode. Endpoint0 will remain in Receive mode until: 1. 2. 3. The SIE receives a SETUP or IN token. The host sends a packet less than the maximum Endpoint0 packet size. The host sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the STALL is transmitted. Rev. 1.1 163 C8051F320/1 Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) R/W R/W R/W R R/W R/W R/W R Reset Value SSUEND SOPRDY SDSTL SUEND DATAEND STSTL INPRDY OPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x11 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 164 SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND. Read: This bit always reads ‘0’. SOPRDY: Serviced OPRDY Write: Software should write ‘1’ to this bit after servicing a received Endpoint0 packet. The OPRDY bit will be cleared by a write of ‘1’ to SOPRDY. Read: This bit always reads ‘0’. SDSTL: Send Stall Software can write ‘1’ to this bit to terminate the current transfer (due to an error condition, unexpected transfer request, etc.). Hardware will clear this bit to ‘0’ when the STALL handshake is transmitted. SUEND: Setup End Hardware sets this read-only bit to ‘1’ when a control transaction ends before software has written ‘1’ to the DATAEND bit. Hardware clears this bit when software writes ‘1’ to SSUEND. DATAEND: Data End Software should write ‘1’ to this bit: 1. When writing ‘1’ to INPRDY for the last outgoing data packet. 2. When writing ‘1’ to INPRDY for a zero-length data packet. 3. When writing ‘1’ to SOPRDY after servicing the last incoming data packet. This bit is automatically cleared by hardware. STSTL: Sent Stall Hardware sets this bit to ‘1’ after transmitting a STALL handshake signal. This flag must be cleared by software. INPRDY: IN Packet Ready Software should write ‘1’ to this bit after loading a data packet into the Endpoint0 FIFO for transmit. Hardware clears this bit and generates an interrupt under either of the following conditions: 1. The packet is transmitted. 2. The packet is overwritten by an incoming SETUP packet. 3. The packet is overwritten by an incoming OUT packet. OPRDY: OUT Packet Ready Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This bit is cleared only when software writes ‘1’ to the SOPRDY bit. Rev. 1.1 C8051F320/1 Figure 15.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register) R R R R Bit7 R R R R E0CNT Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x16 Bit7: Bits6-0: Unused. Read = 0; Write = don’t care. E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’. Rev. 1.1 165 C8051F320/1 15.11. Configuring Endpoints1-3 Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/ status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX register (Figure 15.6). Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 15.5.1. The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH. When SPLIT = ‘1’, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available. When SPLIT = ‘0’, the corresponding endpoint functions as either IN or OUT; the endpoint direction is selected by the DIRSEL bit in register EINCSRH. 15.12. Controlling Endpoints1-3 IN Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 IN interrupt is generated by any of the following conditions: 1. 2. 3. An IN packet is successfully transferred to the host. Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty. Hardware generates a STALL condition. 15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode When the ISO bit (EINCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt Mode. Once an endpoint has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an interrupt. Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’. The STSTL bit must be reset to ‘0’ by firmware. Hardware will automatically reset INPRDY to ‘0’ when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. When firmware writes ‘1’ to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled continuously, regardless of the handshake received from the host. This feature is typically used by Interrupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = ‘0’, the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet. 166 Rev. 1.1 C8051F320/1 15.12.2.Endpoints1-3 IN Isochronous Mode When the ISO bit (EINCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per frame; the location of data within each frame may vary. Because of this, it is recommended that double buffering be enabled for ISO IN endpoints. Hardware will automatically reset INPRDY (EINCSRL.0) to ‘0’ when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host, USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to ‘1’. The ISO Update feature (see Section 15.7) can be useful in starting a double buffered ISO IN endpoint. If the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. Rev. 1.1 167 C8051F320/1 Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register) R W R/W R/W W R/W R/W R/W Reset Value - CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x11 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 168 Unused. Read = 0; Write = don’t care. CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’. Read: This bit always reads ‘0’. STSTL: Sent Stall Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. The FIFO is flushed, and the INPRDY bit cleared. This flag must be cleared by software. SDSTL: Send Stall. Software should write ‘1’ to this bit to generate a STALL handshake in response to an IN token. Software should write ‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode. FLUSH: FIFO Flush. Writing a ‘1’ to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains multiple packets, software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’ when the FIFO flush is complete. UNDRUN: Data Underrun. The function of this bit depends on the IN Endpoint mode: ISO: Set when a zero-length packet is sent after an IN token is received while bit INPRDY = ‘0’. Interrupt/Bulk: Set when a NAK is returned in response to an IN token. This bit must be cleared by software. FIFONE: FIFO Not Empty. 0: The IN Endpoint FIFO is empty. 1. The IN Endpoint FIFO contains one or more packets. INPRDY: In Packet Ready. Software should write ‘1’ to this bit after loading a data packet into the IN Endpoint FIFO. Hardware clears INPRDY due to any of the following: 1. A data packet is transmitted. 2. Double buffering is enabled (DBIEN = ‘1’) and there is an open FIFO packet slot. 3. If the endpoint is in Isochronous Mode (ISO = ‘1’) and ISOUD = ‘1’, INPRDY will read ‘0’ until the next SOF is received. An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a packet being transmitted. Rev. 1.1 C8051F320/1 Figure 15.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) R/W R/W R/W R R/W R/W R R Reset Value DBIEN ISO DIRSEL - FCDT SPLIT - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x12 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bits1-0: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. ISO: Isochronous Transfer Enable. This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. DIRSEL: Endpoint Direction Select. This bit is valid only when the selected FIFO is not split (SPLIT = ‘0’). 0: Endpoint direction selected as OUT. 1: Endpoint direction selected as IN. Unused. Read = ‘0’. Write = don’t care. FCDT: Force Data Toggle. 0: Endpoint data toggle switches only when an ACK is received following a data packet transmission. 1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of ACK reception. SPLIT: FIFO Split Enable. When SPLIT = ‘1’, the selected endpoint FIFO is split. The upper half of the selected FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint. Unused. Read = 00b; Write = don’t care. Rev. 1.1 169 C8051F320/1 15.13. Controlling Endpoints1-3 OUT Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 OUT interrupt may be generated by the following: 1. 2. Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’. Hardware generates a STALL condition. 15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode When the ISO bit (EOUTCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt mode. Once an endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL registers. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to ‘0’. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The STSTL bit must be reset to ‘0’ by firmware. Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time. In this case, hardware will set OPRDY to ‘1’ immediately after firmware unloads the first packet and resets OPRDY to ‘0’. A second interrupt will be generated in this case. 15.13.2.Endpoints1-3 OUT Isochronous Mode When the ISO bit (EOUTCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB frame; the location of the data packet within each frame may vary, however. Because of this, it is recommended that double buffering be enabled for ISO OUT endpoints. Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO, set the OPRDY bit (EOUTCSRL.0) to ‘1’, and generate an interrupt (if enabled). Firmware would typically use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to ‘0’. If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and the OVRUN bit (EOUTCSRL.2) set to ‘1’. If USB0 receives an ISO data packet with a CRC error, the data packet will be loaded into the endpoint FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be generated, and the DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO. 170 Rev. 1.1 C8051F320/1 Figure 15.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) W R/W R/W W R R/W R R/W Reset Value CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x14 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’. Read: This bit always reads ‘0’. STSTL: Sent Stall Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. This flag must be cleared by software. SDSTL: Send Stall Software should write ‘1’ to this bit to generate a STALL handshake. Software should write ‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode. FLUSH: FIFO Flush Writing a ‘1’ to this bit flushes the next packet to be read from the OUT endpoint FIFO. The FIFO pointer is reset and the OPRDY bit is cleared. If the FIFO contains multiple packets, software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’ when the FIFO flush is complete. DATERR: Data Error In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode. OVRUN: Data Overrun This bit is set by hardware when an incoming data packet cannot be loaded into the OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software. 0: No data overrun. 1: A data packet was lost because of a full FIFO since this flag was last cleared. FIFOFUL: OUT FIFO Full This bit indicates the contents of the OUT FIFO. If double buffering is enabled for the endpoint (DBIEN = ‘1’), the FIFO is full when the FIFO contains two packets. If DBIEN = ‘0’, the FIFO is full when the FIFO contains one packet. 0: OUT endpoint FIFO is not full. 1: OUT endpoint FIFO is full. OPRDY: OUT Packet Ready Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Software should clear this bit after each data packet is unloaded from the OUT endpoint FIFO. Rev. 1.1 171 C8051F320/1 Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) R/W R/W R/W R/W R R R R Reset Value DBOEN ISO - - - - - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x15 Bit7: Bit6: Bits5-0: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. ISO: Isochronous Transfer Enable This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. Unused. Read = 000000b; Write = don’t care. Figure 15.26. EOUTCNTL: USB0 OUT Endpoint Count Low (USB Register) R R R R R R R R EOCL Bit7 Bit6 Bit5 Bit4 Reset Value 00000000 Bit3 Bit2 Bit1 Bit0 USB Address: 0x16 Bits7-0: EOCL: OUT Endpoint Count Low Byte EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’. Figure 15.27. EOUTCNTH: USB0 OUT Endpoint Count High (USB Register) R R R R R R - - - - - - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R R Reset Value Bit0 USB Address: E0CH Bit1 00000000 0x17 Bits7-2: Bits1-0: 172 Unused. Read = 00000. Write = don’t care. EOCH: OUT Endpoint Count High Byte EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’. Rev. 1.1 C8051F320/1 Table 15.4. USB Transceiver Electrical Characteristics VDD = 3.0 to 3.6V, -40°C to +85°C unless otherwise specified PARAMETERS SYMBOL CONDITIONS MIN TYP TRANSMITTER VOH Output High Voltage 2.8 VOL Output Low Voltage VCRS 1.3 Output Crossover Point Driving High 38 ZDRV Output Impedance Driving Low 38 Full Speed (D+ Pull-up) RPU Pull-up Resistance 1.425 1.5 Low Speed (D- Pull-up) Low Speed 75 TR Output Rise Time Full Speed 4 Low Speed 75 TF Output Fall Time Full Speed 4 RECEIVER Differential Input VDI | (D+) - (D-) | 0.2 Sensitivity Differential Input ComVCM 0.8 mon Mode Range IL Input Leakage Current Pullups Disabled