CY28446
Clock Generator for Intel®Calistoga Chipset
Features
• 33 MHz PCI clocks
• Buffered 14.318 MHz reference clock
• Compliant to Intel® CK410M
• Low-voltage frequency select input
• Selectable CPU frequencies
• I2C support with readback capabilities
• Low power differential CPU clock pairs
• 100 MHz Low power differential SRC clocks
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 96 MHz Low power differential DOT clock
• 3.3V Power supply
• 48 MHz USB clock
• 64 pin QFN package
• SRC clocks stoppable through OE#
Table 1. Output Configuration Table
CPU
SRC
PCI
REF
DOT96
48M
x2/x3
x9/10
x5
x1
x1
x1
PCI3
PCI2
PCI1
PCI0
PCIF0/ITP_EN
VDD_PCI
VSS_PCI
VTTPWRGD#/PD
FS_C/TEST_SEL
USB_48/FS_A
VSS_PCI
VDD_48
DOTT_96
DOTC_96
FS_B/TEST_MODE
OE1#
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VSS_48
SRCT0
SRCC0
OE0#
SRCT1
SRCC1
OEA#
SRCT2
SRCC2
VDD_SRC
VSS_SRC
OE3#
SRCT3
SRCC3
OE6#
PCI_STOP#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CY28446
VDD_PCI
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
CPU_STOP#
CPUT0
CPUC0
VSS_CPU
VDD_CPU
CPUT1
CPUC1
VSS_SRC
....................... Document #: 001-00168 Rev *F Page 1 of 19
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VSS_SRC
VDD_SRC
SRCC10
SRCT10
SRCT9
SRCC9
OEB#
SRCC8
SRCT8
SRCT6
SRCC6
SRCC5
SRCT5
VDD_SRC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1+(512) 416-9669
www.silabs.com
CY28446
Table 2. Frequency Table
FS_C
FS_B
FS_A
CPU
SRC/SATA
PCIF/PCI
REF
LCD
DOT96
USB
MID
0
1
100
100
33
14.318
100
96
48
0
0
1
133
100
33
14.318
100
96
48
0
1
1
166
100
33
14.318
100
96
48
0
1
0
200
100
33
14.318
100
96
48
0
0
0
MID
0
0
MID
1
0
MID
1
1
Reserved
100
33
14.318
100
96
1
0
x
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
0
REF/2
REF/8
REF/24
REF
REF/8
REF
REF
1
1
1
REF/2
REF/8
REF/24
REF
REF/8
REF
REF
.......................Document #: 001-00168 Rev *F Page 2 of 19
48
CY28446
Pin Description
Pin No.
1
Name
VSS_48
2, 3, 5, 6, 8, SRC(0:3, 5:6, 8:10)
9, 13, 14, 18, [T/C]
19, 20, 21,
22, 23, 25,
26, 27, 28
Type
Description
GND Ground for outputs.
O, DIF 100 MHz Differential serial reference clocks
4, 7, 12, 15,
24, 64
OE[0, 1, 3, 6, A, B]#
I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW)
10, 17, 29,
VDD_SRC
PWR 3.3V power supply for outputs.
11, 30, 33
VSS_SRC
GND Ground for outputs.
16
PCI_STP#
I, PU 3.3V LVTTL input for PCI_STP#
Stops SRC and PCI clocks not set to free running in the SMBUS registers.
31, 32
CPU2_ITPT/SRCT7, O, DIF Selectable differential CPU clock/100 MHz Differential serial reference clock.
CPU2_ITPC/SRCC7
Selectable via Pin 53 PCIF0/ITP_EN
34, 35, 38, 39 CPUT/C[0:1]
O, DIF Differential CPU clock outputs.
36
VDD_CPU
PWR 3.3V power supply for outputs.
37
VSS_CPU
GND Ground for outputs.
40
CPU_STP#
I, PU 3.3V LVTTL input for CPU_STP# active LOW.
41
SCLK
I
42
SDATA
I/O,
OD
SMBus-compatible SCLOCK.
43
VDD_REF
PWR 3.3V power supply for outputs.
O, SE 14.318 MHz crystal output.
SMBus-compatible SDATA.
44
XOUT
45
XIN
46
VSS_REF
GND Ground for outputs.
47
REF
O,SE Fixed 14.318 MHz clock output.
48, 54
VDD_PCI
49, 50, 51, 52 PCI[0:3]
I
14.318 MHz crystal input.
PWR 3.3V power supply for outputs.
O, SE 33 MHz clock output
53
PCIF0/ITP_EN
I/O, PD 33 MHz clock output (not stoppable by PCI_STOP#)/3.3V LVTTL input for
selecting pins 31/32 (CPU2_ITP[T/C]/SRC7[T/C]) (sampled on the
VTT_PWRGD# assertion).
0 (default): SRC7[T/C]
1: CPU2_ITP[T/C]
55, 59
VSS_PCI
GND Ground for outputs.
56
VTT_PWRGD#/PD
I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and all I/O configuration pins,. After VTT_PWRGD# (active LOW) assertion,
this pin becomes a real-time input for asserting power-down (active HIGH).
57
FS_C/TEST_SEL
I, PD 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to
VIMFS_C when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications.
58
USB_48/FS_A
60
VDD_48
61,62
DOT_96[T/C]
63
FS_B/TEST_MODE
I/O, PU Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
PWR 3.3V power supply for outputs.
O, DIF Fixed 96 MHz clock output.
I, PU 3.3V-tolerant input for CPU frequency selection Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
.......................Document #: 001-00168 Rev *F Page 3 of 19
CY28446
Frequency Select Pins (FS_A, FS_B, and FS_C)
Apply the appropriate logic levels to FSA, FSB, and FSC
before CK-PWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CK-PWRGD
and indicates that VTT voltage is stable then FSA, FSB, and
FSC input values are sampled. This process employs a
one-shot functionality and once the CK-PWRGD sampled a
valid HIGH, all other FSA, FSB, FSC and CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up, making this interface
optional. Clock device register changes are made at system
initialization if required. The interface cannot be used during
system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest byte (most significant bit first) with
the ability to stop after complete byte has been transferred. For
byte write and byte read operations, the system controller
accesses individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in
Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'.
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Block Read Protocol
Bit
1
8:2
9
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
Acknowledge from slave
27:21
Slave address–7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
46
Acknowledge from slave
....
Data Byte/Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
.......................Document #: 001-00168 Rev *F Page 4 of 19
37:30
38
46:39
47
55:48
56
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
CY28446
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
Byte Read Protocol
Description
Bit
Start
1
Slave address–7 bits
8:2
Write
9
Acknowledge from slave
10
Command Code–8 bits
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
28
29
37:30
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
Control Registers
Byte 0: Control Register 0
Bit
7
@Pup
1
6
1
5
1
4
3
1
1
2
1
1
1
0
1
Name
Description
CPU2_ITP[T/C]/SRC7[T/C] CPU2_ITP[T/C]/SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
Reserved
Reserved
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
6
1
DOT_96[T/C]
5
1
USB_48
USB_48 Output Enable
0 = Disable, 1 = Enable
4
1
REF
REF Output Enable
0 = Disable, 1 = Enable
3
1
Reserved
Reserved
2
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
1
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
PCIF0 Output Enable
0 = Disable, 1 = Enable
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enable
.......................Document #: 001-00168 Rev *F Page 5 of 19
CY28446
Byte 1: Control Register 1
Bit
@Pup
0
0
Name
Description
CPU PLL Spread Enable PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off
1 = Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks)
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
Reserved
Reserved set to 1
6
1
Reserved
Reserved set to 1
5
1
PCI3
PCI3 Output Enable
0 = Disable, 1 = Enable
4
1
PCI2
PCI2 Output Enable
0 = Disable, 1 = Enable
3
1
PCI1
PCI1Output Enable
0 = Disable, 1 = Enable
2
1
PCI0
PCI0 Output Enable
0 = Disable, 1 = Enable
1
1
Reserved
Reserved set to 1
0
1
Reserved
Reserved set to 1
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
6
0
Reserved
5
0
SRC5
4
0
Reserved
3
0
Reserved
2
0
SRC2
1
0
Reserved
Reserved set to 0
0
0
Reserved
Reserved set to 0
Allow control of SRC[T/C]7 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
Reserved set to 0
Allow control of SRC[T/C]5 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
Reserved set to 0
Reserved set to 0
Allow control of SRC[T/C]2 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
Reserved
6
0
DOT96[T/C]
5
0
Reserved
4
1
Reserved
3
0
PCIF0
2
1
CPU[T/C]2
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
1
CPU[T/C]1
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU[T/C]0
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Reserved set to 1
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
Reserved set to 0
Reserved set to 1
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
.......................Document #: 001-00168 Rev *F Page 6 of 19
CY28446
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
Reserved
Reserved set to 0
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
5
0
CPU[T/C]1
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
4
0
CPU[T/C]0
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
3
0
SRC[T/C]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
7
0
Name
Description
6
0
Test Mode
Test Mode Control
1 = Ref/N or Tristate, 0 = Normal Operation
5
1
Reserved
Reserved set to 1
4
0
REF
3
1
2
HW
FS_C
FSC Reflects the value of the FS_C pin sampled on power-up
0 = FSC was low during VTT_PWRGD# assertion
1
HW
FS_B
FSB Reflects the value of the FS_B pin sampled on power-up
0 = FSB was low during VTT_PWRGD# assertion
0
HW
FS_A
FSA Reflects the value of the FS_A pin sampled on power-up
0 = FSA was low during VTT_PWRGD# assertion
REF/N or Tri-state Select REF/N or Tri-state Select
1 = REF/N, 0 = Tri-state
REF Output Drive Strength
0 = Low, 1 = High
SW PCI_STP Function
PCI and PCIF clock
outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs are
to free running
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs resumes in
a synchronous manner with no short pulses.
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
Revision Code Bit 3
6
0
Revision Code Bit 2
Revision Code Bit 2
5
1
Revision Code Bit 1
Revision Code Bit 1
4
1
Revision Code Bit 0
Revision Code Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
.......................Document #: 001-00168 Rev *F Page 7 of 19
CY28446
Byte 8: Control Register 7
Bit
@Pup
Name
Description
7
0
Reserved
6
1
SRC[T/C]10
SRC[T/C]10 Output Enable
0 = Disable (Tri-state), 1 = Enable
5
1
SRC[T/C]9
SRC[T/C]9 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
1
SRC[T/C]8
SRC[T/C]8 Output Enable
0 = Disable (Tri-state), 1 = Enable
3
0
Reserved
Reserved set to 0
2
0
SRC10
Allow control of SRC[T/C]10 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
1
0
SRC9
Allow control of SRC[T/C]9 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
0
0
SRC8
Allow control of SRC[T/C]8 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
Reserved set to 0
Byte 9: Control Register 8
Bit
@Pup
Name
7
0
PCI3
33-MHz Output drive strength
0 = Low, 1 = High
Description
6
0
PCI2
33-MHz Output drive strength
0 = Low, 1 = High
5
0
PCI1
33-MHz Output drive strength
0 = Low, 1 = High
4
0
PCI0
33-MHz Output drive strength
0 = Low, 1 = High
3
0
PCIF0
33-MHz Output drive strength
0 = Low, 1 = High
2
1
Reserved
Reserved set to 1
1
1
Reserved
Reserved set to 1
0
1
Reserved
Reserved set to 1
.
Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The CY28446 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the CY28446 to
operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
.......................Document #: 001-00168 Rev *F Page 8 of 19
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
CY28446
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Clock Chip
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
Ci2
Ci1
(lead frame, bond wires etc.)
Pin
3 to 6p
OE# Description
X2
X1
Cs1
Cs2
Trace
2.8 pF
XTAL
Ce1
Ce2
Trim
33 pF
OE# Assertion (OE# -> LOW)
Figure 2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
All differential stopped outputs resume normal operation in a
glitch-free manner. The maximum latency from the assertion
to active outputs is between 2 and 6 SRC clock periods (2
clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven HIGH within 10
ns of OE# deassertion to a voltage er than 200 mV.
OE# Deassertion (OE# -> HIGH)
Ce = 2 * CL – (Cs + Ci)
CLe
The OE# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by OE[A,B]# are determined by the settings in
register byte 3 and byte 8. OE[0,1,3,6]# controls SRC[0,1,3,6],
respectively. The OE# signal is a debounced signal and its
state must remain unchanged during two consecutive rising
edges of SRCC to be recognized as a valid assertion or
deassertion. (The assertion and deassertion of this signal is
absolutely asynchronous.)
)
The impact of deasserting the OE# pins is that all SRC outputs
that are set in the control registers to stoppable via deassertion
of OE# are stopped after their next transition. The final state
of all stopped SRC clocks is Low/low.
OE#
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. OE# Deassertion/Assertion Waveform
.......................Document #: 001-00168 Rev *F Page 9 of 19
CY28446
PD (Power down) Clarification
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power-up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internal to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the
system. When PD# is asserted LOW, all clocks need to be
driven to a LOW value and held before turning off the VCOs
and the crystal oscillator.
PD (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to ‘0’, the clock
output are held with “Diff clock” pin driven HIGH and “Diff
clock#” driven LOW. If the control register PD drive mode bit
corresponding to the output of interest is programmed to “1”,
then both the “Diff clock” and the “Diff clock#” are LOW.
Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166 and 200 MHz. If
PD mode has the initial power-on state, PD must be asserted
HIGH in less than 10 s after asserting Vtt_PwrGd#. The
96_100_SSC follows the DOT waveform selected for 96 MHz
and the SRC waveform in 100 MHz mode.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power-down will be driven HIGH in
less than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up. It should be noted that 96_100_SSC will
follow the DOT waveform is selected for 96 MHz and the SRC
waveform when in 100-MHz mode.
PD
C P U T , 133M H z
C P U C , 133M H z
S R C T 100M H z
S R C C 100M H z
U S B , 48M H z
D O T 96T
D O T 96C
P C I, 3 3 M H z
REF
Figure 4. Power down Assertion Timing Waveform
T stable
200 mV
Figure 6. CPU_STP# Deassertion Waveform
1.8 ms
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
CPU_STP#
CPUT
CPUC
Figure 8. CPU_STP# Assertion Waveform
..................... Document #: 001-00168 Rev *F Page 11 of 19
CY28446
PCI_STP# Assertion
PCI_STP# Deassertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transitions to a high level.
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
.....................Document #: 001-00168 Rev *F Page 12 of 19
CY28446
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
State 0
Clock State
W ait for
VTT_PW RGD#
State 1
State 2
Off
Clock Outputs
State 3
On
On
Off
Clock VCO
Device is not affected,
VTT_PW RGD# is ignored
Sample Sels
Figure 12. VTT_PWRGD# Timing Diagram
S2
S1
Delay
>0.25mS
VTT_PWRGD# = Low
Sample
Inputs straps
VDD_A = 2.0V
Wait for