S i 4 0 6 3/60
H I G H - P ERFORMANCE , L O W -C U R R E N T T RANSMITTER
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XOUT
1
20
19
18
17
16
NC 2
15 nSEL
NC 3
14 SDI
GND
PAD
TX 4
13 SDO
NC 5
12 SCLK
6
7
8
9
10
11 nIRQ
Patents pending
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Silicon Laboratories' Si406x devices are high-performance, low-current
transmitters covering the sub-GHz frequency bands from 142 to 1050 MHz.
The radios are part of the EZRadioPRO® family, which includes a complete
line of transmitters, receivers, and transceivers covering a wide range of
applications. All parts offer extremely low active and standby current
consumption. The Si406x includes optimal phase noise performance for
narrow band applications, such as FCC Part90 and 169 MHz wireless Mbus.
The Si4063 offers exceptional output power of up to +20 dBm with
outstanding TX efficiency. The high output power allows extended ranges and
highly robust communication links. The Si4060 active mode TX current
consumption of 18 mA at +10 dBm coupled with extremely low standby
current and fast wake times ensure extended battery life in the most
demanding applications. The Si4063 can achieve up to +27 dBm output
power with built-in ramping control of a low-cost external FET. The devices
are compliant with all worldwide regulatory standards: FCC, ETSI, and ARIB.
All devices are designed to be compliant with 802.15.4g and WMbus smart
metering standards.
SDN
XIN
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Electronic shelf labels
GND
Smart metering
Remote control
Home security and alarm
Telemetry
Garage and gate openers
GPIO1
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Description
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Pin Assignments
Applications
GPIO0
GPIO2
VDD
GPIO3
Power supply = 1.8 to 3.6 V
Highly configurable packet handler
TX 64 byte FIFO
Low BOM
Low battery detector
Temperature sensor
20-Pin QFN package
IEEE 802.15.4g compliant
FCC Part 90 Mask D, FCC part 15.247,
15,231, 15,249, ARIB T-108, T-96, T-67,
China regulatory
ETSI Class-I Operation
TXRamp
Frequency range = 142–1050 MHz
Modulation
(G)FSK, 4(G)FSK, (G)MSK
OOK
Max output power
+20 dBm (Si4063)
+13 dBm (Si4060)
PA support for +27 or +30 dBm
Ultra low current powerdown modes
30 nA shutdown, 50 nA standby
Data rate = 100 bps to 1 Mbps
Fast wake times
VDD
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Features
Rev 0.1 12/12
Copyright © 2012 by Silicon Laboratories
Si4063/60
Si4063/60
Functional Block Diagram
XIN XOUT
Loop
Filter
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GPIO3 GPIO2
PFD / CP
VCO
FBDIV
30 MHz XO
Frac-N Div
LO
Gen
TX DIV
Bootup
OSC
D
SDN
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PA
LDO
LBD
32K LP
OSC
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VDD
TXRAMP
VDD
GPIO0 GPIO1
Freq. Range
Max Output
Power
TX Current
Narrowband
Operation
Si4063
Major bands
142–1050 MHz
+20 dBm
169 MHz: 70 mA
915 MHz: 85 mA
Si4060
Major bands
142–1050 MHz
+13 dBm
+10 dBm: 18 mA
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Product
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Digital
Logic
POR
Rev 0.1
SPI Interface
Controller
ADC
Temp
sensor
PowerRamp
Cntl
PA
TX
MODEM
FIFO
Packet
Handler
nSEL
SDI
SDO
SCLK
nIRQ
Si4063/60
TABLE O F C ONTENTS
Section
Page
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1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2. Fast Response Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.3. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4. Application Programming Interface (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Modulation and Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Modulation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.2. Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.1. TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Auxiliary Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1. Wake-up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3. Temperature, Battery Voltage, and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Pin Descriptions: Si4063/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. Package Outline: Si4063/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11. PCB Land Pattern: Si4063/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
12.1. Si4063/60 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev 0.1
3
Si4063/60
1. Electrical Specifications
Table 1. DC Characteristics1
Symbol
Supply Voltage
Range
Test Condition
VDD
Power Saving Modes IShutdown
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
Min
Typ
Max
Unit
1.8
3.3
3.6
V
—
30
—
nA
—
50
—
nA
—
900
—
nA
—
1.7
—
µA
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Parameter
Register values maintained and RC
oscillator/WUT OFF
ISleepRC
RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF
ISleepXO
Sleep current using an external 32 kHz crystal.2
ISensor
Low battery detector ON, register values maintained,
and all other blocks OFF
—
1
—
µA
IReady
Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF
—
1.8
—
mA
TUNE Mode Current
ITune_TX
TX Tune, High Performance Mode
—
8
—
mA
TX Mode Current
(Si4063)
ITX_+20
+20 dBm output power, class-E match, 915 MHz,
3.3 V
—
85
—
mA
+20 dBm output power, class-E match, 460 MHz,
3.3 V
—
75
—
mA
+20 dBm output power, square-wave match,
169 MHz, 3.3 V
—
70
—
mA
+10 dBm output power, Class-E match, 868 MHz,
3.3 V2
—
18
—
mA
TX Mode Current
(Si4060)
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-LBD
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IStandby
ITX_+10
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Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 10.
2. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions” section in "1.1.
Definition of Test Conditions" on page 10.
4
Rev 0.1
Si4063/60
Table 2. Synthesizer AC Electrical Characteristics1
Symbol
Synthesizer Frequency
Range (Si4063/60)
Test Condition
FSYN
Min
Typ
Max
Unit
850
—
1050
MHz
420
284
142
Synthesizer Frequency
Resolution2
850–1050 MHz
—
FRES-525
420–525 MHz
—
FRES-350
283–350 MHz
FRES-175
Synthesizer Settling Time3
Phase Noise3
—
525
MHz
—
350
MHz
—
175
MHz
28.6
—
Hz
14.3
—
Hz
D
FRES-960
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Parameter
9.5
—
Hz
142–175 MHz
—
4.7
—
Hz
tLOCK
Measured from exiting Ready mode with
XOSC running to any frequency.
Including VCO Calibration.
—
50
—
µs
L(fM)
F = 10 kHz, 460 MHz, High Perf Mode
—
–106
—
dBc/Hz
F = 100 kHz, 460 MHz, High Perf Mode
—
–110
—
dBc/Hz
F = 1 MHz, 460 MHz, High Perf Mode
—
–123
—
dBc/Hz
F = 10 MHz, 460 MHz, High Perf Mode
—
–130
—
dBc/Hz
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production Test Conditions” section in "1.1. Definition of Test Conditions" on page 10.
2. Default API setting for modulation deviation resolution is double the typical value specified.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 10.
Rev 0.1
5
Si4063/60
Table 3. Transmitter AC Electrical Characteristics1
Symbol
Test Condition
Min
Typ
Max
Unit
850
—
1050
MHz
420
FTX
284
142
4(G)FSK Data Rate2,3
DR4FSK
OOK Data Rate2,3
DROOK
Output Power Range
(Si4063)5
Output Power Range
(Si4060)5
TX RF Output Steps2
MHz
—
350
MHz
—
175
MHz
—
500
kbps
0.2
—
1000
kbps
0.1
—
120
kbps
850–1050 MHz
—
1.5
—
MHz
f525
420–525 MHz
—
750
—
kHz
f350
283–350 MHz
—
500
—
kHz
f175
142–175 MHz
—
250
—
kHz
FRES-960
850–1050 MHz
—
28.6
—
Hz
FRES-525
420–525 MHz
—
14.3
—
Hz
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Modulation Deviation
Resolution2,4
525
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Modulation Deviation
Range2
0.1
—
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DRFSK
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Parameter
TX Frequency
Range (Si4063/60)
FRES-350
283–350 MHz
—
9.5
—
Hz
FRES-175
142–175 MHz
—
4.7
—
Hz
PTX
–20
—
+20
dBm
PTX60
–40
—
+13
dBm
Using switched current match within
6 dB of max power
—
0.1
—
dB
PRF_OUT
PRF_TEMP
–40 to +85 C
—
1
—
dB
TX RF Output Level
Variation vs. Frequency2
PRF_FREQ
Measured across 902–928 MHz
—
0.5
—
dB
B*T
Gaussian Filtering Bandwith Time
Product
—
0.5
—
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TX RF Output Level2
Variation vs. Temperature
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Transmit Modulation
Filtering2
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 10.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 10.
3. The maximum data rate is dependent on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
4. Default API setting for modulation deviation resolution is double the typical value specified.
5. Output power is dependent on matching components and board layout.
6
Rev 0.1
Si4063/60
Table 4. Auxiliary Block Specifications1
Min
Typ
Max
Unit
TSS
—
4.5
—
LBDRES
—
Temperature Sensor
Sensitivity2
Low Battery Detector
Resolution
Microcontroller Clock
Output Frequency Range3
FMC
Test Condition
Configurable to Fxtal or Fxtal
divided by 2, 3, 7.5, 10, 15, or
30 where Fxtal is the reference
XTAL frequency. In addition,
32.768 kHz is also supported.
Programmable setting
—
—
Fxtal
Hz
3
—
ms
25
—
—
250
32
—
MHz
µs
—
70
—
fF
—
—
2
2500
—
—
sec
ppm
—
—
5
ms
32.768K
—
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TEMPCT
Temperature Sensor
Conversion2
XTAL Range4
XTALRange
30 MHz XTAL Start-Up Time
t30M
Using XTAL and board layout in
reference design. Start-up time
will vary with XTAL type and
board layout.
30MRES
30 MHz XTAL Cap
Resolution2
32 kHz XTAL Start-Up Time2
t32k
32 kHz Accuracy using
32KRCRES
Internal RC Oscillator2
POR Reset Time
tPOR
50
ADC
Codes/
°C
mV
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Symbol
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Parameter
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 10.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 10.
3. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz and 32.768 kHz. Other frequencies tested in
bench characterization.
4. XTAL Range tested in production using an external clock source (similar to using a TCXO).
Rev 0.1
7
Si4063/60
Table 5. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)1
Rise Time
Fall Time3,4
Symbol
Test Condition
Min
Typ
Max
Unit
TRISE
0.1 x VDD to 0.9 x VDD,
CL = 10 pF,
DRV = HH
—
2.3
—
ns
TFALL
0.9 x VDD to 0.1 x VDD,
CL = 10 pF,
DRV = HH
—
CIN
—
Logic High Level Input Voltage
VIH
VDD x 0.7
Logic Low Level Input Voltage
VIL
—
Input Current
IIN
0 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be
smaller also.
Summary
D
Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10 µA need to be sunk into the chip, Vlo will be
10 µA x 10k = 100 mV.
Number
Command
0x2200
PA_MODE
0x2201
PA_PWR_LVL
0x2202
PA_BIAS_CLKDUTY
Adjust TX power in coarse steps
and optimizes for different
match configurations.
0x2203
PA_TC
Changes the ramp up/down time
of the PA.
Sets PA type.
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Adjust TX power in fine steps.
5.2.1. Si4063: +20 dBm PA
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The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz band
for output power steps, voltage, and temperature are shown in Figures 8–10. The output power is changed in 128
steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer
to the PA Matching application note.
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
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TX Power(dBm)
TX Power vs. PA_PWR_LVL
0
10
20
30
40
50
60
70
80
90 100 110 120
PA_PWR_LVL
Figure 8. +20 dBm TX Power vs. PA_PWR_LVL
Rev 0.1
23
Si4063/60
TX Power vs. VDD
20
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TX Power (dBm)
22
18
16
14
12
10
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
D
1.8
Supply Voltage (VDD)
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Figure 9. +20 dBm TX Power vs. VDD
TX Power vs Temp
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19.5
19
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TX Power (dBm)
20.5
18.5
18
-40 -30 -20 -10
0
10
20
30
40
50
60
Temperature (C)
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Figure 10. +20 dBm TX Power vs. Temp
24
Rev 0.1
70
80
Si4063/60
5.3. Crystal Oscillator
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The Si406x includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The design is
differential with the required crystal load capacitance integrated on-chip to minimize the number of external
components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is
designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API
boot command must be modified. The WDS calculator crystal frequency field must also be changed to reflect the
frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with
various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal
load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is
11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for
crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in
Figure 11.
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Figure 11. Capacitor Bank Frequency Offset Characteristics
R
Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
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A TCXO or external signal source can easily be used in place of a conventional XTAL and should be connected to
the XIN pin. The incoming clock signal is recommended to be peak-to-peak swing in the range of 600 mV to 1.4 V
and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds 1.4 V peak-to-peak, then dc
coupling to the XIN pin should be used. The maximum allowed swing on XIN is 1.8 V peak-to-peak.
The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the
POWER_UP command should be invoked with the TCXO option whenever external drive is used.
Rev 0.1
25
Si4063/60
6. Data Handling and Packet Handler
6.1. TX FIFOs
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One 64-byte FIFO is integrated into the chip for TX as shown in Figure 12. Writing to command Register 66h loads
data into the TX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the
“TX_FIFO_EMPTY” property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty
threshold. If more data is not loaded into the FIFO, the chip automatically exits the TX state after the
PACKET_SENT interrupt occurs. The TX FIFO may be cleared or reset with the “FIFO_RESET” command.
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TX FIFO
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TX FIFO Almost
Empty Threshold
Figure 12. TX FIFO
6.2. Packet Handler
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Config
0, 2, o r 4
Bytes
Con fig
0, 2, o r 4
Bytes
Con fig
0, 2, o r 4
B ytes
C RC Field 5 (op t)
Field 5 (opt)
Data
C RC Field 4 (op t)
Field 4 (opt)
Data
C RC Field 3 (op t)
Field 3 (opt)
Data
C RC Field 2 (op t)
Con fig
F ield 2 (o pt)
Pkt Len gth or Data
1-4 Bytes
C RC Field 1 (op t)
Field 1
Header or Data
1-255 Bytes
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Preamble
Sync Word
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When using the FIFOs, automatic packet handling may be enabled. The usual fields for network communication,
such as preamble, synchronization word, headers, packet length, and CRC, can be configured to be automatically
added to the data payload. The fields needed for packet generation normally change infrequently and can
therefore be stored in registers. Automatically adding these fields to the data payload in TX mode greatly reduces
the amount of communication between the microcontroller and Si406x. It also greatly reduces the required
computational power of the microcontroller. The general packet structure is shown in Figure 13. Any or all of the
fields can be enabled and checked by the internal packet handler.
Con fig
0, 2, or 4
Bytes
0, 2, or 4
Bytes
Figure 13. Packet Handler Structure
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The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The
general functions of the packet handler include the following:
Construction
of Preamble field in TX mode
Construction of Sync field in TX mode
Construction of Data Field from FIFO memory in TX mode
Construction of CRC field (if enabled) in TX mode
Data whitening and/or Manchester encoding (if enabled) in TX mode
26
Rev 0.1
Si4063/60
7. Auxiliary Blocks
7.1. Wake-up Timer and 32 kHz Clock Source
The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The
wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL.
D
WUT_R
42
WUT = WUT_M ----------------------------- ms
32 768
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ns
The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG
property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the
GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated
on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then
need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response
register. The formula for calculating the Wake-Up Period is as follows:
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The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator
is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the
recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration
period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the
32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration
needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD
results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL
parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging +
XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is
typically less than 10 ppm.
Rev 0.1
27
Si4063/60
Table 12. WUT Specific Commands and Properties
Description
Requirements/Notes
GLOBAL_WUT_CONFIG
GLOBAL WUT configuration
WUT_EN—Enable/disable wake up timer.
WUT_LBD_EN—Enable/disable low battery detect
measurement on WUT interval.
WUT_LDC_EN:
0 = Disable low duty cycle operation.
2 = TX LDC operation
treated as wakeup START_TX
WUT state is used
CAL_EN—Enable calibration of the 32 kHz RC
oscillator
WUT_CAL_PERIOD[2:0]—Sets calibration period.
GLOBAL_WUT_M_15_8
Sets HW WUT_M[15:8]
WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_ WUT_M_7_0
Sets HW WUT_M[7:0]
WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_WUT_R
Sets WUT_R[4:0]
Sets WUT_SLEEP to choose
WUT state
WUT_R—Parameter to set the actual wakeup time.
See equation above.
WUT_SLEEP:
0 = Go to ready state after WUT
1 = Go to sleep state after WUT
GLOBAL_WUT_LDC
Sets FW internal WUT_LDC
WUT_LDC—Parameter to set the actual wakeup
time.
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API Properties
Table 13. WUT Related API Commands and Properties
Command/Property
Description
Requirements/Notes
WUT Interrupt Enable
INT_CTL_ENABLE
ec
GLOBAL_CLK_CFG
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GPIO_PIN_CFG
START_TX
28
CHIP_INT_STATUS_EN—Enables chip status
interrupt.
Chip interrupt enable property WUT_EN—Enables WUT interrupt.
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INT_CTL_CHIP_ENABLE
Interrupt enable property
32 kHz Clock Source Selection
Clock configuration options
CLK_32K_SEL[2:0]—Configuring the source of
WUT.
WUT Interrupt Output
Host can enable interrupt on
WUT expire
GPIOx_MODE[5:0] = 14 and
NIRQ_MODE[5:0] = 39.
TX Operation
START TX when wake up timer
START = 1.
expire
Rev 0.1
Si4063/60
7.2. Low Duty Cycle Mode
WUT_R
42
LDC = WUT_LDC ----------------------------- ms
32 768
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The low duty cycle (LDC) mode is implemented to automatically wake-up the transmitter to send a packet. It allows
low average current polling operation by the Si406x for which the wake-up timer (WUT) is used. TX LDC operation
must be set via the GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is
determined by the following formula:
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where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in
conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer (WUT) section.
Figure 14. TX LDC Sequences
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In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a
packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After
transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time
expires.
Rev 0.1
29
Si4063/60
7.3. Temperature, Battery Voltage, and Auxiliary ADC
Command
Stream
GET_ADC_READING
Command
7
6
5
4
3
CMD
2
0
0
0
ADC_CFG
UDTIME[3:0]
CTS
7
6
5
4
3
2
1
GPIO_ADC[15:8]
GPIO_ADC[7:0]
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GPIO_ADC
BATTERY_ADC
BATTERY_ADC[15:8]
BATTERY_ADC
BATTERY_ADC[7:0]
TEMP_ADC
TEMP_ADC[15:8]
TEMP_ADC
TEMP_ADC[7:0]
RESERVED
Reserved
RESERVED
Reserved
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Parameters
ADC_GPIO_
PIN[1:0]
CTS[7:0]
GPIO_ADC
TEMPERATURE_EN
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0 = Do not perform ADC conversion of temperature. This will read 0 value in reply TEMPERATURE.
1 = Perform ADC conversion of temperature. This results in TEMP_ADC.
Temp (°C) = TEMP_ADC[15:0] x 568/2560 – 297
BATTERY_VOLTAGE_EN
0 = Don't do ADC conversion of battery voltage, will read 0 value in reply BATTERY_ADC
1 = Do ADC conversion of battery voltage, results in BATTERY_ADC. Vbatt = 3*BATTERY_ADC/1280
ADC_GPIO_EN
0 = Don't do ADC conversion on GPIO, will read 0 value in reply
1 = Do ADC conversion of GPIO, results in GPIO_ADC. Vgpio = GPIO_ADC/GPIO_ADC_DIV where
GPIO_ADC_DIV is defined by GPIO_ATT selection.
ADC_GPIO_PIN[1:0] - Select GPIOx pin. The pin must be set as input.
0 = Measure voltage of GPIO0
1 = Measure voltage of GPIO1
2 = Measure voltage of GPIO2
30
0
GPIO_ATT[3:0]
Stream
GET_ADC_READING Reply
ADC_GPIO_
EN
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Reply
TEMPERATURE_EN BATTERY_VOLTAGE_EN
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ADC_EN
1
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The Si406x family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal
temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves
11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input
voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first
sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or
temp. The temperature sensor accuracy at 25 °C is typically ±2 °C.
Rev 0.1
0
Si4063/60
3 = Measure voltage of GPIO3
- ADC conversion Time = SYS_CLK / 12 / 2^(UDTIME + 1). Defaults to 0xC if ADC_CFG is 0.
Selecting shorter conversion times will result in lower ADC resolution and longer times will result in higher ADC
resolution.
GPIO_ATT[3:0] - Sets attenuation of gpio input voltage when vgpio measured. Defaults to 0xC if ADC_CFG is 0.
0x0 = ADC range 0 to 0.8V. GPIO_ADC_DIV = 2560
0x4 = ADC range 0 to 1.6V. GPIO_ADC_DIV = 1280
0x8 = ADC range 0 to 2.4V. GPIO_ADC_DIV = 853.33
0x9 = ADC range 0 to 3.6V. GPIO_ADC_DIV = 426.66
0xC = ADC range 0 to 3.2V. GPIO_ADC_DIV = 640
GPIO_ADC[15:0]
- ADC value of voltage on GPIO
- ADC value of battery voltage
TEMP_ADC[15:0] - ADC value of temperature sensor voltage
RESERVED[7:0] - RESERVED FOR FUTURE USE
RESERVED[7:0] - RESERVED FOR FUTURE USE
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UDTIME[7:4]
7.4. Low Battery Detector
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The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not
available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the
auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will
be compared against the threshold each time the WUT expires. The threshold for the LBD function is set in
GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of
1.5 V up to 3.05 V. The accuracy of the LBD is ±3%. The LBD notification can be configured as an interrupt on the
nIRQ pin or enabled as a direct function on one of the GPIOs.
Rev 0.1
31
Si4063/60
XOUT
XIN
GND
20 19 18 17 16
NC 2
15 nSEL
NC 3
14 SDI
GND
PAD
TX 4
13 SDO
7
8
9
TXRamp
VDD
GPIO0
10 11 nIRQ
GPIO1
6
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Pin Name
12 SCLK
VDD
NC 5
Pin
I/0
SDN
I
2
NC
3
NC
4
TX
5
NC
6
VDD
7
TXRAMP
O
8
VDD
VDD
Description
Shutdown Input Pin.
0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.
When SDN = 1, the chip will be completely shut down, and the contents of the
registers will be lost. Can be used to reset the chip
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1
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SDN
GPIO2
GPIO3
8. Pin Descriptions: Si4063/60
Transmit Output Pin.
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11
32
GPIO1
The PA output is an open-drain connection, so the L-C match must supply
VDD (+3.3 VDC nominal) to this pin.
No Connect. Not connected internally to any circuitry.
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GPIO0
R
9
O
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
The recommended VDD supply voltage is +3.3 V.
Programmable Bias Output with Ramp Capability for External FET PA.
See "5.2. Transmitter (TX)" on page 22.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
The recommended VDD supply voltage is +3.3 V.
I/O
General Purpose Digital I/O.
I/O
May be configured through the registers to perform various functions including:
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, etc.
General Microcontroller Interrupt Status Output.
nIRQ
O
When the Si406x exhibits any one of the interrupt events, the nIRQ pin will be
set low = 0. The Microcontroller can then determine the state of the interrupt
by reading the interrupt status. No external resistor pull-up is required, but it
may be desirable if multiple interrupt lines are connected.
Rev 0.1
Si4063/60
Pin
Pin Name
I/0
Description
Serial Clock Input.
I
13
SDO
O
0–VDD V digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the Si406x on positive edge transitions.
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SCLK
0–VDD V Digital Output.
Provides a serial readback function of the internal control registers.
Serial Data Input.
14
SDI
I
0–VDD V digital input. This pin provides the serial data stream for the 4-line
serial data bus.
Serial Interface Select Input.
nSEL
I
0–VDD V digital input. This pin provides the Select/Enable function for the
4-line serial data bus.
Crystal Oscillator Output.
O
17
XIN
I
18
GND
GND
19
GPIO2
20
GPIO3
PADDLE_GND
Crystal Oscillator Input.
Connect to an external 25 to 32 MHz crystal, or connect to an external source.
Connect to PCB ground.
I/O
General Purpose Digital I/O.
I/O
May be configured through the registers to perform various functions, including
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect.
GND
The exposed metal paddle on the bottom of the Si406x supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the
PCB underlying the Si406x.
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PKG
Connect to an external 25 to 32 MHz crystal, or leave floating when driving
with an external source on XIN.
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12
Rev 0.1
33
Si4063/60
9. Ordering Information
Package Type
Si4063-Bxx-FM
ISM EZRadioPRO Transmitter
QFN-20
Pb-free
–40 to 85 °C
Si4060-Bxx-FM
ISM EZRadioPRO Transmitter
QFN-20
Pb-free
–40 to 85 °C
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Notes:
1. Add an “(R)” at the end of the device part number to denote tape and reel option.
2. For Bxx, the first “x” indicates the ROM version, and the second “x” indicates the FW version in OTP.
34
Operating
Temperature
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Description
Part Number1,2
Rev 0.1
Si4063/60
10. Package Outline: Si4063/60
2X
bbb C
A
D
B
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Figure 15 illustrates the package details for the Si406x. Table 14 lists the values for the dimensions shown in the
illustration.
D2
Pin 1 (Laser)
e
20
2X
aaa C
A1
ccc C
20x L
20x b
ddd
C A B
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E
E2
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1
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A3
C
A
SEATING PLANE
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Figure 15. 20-Pin Quad Flat No-Lead (QFN)
Rev 0.1
35
Si4063/60
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
A3
0.18
0.25
D
D2
4.00 BSC
2.45
2.60
e
0.50 BSC
E
4.00 BSC
2.45
2.60
L
0.30
0.40
2.75
2.75
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E2
0.15
bbb
0.15
ccc
0.10
ddd
0.10
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aaa
eee
0.30
D
b
0.20 REF
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Table 14. Package Dimensions
0.50
0.08
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Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
Variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
36
Rev 0.1
Si4063/60
11. PCB Land Pattern: Si4063/60
Figure 16. PCB Land Pattern
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Figure 16 illustrates the PCB land pattern details for the Si406x. Table 15 lists the values for the dimensions shown
in the illustration.
Rev 0.1
37
Si4063/60
Table 15. PCB Land Pattern Dimensions
Millimeters
Min
Max
C1
3.90
4.00
C2
3.90
4.00
E
0.50 REF
0.20
0.30
X2
2.55
2.65
Y1
0.65
0.75
Y2
2.55
2.65
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X1
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Symbol
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Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for the
perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
38
Rev 0.1
Si4063/60
12. Top Marking
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12.1. Si4063/60 Top Marking
12.2. Top Marking Explanation
YAG Laser
Line 1 Marking
Part Number
40631B = Si4063 Rev 1B1
40601B = Si4060 Rev 1B1
Line 2 Marking
TTTTT = Internal Code
Internal tracking code.2
Line 3 Marking
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
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Mark Method
Notes:
1. The first letter after the part number is part of the ROM revision. The last letter indicates the firmware
revision.
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2. The first letter of this line is part of the ROM revision.
Rev 0.1
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One-click access to MCU tools,
documentation, software, source
code libraries & more. Available
for Windows, Mac and Linux!
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MCU Portfolio
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Simplicity Studio
SW/HW
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Quality
www.silabs.com/quality
Support and Community
community.silabs.com
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
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