Si4322
Si4322 U NIVERSAL ISM B AND F S K R ECEIVER
Features
Fully integrated
(low BOM, easy design-in)
No alignment required in production
Fast settling, programmable, high-
resolution PLL
Fast frequency hopping capability
High bit rate (up to 115.2 kbps in
digital mode and 256 kbps in analog
mode)
Direct differential antenna input
Programmable baseband
bandwidth (135 to 400 kHz)
Analog and digital RSSI
Automatic frequency control (AFC)
Data quality detection (DQD)
Internal data filtering and clock
recovery
RX pattern recognition
SPI compatible serial control
interface
Clock and reset signals for
microcontroller
64-bit RX data FIFO
Autonomous low duty-cycle
mode down to 0.006%
Standard 10 MHz crystal
reference
Wake-up timer
Low battery detector
2.2 to 3.8 V supply voltage
Low power consumption
Low standby current
(typical 0.3 µA)
Pin Assignments
SDI
1
16
VDI
SCK
2
15
ARSSI
nSEL
3
14
VDD
SDO/FFIT
4
13
IN1
nIRQ
5
12
IN2
DATA/nFFS
6
11
VSS
DCLK/FFIT/CFIL
7
10
nRES
CLK
8
9
XTL/REF
Si4322
Patents pending
This data sheet refers to version A1
Applications
Remote control
Home security and alarm
Wireless keyboard/mouse and other
PC peripherals
Toy control
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
Description
Silicon Labs’ Si4322 is a single chip, low power, multi-channel FSK receiver
designed for use in applications requiring FCC or ETSI conformance for
unlicensed use in the 433, 868, and 915 MHz bands. Used in conjunction with
Silicon Labs' FSK transmitters, the Si4322 is a flexible, low cost, and highly
integrated solution that does not require production alignments. All required RF
functions are integrated. Only an external crystal and bypass filtering capacitors
are needed for operation.
The Si4322 is a complete analog RF and baseband receiver including a multiband PLL synthesizer with an LNA, I/Q down converter mixers, baseband filters
and amplifiers, and I/Q demodulator. The receiver employs zero-IF approach with
I/Q demodulation, therefore no external components (except crystal and
decoupling) are needed in a typical application. The Si4322 has a completely
integrated PLL for easy RF design, and its rapid settling time allows for fast
frequency hopping, bypassing multipath fading, and interference to achieve robust
wireless links. The PLL's high resolution allows the usage of multiple channels in
any of the bands. The baseband bandwidth (BW) is programmable to
accommodate various deviation, data rate, and crystal tolerance requirements.
The chip dramatically reduces the load on the microcontroller with integrated
digital data processing: data filtering, clock recovery, data pattern recognition and
integrated FIFO. The automatic frequency control (AFC) feature allows using a
low accuracy (low cost) crystal. To minimize the system cost, the chip can provide
a clock signal for the microcontroller, avoiding the need for two crystals.
Rev. 1.2 3/09
Copyright © 2009 by Silicon Laboratories
Si4322
Si4322
Functional Block Diagram
MIX
I
AMP
OC
7 DCLK
clk
IN1 13
I/Q
Demod.
Self cal.
LNA
IN2 12
MIX
Q
AMP
Data Filt
CLK Rec
data
OC
FIFO
RSSI
PLL & I/Q VCO
with cal.
RF Parts
CLK div
COMP
DQD
AFC
BB Amp/Filt./Limiter
Xosc
WTM
with cal.
Data processing units
LBD
Controller
Bias
2
3
4
5
16
10
1
SDI SCK nSEL SDO nIRQ VDI nRES
VSS VDD
Low Power parts
8
CLK
2
9
XTL/REF
15
ARSSI
Rev. 1.2
11
14
6 DATA
Si4322
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Recommended Supply Decoupling Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . .9
3. Internal Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Baseband Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4. Data Filtering and Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.5. Data Validity Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6. Crystal Oscillator and Microcontroller Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7. Low Battery Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.8. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.9. Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.10. Interface and Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1. Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2. Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3. Configuration Setting Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4. Frequency Setting Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.5. Receiver Setting Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6. Synchron Pattern Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7. Wake-Up Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8. Extended Wake-Up Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9. Low Duty Cycle Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.10. Low Battery Detector and Microcontroller Clock Divider Command . . . . . . . . . . . . 21
5.11. AFC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.12. Data Filter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.13. Data Rate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.14. FIFO Settings Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.15. Extended Features Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.16. Status Register Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7. FIFO Buffered Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1. Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7.2. Interrupt Controlled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3. FIFO Read Example with FFIT Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8. Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
9. Dual Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10. Wake-Up Timer Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11. RX-TX Alignment Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Rev. 1.2
3
Si4322
12. Crystal Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12.1. Maximum Crystal Tolerances Including Temperature and Aging [ppm] . . . . . . . . . 32
13. Reset modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13.1. Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13.2. Power Glitch Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
14. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
15. Reference Design: Evaluation Board with 50 Matching Network . . . . . . . . . . . . . . 38
16. PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
17. Pin Descriptions—Si4322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
18. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4
Rev. 1.2
Si4322
1. Electrical Specifications
Table 1. DC Characteristics
(Test conditions: TOP = 25 °C; VDD = 2.7 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
—
12
14
mA
—
0.3
—
µA
—
—
5
µA
0.5
—
mA
3.5
V
Supply Current
Idd
Standby Current
Ipd
Low Battery Voltage Detector
and Wake-Up Timer Current1
Ilb
Idle Current
Ix
crystal oscillator is on1
—
Low Battery Detection Threshold
Vlb
programmable in 0.1 V
steps
2.0
Low Battery Detection Accuracy
Vlba
—
±2.5
—
%
VPOR
—
1.5
—
V
Vdd Threshold Required to
Generate a POR
all blocks disabled
POR Hysteresis
VPORhyst
larger glitches on the Vdd
generate a POR even above
the threshold VPOR2
—
—
0.6
V
VDD Slew Rate
SRVdd
for proper POR generation
0.1
—
—
V/ms
Digital Input Low Level
Vil
—
—
0.3 x VDD
V
Digital Input High Level
Vih
0.7 x VDD
—
—
V
Digital Input Current
Iil
VIL = 0 V
–1
—
1
µA
Digital Input Current
Iih
VIH = VDD, VDD = 3.8 V
–1
—
1
µA
Digital Output Low Level
Vol
IOL = 2 mA
—
0.4
V
Digital Output High Level
Voh
Ioh = –2 mA
—
—
V
VDD – 0.4
Notes:
1. Measured with disabled clock output buffer.
2. For detailed information see "13. Reset modes" on page 34.
Rev. 1.2
5
Si4322
Table 2. AC Characteristics
(Test conditions: TOP = 25 °C; VDD = 2.7 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
—
—
—
439.03
878.06
958.06
MHz
Receiver Frequency
fLO
Receiver Bandwidth
BW
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
120
180
240
300
360
135
200
270
350
400
150
225
300
375
450
kHz
FSK Bit Rate
BR
With internal digital filters
—
—
115.2
kbps
FSK Bit Rate
BRA
With analog filter
—
256
kbps
Receiver Sensitivity
Pmin
BER 10–3, BW = 135 kHz,
BR = 1.2 kbps, fFSK = 60 kHz
—
–109
—
dBm
AFC Locking Range
AFCrange
fFSK: FSK deviation in the
received signal
—
0.8 x fFSK
—
Input IP3
IIP3inh
In band interferers
—
–21
—
dBm
Input IP3
IIP3outh
Out of band interferers: f – fLO >
4 MHz
—
–18
—
dBm
CCR
BER = 10–2 with continuous wave
interferer in the channel
—
–4
—
dB
BR2MHz
BER = 10–2, BW = 135 kHz,
BR = 9.6 kbps, fFSK = 60 kHz,
interferer offset 2 MHz
—
54
—
dB
BR10MHz
Same as above,
interferer offset 10 MHz
—
59
—
dB
Maximum Input Power
Pmax
LNA: maximum gain
0
—
—
dBm
RF Input Impedance
Real Part (differential)1
Rin
LNA gain (0, –12 dB)
LNA gain (–6, –18 dB)
—
—
250
500
—
—
RF Input Capacitance
(differential)1
Cin
—
1
—
pF
RSSI Accuracy
RSa
—
±5
—
dB
RSSI Range
RSr
—
46
—
dB
Co-Channel Rejection
Blocking Ratio
with CW Interferer
433 MHz band, 10 kHz resolution 400.96
868 MHz band, 20 kHz resolution 801.92
915 MHz band, 20 kHz resolution 881.92
Notes:
1. See matching circuit parameters and antenna design guide for information, and Application Notes available from
http://www.silabs.com.
2. Using other than a 10 MHz crystal is not recommended because the crystal referred timing and frequency parameters
will change accordingly.
3. During the Power-On Reset period, commands are not accepted by the chip. In case of software reset, (see "13.
Reset modes" on page 34) the reset timeout is 0.25 ms typical.
4. The crystal oscillator start up time strongly depends on the capacitance seen by the oscillator. Low capacitance and
low ESR crystal is recommended with low parasitic PCB layout design.
5. Auto-calibration can be turned off.
6
Rev. 1.2
Si4322
Table 2. AC Characteristics (Continued)
(Test conditions: TOP = 25 °C; VDD = 2.7 V)
Parameter
Symbol
Filter Capacitance for
ARSSI
DRSSI Programmable
Level Steps
DRSSI Response Time
Min
Typ
Max
Units
CARSSI
1
—
—
nF
RSstep
—
6
—
dB
Until the DRSSI goes high
after the input signal exceeds the
pre-programmed limit,
CARRSI = 5 nF
Note 2
—
500
—
μs
9
10
11
MHz
Frequency error < 1 kHz
after 1 MHz step
Initial calibration after power-up
with running crystal oscillator
Recalibration after receiver chain
enable with running crystal
oscillator
Programmable in 0.5 pF steps,
tolerance ±10%
—
30
—
μs
—
—
500
μs
—
—
60
μs
8.5
—
16
pF
—
50
100
ms
tsx
After VDD has reached 90% of
final value
Crystal ESR < 50 , CL = 16pF4
—
—
5
ms
tPBt
Calibrated every 30 seconds5
0.995
1
1.005
ms
twake-up
1
—
8.4 x 106
ms
CinD
—
—
2
pF
RSresp
PLL Reference Frequency
PLL Lock Time
tlock
PLL Startup Time
tst1P
PLL Startup Time
tst2P
Crystal Load Capacitance, see Crystal
Selection Guide
Internal POR Pulse
Width3
Crystal Oscillator
Startup Time
Wake-Up Timer Clock
Period
Programmable WakeUp Time
Digital Input
Capacitance
Digital Output Rise/Fall
Time
Clock Output Rise/Fall
Time
Cxl
Slow Clock Frequency
fref
tPOR
Condition
tr, tf
15 pF pure capacitive load
—
—
10
ns
trckout,
tfckout
10 pF pure capacitive load
—
—
15
ns
fckoutslow
Tolerance ± 1 kHz
—
32
—
kHz
Notes:
1. See matching circuit parameters and antenna design guide for information, and Application Notes available from
http://www.silabs.com.
2. Using other than a 10 MHz crystal is not recommended because the crystal referred timing and frequency parameters
will change accordingly.
3. During the Power-On Reset period, commands are not accepted by the chip. In case of software reset, (see "13.
Reset modes" on page 34) the reset timeout is 0.25 ms typical.
4. The crystal oscillator start up time strongly depends on the capacitance seen by the oscillator. Low capacitance and
low ESR crystal is recommended with low parasitic PCB layout design.
5. Auto-calibration can be turned off.
Rev. 1.2
7
Si4322
Table 3. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Positive Supply Voltage
VDD
2.2
—
3.8
V
Ambient Operating Temperature
TOP
–40
—
+85
Symbol
Min
Max
Units
Positive Supply Voltage
VDD
–0.5
6.0
V
Voltage on Any Pin
VIN
–0.5
Vdd+0.5
V
Input Current into Any Pin Except VDD and VSS
IIN
–25
25
mA
Electrostatic Discharge with Human Body Model
ESD
—
1000
V
o
C
Table 4. Absolute Maximum Ratings
Parameter
Storage Temperature
TST
–55
125
oC
Lead Temperature (soldering, max 10 s)
TLD
—
260
oC
8
Rev. 1.2
Si4322
2. Typical Application Schematic
VDD
µC
nRESET
P0
P1
P2
P3
P4
P5
P6
P7
CLK
VDI (optional)
1
SDI
SCK 2
nSEL 3
SDO 4
nIRQ 5
nFFS 6
FFIT 7
8
Si4322
*
*
VDD
C4
2.2 nF (opt.)
16
15
14
13
12
11
C1
C2
C3
PCB Antenna
or matching
network to
50 Ohm
10
9
1-10 MHz or 32.768 kHz
CLK (optional)
X1
10 MHz
nRES (optional)
connections to
* : Optional
support fast data transfer .
Can be left open if not used .
2.1. Recommended Supply Decoupling Capacitor Values
C2 and C3 should be 0603 size ceramic capacitors to achieve the best supply decoupling.
Band [MHz]
C1
C2
C3
433
2.2 µF
10 nF
220 pF
868
2.2 µF
10 nF
47 pF
915
2.2 µF
10 nF
33 pF
Property
C1
C2
C3
SMD size
A
0603
0603
Dielectric
Tantalum
Ceramic
Ceramic
Table 5. Pin Function vs. Operation Mode
Bit setting
fe
Function
Pin 6
Pin 7
0
Receiver FIFO disabled
RX data output
RX data clock output
1
Receiver FIFO enabled
nFFS input
(RX data FIFO can be accessed)
FFIT output
Note: The fe bit can be found in the "5.14. FIFO Settings Command" on page 25.
Rev. 1.2
9
Si4322
3. Internal Pin Connections
Pin Name
1
SDI
2
SCK
3
nSEL
Internal Connection
Pin Name
Internal Connection
VDD
VDD
XTL
PAD
9
1.5k
PAD
200
200
REF
VSS
VSS
VDD
VDD
SDO
4
100k
10
PAD
nIRQ
PAD
N
VSS
VSS
VDD
VDD
PAD
11
10
VSS
PAD
VSS
VSS
VDD
VDD
DATA
120k
6
PAD
EN
12
IN2
13
IN1
10
nFFS
PAD
VSS
FFIT
VDD
VDD
DCLK
7
10
EN
FFIT
5
nRES
10
PAD
14
10
VDD
PAD
EN
CFIL
VSS
VSS
VDD
8
CLK
PAD
VDD
15
10
ARSSI
PAD
VSS
200
VSS
VDD
2.2M
16
VDI
PAD
10
VSS
10
Rev. 1.2
EN
Si4322
4. Functional Description
The Si4322 FSK receiver is the counterpart of Silicon Labs’ Si4022 FSK transmitter. It covers the unlicensed
frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements.
The receiver employs zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external
components in a typical application. The Si4322 consists of a fully integrated multi-band PLL synthesizer, an LNA
with switchable gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed
by a data filter.
4.1. PLL
The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the
on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows for the use of multiple channels in
any of the bands.
4.2. LNA
The LNA has 250 input impedance, which suits to the recommended antennas. (See Application Notes available
from www.silabs.com.)
If the RF input of the chip is connected to 50 devices, an external matching circuit is required to provide the
correct matching and to minimize the noise figure of the receiver.
The LNA gain can be selected (0, –6, –12, –18 dB relative to the highest gain) according to RF signal strength.
This is useful in an environment with strong interferers.
4.3. Baseband Filters
The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. An appropriate
bandwidth can be selected to accommodate various FSK deviation, data rate, and crystal tolerance requirements.
The filter structure is a 7th order Butterworth low-pass with 40 dB suppression at 2 x BW frequency. Offset
cancellation is accomplished by using a high-pass filter with a cut-off frequency below 15 kHz.
Figure 1. Full Baseband Amplifier Transfer Function, BW = 135 kHz
4.4. Data Filtering and Clock Recovery
The output data filtering can be completed by an external capacitor or by using digital filtering according to the final
application.
Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The resistor (10k) and
the Schmitt-trigger (St) are integrated on the chip. The filter capacitor should be connected externally, its value
should be chosen according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate.
When the analog filter is selected, the FIFO cannot be used and clock is not provided for the demodulated data.
Rev. 1.2
11
Si4322
Digital operation: The data filter is a digital realization of an analog RC filter followed by a comparator with
hysteresis. In this mode, there is a clock recovery circuit (CR), which can provide synchronized clock to the data.
With this clock, the received data can fill the RX Data FIFO. The CR has three operation modes: fast, slow, and
automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate
data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow modes. The
CR starts in fast mode, and then automatically switches to slow mode after locking.
Only the data filter and the clock recovery use the bit rate clock. Therefore, in analog mode, there is no need for
setting the correct bit rate.
4.5. Data Validity Blocks
4.5.1. RSSI
ARSSI voltage [mV]
A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength
exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on
the filter capacitor used.
1150
450
-100
Input Power [dBm]
-65
Figure 2. Typical Analog ARSSI Voltage vs. RF Input Power
4.5.2. DQD
The Data Quality Detector monitors the I/Q output of the baseband amplifier chain by counting the consecutive
01 and 10 transitions during a single bit period. The programmable DQD parameter defines a threshold for this
counter. If the counter result exceeds this parameter, then DQD output indicates good FSK signal quality. Using
this method, it is possible to "forecast” the probability of BER degradation. In cases when the deviation is close to
the bit rate, there should be four transitions during a single one-bit period in the I/Q signals. As the bit rate
decreases in comparison to the deviation, more and more transitions will happen during a bit period.
4.5.3. AFC
By using an integrated Automatic Frequency Control (AFC) feature, the receiver can synchronize its local oscillator
to the received signal, allowing the use of the following:
inexpensive, low accuracy crystals
narrower receiver bandwidth (i.e., increased sensitivity)
higher data rate
4.6. Crystal Oscillator and Microcontroller Clock Output
The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce
external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting
the appropriate crystal can be found later in this data sheet. The receiver can supply the clock signal for the
microcontroller, so accurate timing is possible without the need for a second crystal. In normal operation, it is
divided from the reference 10 MHz. During sleep mode, a low frequency (typical 32 kHz) output clock signal can be
switched on, which is provided by a low-power RC oscillator.
When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the "5.3. Configuration
Setting Command" on page 16, the chip provides a programmable number (default is 512) of further clock pulses
(“clock tail”) for the microcontroller to let it go to idle or sleep mode.
12
Rev. 1.2
Si4322
4.7. Low Battery Voltage Detector
The low battery detector circuit periodically monitors (typ. 8 ms) the supply voltage and generates an interrupt if it
falls below a programmable threshold level.
4.8. Wake-Up Timer
The wake-up timer has very low current consumption (5 µA max) and can be programmed from 1 ms to several
hours.
It calibrates itself to the crystal oscillator at every startup and then at every 30 seconds with an accuracy of ±0.5%.
When the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick
calibration (a few milliseconds) to facilitate accurate wake-up timing. The periodic auto-calibration feature can be
turned off.
4.9. Event Handling
In order to minimize current consumption, the receiver supports sleep mode. Active mode can be initiated by
setting the ex or en bits (in "5.3. Configuration Setting Command" on page 16 or "5.5. Receiver Setting Command"
on page 18).
The Si4322 generates an interrupt signal on several events (wake-up timer timeout, low supply voltage detection,
on-chip FIFO filled up). This signal can be used to wake up the microcontroller, effectively reducing the period the
microcontroller has to be active. The cause of the interrupt can be read out from the receiver by the microcontroller
through the SDO pin.
4.10. Interface and Controller
An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and
the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and
low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled
when not needed. All parameters are set to default after power-on; the programmed values are retained during
sleep mode. The interface supports the read-out of a status register, providing detailed information about the status
of the receiver and the received data. It is also possible to store the received data bits into the 64-bit RX FIFO
register and read them out in a buffered mode. FIFO mode can be enabled through the SPI compatible interface by
setting the fe bit to 1 in the "5.14. FIFO Settings Command" on page 25. During FIFO read the crystal oscillator must be
ON.
Rev. 1.2
13
Si4322
5. Control Interface
Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of
the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial
interface. The number of bits sent is an integer multiple of 8. All commands consist of a command code, followed
by a varying number of parameter or data bits. All data are sent MSB first (e.g., bit 15 for a 16-bit command). Bits
having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built-in
hardware serial port is used. If the port cannot be switched to 16-bit mode then a separate I/O line should be used
to control the nSEL pin to ensure the low level during the whole duration of the command or a software serial
control interface should be implemented. The Power On Reset (POR) circuit sets default values in all control
registers.
The receiver will generate an interrupt request (IRQ) for the microcontroller on the following events:
Supply voltage below the preprogrammed value is detected (LBD)
Wake-up timer timeout (WK-UP)
FIFO received the preprogrammed amount of bits (FFIT)
FIFO overflow (FFOV)
FFIT and FFOV are applicable only when the FIFO is enabled. To find out why the nIRQ was issued, the status bits
should be read out.
5.1. Timing Specification
Symbol
Parameter
Minimum value [ns]
tCH
Clock high time
25
tCL
Clock low time
25
tSS
Select setup time (nSEL falling edge to SCK rising edge)
10
tSH
Select hold time (SCK falling edge to nSEL rising edge)
10
tSHI
Select high time
25
tDS
Data setup time (SDI transition to SCK rising edge)
5
tDH
Data hold time (SCK rising edge to SDI transition)
5
tOD
Data delay time
10
tS HI
tSS
nSEL
tC H
tC L
t OD
tS H
SCK
t DS
SDI
SDO
tD H
BIT15
BIT15
BIT 14
BIT14
BIT13
BIT 13
BIT8
BIT8
BIT7
BIT7
Figure 3. Timing Diagram
14
Rev. 1.2
BIT1
BIT1
BIT0
BIT0
Si4322
5.2. Control Commands
Control Word
1
Related Parameters/Functions
Configuration Setting Command Receiving band, low battery detector,
wake-up timer, crystal oscillator, load
capacitance, baseband filter bandwidth,
clock output buffer
2
Frequency Setting Command
3
Receiver Setting Command
VDI source, LNA gain, RSSI threshold,
enable receiver
4
Synchron Pattern Command
Synchron pattern
5
Wake-up Timer Command
6
Frequency of the local oscillator
Wake-up time period
Extended Wake-up Timer Com- Wake-up time period extended adjustmand
ment
7
Low Duty-Cycle Command
Enable and set low duty-cycle mode
8
Low Battery Detector
and Clock Divider Command
9
AFC Control Command
10
Data Filter Command
Clock recovery parameters, auto-sleep
mode, data filter type, auto wake-up, DQD
threshold
11
Data Rate Command
Bit rate
12
FIFO Settings Command
13
Extended Features Command
14
Status Read Command
Microcontroller clock division ratio, low
frequency oscillator enable, LBD threshold voltage
AFC parameters
Related Control Bits
b1 to b0, eb, et, ex, x3 to x0, i2
to i0, dc
f11 to f0
d1 to d0, g1 to g0, r2 to r0, en
b7 to b0
r3 to r0, m7 to m0
c1 to c0, m13 to m8
d6 to d0, enldc
cd2 to cd0, elfc, t3 to t0
a1 to a0, rl1 to rl0, st, fi, oe,
aen
al, ml, dsfi, sf, ewi, f2 to f0
cs, r6 to r0
FIFO IT level, FIFO start control, FIFO
enable and FIFO fill enable
Clock tail, wake-up auto calibration, PLL
bandwidth, long FIFO IT level
f3 to f0, s1 to s0, ff, fe
ctls, dcal, bw1 to bw0, f5 to f4
Receiver status read
Note: In the following tables the POR column shows the default values of the command registers after power-on.
Rev. 1.2
15
Si4322
Table 6. Control Register Default Values
Control Register
Power-On Reset Value
1
Configuration Setting Command
928Ah
2
Frequency Setting Command
AD57h
3
Receiver Setting Command
C080h
4
Synchron Pattern Command
C1D4h
5
Wake-up Timer Command
E196h
6
Extended Wake-up Timer Command
C300h
7
Low Duty-Cycle Command
CC0Eh
8
Low Battery Detector and Clock Divider Command
C213h
9
AFC Control Command
C687h
10 Data Filter Command
C462h
11 Data Rate Command
C813h
12 FIFO Settings Command
CE87h
13 Extended Features Command
B0CAh
14 Status Register Read Command
0000h
5.3. Configuration Setting Command
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
0
0
b1
b0
eb
et
ex
x3
x2
x1
x0
i2
i1
i0
dc
928Ah
Bit 12-11 :Receiving band selection:
b1
b0 Frequency Band [MHz]
0
0
reserved
0
1
433
1
0
868
1
1
915
Bit 10 : Enables the low battery detector circuit
Bit 9 : When set, enables the operation of the wake-up timer
Bit 8 : If ex is set the crystal oscillator remains turned on during the inactive periods of the chip
16
Rev. 1.2
Si4322
Bit 7:4 : Crystal load capacitance. Set according to the crystal’s specified load capacitance.
x3
x2
x1
x0
Crystal Load
Capacitance [pF]
0
0
0
0
8.5
0
0
0
1
9.0
0
0
1
0
9.5
0
0
1
1
10.0
……
….
1
1
1
0
15.5
1
1
1
1
16.0
Bit 3:1 : Baseband filter bandwidth
i2
i1
i0
Baseband
Bandwidth [kHz]
0
0
0
Reserved
0
0
1
400
0
1
0
340
0
1
1
270
1
0
0
200
1
0
1
135
1
1
0
Reserved
1
1
1
Reserved
Bit 0 : When dc bit is set it disables the clock output.
Note: The internal 32 kHz oscillator is turned on by setting the elfc bit in the "5.10. Low Battery Detector and Microcontroller
Clock Divider Command" on page 21 or the enldc bit in the "5.9. Low Duty Cycle Command" on page 20 or by enabling
the low battery detector using eb bit or by turning on the wake-up timer (et bit) in this command.
Clock tail feature: When the clock output (pin 8) used to provide clock signal for the microcontroller (dc bit is set to 0), it
is possible to use the clock tail feature. This means that the crystal oscillator turn off is delayed, after issuing the command (clearing the ex bit) 512 more clock pulses are provided. This ensures that the microcontroller can switch itself to
low power consumption mode. It is possible to decrease the clock tail length to 128 pulses by clearing the ctls bit in
"5.15. Extended Features Command" on page 26.
Rev. 1.2
17
Si4322
5.4. Frequency Setting Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
0
1
0
f11
f10
f9
f8
f7
f6
f5
f4
f3
f2
f1
f0
AD57h
The 12-bit parameter F (bits f11 to f0) should be in
the range of 96 and 3903. When F is out of range,
the previous value is kept. The synthesizer center
frequency f0 can be calculated as follows:
f0 = 10 x N x (C + F/4000) [MHz]
The constants N and C are determined by the selected band:
Band [MHz]
N
C
433
4
10
868
8
10
915
8
11
Band
Min Frequency
Max Frequency
PLL Frequency Step
433 MHz
400.96 MHz
439.03 MHz
10 kHz
868 MHz
801.92 MHz
878.06 MHZ
20 kHz
915 MHz
881.92 MHz
958.06 MHz
20 kHz
5.5. Receiver Setting Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
1
0
0
0
0
0
0
d1
d0
g1
g0
r2
r1
r0
en
C080h
Bit 7:6 : Select the VDI (valid data indicator) signal:
d1
0
0
1
1
18
d0
0
1
0
1
VDI output
Digital RSSI Out (DRSSI)
Data Quality Detector Output (DQD)
Clock Recovery Lock
Always High
Rev. 1.2
Si4322
Bit 5:4 : Set the LNA gain:
g1
g0
GLNA (dB relative to maximum gain)
0
0
0
0
1
–6
1
0
–12
1
1
–18
Bit 3:1 : Control the threshold of the RSSI detector:
r2
r1
r0
RSSIsetth [dBm]
0
0
0
–103
0
0
1
–97
0
1
0
–91
0
1
1
–85
1
0
0
–79
1
0
1
–73
1
1
0
–67
1
1
1
–61
The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
RSSIth = RSSIsetth + GLNA
Bit 0 : Enables the whole receiver chain and crystal oscillator when set. Enable/disable of the wake-up timer
and the low battery detect or are not affected by this setting.
5.6. Synchron Pattern Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
1
0
0
0
0
0
1
b7
b6
b5
b4
b3
b2
b1
b0
C1D4h
The synchron pattern consists of two bytes. Byte 1 is fixed 2Dh, Byte 0 is programmable (default D4h) by B . For
more details, see"5.14. FIFO Settings Command" on page 25.
5.7. Wake-Up Timer Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
1
1
0
r3
r2
r1
r0
m7
m6
m5
m4
m3
m2
m1
m0
E196h
The wake-up time period can be calculated by M , R and C :
Twake-up = M x 2R – C ms
The upper six bits of M and the C parameter can be found in the Extended Wake-Up Timer
Command, see below.
Note: The wake-up timer generates interrupts continuously at the programmed interval while the et bit ("5.3. Configuration Setting Command" on page 16) is set.
Rev. 1.2
19
Si4322
5.8. Extended Wake-Up Timer Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
0
0
0
0
1
1
c1
c0 m13 m12 m11 m10 m9
0
POR
m8
C300h
These bits can be used to extend the range of the wake-up timer. The explanation of the bits can be found under
the Wake-Up Timer Command description (see above).
5.9. Low Duty Cycle Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
1
0
0
1
1
0
0
d6
d5
d4
d3
d2
d1
d0
enldc
CC0Eh
With this command, autonomous low duty cycle operation can be set up in order to decrease the average power
consumption in receive mode.
Bit 7-1 : The duty cycle can be calculated by using D and M. (M is parameter in a Wake-Up
Timer Command, see above). The time cycle is determined by the Wake-Up Timer Command.
duty cycle= (D x 2 +1) / M x 100%
Bit 0 : Enables the low duty cycle mode. Wake-up timer interrupt is not generated in this mode.
Note: For this operating mode, bit en must be cleared in the "5.5. Receiver Setting Command" on page 18 and bit et must be
set in the "5.3. Configuration Setting Command" on page 16.
In low duty cycle mode the receiver periodically wakes up for a short period of time and checks if there is a valid FSK
transmission is in progress. FSK transmission is detected in the frequency range determined by "5.4. Frequency Setting
Command" on page 18 plus and minus the baseband filter bandwidth set by the "5.3. Configuration Setting Command"
on page 16. This on-time is automatically extended while DQD indicates good received signal condition.
When calculating the on-time take into account the crystal oscillator, the synthesizer, and the PLL need time to start, see
the "Table 2. AC Characteristics" on page 6 depending on the DQD parameter, the chip needs to receive a few valid data
bits before the DQD signal indicates good signal condition "5.12. Data Filter Command" on page 23. Choosing too short
on-cycle can prevent the crystal oscillator from starting or the DQD signal may not go high even when the received signal has good quality.
There is an application proposal shown below. The Si4322 is configured to work in FIFO mode. The chip
periodically wakes up and switches to receiving mode. If valid FSK data received, the chip sends an interrupt to the
microcontroller and continues filling the RX FIFO. After the transmission is over and the FIFO is read out
completely and all other interrupts are cleared, the chip goes back to low power consumption mode.
Transm itter
Packet A
Packet A
Packet A
Packet
B. B . B. B.
Receiver
Twake-up
Receiving
Packet A
Packet A
Packet
B.
DQD
nIRQ
µC activity
FIFO Read
Note : Several packets must be transm itted to ensure safe reception
FF.rd
, depending on the ratio of the packet length and the idle time between packets
.
Figure 4. Application Proposal for LPDM (Low Power Duty-Cycle Mode) Receivers
20
Rev. 1.2
Si4322
5.10. Low Battery Detector and Microcontroller Clock Divider Command
Bit
15
14
13
12
11
10
9
8
1
1
0
0
0
0
1
0
7
6
5
4
cd2 cd1 cd0 elfc
3
2
1
0
POR
t3
t2
t1
t0
C213h
Bit 7:5 :Clock divider configuration (valid only if the crystal oscillator is on):
cd2 cd1 cd0
Clock Output
Frequency [MHz]
0
0
0
1
0
0
1
1.25
0
1
0
1.66
0
1
1
2
1
0
0
2.5
1
0
1
3.33
1
1
0
5
1
1
1
10
Bit 4 :
Enables the low frequency (32 kHz) clock during sleep mode. The clock signal is present on the
CLK pin regardless to the state of the dc bit ("5.3. Configuration Setting Command" on page 16).
Bit 3:0 :
The 4-bit value T of determines the threshold voltage of the threshold voltage Vlb of the
detector:
Vlb= 2.0 V + T x 0.1 V
5.11. AFC Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
1
1
0
a1
a0
rl1
rl0
st
fi
oe aen
POR
C687h
Bit 0 :
Enables the calculation of the offset frequency by the AFC circuit (it allows the addition of the
content of the output register to the frequency control word of the PLL).
Bit 1 :
Enables the output (frequency offset) register
Bit 2 :
Switches the circuit to high accuracy (fine) mode. In this case the processing time is about four
times longer, but the measurement uncertainty is less than half.
Bit 3 :
Strobe edge. When st goes to high, the actual latest calculated frequency error is stored into the
output registers of the AFC block.
Bit 5:4 : Limit the value of the frequency offset register to the following values:
rl1
rl0
Max dev [fres]
0
0
No restriction
0
1
±4
1
0
±2
1
1
±1
Rev. 1.2
21
Si4322
fres:
434MHz band: 10 kHz
868MHz band: 20 kHz
915MHz band: 20 kHz
Bit 7:6 :
Automatic operation mode selector:
a1
a0
Operation mode
0
0
Auto mode off (Strobe is controlled by µC)
0
1
Runs only once after each power-up
1
0
Keep the foffset only during receiving (VDI=high).
1
1
Keep the foffset value
BASEBAND SIGNAL IN
ATGL**
ASAME ***
0
10MHz CLK.
/4
fi (bit2)
en (bit0)
1
M
U
X
CLK
DIGITAL LIMITER
FINE
ENABLE CALCULATION
DIGITAL AFC
CORE LOGIC
au (bit6,7)
AUTO OPERATION
rl1, 0 (bit4,5)
st (bit 3)
oe (bit1)
F
4
IF IN>MaxDEV THEN
OUT=MaxDEV
IF IN O FFS O FFS O FFS< 2> O FFS< 1> O FFS< 0>
FIFO IT
(Sign )
demodulator status
AFC status
NOTE: Bits marked with * are internally latched.
Others are only multiplexed out
.
Figure 6. Status Register Read Sequence
Note: The FIFO IT bit behaves like a status bit, but generates nIRQ pulse if active. To check whether there is a sufficient
amount of data in the FIFO, the SDO output can be tested. In extreme speed critical applications, it can be useful to read
only the first four bits (FIFO IT to LBD) to clear the FFOV, WK-UP, and LBD bits.
26
Rev. 1.2
Si4322
Table 7. Status Register Read Timing Diagram Bits Definitions
Bit Name
Function
FFIT
The number of data bits in the FIFO has reached the preprogrammed limit
FFOV
FIFO overflow
WK-UP
LBD
Wake-up timer overflow
Low battery detect, the power supply voltage is below the preprogrammed limit
FFEM
FIFO is empty
DRSSI
The strength of the incoming signal is above the preprogrammed limit
DQD
Data Quality Detector detected a good quality signal
CRL
Clock recovery lock
ATGL
Toggling in each AFC cycle
ASAME
AFC measured twice the same result
OFFS(6)
MSB of the measured frequency offset (sign of the offset value)
OFFS(4)–OFFS(0)
Offset value to be added to the value of the selected center frequency
Rev. 1.2
27
Si4322
6. Interrupt Handling
In order to achieve low power consumption there is an advanced event handling circuit implemented. The device
has a very low power consumption mode, so called sleep mode. In this mode only a few parts of the circuit are
working. In case of an event, an interrupt signal generated on the nIRQ pin to indicate the changed state to the
microcontroller. If the ewi bit was set in the "5.13. Data Rate Command" on page 24 the device wakes up and
switches into idle mode. The cause of the interrupt can be determined by reading the status word of the device
(see "5.16. Status Register Read Command" on page 26).
Several interrupt sources are available:
FFIT—The number of the received bits in the RX FIFO reached the preprogrammed level: When the number of
received data bits in the receiver FIFO reaches the threshold set by the f5…f0 bits of the "5.14. FIFO Settings
Command" on page 25 and the "5.15. Extended Features Command" on page 26 an interrupt is generated. Valid
only when the fe (enable FIFO mode) bit is set in the FIFO settings command and the receiver is enabled in the
"5.5. Receiver Setting Command" on page 18.
FFOV—FIFO overflow: There are more bits received than the capacity of the FIFO (64 bits). Valid only when the fe
(enable FIFO mode) bit is set in the FIFO settings command and the receiver is enabled in the receiver setting
command.
WKUP—Wake-up timer interrupt: This interrupt event occurs when the time specified by the "5.7. Wake-Up Timer
Command" on page 19 has elapsed. Valid only when the et bit is set in the configuration setting command.
LBD—Low battery detector interrupt: Occurs when the VDD goes below the programmable low battery detector
threshold level (t3…t0 bits in the "5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page
21). Valid only when the eb (enable low battery detector) bit is set in the configuration setting command.
If an interrupt occurs the nIRQ pin will change to logic low level, and the corresponding bit in the status byte will be
1.
Clearing an interrupt actually implies two things:
Releasing the nIRQ pin to return to logic high
Clearing the corresponding bit in the status byte
To clear an interrupt requires different procedure depending on the interrupt type:
FFIT—Both the nIRQ pin and the status bit remain active until the FIFO is read (a FIFO IT threshold number of bits
have been read), the receiver is switched off, or the RX FIFO is switched off.
FFOV—This bit is always set together with FFIT; it can be cleared by the status read command, but the FFIT bit
and hence the nIRQ pin will remain active until the FIFO is read fully or the RX FIFO is switched off.
WKUP—Both the nIRQ pin and the status bit can be cleared by the Status Read Command
LBD—The nIRQ pin can be released by the reading the status, but the status bit will remain active while the VDD is
below the threshold.
The best practice in interrupt handling is to start with a status read when interrupt occurs, and then make a decision
based on the status byte. It is very important to mention that any interrupt can “wake up” the EZradio chip from
sleep mode if the ewi bit is set in the "5.12. Data Filter Command" on page 23. In this case the crystal oscillator will
start and the Si4322 will not go to low current sleep mode if any interrupt remains active regardless to the state of
the ex (enable crystal oscillator) bit in the "5.3. Configuration Setting Command" on page 16. This way the
microcontroller always can have clock signal to process the interrupt. To prevent high current consumption and this
way short battery life, it is strongly advised to process and clear every interrupt before turning off the crystal
oscillator. All unnecessary functions should be turned off to avoid unwanted interrupts. Before freezing the
microcontroller code, a thorough testing must be performed in order to make sure that all interrupt sources are
handled properly and the part goes to low power consumption (sleep) mode when the crystal oscillator turned off.
28
Rev. 1.2
Si4322
7. FIFO Buffered Data Read
In this operating mode, incoming data are clocked into a 64-bit FIFO buffer. The receiver starts to fill up the FIFO
when the Valid Data Indicator (VDI) bit and/or the synchron word recognition circuit indicates potentially real
incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller.
For further details see "5.5. Receiver Setting Command" on page 18 and "5.14. FIFO Settings Command" on page
25.
7.1. Polling Mode
The nFFS signal selects the buffer directly and its content could be clocked out through pin SDO by SCK. Set the
FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to
take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available.
7.2. Interrupt Controlled Mode
The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded.
The status bits report the changed FIFO status in this case.
7.3. FIFO Read Example with FFIT Polling
nSEL
0
1
2
3
4
SCK
SDI
nFFS *
FIFO read out
SDO
FIFO OUT
FO+1
FO+2
FO+3
FO+4
FFIT
NOTE:
*nFFS selects FIFO read mode
Note: During FIFO access fSCK cannot be higher than fref/4, where fref is the crystal oscillator frequency. When the duty-cycle
of the clock signal is not 50% the shorter period of the clock pulse should be at least 2/fref.
Rev. 1.2
29
Si4322
8. Power Saving Modes
The different operating modes of the chip depend on the following control bits:
Operating
Mode
eb or et or
elfc
en
ex
IDD (typ)
Active
X
1
X
12 mA
Idle
X
0
1
0.5 mA
Sleep
1
0
0
5 µA*
Standby
0
0
0
0.3 µA
*Note: Maximum value.
eb, et, ex bits—"5.3. Configuration Setting Command" on page 16
elfc bit—"5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page 21
en bit—"5.5. Receiver Setting Command" on page 18
Active mode—The whole receiver chain and the crystal oscillator both turned on.
Idle mode—The receiver is not active, only the crystal oscillator is running.
Sleep mode—Only the low frequency (32 kHz) RC oscillator is running. This oscillator also runs when the wake-up
timer or the low battery detector is enabled, providing them a timing signal.
Stand-by mode—All circuits are turned off.
9. Dual Clock Output
When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz
clock signal is available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the
"5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page 21. During startup and in sleep
or standby mode (crystal oscillator disabled), the CLK output is pulled to logic low.
On the same pin a low frequency clock signal can be obtained if the elfc bit is set in the low battery and
microcontroller clock divider command. The clock frequency is 32 kHz, which is derived from the low-power RC
oscillator. The clock signal is present on the CLK pin regardless the state of the dc bit in the "5.3. Configuration
Setting Command" on page 16.
Slow clock feature can be enabled by entering into sleep mode (clearing the en and ex bits and setting the elfc bit).
Driving the output will increase the sleep mode supply current. Actual worst-case value can be determined when
the exact load and min/max operating conditions are defined. After power-on reset the chip goes into sleep mode
and the slow frequency clock appears on the CLK pin.
Switching back into fast clock mode can be done by setting the ex bit in the configuration setting command or the
en bit in the "5.5. Receiver Setting Command" on page 18. It is important to leave bit dc in the Configuration Setting
Command at its default state (0) otherwise there will be no clock signal on the CLK pin.
Switching between the fast and slow clock modes is glitch-free in a sense that either state of the clock lasts for at
least a half cycle of the fast clock. During switching the clock can be logic low once for an intermediate period i.e.
for any time between the half cycle of the fast and the slow clock.
30
Rev. 1.2
Si4322
T slow
clock periods are not to scale
slow clock
fast clock
output
0.5 · T fast < T x < 0.5 · Tslow
Tx
T fast
The clock switching synchronization circuit detects the falling edges of the clocks. One consequence is a latency of
0 to Tslow + Tfast from the occurrence of a clock change request (entering into sleep mode or interrupt) until the
beginning of the intermediate length (Tx) half cycle. The other is that both clocks should be up and running for the
change to occur. Changing from fast to slow clock, it is automatically ensured by entering into the sleep mode if the
elfc bit is enabled. As the crystal oscillator is normally stopped while the slow clock is used, when changing back to
fast clock the crystal oscillator startup time has to pass first before the above mentioned latency period starts. The
startup condition is detected internally, so no software timing is necessary.
10. Wake-Up Timer Calibration
By default, the wake-up timer is calibrated every time it is enabled by setting the et bit in the "5.3. Configuration
Setting Command" on page 16. After timeout the timer restarts automatically and can be stopped by resetting the
et bit. If the timer is programmed to run for longer periods, at approximately every 30 seconds it performs additional
self-calibration.
This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software
algorithm can then compensate for the gradual shift caused by temperature change.
Bit dcal in the "5.15. Extended Features Command" on page 26 controls the automatic calibration feature. It is
reset to 0 at power-on and the automatic calibration is enabled. This is necessary to compensate for process
tolerances. After one calibration cycle further (re)calibration can be disabled by setting this bit to 1.
11. RX-TX Alignment Procedures
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these
errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX
and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of
accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the
reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical
reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK
signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the
receiver. By reading out the status byte from the receiver, the actual measured offset frequency will be reported. In
order to get accurate values the AFC has to be disabled during the read by clearing the aen bit in the "5.11. AFC
Command" on page 21.
Rev. 1.2
31
Si4322
12. Crystal Selection Guidelines
The crystal oscillator of the Si4322 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load
capacitor in order to minimize the external component count. The internal load capacitance value is programmable
from 8.5 to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 to 20 pF
so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is
expected for the crystal, the oscillator is able to start up with any crystal having less than 100 ESR (equivalent
series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup.
The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO).
Therefore, fLO is directly proportional to the crystal frequency. The accuracy requirements for production tolerance,
temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error.
Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate
frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required
load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by
its motional capacitance and C0.
The on chip AFC is capable to correct TX/RX carrier offsets as much as 80% of the deviation of the received FSK
modulated signal.
32
Rev. 1.2
Si4322
12.1. Maximum Crystal Tolerances Including Temperature and Aging [ppm]
Table 8. Bit Rate: 2.4 kbps
Transmitter Deviation [± kHz]
20
40
60
80
100
120
140
160
433 MHz
3
25
50
70
80
100
100
100
868 MHz
2
12
25
30
40
50
70
80
915 MHz
2
12
20
30
40
50
60
70
Table 9. Bit Rate: 9.6 kbps
Transmitter Deviation [± kHz]
20
40
60
80
100
120
140
160
433 MHz don't use
15
40
50
70
100
133
156
868 MHz don't use
8
20
30
40
50
60
70
915 MHz don't use
8
15
30
40
50
60
70
Table 10. Bit Rate: 38.4 kbps
Transmitter Deviation [± kHz]
20
40
60
80
100
120
140
160
433 MHz
don't use
don't use
20
40
50
70
100
100
868 MHz
don't use
don't use
10
20
30
40
50
70
915 MHz
don't use
don't use
10
20
30
40
50
60
Table 11. Bit Rate: 115.2 kbps
Transmitter Deviation [± kHz]
20
40
60
80
100
120
140
160
433 MHz
don't use
don't use
don't use
don't use
don't use
3
25
50
868 MHz
don't use
don't use
don't use
don't use
don't use
2
12
25
915 MHz
don't use
don't use
don't use
don't use
don't use
2
12
20
Rev. 1.2
33
Si4322
13. Reset modes
The chip will enter into reset mode if any of the following conditions are met:
Power-on reset: During a power up sequence until the Vdd has reached the correct level and stabilized
Power glitch reset: Transients present on the VDD line
Software reset: Special control command received by the chip
13.1. Power-On Reset
After power up the supply voltage starts to rise from 0 V. The reset block has an internal ramping voltage reference
(reset-ramp signal), which is rising at 100 mV/ms (typical) rate. The chip remains in reset state while the voltage
difference between the actual VDD and the internal reset-ramp signal is higher than the reset threshold voltage,
which is 600 mV (typical). As long as the VDD voltage is less than 1.6 V (typical) the chip stays in reset mode
regardless the voltage difference between the VDD and the internal ramp signal.
The reset event can last up to 100 ms supposing that the VDD reaches 90% its final value within 1 ms. During this
period, the chip does not accept control commands via the serial control interface.
V dd
Reset threshold voltage
(600 mV)
1.6V
Reset ramp line
(100mV/ms)
time
nRes
output
H
L
It stays in reset because the Vdd < 1.6V (even if the voltage
difference is smaller than the reset threshold)
Figure 7. Power-On Reset Example
13.2. Power Glitch Reset
The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is
sensitive, which can be changed by the appropriate control command (see related control commands at the end of
this section). In normal mode the power glitch detection circuit is disabled.
There can be spikes or glitches on the VDD line if the supply filtering is not satisfactory or the internal resistance of
the power supply is too high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if
the positive going edge of the VDD has a rising rate greater than 100 mV/ms and the voltage difference between
the internal ramp signal and the VDD reaches the reset threshold voltage (600 mV). Typical case when the battery
is weak and due to its increased internal resistance a sudden decrease of the current consumption (for example
turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset
cannot be disabled step-by-step decrease of the current consumption (by turning off the different stages one by
one) can help to avoid this problem.
Any negative change in the supply voltage will not cause reset event unless the VDD level reaches the reset
threshold voltage (250 mV in normal mode, 1.6V in sensitive reset mode).
If the sensitive mode is disabled and the power supply turned off the VDD must drop below 250 mV in order to
trigger a power-on reset event when the supply voltage is turned back on. If the decoupling capacitors keep their
charges for a long time it could happen that no reset will be generated upon power-up because the power glitch
detector circuit is disabled.
Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.
34
Rev. 1.2
Si4322
Vdd
Reset threshold voltage
(600mV)
Reset ramp line
(100mV/ms)
1.6V
time
nRes
output
H
L
Figure 8. Sensitive Reset Enabled, Ripple on VDD
Vdd
Reset threshold voltage
(600mV)
Reset ramp line
(100mV/ms)
250mV
time
nRes
output
H
L
Figure 9. Sensitive Reset Disabled
13.2.1. Software Reset
Software reset can be issued by sending the appropriate control command to the chip. The result of the command
is the same as if power-on reset was occurred but the length of the reset event is much less, 0.25 ms typical. The
software reset works only when the sensitive reset mode is selected.
13.2.2. VDD Line Filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command), it is
very important to keep the VDD line as smooth as possible. Noise or periodic disturbing signal superimposed the
supply voltage may prevent the part getting out from reset state. To avoid this phenomenon use adequate filtering
on the power supply line to keep the level of the disturbing signal below 100 mVPP in the DC – 50 kHz range for
200 ms from VDD ramp start. Typical example when a switch-mode regulator is used to supply the radio, switching
noise may be present on the Vdd line. Follow the manufacturer’s recommendations how to decrease the ripple of
the regulator IC and/or how to shift the switching frequency.
13.2.3. Related Control Commands
Reset Mode Command—Sending D540h command to the chip will change the reset mode to normal from the
default sensitive. Write D500h to the control interface in order to switch back to the sensitive mode.
SW Reset Command—Issuing FF00h command will trigger software reset (sensitive reset mode must be
enabled).
Rev. 1.2
35
Si4322
14. Typical Performance Characteristics
90
80
434 MHz
868 MHz
Suppression [dB]
70
60
50
915 MHz
40
30
ETSI limit
20
10
0
0
1
2
3
4
5
6
7
8
9
CW interferer offset from carrier [MHz]
10
11
12
Figure 10. Channel Selectivity and Blocking
Notes:
LNA gain: maximum, filter bandwidth: 135 kHz, data rate: 9.6 kbps, AFC: switched off, FSK deviation: ±60 kHz, VDD = 2.7 V
The measurement was done according to the descriptions in the ETSI Standard EN 300 220-2 v.2.1.2 (2007-06), section
4.3.3. and 4.3.4., referring to EN 300 220-1 v2.1.1 (2006-04), section 9.
The ETSI limit given in the figure is drawn by taking –104 dBm at 9.6 kbps typical sensitivity into account, and corresponds
to receiver class 2 requirements (section 4.1.1).
36
Rev. 1.2
Si4322
1
BER
10-1
10-2
10-3
19.2 kbps
1.2 kbps
2.4 kbps
10-4
115 kbps
38.4 kbps
57.6 kbps
4.8 kbps
9.6 kbps
10-5
-115
-110
-105
-100
-95
-90
-85
Input Power [dBm]
Figure 11. BER Curves in 433 MHz Band
1
BER
10-1
10-2
10-3
10
-4
10
-5
115 kbps
19.2 kbps
1.2 kbps
38.4 kbps
2.4 kbps
57.6 kbps
4.8 kbps
9.6 kbps
-115
-110
-105
-100
-95
-90
-85
Input Power [dBm]
Figure 12. BER Curves in 868 MHz Band
Note: LNA gain: maximum, VDD = 3.0 V
The table below shows the optimal receiver baseband bandwidth (BW) and transmitter deviation frequency (δfFSK)
settings for different data-rates supposing no transmit receive offset frequency. If TX/RX offset (for example due to
crystal tolerances) have to be taken into account, increase the BW accordingly.
1.2 kbps
2.4 kbps
4.8 kbps
9.6 kbps
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
BW=135 kHz
fFSK =60 kHz
BW=135 kHz
fFSK =60 kHz
BW=135 kHz
fFSK =60 kHz
BW=135 kHz
fFSK =60 kHz
BW=135 kHz
fFSK =60 kHz
BW=135 kHz
fFSK =100 kHz
BW=200 kHz
fFSK =120 kHz
BW=270 kHz
fFSK =140 kHz
Rev. 1.2
37
Si4322
15. Reference Design: Evaluation Board with 50 Matching Network
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t
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5SJJz3zch
5
ct
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Figure 13. Schematic
Table 12. Frequency Dependent Component Values
f [MHz]
L1 [nH]
C2 [pF]
C9 [pF]
C10 [pF]
434
33
220
6.8
6.8
868
15
39
2.2
3
915
15
39
2.2
3
Table 13. Recommended Component Types
Component Manufacturer
Part Number
Note
434 MHz
868 MHz
915 MHz
L1
Coilcraft
0603CS-33NX
0603CS-15NX
0603CS-15NX
1
C2
Murata
GRM1885C1H221JA01B
GRM1885C1H390JZ01B
GRM1885C1H390JZ01B
2
C9
Murata
GRM1885C1H6R8DZ01B
GRM1885C1H2R2CZ01B
GRM1885C1H2R2CZ01B
2
C10
Murata
GRM1885C1H6R8DZ01B
GRM1885C1H3R0CZ01B
GRM1885C1H3R0CZ01B
2
Notes:
1. SRF, DCR and Q should be similar if components from other manufacturer used.
2. The dielectric type should be C0G and the resonant frequency should be similar if components from alternative vendor
used.
38
Rev. 1.2
Si4322
16. PCB Layout
Top View
Bottom View
Rev. 1.2
39
Si4322
17. Pin Descriptions—Si4322
SDI
1
16
VDI
SCK
2
15
ARSSI
nSEL
3
14
VDD
SDO / FFIT
4
13
IN1
nIRQ
5
12
IN2
DATA / nFFS
6
11
VSS
DCLK / FFIT / CFIL
7
10
nRES
CLK
8
9
XTL / REF
Figure 14. Pin Configurations
Table 14. Pin Descriptions
Pin
Name
Type
1
SDI
DI
Data input of serial control interface
2
SCK
DI
Clock input of serial control interface
3
nSEL
DI
Chip select input of serial control interface (active low)
4
SDO
DO
Serial data output. Tristate with bus-hold cell if nSEL = H
FFIT
DO
FIFO IT output. See "5.16. Status Register Read Command" on page 26 for details.
5
nIRQ
DO
Interrupt request output (active low)
6*
DATA
DO
Received data output (FIFO not used)
nFFS
DI
FIFO select input (active low) with internal pull-up resistor (120 k)
DCLK
DO
Received data clock output (digital filter used, FIFO not used)
FFIT
DO
FIFO IT output. FIFO empty function can be achieved if FIFO IT level is set to 1.
CFIL
AIO
External data filter capacitor connection (if analog RC filter is used)
8
CLK
DO
Clock output for the microcontroller
9
XTL
AIO
Crystal connection (connect the other terminal of the crystal to VSS)
REF
DI
External reference input
10
nRES
DO
Reset output (active low)
11
VSS
S
Negative supply voltage
12
IN2
AI
RF differential signal input
13
IN1
AI
RF differential signal input
14
VDD
S
Positive supply voltage
15
ARSSI
AO
Analog RSSI output
16
VDI
DO
Valid Data Indicator output
7*
Description
Note: For detailed information about the functions of pin 6 and pin 7 see Table 5 on page 9.
40
Rev. 1.2
Si4322
18. Ordering Guide
Part Ordering #
Temperature
Package
Si4322-A1-FT
–40 to +85 °C
16-Pin TSSOP
Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
Rev. 1.2
41
Si4322
19. Package Outline: 16-Pin TSSOP
Figure 15 illustrates the package details for the Si4322. Table 15 lists the values for the dimensions shown in the
illustration.
Figure 15. 16-Pin TSSOP
Table 15. Package Diagram Dimensions (mm)
Dimension
A
A1
A2
b
c
D
E
E1
e
L
L2
θ
aaa
bbb
ccc
42
Min
—
0.05
0.80
0.19
0.09
4.90
4.30
0.45
0°
Nom
—
—
1.00
—
—
5.00
6.40 BSC
4.40
0.65 BSC
0.60
0.25 BSC
—
0.10
0.10
0.20
Rev. 1.2
Max
1.20
0.15
1.05
0.30
0.20
5.10
4.50
0.75
8°
Si4322
NOTES:
Rev. 1.2
43
Si4322
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: wireless@silabs.com
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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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44
Rev. 1.2
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