SI8902D-A01-GSR

Si8900/1/2 I SOLA TED M ONITORING ADC Features   ADC 3  input channels 10-bit resolution 2.5 µs conversion time  Isolated serial I/O port  UART I 2 2  (Si8900) C/SMbus (Si8901) MHz SPI port (Si8902) Transient immunity: 45 kV/µs (typ)    Temperature range: –40 to +85 °C >60-year life at rated working voltage CSA component notice 5A approval IEC 60950, 62368, 60601 VDE 0884-10 UL1577 recognized Up Ordering Information: See page 27. to 5 kVrms for 1 minute Applications  Isolated data acquisition  AC mains monitor  Solar inverters Pin Assignments  Isolated temp/humidity sensing  Switch mode power systems  Telemetry Description VDDA VDDB VREF NC AIN0 NC AIN1 The Si8900/1/2 series of isolated monitoring ADCs are useful as linear signal galvanic isolators, level shifters, and/or ground loop eliminators in many applications including power-delivery systems and solar inverters. These devices integrate a 10-bit SAR ADC subsystem, supervisory state machine and isolated UART (Si8900), I2C/SMbus port (Si8901), or SPI Port (Si8902) in a single package. Based on Silicon Labs’ proprietary CMOS isolation technology, ordering options include a choice of 2.5 or 5 kV isolation ratings. All products are safety certified by UL, CSA, and VDE. The Si8900/1/2 devices offer a typical common-mode transient immunity performance of 45 kV/µs for robust performance in noisy and high-voltage environments. Devices in this family are available in 16-pin SOIC wide-body packages. Safety Approval  UL 1577 recognized  Up to 5  kVrms for 1 minute  VDE certification conformity VDE 0884-10 CSA component notice 5A approval IEC Si8900 NC Tx NC VDDB GNDA GNDB VDDA VDDB VREF NC AIN0 NC AIN1 AIN2 Si8901 RST SCL SDA NC RSDA VDDB GNDA GNDB VDDA VDDB RST VREF AIN0 Copyright © 2019 by Silicon Laboratories Rx RST NC NC 60950, 62368, 60601 Rev. 1.2 4/19 AIN2 SDO Si8902 SCLK SDI AIN1 EN AIN2 VDDB GNDA GNDB Si8900/1/2 Si8900/1/2 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. Demand Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3. Multiple Channel Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5. I2C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Rev. 1.2 2 Si8900/1/2 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Condition Min Typ Max Unit Input Side Supply Voltage VDDA With respect to GNDA 2.7 — 3.6 V Input Side Supply Current IDDA VDDA = 3.3 V, Si890x active — 10 13.3 mA VDDA = 3.3 V, Si890x idle — 8.6 11.4 Output Side Supply Voltage VDDB With respect to GNDB 2.7 — 5.5 V Output Side Supply Current IDDB VDDB = 3.3 V to 5.5 V, Si890x active — 4.4 5.8 mA VDDB = 3.3 V to 5.5 V, Si890x idle — 3.3 3.9 –40 — +85 Operating Temperature TA °C Table 2. Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit ADC Resolution R 10 bits Integral Nonlinearity INL VREF = 2.4 V — ±0.5 ±1 LSB Differential Nonlinearity DNL VREF = 2.4 V, Guaranteed Monotonic — ±0.5 ±1 LSB Offset Error OFS –2 0 +2 LSB Full Scale Error FSE –2 0 +2 LSB Offset Tempco TOS — 45 — ppm/°C Input Voltage Range VIN 0 VREF V Sampling Capacitance CIN — 5 — pF Input MUX Impedance RMUX — 5 — k Power Supply Rejection PSRR — –70 — dB Reference Voltage VREF 0 — VDDA V VREF Supply Current IVREF — 12 — µA ADC Conversion Time tCONV Default VREF = VDDA 2.5 Rev. 1.2 µs 3 Si8900/1/2 Table 2. Electrical Specifications (Continued) Parameter Symbol Test Condition Min Typ Max Unit Reset and Undervoltage Lockout Power-on RESET Voltage Threshold High VRSTH — — 1.8 V Power-on RESET Voltage Threshold Low VRSTL 1.7 — — V VDDA Power-On Reset Ramp Time tRAMP Time from VDDA = 0 V to VDDA > VRST — — 1 ms Power-On Reset Delay Time tPOR tRAMP < 1 ms 0.3 ms Output Side UVLO Threshold UVLO — 2.3 — V H — 100 — mV Logic High Level Input Voltage VIH 0.7 x VDDB — — V Logic Low Level Input Voltage VIL — — 0.6 V Logic Input Current IIN +10 µA Input Capacitance CIN Output side UVLO Hysteresis Digital Inputs VIN = 0 V or VDD –10 — 15 — pF VDDB = 5 V, IOH = –4 mA VDDB – 0.4 4.8 — V VDDB = 3.3 V, IOH = –4 mA VDDB – 0.4 3.1 — V VDDB = 3.3 to 5 V, IOL = 4 mA — 0.2 0.4 V — 50 —  60 — 500 kbps Digital Outputs Logic High Level Output Voltage Logic Low Level Output Voltage Digital Output Source Impedance VOH VOL ROUT Serial Ports UART Bit Rate SMBus/I2C Bit Rate Slave Address = 1111000x — — 240 kbps SPI Port Bit Rate Mode 3: CPOL = 1, CPHA = 1 — — 2 Mbps 4 Rev. 1.2 Si8900/1/2 Table 2. Electrical Specifications (Continued) Parameter Symbol Test Condition Min Typ Max Unit SPI Port Timing EN Falling Edge to SCLK Rising Edge tSE 80 — — ns Last Clock Edge to /EN Rising tSD 80 — — ns EN Falling to SDO Valid tSEZ — — 160 ns SCLK High Time tCKH 200 — — ns SCLK Low Time tCKL 200 — — ns SDI Valid to SCLK Sample Edge tSIS 80 — — ns SCLK Sample Edge to SDI Change tSIH 80 — — ns SCLK Shift Edge to SDO Change tSOH — — 160 ns EN tSE tCKL tSD SCLK tCLKH tSIS tSIH SDI tSEZ tSOH tSDZ SDO Figure 1. SPI Port Timing Characteristics Rev. 1.2 5 Si8900/1/2 Table 3. Thermal Characteristics Parameter Symbol Test Condition JA IC Junction-to-Air Thermal Resistance WB SOIC-16 Unit 100 ºC/W Safety-Limiting Current (mA) 500 450 VDDA, VDDB = 2.70 V 400 370 VDDA, VDDB = 3.6 V 300 220 200 VDDA, VDDB = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature 6 Rev. 1.2 Si8900/1/2 Table 4. Absolute Maximum Ratings Parameter Symbol Min Typ Max Unit TSTG –65 — 150 °C TA –40 — 85 °C Input-Side Supply Voltage VDDA –0.5 — 6.0 V Output-Side Supply Voltage VDDB –0.5 — 6.0 V Input/Output Voltage VI –0.5 — VDD +0.5 V Output Current Drive IO — — 10 mA Lead Solder Temperature (10 s) — — 260 °C Maximum Isolation Voltage — — 6500 VRMS Storage Temperature Ambient Temperature under Bias *Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 1.2 7 Si8900/1/2 2. Regulatory Information The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes the certification levels supported. Table 5. Regulatory Information CSA The Si89xx is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873. 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si89xx is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001. 0884-10: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si89xx is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. 8 Rev. 1.2 Si8900/1/2 3. Functional Description The Si8900/1/2 (Figure 3) are isolated monitoring ADCs that convert input signals into digital format and transmit the resulting data through an on-chip isolated serial port to an external master processor (typically a microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC conversion by writing a configuration register (CNFG_0) Command Byte to the Si890x. The master then acquires ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port. Options include a UART with on-chip baud rate generator that operates at 500 kbps max (Si8900), an SMBus/I2C port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2 MHz max (Si8902). The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user to select VDDA or a different reference voltage applied to the VREF pin, set the programmable gain amplifier (PGA), and select the ADC MUX address. The master can configure the Si890x to return ADC data on-demand (Demand Mode) or continuously (Burst Mode). For more information, see " CNFG_0 Command Byte" on page 20. The RST pin on the input side resets the state machine. For the Si8901, the RSDA pin connects to an external pullup resistor to VDDA to allow operation of I2C/SMBus communication. Rev. 1.2 9 Si8900/1/2 VDDA VDDB AIN1 MUX PGA 10‐Bit ADC AIN2 VREF VREF ADC Subsystem Tx Tx Data UART Rx Rx Data AIN0 All  Blocks GNDB ISOLATION State Machine/  User Registers RST GNDA Si8900 VDDA VDDB AIN0 MUX PGA AIN2 10‐Bit ADC VREF VREF Tx Data Rx Data AIN1 SDA SMBus/ 2 IC SCL All  Blocks ADC Subsystem GNDB ISOLATION State Machine/  User Registers RST RSDA GNDA Si8901 VDDA VDDB SCK SDI AIN0 PGA AIN2 VREF 10‐Bit ADC VREF ADC Subsystem RST Tx Data SPI Port Rx Data AIN1 MUX SDO EN All  Blocks ISOLATION State Machine/  User Registers GNDA Si8902 Figure 3. Si8900/1/2 Block Diagrams 10 Rev. 1.2 GNDB Si8900/1/2 4. ADC Data Transmission Modes The Si890x ADC performs conversions by exercising the serial port. Each of the three channels can be in Demand Mode (MODE=1) or Burst Mode (MODE=0). Upon power cycle or reset, all channels are initialized to Demand Mode. The CNFG=0 command byte can be used to switch a channel between Demand and Burst modes. Demand Mode ADC conversions are initiated by Demand Mode CNFG=0 commands. Once a channel is in Burst Mode, ADC conversions are initiated by byte reads of the serial port. An advantage of Burst Mode is the conversion time of each ADC sample is masked by the time it takes to read data bytes on the serial port. An advantage of Demand Mode over multiple channels in Burst Mode is the master controller will dictate which ADC channel is sampled immediately. 4.1. Demand Mode Master to Slave Slave to Master Master writes CNFG _0  Command Byte to Si 8900 Rx  CNFG_0 Command  Byte MODE  = 1 t CONV CNFG_0 Command  Byte ADC_H ADC_L Master reads updated CNFG _0 and ADC  Data From Si8900 (Tx output) B)  Si8900 Demand Mode ADC Read  Master to Slave Slave to Master Master writes Slave Address and  CNFG_0 Command Byte to Si 8901 SDA Slave Address  CNFG_0 Command  Byte Slave  Address tCONV MODE = 1 CNFG_0 Command  ADC_H ADC_L Byte Master reads Slave Address , updated CNFG_0  and ADC Data from Si 8901 (SDA pin)  C)  Si8901 Demand Mode ADC Read Master to Slave Master writes CNFG_0  Command Byte to Si 8902 SDI  Slave to Master CNFG_0 Command  Byte tCONV MODE  = 1 The master must wait  8µS  (track‐and‐hold time) before  reading ADC data packet .  CNFG_0  Command  Byte ADC_H ADC_L Master reads updated CNFG _0 and  ADC Data from Si 8902 SDO D)  Si8902 Demand Mode ADC Read   Figure 4. ADC Demand Mode Operation Rev. 1.2 11 Si8900/1/2 Referring to Figure 4A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the Si8900. Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900 UART. The ADC conversion data packet contains an echo of the Command Byte for verification and two-bytes of ADC conversion data. The Si8901 (Figure 4B) ADC read transaction is identical to that of the Si8900 with the exception of the added I2C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). For the slower UART and I2C, the required tconv delay is consumed by reading the echo command byte. Since SPI supports the fastest data rate, the master controller may need to delay before reading the SPI port. If the SPI read request occurs before valid data is available, the Si8902 will output 0xFF bytes until valid data is available. The Si8902 Demand Mode ADC read transaction (Figure 4C) is the same as that of the Si8900, except the master must wait 8 µs after the transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two times shorter versus the Si8900/01. 4.2. Burst Mode Figure 5 shows the byte sequence for a channel operating in Burst Mode. A channel is switched from Demand Mode to Burst Mode by writing a command CNFG_0 byte with MODE=0. Placing a channel in Burst Mode negates the need to write subsequent CNFG_0 commands to initiate ADC conversions. At all serial port communication speeds, the tconv is masked by the data rate of the data byte reads. Like the Demand Mode example, the Si8901 has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must write the I2C port address prior to reading the serial port. The Si8902 Burst Mode (Figure 5C) is similar to that of the Si8900/ 1, except the master must wait 8 µs before reading the first Burst Mode ADC data packet. After reading the first Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay. 12 Rev. 1.2 Si8900/1/2 Master writes CNFG_0  Command Byte to Si8900 Rx CNFG_0 Command  Byte 0 MODE = 0 Master to Slave tCONV Slave to Master tCONV tCONV CNFG_0  Command  Byte ADC_H Data ADC_H Data ADC_L Data ADC_L Data Master reads updated CNFG_0 Command Byte and ADC data from Si8900 Tx  A)  Si8900 ADC Burst Mode (MODE = 0) Master writes Slave Address & CNFG_0  Command Byte to Si8901 SDA  Slave Addrress  Write CNFG_0 Command  Byte 0 MODE = 0 tCONV tCONV Master to Slave Slave Address Read Slave to Master CNFG_0  Command  Byte ADC_H Data ADC_L Data tCONV ADC_H Data ADC_L Data Master reads Slave Address, updated CNFG_0  and ADC data from Si8901 SDA B)  Si8901 ADC Burst Mode (MODE = 0) Master writes CNFG_0 Command  Byte to Si8902 SDI  Master to Slave Slave to Master CNFG_0 Command  Byte MODE = 0 tCONV tCONV CNFG_0 Command  Byte ADC_H Data ADC_L Data tCONV ADC_H Data ADC_L Data Master reads updated CNFG_0 and ADC data  from Si8902 SDO  C)  Si8902 ADC Burst Mode (MODE = 0) Figure 5. ADC Burst Mode Operation Rev. 1.2 13 Si8900/1/2 4.3. Multiple Channel Burst Mode It is possible to set any channel from Demand to Burst Mode and any Burst Mode Channel back to Demand Mode. However, CNFG_0 command byte can only write to one channel at a time. To operate two or more channels in Burst Mode, first set one channel to Burst Mode. This will enable the first Burst Channel operation. The master controller will then need to set additional channels to Burst Mode by writing another CNFG_0 command byte. For the Si8901, communication is half duplex. Therefore, the data reads of a previously set burst channel must be interrupted by writing a new CNFG_0 command to set the additional channel to Burst Mode. For the Si8900 and Si8902, communication is full duplex, and a new CFNG_0 command byte can be written at the same time as reading data from a previously set burst channel. Depending on where the new CNFG_0 command is received during the burst read, the Si8902 may output data with MX0 = 1 and MX1 = 1 (see “5. Si8900/1/2 Configuration Registers” ), which does not point to a valid channel. Ignore that ADC_H byte and the following ADC_L byte. This is a temporary artifact of having restarted the burst sequence with an additional burst-enabled channel. See "4.7. Master Controller Firmware" on page 19. To parse the data stream for multiple burst mode channels, the master controller must analyze the MX0 and MX1 bits of the ADC_H byte. For each ADC_H byte received, the next ADC_L byte received is the second part of that channel's data. The Si890x will cycle through all Burst Mode channels sequentially. For example, if channels 0 and 1 are in Burst Mode, the data read back will have this order: ADC_H (MX1=0, MX0=0), ADC_L, ADC_H (MX1=0, MX0=1), ADC_L, ADC_H (MX1=0, MX0=0), ADC_L, and so on. 14 Rev. 1.2 Si8900/1/2 4.4. UART (Si8900) The UART is a two-wire interface (Tx, Rx) and operates as an asynchronous, full-duplex serial port with internal auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal baud rate generator to match. The auto baud rate detection and matching optimizes UART timing for minimum bit error rate. For more information, see “AN635: Si8900 Automatic Baud Rate Detection”. There are a total of 10 bits per data byte: One start bit, eight data bits (LSB first), and one stop bit with data transmitted LSB first as shown in Figure 6. Figure 7A and Figure 7B show master/Si8900 ADC read transactions for Demand Mode and Burst Mode, respectively. MARK SPACE BIT TIMES Start Bit D0 D2 D1 D5 D4 D3 D6 D7 STOP BIT BIT SAMPLING Figure 6. UART Data Byte Master to Slave Slave to Master CNFG_0 Read Data D0 D1 D2 D3  D4 D5 D6 D7 STOP D0 D1 D2 D3 D4 D5 0 P S START D0  D1  D2 D3 D4 D5 D6  D7 STOP D6 D7 D8 D9 MX0 MX1 0 1 P S 0 START D0  D1  D2 D3 D4 D5 D6 D7 STOP 0 P S START D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 MX0 MX1 D0  D1 D2 D3 D4 D5  D6 D7 STOP CNFG_0 Read Data 0 1 P S 0 START D0  D1 D2 D3  D4 D5 D6  D7 STOP 1 1 P S START ‐ VREF MX0 MX1 S Periodic ADC Data MOD E = 0 D0    D1     D2    D3   D4   D5    D6    D7 STOP 1 P PGA MX1 MX0 VREF MODE=0 PGA 1 START START ‐ D0  D1   D2   D3   D4  D5   D6  D7 A)  Si8900 Demand Mode ADC Read  CNFG_0 Write Command Byte S D0   D1   D2   D3  D4   D5  D6   D7 0 S STOP D0   D1   D2   D3   D4   D5   D6   D7 0 1 P S 0 STOP 1 1 P S D6 D7 D8 D9 MX0 MX1 ‐ START START S D0 D1 D2 D3 D4 D5 ADC Data STOP START D0     D1    D2    D3    D4     D5    D6    D7 P VREF MX0 MX1 1 PGA 1 MODE = 1 MX1 MX0 VREF PGA ‐ STOP START S MODE = 1 CNFG_0 Write Command Byte B)  Si8900 Burst Mode ADC Read   Figure 7. Si8900 ADC Read Operation Rev. 1.2 15 Si8900/1/2 4.5. I2C/SMBus (Si8901) The I2C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I2C/SMBus master controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up resistors of 5 k or less. An Si8901 ADC read transaction begins with a START condition (“S” or Repeated START condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 8). The master terminates a transmission with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high. The data on SDA must remain stable during the high period of the SCL clock pulse because such changes in either line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is not busy. Acknowledge bits (Figure 9) provide detection of successful data transfers, whereas unsuccessful transfers conclude with a not-acknowledge bit (NACK). Both the master and the Si8901 generate ACK and NACK bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master attempts communication at a later time. Figure 10A shows the I2C Slave Address Byte and CNFG_0 byte for the Si8901. Figure 10B and Figure 10C show master/Si8901 ADC read transactions for Demand Mode and Burst Mode, respectively. P SR S SDA SCL Figure 8. Start and Stop Conditions Not Acknowledge (NACK) S SDA Acknowledge (ACK) SCL 1 2 Figure 9. Acknowledge Cycle 16 Rev. 1.2 9 Si8900/1/2 ‐ MODE PGA A 1 1 A P ACK Si8901  CNFG_0 Write Data STOP Write Si8901  Slave Address D7  D6   D5    D4    D3    D2   D1    D0 ACK START S s6 s5 s4 s3 s2 s1 s0 R/W = 0 D7   D6   D5   D4   D3    D2   D1    D0 MX1 MX0 VREF Master to Slave Slave to Master A)  Si8901 CNFG_0 Write  STOP 0 A P D7   D6   D5   D4   D3  D2   D1   D0 ACK STOP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D7   D6   D5  D4   D3  D2   D1   D0 A 0 ACK Si8901  CNFG_0  Read Data A 1 0 MX1 MX0 PGA MODE=1 ‐ ACK START R/W = 1 Si8901  Read  Slave Address A S 1 1 ACK START S s6 s5 s4 s3 s2 s1 s0 ADC Data D7    D6   D5    D4   D3   D2  D1   D0 Read D7   D6   D5  D4   D3   D2    D1   D0 Si8901  Slave Address = 0xF0 MX1 MX0 VREF Si8901  CNFG_0  Write Data A P ACK ‐ MODE=1 PGA R/W = 0 A 1 1 ACK START Si8901  Write  Slave Address Write S s6 s5 s4 s3 s2 s1 s0 MX1 MX0 VREF D7    D6    D5    D4    D3   D2   D1   D0 D7   D6    D5    D4   D3   D2   D1   D0 B)  Si8901 Demand Mode ADC Read STOP Periodic ADC Data 0 A D7  D6  D5  D4   D3   D2   D1   D0 P STOP D0 D1 D2 D3 D4 A ACK D7  D6  D5   D4   D3  D2   D1   D0 A 0 D5 D6 D7 D8 D9 MX1 MX0 A 1 0 ACK Si8901  CNFG_0  Read Data PGA R/W = 1 ‐ ACK Si8901  Read  Slave Address A S 1 1 Read ACK START START S s6 s5 s4 s3 s2 s1 s0 MODE=0 D7  D6 D5 D4 D3 D2 D1  D0 D7  D6  D5   D4   D3 D2  D1 D0 MX1 MX0 VREF Si8901  CNFG_0 Write Data A P ACK ‐ MODE=0 PGA R/W = 0 A 1 1 ACK Si8901  Slave Address Write START S s6 s5 s4 s3 s2 s1 s0 MX1 MX0 VREF D7   D6    D5    D4    D3   D2   D1   D0 D7    D6   D5    D4   D3   D2   D1   D0 C)  Si8901 Burst Mode ADC Read Figure 10. Si8901 ADC Read Operation Rev. 1.2 17 Si8900/1/2 4.6. SPI Port (Si8902) MASTER SPI Shift Register 7 6 5 4 3 2 1 0 Si8902 MOSI SDI MISO SDO SPI Shift Register 7 6 5 4 3 2 1 0 EN Receive Buffer Receive Buffer Baud Rate  Generator SCLK SCLK EN or Px.y Figure 11. Master Connection to Si8902 EN SCLK SDI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SDO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 12. Si8902 Data/Clock Relationship The Serial Peripheral Interface (SPI port) is a slave mode, full-duplex, synchronous, 4-wire serial bus that connects to the master as shown in Figure 11. The master's clock and data timing must match the Si8902 timing shown Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on page 5). As shown in Figure 13, the Si8902 will update output data on SDO with falling SCLK edge and sample data on SDI with rising SCLK edge. For idle condition between bytes, EN and SCLK should be held high by the master controller. Also, during ADC_H and ADC_L byte reads, the master controller must hold SDI high. The master transmits data from its master-out/slave-in terminal (MOSI) to the Si8902 serial read/write input terminal (SDI). The Si8902 transmits data to the master from its serial data-out terminal (SDO) to the master-in/slave-out terminal (MISO), and data transfer ends when the master returns EN to the high state. Figure 13A shows the Si8902 CNFG_0 Command Byte format, while Figures 13B and 13C show Si8902 Demand Mode and Burst Mode ADC reads. The Si8902 SDO pin will either drive low or drive high. It does not go into Hi-Z when EN is deasserted. Therefore, a system with multiple SPI slaves should use separate MISO signals to avoid SPI bus contentions. 18 Rev. 1.2 Si8900/1/2 ‐ PGA 1 MODE 1 MX0 Slave to Master VREF D7   D6   D5   D4   D3  D2   D1   D0 MX1 Master to Slave A)  Si8902 CNFG_0 Command Byte 8µS  Delay SDI High during Read 1 1 CNFG_0 Write Byte ‐ MODE = 1 PGA D7                                D0 MX1 MX0 VREF 8µS  Delay CNFG_0 Write Byte CNFG_0 Read Byte 0 D5 D4 D3 D2 D1 D0 1 0 MX1 MX0 D9 D8 D7 D6 ‐ MODE = 1 PGA 1 1 MX1 MX0 VREF D7                                D0 D7                                D0 D7                                D0 0 D7                     A new CNFG _0 Write Byte  and 8µS Delay are required  to re‐sample a Demand  Mode Channel 1 1 MX1 MX0 VREF ‐ MODE = 1 PGA 1 1 MX1 MX0 VREF D7                                D0 Demand Channel ADC Sample B)  Si8902 ADC Demand Mode 8µS  Delay SDI High during Idle 1 1 ‐ MODE = 0 PGA D7                                D0 MX1 MX0 VREF ‐ MODE = 0 PGA 1 1 MX1 MX0 VREF D7                                D0 CNFG_0 Write Byte SDI High during Idle Optional CNFG_0 Write Byte to Enable  Another Burst Channel or to Place an Existing  Burst Channel Back to Demand Mode CNFG_0 Read Byte Fisrt Burst Channel ADC Sample 0 D5 D4 D3 D2 D1 D0 0 1 0 MX1 MX0 D9 D8 D7 D6 0 D5 D4 D3 D2 D1 D0 1 0 MX1 MX0 D9 D8 D7 D6 ‐ MODE = 0 PGA 1 1 MX1 MX0 VREF D7                                D0 D7                                D0 D7                                D0 D7                                D0 D7                                D0 0 Next Burst Channel ADC Sample Periodic ADC Data C)  Si8902 ADC Burst Mode Figure 13. Si8902 ADC Read Operation 4.7. Master Controller Firmware The user's master controller must include firmware to manage the Si890x Demand and Burst operating modes and serial port control. For more information on master controller firmware, see “AN637: Si890x Master Controller Recommendations”, available for download at www.silabs.com/isolation. Rev. 1.2 19 Si8900/1/2 5. Si8900/1/2 Configuration Registers CNFG_0 Command Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 1 1 MX1 MX0 VREF — MODE PGA Type R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 7:6 1,1 5:4 MX1, MX0 Function Internal use. These bits are always set to 1. ADC MUX Address. ADC MUX address selection is controlled by MX1, MX0 as follows: 3 VREF 2 — 1 MODE 0 PGA MX1 MX0 Selected ADC MUX Channel 1 1 Not Used 1 0 AIN2 0 1 AIN1 0 0 AIN0 ADC Voltage Reference Source VDD is selected as the reference voltage when this bit is set to 1. An externally connected voltage reference generator is selected when this bit is reset to 0. Not used. ADC Read Mode ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled when this bit is 0. For more information on Demand and Burst mode operation, please see "4. ADC Data Transmission Modes" on page 11. PGA Gain Set PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0. ADC_H Byte 20 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 1 0 MX1 MX0 D9 D8 D7 D6 Type R R R R R R R R Rev. 1.2 Si8900/1/2 Bit Name 7:6 1,0 5:4 MX1, MX0 3:0 D9: D6 Function Internal use. These bits are always set to 1,0. ADC MUX Address ADC input MUX address for the converted data in ADC_H, ADC_L. ADC conversion data bits D9:D6 Most significant 4 bits of ADC conversion data. ADC_L Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 0 D5 D4 D3 D2 D1 D0 0 Type R R R R R R R R Bit Name 7 0 6:1 D5:D0 Function Internal use. This bit is always set to 0. ADC Conversion Data Bits D5:D0 Least significant 6 bits of ADC conversion data. 0 0 Internal use. This bit is always set to 0. Rev. 1.2 21 Si8900/1/2 6. Applications 6.1. Isolated Outputs The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (i.e., circuits with