SI8902EDB-T2-E1

Si8902EDB Vishay Siliconix Bi-Directional N-Channel 20-V (D-S) MOSFET PRODUCT SUMMARY VS1S2 (V) RS1S2(on) (Ω) 0.045 at VGS = 4.5 V 20 0.048 at VGS = 3.7 V 0.057 at VGS = 2.5 V 0.072 at VGS = 1.8 V IS1S2 (A) 5.0 4.8 4.4 3.9 FEATURES • • • • • Halogen-free According to IEC 61249-2-21 TrenchFET® Power MOSFET Ultra-Low RSS(on) ESD Protected: 4000 V MICRO FOOT® Chipscale Packaging Reduces Footprint Area Profile (0.62 mm) and On-Resistance Per Footprint Area APPLICATIONS • Battery Protection Circuit - 1-2 Cell Li+/LiP Battery Pack for Portable Devices S1 MICRO FOOT Bump Side View Backside View S2 5 4 S2 Pin 1 Identifier G1 4 kΩ 8902E xxx G2 6 3 G1 Device Marking: 8902E = P/N Code xxx = Date/Lot Traceability Code Ordering Information: Si8902EDB-T2-E1 (Lead (Pb)-free and Halogen-free) G2 4 kΩ S1 1 2 S1 N-Channel S2 ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Source1- Source2 Voltage Gate-Source Voltage Continuous Source1- Source2 Current (TJ = 150 °C)a Pulsed Source1- Source2 Current Maximum Power Dissipationa Operating Junction and Storage Temperature Range Package Reflow Conditionsc IR/Convection TA = 25 °C TA = 85 °C TA = 25 °C TA = 85 °C Symbol VS1S2 VGS IS1S2 ISM PD TJ, Tstg 1.7 0.8 - 55 to 150 260 5.0 3.4 40 1 0.5 W °C 5s 20 ± 12 3.9 2.8 A Steady State Unit V THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot b Symbol t≤5s Steady State Steady State RthJA RthJF Typical 60 95 18 Maximum 75 120 22 Unit °C/W Notes: a. Surface Mounted on 1" x 1" FR4 board. b. The foot is defined as the top surface of the package. c. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering. Document Number: 71862 S-83049-Rev. I, 22-Dec-08 www.vishay.com 1 Si8902EDB Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Source Current On-State Source Currenta VGS(th) IGSS IS1S2 IS(on) VSS = VGS, ID = 980 µA VSS = 0 V, VGS = ± 4.5 V VSS = 0 V, VGS = ± 12 V VSS = 20 V, VGS = 0 V VSS = 20 V, VGS = 0 V, TJ = 85 °C VSS = 5 V, VGS = 4.5 V VGS = 4.5 V, ISS = 1 A Source1-Source2 On State Resistancea RS1S2(on) VGS = 3.7 V, ISS = 1 A VGS = 2.5 V, ISS = 1 A VGS = 1.8 V, ISS = 1 A Forward Transconductance Dynamic b a Symbol Test Conditions Min. 0.45 Typ. Max. 1.0 ±4 ± 10 1 5 Unit V µA mA µA A 5 0.038 0.041 0.048 0.060 20 0.045 0.048 0.057 0.072 Ω gfs td(on) tr td(off) tf VSS = 10 V, ISS = 1 A S Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time 1 VSS = 10 V, RL = 10 Ω ISS ≅ 1 A, VGEN = 4.5 V, Rg = 6 Ω 3 17 10 1.5 4.5 26 15 µs Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 20 IGSS at 25 °C (mA) I GSS - Gate Current (mA) I GSS - Gate Current (µA) 16 10 000 1000 100 TJ = 150 °C 10 12 8 1 TJ = 25 °C 0.1 4 0 0 3 6 9 12 15 0.01 0 3 6 9 12 15 VGS - Gate-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Gate-Current vs. Gate-Source Voltage Gate Current vs. Gate-Source Voltage www.vishay.com 2 Document Number: 71862 S-83049-Rev. I, 22-Dec-08 Si8902EDB Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 VGS = 5 thru 1.5 V 8 ID - Drain Current (A) I D - Drain Current (A) 8 10 6 6 4 4 TC = 125 °C 2 25 °C - 55 °C 2 1V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics 0.10 1.6 Transfer Characteristics RDS(on) - On-Resistance (Ω ) 0.08 VGS = 1.8 V 0.06 VGS = 2.5 V 0.04 VGS = 3.7 V 0.02 VGS = 4.5 V RDS(on) - On-Resistance (Normalized) VGS = 4.5 V IS1S2 = 1 A 1.4 1.2 1.0 0.8 0.00 0 2 4 6 8 10 0.6 - 50 - 25 0 25 50 75 100 125 150 ID - Drain Current (A) TJ - Junction Temperature (°C) On-Resistance vs. Drain Current 0.10 IS1S2 = 5 A 0.1 R DS(on) - On-Resistance (Ω ) 0.08 V GS(th) Variance (V) IS1S2 = 1 A 0.06 0.0 0.2 On-Resistance vs. Junction Temperature IS1S2 = 980 µA - 0.1 0.04 - 0.2 0.02 - 0.3 0.00 0 1 2 3 4 5 - 0.4 - 50 - 25 0 25 50 75 100 125 150 VGS - Gate-to-Source Voltage (V) TJ - Temperature (°C) On-Resistance vs. Gate-to-Source Voltage Threshold Voltage Document Number: 71862 S-83049-Rev. I, 22-Dec-08 www.vishay.com 3 Si8902EDB Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 100 30 25 10 I D - Drain Current (A) 20 Power (W) 0.001 s 0.01 s ID(on) Limited 0.1 s 0.1 5 0.01 0.1 0.1 1 Time (s) 10 100 1000 TA = 25 °C Single Pulse BVDSS Limited 0 0.01 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum V GS at which RDS(on) is specified 1s 10 s DC Limited by R DS(on) * IDM Limited 0.0001 s 15 1 10 Single Pulse Power, Junction-to-Ambient 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Safe Operating Area 0.2 Notes: 0.1 0.1 0.05 0.02 PDM t1 t2 1. Duty Cycle, D = 2. t1 t2 PER UNIT BASE = RTHJA = 95 °C/W Single Pulse 0.01 10- 4 10- 3 10- 2 10- 1 1 Square Wave Pulse Duration (s) 3. T JM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 Square Wave Pulse Duration (s) 10-1 1 Normalized Thermal Transient Impedance, Junction-to-Foot www.vishay.com 4 Document Number: 71862 S-83049-Rev. I, 22-Dec-08 Si8902EDB Vishay Siliconix PACKAGE OUTLINE MICRO FOOT: 6 BUMP (2 x 3, 0.8 mm PITCH) 6 x 0.30 0.31 Note 3 Solder Mask - 0.4 Note 2 A2 e b Diameter Bump Note 1 e e A1 A Recommended Land 8902E XXX e D s Mark on Backside of Die s e E e Notes (Unless Otherwise Specified): 1. 6 solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 2. Backside surface is coated with a Ag/Ni/Ti layer. 3. Non-solder mask defined copper landing pad. 4. Laser marks on the silicon die back. Dim. A A1 A2 b D E e s Millimetersa Min. 0.600 0.260 0.33 0.370 1.520 2.320 0.750 0.380 Max. 0.650 0.290 0.360 0.410 1.600 2.400 0.850 0.400 Min. 0.0236 0.102 0.0134 0.0146 0.0598 0.0913 0.0295 0.0150 Inches Max. 0.0256 0.114 0.0142 0.0161 0.0630 0.0945 0.0335 0.0157 Notes: a. Use millimeters as the primary measurement. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71862. Document Number: 71862 S-83049-Rev. I, 22-Dec-08 www.vishay.com 5 AN824 Vishay Siliconix PCB Design and Assembly Guidelines For MICRO FOOTr Products Johnson Zhao INTRODUCTION Vishay Siliconix’s MICRO FOOT product family is based on a wafer-level chip-scale packaging (WL-CSP) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. MICRO FOOT products include power MOSFETs, analog switches, and power ICs. For battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. For example, the 6−bump MICRO FOOT Si8902EDB common drain power MOSFET, which measures just 1.6 mm x 2.4 mm, achieves the same performance as TSSOP−8 devices in a footprint that is 80% smaller and with a 50% lower height profile (Figure 1). A MICRO FOOT analog switch, the 6−bump DG3000DB, offers low charge injection and 1.4 W on−resistance in a footprint measuring just 1.08 mm x 1.58 mm (Figure 2). Vishay Siliconix MICRO FOOT products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. With proper attention to PCB and stencil design, the device will achieve reliable performance without underfill. The advantage of the device’s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, PDAs, cellular phones, and notebook computers. This application note discusses the mechanical design and reliability of MICRO FOOT, and then provides guidelines for board layout, the assembly process, and the PCB rework process. FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and Si8900EDB 3 0.18 ~ 0.25 A 0.5 B 0.285 0.285 0.5 1.58 1.08 2 1 FIGURE 2. Outline of MICRO FOOT CSP & Analog Switch DG3000DB Document Number: 71990 06-Jan-03 www.vishay.com 1 AN824 Vishay Siliconix TABLE 1 MICRO FOOT’S DESIGN AND RELIABILITY As a mechanical, electrical, and thermal connection between the device and PCB, the solder bumps of MICRO FOOT products are mounted on the top active surface of the die. Table 1 shows the main parameters for solder bumps used in MICRO FOOT products. A silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. A green laser is used to mark the backside of the die without damaging it. Reliability results for MICRO FOOT products mounted on a FR-4 board without underfill are shown in Table 2. ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Test Condition C: −65_ to 150_C Test condition B: −40_ to 125_C 121_C @ 15PSI 100% Humidity Test The main failure mechanism associated with wafer-level chip-scale packaging is fatigue of the solder joint. The results shown in Table 2 demonstrate that a high level of reliability can be achieved with proper board design and assembly techniques. www.vishay.com 2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á MICRO FOOT CSP Bump Material Eutectic Solder: 63Sm/37Pb 63Sm/37Pb Main Parameters of Solder Bumps in MICRO FOOT Designs Bump Pitch* 0.8 0.5 0.5 0.37-0.41 0.18-0.25 0.32-0.34 Bump Diameter* Bump Height* 0.26-0.29 0.14-0.19 0.21-0.24 MICRO FOOT CSP MOSFET MICRO FOOT CSP Analog Switch * All measurements in millimeters MICRO FOOT UCSP Analog Switch BOARD LAYOUT GUIDELINES Board materials. Vishay Siliconix MICRO FOOT products are designed to be reliable on most board types, including organic boards such as FR-4 or polyamide boards. The package qualification information is based on the test on 0.5-oz. FR-4 and polyamide boards with NSMD pad design. Land patterns. Two types of land patterns are used for surface-mount packages. Solder mask defined (SMD) pads have a solder mask opening smaller than the metal pad (Figure 3), whereas on-solder mask defined (NSMD) pads have a metal pad smaller than the solder-mask opening (Figure 4). NSMD is recommended for copper etch processes, since it provides a higher level of control compared to SMD etch processes. A small-size NSMD pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the PCB. By contrast, SMD pad definition introduces a stress concentration point near the solder mask on the PCB side that may result in solder joint cracking under extreme fatigue conditions. Copper pads should be finished with an organic solderability preservative (OSP) coating. For electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 mm to avoid solder joint embrittlement. MICRO FOOT Reliability Results >500 Cycles 96 Hours >1000 Cycles TABLE 2 Solder Mask Copper Copper Solder Mask FIGURE 3. SMD FIGURE 4. NSMD Document Number: 71990 06-Jan-03 AN824 Vishay Siliconix Board pad design. The landing-pad size for MICRO FOOT products is determined by the bump pitch as shown in Table 3. The pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. Chip pick-and-placement. MICRO FOOT products can be picked and placed with standard pick-and-place equipment. The recommended pick-and-place force is 150 g. Though the part will self-center during solder reflow, the maximum placement offset is 0.02 mm. Reflow Process. MICRO FOOT products can be assembled using standard SMT reflow processes. Similar to any other package, the thermal profile at specific board locations must be determined. Nitrogen purge is recommended during reflow operation. Figure 6 shows a typical reflow profile. Thermal Profile 250 Dimensions of Copper Pad and Solder Mask Opening in PCB and Stencil Aperture TABLE 3 Temperature (_C) Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Pitch Copper Pad Solder Mask Opening 0.41 " 0.01 mm 0.27 " 0.01 mm Stencil Aperture 0.80 mm 0.50 mm 0.30 " 0.01 mm 0.17 " 0.01 mm 0.33 " 0.01 mm in ciircle aperture 0.30 " 0.01 mm in square aperture 200 ASSEMBLY PROCESS MICRO FOOT products’ surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (Figure 5). Stencil Design IIncoming Tape and Reel Inspection Solder Paste Printing Chip Placement Reflow Solder Joint Inspection Pack and Ship 150 100 50 0 0 100 200 Time (Seconds 300 400 FIGURE 6. Reflow Profile PCB REWORK To replace MICRO FOOT products on PCB, the rework procedure is much like the rework process for a standard BGA or CSP, as long as the rework process duplicates the original reflow profile. The key steps are as follows: 1. Remove the MICRO FOOT device using a convection nozzle to create localized heating similar to the original reflow profile. Preheat from the bottom. Once the nozzle temperature is +190_C, use tweezers to remove the part to be replaced. Resurface the pads using a temperature-controlled soldering iron. Apply gel flux to the pad. Use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. Reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile. www.vishay.com FIGURE 5. SMT Assembly Process Flow Stencil design. Stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). The stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. In MICRO FOOT products, the stencil is 0.125-mm (5-mils) thick. The recommended apertures are shown in Table 3 and are fabricated by laser cut. Solder-paste printing. The solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. In MICRO FOOT products, the solder paste used is UP78 No-clean eutectic 63 Sn/37Pb type3 or finer solder paste. Document Number: 71990 06-Jan-03 2. 3. 4. 5. 6. 3 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1