SP7663_1

Solved by SP7663 TM Evaluation Board Manual Easy Evaluation for the SP7663ER 0 to 22V Input, 0 to 6A Output Synchronous Buck Converter Built-in low RDS(ON) Power FETs UVLO Detects Both VCC and VIN High Integrated Design, Minimal Components High Efficiency: 90% Feature Rich: UVIN, Programmable Soft Start, Built-in VCC Supply, Current Limiting and Output Short Circuit Protection SP7663EB SCHEMATIC SP7663 Evaluation Board Manual ©2006 Sipex Corporation USING THE EVALUATION BOARD 1) Powering Up the SP7663EB Circuit Connect the SP7663 Evaluation Board with an external +12V power supply. Connect with short leads and large diameter wire directly to the “VIN” and “GND2” posts. Connect a Load between the VOUT and GND1 posts, again using short leads with large diameter wire to minimize inductance and voltage drops. 2) Measuring Output Load Characteristics It’s best to GND reference all scope and digital meters using the Star GND post in the center of the board. VOUT ripple can best be seen by touching the probe tip to the pad for C3 and the scope to the GND collar touching Star GND post – avoid a GND lead on the scope which will increase noise pickup. 3) Using the Evaluation Board with Different Output Voltages While the SP7663 Evaluation Board has been tested and delivered with the output set to 3.30V, by simply changing one resistor, R2, the SP7663 can be set to other output voltages. The relationship in Equation 1 is based on a voltage divider from the output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V. Note, due to the common mode voltage range of the current sense amplifier, output voltages greater than 3.3V are only possible if the current sense is disabled. To disable current limit, remove R3 and R4. Standard 1% metal film resistors of surface mount size 0603 are recommended. R2 = R1 VOUT ( − 1) .80V Equation1 Where R1 = 68.1KΩ and for VOUT = 0.80V setting, simply remove R2 from the board. Furthermore, one could select the value of the R1 and R2 combination to meet the exact output voltage setting by restricting R1 resistance range such that 50KΩ ≤ R1 ≤ 100KΩ for overall system loop stability. Note that since the SP7663 Evaluation Board design was optimized for 12V down conversion to 3.30V, changes of output voltage and/or input voltage will alter performance from the data given in the Power Supply Data section. In addition, the SP7663ER provides short circuit protection by sensing VOUT at GND. The current limit of the converter is set to about 9A which is accomplished by sensing the current through the inductor. To adjust the current limit, follow Equations 2 and 3 to set the current limit accordingly. The current limit should be set to about 50% higher than the maximum output current that is desired. This will prevent the part from accidentally triggering the current limit during large transient load steps. Adjusting the current upwards is done by adjusting resistor R9. 60mV • ( R3 + R4) R9 = Equation 2 I max • ( DCR - 60mV) Where: DCR is the Inductor winding resistance IMAX is the desired output current Mar12-07 RevD SP7663 Evaluation Board Manual Page 2 of 16 ©2007 Sipex Corp. Adjusting the current downwards is controlled by adjusting R8.  (Vout - 60mV) + (Imax • DCR) R8 = R 4 ⋅   60mV - (Imax • DCR)    Equation 3   Where: DCR is the Inductor winding resistance IMAX is the desired output current Further details on the current limit can be found in the SP7663 data sheet. POWER SUPPLY DATA The SP7663ER is designed with an accurate 2.0% reference over line, load and temperature. Figure 1 data shows a typical SP7663 evaluation board efficiency plot, with efficiencies up to 90% and output currents up to 6A. The output voltage ripple of less than 50mV at full load and the LX node are shown in figure 2. Figures 3 and 4 illustrate a 3A-to-6A and 0A-to-6A Load Step. Short circuit and current limit are shown in Figures 5 and 6. Typical startup characteristics into a full load and no load are shown in figure 7 and 8. All data was taken at 12VIN. While data on individual power supply boards may vary, the capability of the SP7663ER of achieving high accuracy over a range of load conditions shown here is quite impressive and desirable for accurate power supply design. SP7663 Efficiency 12Vin - 3.3Vout - 6Amp 95.00 90.00 Efficiency . 85.00 80.00 75.00 70.00 0.00 1.00 2.00 3.00 4.00 5.00 6.00 Iout (Amps) Figure 1. Efficiency vs. Load Mar12-07 RevD SP7663 Evaluation Board Manual Page 3 of 16 ©2007 Sipex Corp. Vout Voutripple Iout (2A/div) Figure 2. LX node output ripple voltage Figure 3. Load Step Response: 3->6A Vout Vout SoftStart Iout (2A/div) Iout (5A/div) Figure 4. Load Step Response 0->6A Figure 5. Current Limit set point 9A Vout Vout SoftStart Soft Start Iout (5A/div) Vin Iout (5A/div) Figure 6. Output load Short Circuit Figure 7. Startup into full load Mar12-07 RevD SP7663 Evaluation Board Manual Page 4 of 16 ©2007 Sipex Corp. Iout (5A/div) Figure 8. Startup into no load TYPE III LOOP COMPENSATION DESIGN The open loop gain of the SP7663EB can be divided into the gain of the error amplifier Gamp(s), PWM modulator Gpwm, buck converter output stage Gout(s), and feedback resistor divider Gfbk. In order to cross over at the selecting frequency fco, the gain of the error amplifier must compensate for the attenuation caused by the rest of the loop at this frequency. The goal of loop compensation is to manipulate the open loop frequency response such that its gain crosses over 0dB at a slope of –20dB/dec. The open loop crossover frequency should be higher than the ESR zero of the output capacitors but less than 1/5 to 1/10 of the switching frequency fs to insure proper operation. Since the SP7663EB is designed with Ceramic Type output capacitors, a Type III compensation circuit is required to give a phase boost of 180° in order to counteract the effects of the output LC underdamped resonance double pole frequency. Mar12-07 RevD SP7663 Evaluation Board Manual Page 5 of 16 ©2007 Sipex Corp. Figure 9. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation The simple guidelines for positioning the poles and zeros and for calculating the component values for Type III compensation are as follows. As a particular example, consider for the following SP7663EB with a Type III Voltage Loop Compensation component selections: Input requirements and inductor selection Vin = 5 to 13.5V Vout = 3.30V @ 0 to 6A load Select L = 1.5uH => yield ≈ 48% of maximum 6A output current ripple. Select Cout = 100uF Ceramic capacitor (RESR ≈ 4mΩ) fs = 600kHz SP7663 internal Oscillator Frequency VRAMP_PP = 1.0V SP7663 internal Ramp Peak-to-Peak Amplitude Mar12-07 RevD SP7663 Evaluation Board Manual Page 6 of 16 ©2007 Sipex Corp. Step by step design procedures: Note: Loop Compensation component calculations discussed in this section are further elaborated in the application note #ANP16, “Loop Compensation of Voltage-Mode Buck Converters”. These calculations shown here can be quickly iterated with the Type III Loop Compensation Calculator on the web at: www.sipex.com/files/Application-Notes/TypeIIICalculator.xls Choose fco = fs/10 fco = 600Khz/10 = 60Khz Calculate fp_LC, the double pole frequency of the filter fp_LC = 1 2π ( L ⋅ C ) fp_LC = 1 = 12.99 Khz ≈ 13Khz 2π ⋅ 1.5uH ⋅100uF ) Calculate fz_ESR the ESR zero frequency fz_ESR = 1 2π ⋅ Cesr ⋅ Cout 1 = 397.88 Khz ≈ 400Κhz 2π ⋅ ( 4m ) ⋅ (100 µF ) fz _ ESR = Select R1 component value such that 50kΩ ≤ R1 ≤ 100kΩ R1 = 68.1kΩ, 1% Calculate R2 base on the desired VOUT R2 = R1 Vout   .8V  − 1   R2 = 68.1KΩ = 21.79 KΩ ≈ 21.5 KΩ  3.3V  −1  .8V    Select the ratio of RZ2 / R1 gain for the desired gain bandwidth Vramp _ pp   fco   RZ 2 = R1 ⋅   ⋅    Vin _ max   fp _ LC   1V   60 KHz  RZ 2 = R1 ⋅  ⋅  = 23.2 KΩ 13.5V   13KHz   Mar12-07 RevD SP7663 Evaluation Board Manual Page 7 of 16 ©2007 Sipex Corp. Calculate CZ2 by placing the zero at ½ of the output filter pole frequency 1 CZ 2 = π ⋅ RZ 2 ⋅ fp _ LC CZ 2 = 1 = 1.055nF ≈ 1nF π ⋅ 23.2 KΩ ⋅13KHz Calculate CP1 by placing the first pole at ESR zero frequency 1 CP1 = 2π ⋅ ( Rz 2 ⋅ fz _ ESR ) CP1 = 1 = 5.84 pF ≈ 10 pF 2π ⋅ (68.1K ⋅ 400 KHz ) Calculate RZ3 by setting the second pole at ½ of the switching frequency and the second zero at the output filter double pole frequency 2 ⋅ ( R1) ⋅ ( fp _ LC ) RZ 3 = fs − 2 fp _ LC RZ 3 = 2 ⋅ (68.1KΩ) ⋅ (13KHz ) = 3.084 KΩ 600 KHz − 2 f 13KHz Calculate CZ3 from RZ3 component value above 1 CZ 3 = π ⋅ RZ 3 ⋅ fs CZ 3 = 1 = 172 pF ≈ 180 pF π ⋅ 3.084 KΩ ⋅ 600 KHz Choose 100pF ≤ CF1 ≤ 220pF to stabilize the SP7663ER internal Error Amplifier Mar12-07 RevD SP7663 Evaluation Board Manual Page 8 of 16 ©2007 Sipex Corp. TYPE II LOOP COMPENSATION DESIGN Type II compensation is specifically used when an Electrolytic or Tantalum output capacitor is chosen at the converter output due to its low cost. In that case, the zero caused by the output capacitor ESR is within a few kHz and this is of course greatly simplifying the voltage loop compensation design. By adding an additional zero in the compensation loop before the first pole, the voltage loop bandwidth is extended with a 90º phase boost and hence the overall transient response time is improved. Most previous guidelines for calculating the component values for Type III compensation can be carries over for Type II except for the new Rz, Cz and Cp components. Note that RZ2, CZ2, CP1, RZ3, and CZ3 components are not required for the Type II Loop Compensation Design. Figure 10. Voltage Mode Control Loop with Loop Dynamic for Type II Compensation Mar12-07 RevD SP7663 Evaluation Board Manual Page 9 of 16 ©2007 Sipex Corp. As a particular example, consider for the following SP7663EB with a Type II Voltage Loop Compensation component selections: Input requirements and inductor selection Vin = 5 to 13.5V Vout = 3.30V @ 0 to 6A load Select L = 1.5uH => yield ≈ 48% of maximum 6A output current ripple. Select COUT = 330uF Tantalum capacitor (RESR ≈ 35mΩ) fs = 600kHz SP7663 Internal Oscillator Frequency VRAMP_PP = 1.0V SP7663 internal Ramp Peak-to-Peak Amplitude Step-by-step design procedures: Note: Type II Loop Compensation component calculations discussed in this section are further elaborated in the application note #ANP18, “Selecting Appropriate Compensation: Type-II or Type-III”. These calculations shown here can be quickly iterated with the Type III Loop Compensation Calculator on the web at: http://www.sipex.com/files/ApplicationNotes/Copy%20of%20Type%20II%20calculator5.xls Choose fco = fs/10 fco = 600Khz/10 = 60Khz Calculate fp_LC, the double pole frequency of the filter fp_LC = 1 2π ( L ⋅ C ) fp_LC = 1 = 7.153Khz ≈ 7.2Khz 2π ⋅ 1.5uH ⋅ 330uF Calculate fz_ESR, the ESR zero frequency fz_ESR = 1 2π ⋅ Cesr ⋅ Cout 1 = 13.77 Khz ≈ 14Κhz 2π ⋅ (35m ) ⋅ (330 µF ) fz _ ESR = Select R1 component value such that 50kΩ ≤ R1 ≤ 100kΩ R1 = 68.1kΩ, 1% Mar12-07 RevD SP7663 Evaluation Board Manual Page 10 of 16 ©2007 Sipex Corp. Calculate R2 base on the desired VOUT R2 = R1 Vout   .8V  − 1   R2 = 68.1KΩ = 21.79 KΩ ≈ 21.5 KΩ  3.3V   .8V  − 1   Select the ratio of RZ2 / R1 gain for the desired gain bandwidth  Vramp _ pp   Fz _ ESR RZ 2 = R1 ⋅  2  Vin _ max  ⋅      (Fp _ LC )   ⋅ fco   1 RZ 2 = 68.1KΩ ⋅   13.5V   13Khz ⋅ 2   7.2 Khz   ⋅ 60 Khz = 75.89 KΩ ≈ 75 KΩ  Calculate CZ2 by placing the zero at 1/10 of the output filter pole frequency CZ 2 = 1 .1 ⋅ 2 ⋅ π ⋅ RZ 2 ⋅ fp _ LC CZ 2 = 1 = 294 pF ≈ 330 pF .1 ⋅ 2 ⋅ π ⋅ 75KΩ ⋅ 7.2 Khz Calculate CP1 by placing the second pole at ½ of the switching frequency CP1 = 1 π ⋅ RZ 2 ⋅ fs 1 = 7.07 pF ≈ 10 pF π ⋅ 75 KΩ ⋅ 600 Khz CP1 = Cf1 = 100pF to stabilize SP7663ER internal Error Amplifier Mar12-07 RevD SP7663 Evaluation Board Manual Page 11 of 16 ©2007 Sipex Corp. OUTPUT WITH A TYPE II COMPENSATION APPLICATION SCHEMATIC SP76562ER with Tantalum output capacitor configures for VIN = 12V, VOUT = 3.3V at 0-6A output current. Figure 13 and 14 show output voltage ripple to be about 150mV at no load to 6A load. Figure 13 and 14 show a transient response for a load step of 3->6A and 0->6A. Mar12-07 RevD SP7663 Evaluation Board Manual Page 12 of 16 ©2007 Sipex Corp. TYPICAL RESULTS FOR TYPE II COMPENSATION LX node LX node Vout Ripple Vout Ripple FIGURE 11 VOUT RIPPLE AND LX NODE 6A OUT FIGURE 12 VOUT RIPPLE LX NODE 0A OUT Vout Vout Iout (2A/div) Iout (2A/div) FIGURE 13 TRANSIENT RESPONSE 3->6A FIGURE 14 VOUT RIPPLE LX NODE 0->6A Mar12-07 RevD SP7663 Evaluation Board Manual Page 13 of 16 ©2007 Sipex Corp. PC Layout Drawings Figure 15. SP7663EB Top Side Component Placement Figure 16. SP7663EB PC Layout Top Side Figure 17. SP7663EB PC Layout 2nd Layer Side Mar12-07 RevD SP7663 Evaluation Board Manual Page 14 of 16 ©2007 Sipex Corp. Figure 18. SP7663EB PC Layout 3rd Layer Side Figure 19. SP7663EB PC Layout Bottom Side Mar12-07 RevD SP7663 Evaluation Board Manual Page 15 of 16 ©2007 Sipex Corp. Table 1: SP7663EB Suggested Components and Vendor Lists Line No. 1 2 DBST 3 4 5 C5 6 7 8 C4, CBST C7, C8, C6, C3 C9 CVCC CF1 12 Cs1 Cs2 13 CSS 15 CP1 16 CZ3 17 CZ2 18 R1 19 20 21 22 23 23a 24 27 28 29 30 31 R2 R3, R4 R12 R6, R7 R8 R9 RBST Rs1, Rs2 RZ2 RZ3 VIN, VOUT, GND, GND 1 2 0 0 1 0 1 2 1 1 4 Panasonic Panasonic Not Populated Not Populated Panasonic Not Populated Panasonic Panasonic Panasonic Panasonic Vector Electronic ERJ-3GEYJ00R0V ERJ-3GEYJ2R0V ERJ-3EKF2372V ERJ-3EKF3091V K24C/M ERJ-3EKF1104V ERJ-3EKF2152V ERJ-3EKF4991V 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 .042 Dia 21.5K 4.99K Thick Film Res 1% Thick Film Res 1% 800-344-4539 800-344-4539 1 1 1 TDK Murata TDK Murata Panasonic 1 1 1 1 1 0 1 1 1 1 L1 C1, C2, 1 2 Wurth TDK Murata TDK Murata TDK TDK Murata Not Populated TDK Murata TDK TDK Murata TDK Murata TDK Murata TDK 7443552150 C3225X5R1C226M GRM32ER61E226K C3225X5R0J107M GRM32ER60J107M C1608X7R1H104K C1608X7R1H682K GRM188R71H682KA01 1 Vishay Semi SD101AWS Ref. Des. PCB U1 Qty. 1 1 Manufacturer Sipex Sipex Manuf. Part Number 146-6631-00 SP7663EU Layout Size SP7663EB DFN26 SOD323 5050 1210 1210 0603 0603 0603 C1608X7R1H682K GRM188R71H682KA01 C1608X5R1A475M C1608CH1H101J GRM1885C1H101JA01 C1608CH1H222J GRM1885C1H222JA01 C1608X7R1H473K GRM188R71E473KA01 C1608CH1H100J GRM1885C1H100JA01 C1608CH1H181J GRM1885C1H181JA01 C1608CH1H102J GRM1885C1H102JA01 ERJ-3EKF6812V 0603 0603 0603 0603 0603 0603 0603 0603 0603 Synchronous Buck Regulator 15mA-30V Schottky Diode 1.5uH Coil, 5.5m 22uF Ceramic X5R 16V 100uF Ceramic X5R 6.3V 0.1uF Ceramic X7R 50V 6.8nF Ceramic X7R 50V Not Populated 6.8nF Ceramic X7R 50V 4.7uF Ceramic X5R 10V 100pF Ceramic C0G 50V 2.2nF Ceramic C0G 50V 47nF Ceramic X7R 50V 10pF Ceramic C0G 50V 180pF Ceramic C0G 50V 1nF Ceramic C0G 50V 68.1K Thick Film Res 1% 978-779-3111 770-436-1300 978-779-3111 978-779-3111 770-436-1300 978-779-3111 770-436-1300 978-779-3111 770-436-1300 978-779-3111 770-436-1300 978-779-3111 770-436-1300 978-779-3111 770-436-1300 800-344-4539 Component Vendor Phone # 408-935-7500 408-935-7500 800-344-4539 201-785-8800 978-779-3111 770-436-1300 978-779-3111 770-436-1300 978-779-3111 978-779-3111 770-436-1300 9 10 11 Not Populated Not Populated 1.1Meg 0 1 Thick Film Res 800-344-4539 800-344-4539 800-344-4539 800-344-4539 800-344-4539 800-344-4539 Not Populated Thick Film Res 1% Thick Film Res 1% Thick Film Res 1% Thick Film Res 1% 23.2K 3.09K Test Point Post ORDERING INFORMATION Model Temperature Range Package Type SP7663EB…................................-40°C to +85°C...............…SP7663 Evaluation Board SP7663ER..............................…. -40°C to +85°C.................................……26-pin DFN Mar12-07 RevD SP7663 Evaluation Board Manual Page 16 of 16 ©2007 Sipex Corp.