XRT7295AEIWTR-F

XRT7295AE E3 (34.368Mbps) Integrated line Receiver March 2003 FEATURES APPLICATIONS l Fully Integrated Receive Interface for E3 Signals l Interface to E3 Networks l CSU/DSU Equipment l Integrated Equalization (Optional) and Timing Recovery l PCM Test Equipment l l Loss-of-Signal and Loss-of-Lock Alarms Fiber Optic Terminals l l Variable Input Sensitivity Control Multiplexers l 5V Power Supply l Compliant with G703, G.775 and G.824 Specifications GENERAL DESCRIPTION The XRT7295AE E3 Integrated Line Receiver is a fully integrates receive interface that terminates a bipolar E3 (34.3684 Mbps) signal transmitted over coaxial Cable. This device can be used with the XRT7296 Integrated Line Transmitter (see Figure 10), The device provides the functions of receive equalization (optional) automatic gain control (AGC), clock recovery and data re-timing, loss of signal and loss-of frequency lock detection. The digital system interface is a dual-rail with received positive and negative 1s appearing as unipolar digital signals on separate output leads. The on-chip equalizer is designed for cable losses of 0 to 15dB. The receive input has a variable input sensitivity control, providing three different sensitivity settings. High input sensitivity allows for significant amounts of flat loss or for use with input signals at the monitor level. Figure 1 shows the block diagram of the device. The XRT7295AE is manufactured by using linear CMOS technology. The XRT7295AE is available in a 20-pin plastic SOJ package for surface mounting. A pin compatible version is available for DS3 or STS-1 applications. Please refer to the XRT7295AT data sheet ORDERING INFORMATION Part No. XRT7295AEIW Package 20 J-lead 300 MIL JEDEC SOJ Operating Temperature Range -40°C to +85°C Rev. 2.0.0 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XRT7295AE Figure 1. Block Diagram PIN CONFIGURATION Rev. 2.0.0 2 XRT7295AE PIN DESCRIPTION Pin # Symbol Type Description 1 GNDA 2 RIN I Receive Input. Unbalanced analog receive input 3,6 TMC1-TMC2 I Test Mode Control 1 and 2. Internal test modes are enabled within the device by using TMC1 and TMC2. Users must tie these pins to the ground plane. 4,5 LPF-1-LPF-2 I PLL Filter 1 and 2. An external capacitor (0.1µF +/-20%) is connected between these pins (See Figure 3). 7 RLOS O Receive Loss-of-Signal. This pin is set high on loss of signal at the receive input. 8 RLOL O Receive PLL Loss-of-Lock. This pin is set high on loss of PLL frequency lock. 9 GNDD Digital Ground for PLL Lock. Ground lead for all circuitry running synchronously with PLL clock. 10 GNDC Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with EXCLK. 11 VDDD 5V Digital Supply (+/-10%) for PLL Clock. Power for all circuitry running synchronously with PLL clock. 12 VDDC 5V Digital Supply (+/-10%) for EXCLK. Power for all circuitry running synchronously with EXCLK. 13 EXCLK I External Reference Clock. A valid E3 (34.368MHz +/-100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD/2 levels, must be 40%-60%. 14 RCLK O Receive Clock. Recovered clock signal to the terminal equipment. 15 RNDATA O Receive Negative Data. Negative pulse data output to the terminal equipment. 16 RPDATA O Receive Positive Data. Positive pulse data output to the terminal equipment. 17 ICT I Output In-Circuit Test Control (Active-Low). If ICT is forced low, all digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a highimpedance state to allow for in-circuit testing. 18 REQB I Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low places the equalizer in the data path. 19 LOSTHR I Loss-of-Signal Threshold Control. The voltage forced on this pin controls the input loss-of-signal threshold. Three settings are provided by forcing the GND, VDD/2, or VDD at LOSTHR. 20 VDDA Analog Ground. 5V Analog Supply (+/-10%). Rev. 2.0.0 3 XRT7295AE DC ELECTRICAL CHARACTERISTICS Test Conditions: -40°C < TA < +85°C, VDD = 5V +/-10% Typical values are for VDD =5.0V, 25°C, and random data. Maximum values for VDD = 5.5V at 85°C all 1s data. Symbol Parameter Min. Typ. Max. Unit 82 79 106 103 mA mA GNDD VDDD -0.5 0.5 VDDD V V GNDD VDDD -0.5 0.4 VDDD V V Conditions Electrical Characteristics IDD Power Supply Current REQB=0 REQB=1 Logical Interface Characteristics VIL VIH Input Voltage Low High VOL VOH Output Voltage Low High CI Input Capacitance 10 pF CL Load Capacitance 10 pF IL Input Leakage -10 10 µA 0.02 10 -50 0.5 100 -5 mA µA µA Note: Specifications are subject to change without notice. ABSOLUTE MAXIMUM RATINGS Power Supply ....................... -0.5V to +6.5V Storage Temperature ............ -40°C to +125°C Voltage at any Pin ................ -0.5V to VDD +0.5V Power Dissipation ................. 700mW Maximum Allowable Voltages (RIN) with Respect to GND .......... -0.5 to +5V Rev. 2.0.0 4 -5.0mA 5.0mA -0.5 to VDD +0.5V (all input pins except 2 and 17) 0V (pin 17) VDD (pin 2) GND (pin 2) XRT7295AE XRT7296 XRT7295AE Transmitter XRT7296 XRT7295AE Transmitter Figure 2. Application Diagram SYSTEM DESCRIPTION Pulse Mask at the 34.368 Mbps Interface Table 2 shows the pulse specifications at the transmitter output post and Figure 4 shows the pulse mask requirement for E3 as recommended in G.703. Receive Path Configurations The diagram in Figure 2 shows a typical system application for the XRT7295AE. In the receive signal path (see Figure 1), the internal equalizer can be included by setting REQB=0 or bypass by setting REQB=1. The equalizer bypass option allows easy interfacing of the XRT7295AE into systems already containing the external equalizers. Figure 3 illustrates the receive path option for two separate cases. Minimum Signal In case 1, the signal from the coaxial cable feeds directly into the RIN input. In this mode, the user should set REQB=0, engaging the equalizer in the data path if the cable loss is greater than 6dB. If the cable loss is less than 6dB, the equalizer is bypassed by setting the REQB=1. REQB LOSTHR SOJ2 DIP Unit3 0 0 80 115 mV pk VDD/2 60 85 mV pk VDD 40 60 mV pk 0 80 115 mV pk VDD/2 80 115 mV pk VDD 80 115 mV pk 1 In case 2, an external line and equalizer network precedes the XRT7295AE. In this mode, the signal at RIN is already equalized, and the on-chip equalizer should be bypassed by setting REQB1=1. In both cases, the signal at RIN must meet the amplitude limits described in Table 1. NOTES: The recommended receive termination is also shown in Figure 3. The 75Ω resistor terminates the coaxial cable with its characteristic impedance. In Figure 3 case 2, if the fixed equalizer includes the line termination, the 75Ω resistor is not required. The signal is AC coupled through the 0.01µF capacitor to RIN. The DC bias at RIN is generated internally. The input capacitance at the RIN pin is typically 2.8pF (SOJ package). 1 Maximum input amplitude under all conditions is 1.1 Vpk. 2 The SOJ package performance is enhanced by decreased package parasitics. 3 Although system designers typically use power in dBm to describe input levels, the XRT7295AE responds to peak input signal amplitude. Therefore, the XRT7295AE input signal limits are given in mV pk. Table 1. Receive Input Signal Amplitude Requirements Rev. 2.0.0 5 XRT7295AE Line Termination and Input Capacitance External Loop Filter Capacitor The recommended receive termination is shown in Figure 3. The 75Ω resistor terminates the coaxial cable with its characteristic impedance. The 0.01µF capacitor to RIN couples the signal into the receive input without disturbing the internally generated DC bias level present on RIN. The input capacitance at the RIN pin is 2.8pF. Figure 3 shows the connection to an external 0.1µF capacitor at the LPF1/LPF2 pins. This capacitor is part of the PLL filter. A non-polarized, low-leakage capacitor should be used. A ceramic capacitor with the value 0.1µF +/-20% is acceptable. XRT7295AE XRT7295AE Figure 3. Receiver Configuration some jitter appears on RCLK because of jitter on the incoming signal. (The following section discussed the jitter transfer characteristic, which describes the relationship between input and output jitter.) Second, noise sources within the XRT7295AE or noise sources that are coupled into the device through the power supplies create jitter on RCLK. The magnitude of this TIMING RECOVERY Output Jitter The total jitter appearing on the RCLK output during normal operation consists of two components. First, Rev. 2.0.0 6 XRT7295AE internally generated jitter is a function of the PLL bandwidth, which in turn is a function of the input 1s density. For higher 1s densities, the amount of generated jitter decreases. Generated jitter also depends on the quality of the power supply bypassing networks used. Figure 8 shows the suggested bypassing network, and Table 3 lists the typical generated jitter performance achievable with this network. Figure 4. Pulse Mask at the 34.368 Mbit/s Interface Parameter Value Pulse Shape (Nominally Rectangular) All marks of a valid signal must conform with the mask (see Figure 4), irrespective of the sign Pair(s) in Each Direction One coaxial pair Test Load Impedance 75Ω Resistive Nominal Peak Voltage of a Mark (Pulse) 1.0V Peak Voltage of a Space (No Pulse) 0V +/-0.1V Nominal Pulse Width 14.55ns Ratio of the Amplitudes of Positive and Negative Pulses at the Center of a Pulse Interval 0.95 to 1.05 Ratio of the Widths of Positive and Negative Pulses at the Nominal Half Amplitude 0.95 to 1.05 Table 2. E3 Pulse Specification at the Transmitter Output Port Rev. 2.0.0 7 XRT7295AE Jitter Transfer Characteristic Jitter Accommodation The jitter transfer characteristic indicates the fraction of input jitter that reaches the RCLK output as a function of input jitter frequency. Table 3 shows important jitter transfer characteristic parameters. Figure 6 also shows a typical characteristic , with the operating conditions as described in Table 3. Under all allowable operating conditions, the jitter accommodation of XRT7295AE exceeds limits for error-free operation (BER < 1E-9). The typical (VDD = 5V, T = 25°C, E3 nominal signal level) jitter accommodation of the device is shown in Figure 6. Parameter Typ. Max. Unit Generated Jitter1 All-1s patter 1.0 ns peak-to-peak Repetitive 1000 pattern 1.5 ns peak-to-peak Jitter Transfer Characteristic2 Peaking 0.05 f3dB 205 0.1 dB kHz Notes: 1 Repetitive input data pattern at nominal E3 level with VDD=5V TA=25°C. Figure 5. Typical PLL Jitter Transfer Characteristics 2 Repetitive 1000 input at nominal E3 level with VDD=5V, TA=25°C. Table 3. Generated Jitter and Jitter Transfer Characteristics Figure 6. Lower Limit of Maximum Tolerable Input Jitter at 34.368Mbps Rev. 2.0.0 8 XRT7295AE Data Rate False-Lock Immunity REQB LOSTHR 0 False-lock is defined as the condition where a PLL recovered clock obtains stable phase-lock at a frequency not equal to the incoming data rate. The XRT7295AE uses a combination frequency/phaselock architecture to prevent false-lock. An on-chip frequency comparator continuously compares the EXCLK reference to the PLL clock. If the frequency difference between the EXCLK and PLL clock exceeds approximately +/-0.5% of EXCLK, correction circuitry acts to force the reacquisition of the proper frequency and phase. E3 34.368 Mbps 1 Threshold MIN Max Unit 0 60 220 mV pk VDD/2 40 145 mV pk VDD 25 90 mV pk 0 45 175 mV pk VDD/2 30 115 mV pk VDD 20 70 mV pk Notes: 1 The RLOS alarm is an indication of the presence of an input signal, not a bit error rate indication. Table 1 gives the minimum input amplitude needed for errorfree operation (BER