XRT7295ATIW

XRT7295AT DS3/Sonet STS-1 Integrated Line Receiver December 2000-2 FEATURES APPLICATIONS D Fully Integrated Receive Interface for DS3 and STS-1 Rate Signals D Interface to DS-3 Networks D Digital Cross-Connect Systems D Integrated Equalization (Optional) and Timing Recovery D CSU/DSU Equipment D Loss-of-Signal and Loss-of-Lock Alarms D PCM Test Equipment D Variable Input Sensitivity Control D Fiber Optic Terminals D 5V Power Supply D Pin Compatible with XRT7295AE and XRT7295AC D Companion Device to T7296 Transmitter GENERAL DESCRIPTION The XRT7295AT DS3/SONET STS-1 integrated line receiver is a fully integrated receive interface that terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1 (51.84Mbps) signal transmitted over coaxial cable. (See Figure 13). The device also provides the functions of receive equalization (optional), automatic-gain control (AGC), clock-recovery and data retiming, loss-of-signal and loss-of-frequency-lock detection. The digital system interface is dual-rail, with received positive and negative 1s appearing as unipolar digital signals on separate output leads. The on-chip equalizer is designed for cable distances of 0 to 450ft. from the cross-connect frame to the device. The receive input has a variable input sensitivity control, providing three different sensitivity settings, to adapt longer cables. High input sensitivity allows for significant amounts of flat loss within the system. Figure 1 shows the block diagram of the device. The XRT7295AT device is manufactured using linear CMOS technology. The XRT7295AT is available in a 20-pin plastic SOJ package for surface mounting. Two versions of the chip are available, one is for either DS3 or STS-1 operation (the XRT7295AT, this data sheet), and the other is for E3 operation (the XRT7295AE, refer to the XRT7295AE data sheet). Both versions are pin compatible. For either DS3 or STS-1, an input reference clock at 44.736MHz or 51.84MHz provides the frequency reference for the device. ORDERING INFORMATION Part No. Package Operating Temperature Range XRT7295ATIW 20 Lead 300 Mil JEDEC SOJ -40°C to + 85°C Rev. 1.20 E2000 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 XRT7295AT BLOCK DIAGRAM LPF1 LPF2 VDDA GNDA VDDD GNDD VDDC GNDC REQB 4 18 2 Attenuator Gain & Equalizer Loop Filter Phase Detector Slicers RIN 5 20 1 11 9 12 14 RCLK VCO 16 RPDATA Retimer 15 RNDATA Peak Detector 19 Analog LOS Digital LOS Detector Frequency Phase Aquisition Circuit AGC LOSTHR Analog LOS Equalizer Tuning Ckt. 17 3 6 13 ICT TMC1 TMC2 EXCLK 8 RLOL Figure 1. Block Diagram Rev.1.20 2 10 7 RLOS XRT7295AT PIN CONFIGURATION GNDA RIN TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VDDA LOSTHR REQB ICT RPDATA RNDATA RCLK EXCLK VDDC VDDD 20 Lead SOJ (Jedec, 0.300”) PIN DESCRIPTION Pin # Symbol Type 1 2 GNDA RIN I 3,6 TMC1-TMC2 I 4,5 7 LPF1-LPF2 RLOS I O 8 9 RLOL GNDD O 10 GNDC 11 VDDD 12 VDDC 13 EXCLK I 14 15 RCLK RNDATA O O 16 RPDATA O 17 ICT I 18 REQB I 19 LOSTHR I 20 VDDA Description Analog Ground. Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series with 50 kW. Test Mode Control 1 and 2. Internal test modes are enabled within the device by using TMC1 and TMC2. Users must tie these pins to the ground plane. PLL Filter 1 and 2. An external capacitor (0.1mF ±20%) is connected between these pins. Receive Loss-of-signal. This pin is set high on loss of the data signal at the receive input. (See Table 6) Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock. Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with PLL clock. Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with EXCLK. 5V Digital Supply (±10%) for PLL Clock. Power for all circuitry running synchronously with PLL clock. 5V Digital Supply (±10%) for EXCLK. Power for all circuitry running synchronously with EXCLK. External Reference Clock. A valid DS3 (44.736MHz ±100ppm) or STS-1 (51.84MHz + 100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD /2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns. Receive Clock. Recovered clock signal to the terminal equipment. Receive Negative Data. Negative pulse data output to the terminal equipment. (See Figure 11.) Receive Positive Data. Positive pulse data output to the terminal equipment. (See Figure 11) In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-circuit testing. There is an internal pull-up on this pin. Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low places the equalizer in the data path. Loss-of-signal Threshold Control. The voltage forced on this pin controls the input lossof-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD. This pin must be set to the desired level upon power-up and should not be changed during operation. 5V Analog Supply (±10%). Rev.1.20 3 XRT7295AT ELECTRICAL CHARACTERISTICS Test Conditions: TA = -40°C to +85°C, VDD = 5V + 10% Typical Values are for VDD = 5.0 V, 25°C, and Random Data. Maximum Values are for VDD = 5.5V all 1s Data. Symbol Parameter Min. Typ. Max. Unit Condition 82 106 mA REQB=0 79 103 mA REQB=1 87 111 mA REQB=0 83 108 mA REQB=1 Electrical Characteristics IDD Power Supply Current DS3 STS--1 Logic Interface Characteristics Input Voltage VIL Low GNDD 0.5 V VIH High VDDD-0.5 VDDD V Output Voltage VOL Low GNDD 0.4 V -5.0mA VOH High VDDD-0.5 VDDD V 5.0mA 10 pF CI Input Capacitance CL Load Capacitance IL Input Leakage 10 pF -10 10 mA -0.5 to VDD + 0.5V (all input pins except 2, 3, 4, 5, 6, 17, 18, & 19) 20 500 mA 0 V (pin 17) 10 100 mA VDD (pin 2) -50 -5 mA GNDD (pin 2) Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Storage Temperature . . . . . . . . . . . . -40°C to +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 700 mW Rev.1.20 4 XRT7295AT System A 0-450 ft. 0-450 ft. System B Cross Connect XR-T7296 Transmitter XRT7295AT Frame Receiver DSX-3 or STSX-1 Type 728A Coaxial Cable Figure 2. Application Diagram SYSTEM DESCRIPTION Receive Path Configurations In the receive signal path (see Figure 1), the internal equalizer can be included by setting REQB = 0 or bypassed by setting REQB = 1. The equalizer bypass option allows easy interfacing of the XRT7295AT device into systems already containing external equalizers. Figure 3 illustrates the receive path options. In Case 2 of Figure 3, external line build-out (LBO) and equalizer networks precede the XRT7295AT device. In this mode, the signal at RIN is already equalized, and the on-chip filters should be bypassed by setting REQB=1. In applications where the XRT7295AT device is used to monitor DS3 transmitter outputs directly, the receive equalizer should be bypassed. Maximum input amplitude under all conditions is 850mV pk. In Case 1 of Figure 3, the signal from the DSX-3 cross-connect feeds directly into RIN. In this mode, the user should set REQB = 0, engaging the equalizer in the data path. Rev.1.20 5 XRT7295AT 0-450 ft. CASE 1: D 0 REQB 0.01mF RIN S 75 X CASE 2: LPF1 0.1mF LPF2 XRT7295AT Existing Off-chip Networks 0-450 ft. D 1 REQB 0.01mF Fixed Equalizer 225 ft. LBO S RIN 75 X Closed For 225-450 ft. Of Cable Figure 3. Receiver Configurations Rev.1.20 6 LPF1 LPF2 XRT7295AT 0.1mF XRT7295AT DS3 SIGNAL REQUIREMENTS AT THE DSX Pulse characteristics are specified at the DSX-3, which is an interconnection and test point referred to as the cross-connect (see Figure 2.) The cross-connect exists at the point where the transmitted signal reaches the distribution frame jack. Table 1 lists the signal requirements. Currently, two isolated pulse template Parameter requirements exist: the ACCUNET T45 pulse template (see Table 2 and Figure 4)and the G.703 pulse template (see Table 3 and Figure 5). Table 2 and Table 3 give the associated boundary equations for the templates. The XRT7295AT correctly decodes any transmitted signal that meets one of these templates at the cross-connect. Specification Line Rate 44.736 Mbps ¦20 ppm Line Code Bipolar with three-0 substitution (B3ZS) Test Load 75 W ¦5% Pulse Shape An isolated pulse must fit the template in NO TAG or Figure 5.1 The pulse amplitude may be scaled by a constant factor to fit the template. The pulse amplitude must be between 0.36vpk and 0.85vpk, measured at the center of the pulse. Power Levels For and all 1s transmitted pattern, the power at 22.368 ± 0.002MHz must be -1.8 to +5.7dBm, and the power at 44.736 ±0.002MHz must be -21.8dBm to -14.3dBm.2, 3 Notes 1 The pulse template proposed by G.703 standards is shown in Figure 5 and specified in Table 3. The proposed G.703 standards further state that the voltage in a time slot containing a 0 must not exceed ± 5% of the peak pulse amplitude, except for the residue of preceding pulses. 2 The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands. 3 The all 1s pattern must be a pure all 1s signal, without framing or other control bits. Table 1. DSX-3 Interconnection Specification Lower Curve Upper Curve Time Equation Time Equation T ± -0.36 0 T±-0.68 0 -0.36 ± T ± +0.28 0.5 (1+sin {p/2}[1+T/0.18]) -0.68 ± T± +0.36 0.5 (1+sin {p/2} [1+T/0.34]) 0.28 ± T 0.11e-3.42(T-0.3) 0.36 ± T 0.05 + 0.407e-1.84(T-0.36) Table 2. DSX-3 Pulse Template Boundaries for ACCUNET T45 Standards (See Figure 4.) Rev.1.20 7 XRT7295AT Normalized Amplitude 1.0 0.8 0.6 0.4 0.2 0 -1.0 -0.5 0 0.5 1.0 1.5 2.0 Time Slots - Normalized To Peak Location Figure 4. DSX-3 Isolated Pulse Template for ACCUNET T45 Standards Lower Curve Upper Curve Time Function Time Function T± -0.36 0 T ± -0.65 0 -0.36 ± T±+0.28 0.5 (1+sin {p/2} [1+T/0.18]) -0.65 ± T± 0 1.05 1-e-4.6(T+0.65) 0.28 ± T 0.11e-3.42(T-0.3) 0 ± T ± 0.36 0.5 (1+sin {p/2} [1+T/0.34]) 0.36 ± T 0.05+0.407e-1.84(T-0.36) Table 3. DSX-3 Pulse Template Boundaries for G.703 Standards (See Figure 5) Normalized Amplitude 1.0 0.8 0.6 0.4 0.2 0 -1.0 -0.5 0 0.5 1.0 1.5 Time Slots - Normalized To Peak Location 2.0 Figure 5. DSX-3 Isolated Pulse Template for G.703 Standards Rev.1.20 8 XRT7295AT STS-1 SIGNAL REQUIREMENTS AT THE STSX Specification Parameter For STS-1 operation, the cross-connect is referred at the STSX-1. Table 4 lists the signal requirements at the STSX-1. Instead of the DS3 isolated pulse template, an eye diagram mask is specified for STS-1 operation (TA-TSY-000253). The XRT7295AT correctly decodes any transmitted signal that meets the mask shown in Figure 6 at the STSX-1. Line Rate 51.84 Mbps Line Code Bipolar with three-0 substitution (B3ZS) Test Load 75W±5% Power Levels A wide-band power level measurement at the STSX-1 interface using a low-pass filter with a 3dB cutoff frequency of at least 200MHz is within -2.7 dBm and 4.7 dBm. Table 4. STSX-1 Interconnection Specification Normalized Amplitude 1.0 0.8 0.6 0.4 0.2 0 -1.0 -0.5 0 0.5 1.0 1.5 2.0 Time Slots - Normalized To Peak Location Figure 6. STSX-1 Isolated Pulse Template for Bellcore TA-TSY-000253 The distribution frame jack may introduce 0.6 ±0.55 dB of loss. This loss may be any combination of flat or shaped (cable) loss. LINE TERMINATION AND INPUT CAPACITANCE The recommended receive termination is shown in Figure 3 The 75 W resistor terminates the coaxial cable with its characteristic impedance. The 0.01mF capacitor to RIN couples the signal into the receive input without disturbing the internally generated DC bias level present on RIN. The input capacitance at the RIN pin is 2.8pF typical. The maximum cable distance between the point where the transmitted signal exits the distribution frame jack and the XRT7295AT device is 450 ft. (see Figure 2.) The coaxial cable (Type 728A) used for specifying this distance limitation has the loss and phase characteristics shown in Figure 7 and Figure 8. Other cable types also may be acceptable if distances are scaled to maintain cable loss equivalent to Type 728A cable loss. LOSS LIMITS FROM THE DSX-3 TO THE RECEIVE INPUT TIMING RECOVERY External Loop Filter Capacitor The signal at the cross-connect may travel through a distribution frame, coaxial cable, connector, splitters, and back planes before reaching the XRT7295AT device. This section defines the maximum distribution frame and cable loss from the cross-connect to the XRT7295AT input. Figure 3 shows the connection to an external 0.1mF capacitor at the LPF1/LPF2 pins. This capacitor is part of the PLL filter. A non-polarized, low-leakage capacitor should be used. A ceramic capacitor with the value 0.1mF ± 20% is acceptable. Rev.1.20 9 XRT7295AT data pattern dependent jitter due to misequalization of the input signal, all create jitter on RCLK. The magnitude of this internally generated jitter is a function of the PLL bandwidth, which in turn is a function of the input 1s density. For higher 1s density, the amount of generated jitter decreases. Generated jitter also depends on the quality of the power supply bypassing networks used. Figure 12 shows the suggested bypassing network, and Table 5 lists the typical generated jitter performance. OUTPUT JITTER The total jitter appearing on the RCLK output during normal operation consists of two components. First, some jitter appears on RCLK because of jitter on the incoming signal. (The next section discusses the jitter transfer characteristic, which describes the relationship between input and output jitter.) Second, noise sources within the XRT7295AT device and noise sources that are coupled into the device through the power supplies and 12 100 80 8 Phase (Degree) Loss (dB) 10 6 4 40 20 2 0 60 1.0 2.0 5.0 10 20 Frequency (MHz) 50 0 100 Figure 7. Loss Characteristic of 728A Coaxial Cable (450 ft.) 1.0 2.0 5.0 10 20 Frequency (MHz) 50 100 Figure 8. Phase Characteristic of 728A Coaxial Cable (450 ft.) JITTER TRANSFER CHARACTERISTIC Parameter Typ Max Unit Generated Jitter1 The jitter transfer characteristic indicates the fraction of input jitter that reaches the RCLK output as a function of input jitter frequency. Table 5 shows Important jitter transfer characteristic parameters. Figure 9 also shows a typical characteristic, with the operating conditions as described in Table 5. Although existing standards do not specify jitter transfer characteristic requirements, the XRT7295AT information is provided here to assist in evaluation of the device. All 1s pattern 1.0 ns peak-to-peak Repetitive “100” pattern 1.5 ns peak-to-peak 0.05 dB 205 kHz Jitter Transfer Characteristic2 Peaking f 3dB Notes 1 Repetitive input data pattern at nominal DSX-3 level with V DD = 5V TA = 25°C. 2 Repetitive “100 ” input at nominal DSX-3 level with V DD = 5V, TA = 25°C. Table 5. Generated Jitter and Jitter Transfer Characteristics Rev.1.20 10 XRT7295AT JITTER ACCOMMODATION LOSS-OF-LOCK DETECTION Under all allowable operating conditions, the jitter accommodation of the XRT7295AT device exceeds all system requirements for error-free operation (BER