SI8445BB-D-IS

Si8440/41/42/45 L O W - P O W E R Q U A D - C H A N N E L D I G I TA L I S O L ATO R Features  High-speed operation DC  Up to 2500 VRMS isolation to 150 Mbps  60-year life at rated working No start-up initialization required voltage  Wide Operating Supply Voltage:  Precise timing (typical) 2.70–5.5 V 109  *Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21. Table 10. IEC Safety Limiting Values1 Max Parameter Symbol Case Temperature TS Safety input, output, or supply current IS Device Power Dissipation2 PD Test Condition JA = 100 °C/W (WB SOIC-16), 105 °C/W (NB SOIC-16), VI = 5.5 V, TJ = 150 °C, TA = 25 °C Min Typ WB SOIC-16 NB SOIC-16 Unit — — 150 150 °C — — 220 210 mA — — 275 275 mW Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4. 2. The Si844x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 15 Rev. 1.7 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 11, 2021 Si8440/41/42/45 Table 11. Thermal Characteristics Typ Parameter Symbol IC Junction-to-Air Thermal Resistance JA Test Condition Min — WB NB SOIC-16 SOIC-16 100 105 Max Unit — ºC/W 450 N ot fo R r N ec ew om m D e es n d ig e ns d Safety-Limiting Current (mA) 500 VDD1, VDD2 = 2.70 V 400 370 VDD1, VDD2 = 3.6 V 300 220 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 430 VDD1, VDD2 = 2.70 V 400 360 VDD1, VDD2 = 3.6 V 300 210 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 16 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.7 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 11, 2021 Si8440/41/42/45 2. Functional Description 2.1. Theory of Operation The operation of an Si844x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si844x channel is shown in Figure 5. Transmitter Receiver A N ot fo R r N ec ew om m D e es n d ig e ns d RF OSCILLATOR MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 5. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 6 for more details. Input Signal Modulation Signal Output Signal Figure 6. Modulation Scheme Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 17 Rev. 1.7 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 11, 2021 Si8440/41/42/45 2.2. Eye Diagram N ot fo R r N ec ew om m D e es n d ig e ns d Figure 7 illustrates an eye-diagram taken on an Si8440. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8440 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited. Figure 7. Eye Diagram 18 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.7 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 11, 2021 Si8440/41/42/45 2.3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an overview of the output states when the Enable pins are active. Table 12. Si84xx Logic Operation Table VI Input1,2 EN Input1,2,3,4 VDDI State1,5,6 VDDO State1,5,6 VO Output1,2 H H or NC P P H L H or NC P P L X7 X7 X7 L P P Hi-Z or L8 H or NC UP P L L UP P Hi-Z or L8 Enabled, normal operation. N ot fo R r N ec ew om m D e es n d ig e ns d X7 Comments X7 P UP Disabled. Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Disabled. Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within Undetermined 1 µs, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1 µs if EN is L. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is operating in noisy environments. 4. No Connect (NC) replaces EN1 on Si8440/45. No Connect replaces EN2 on the Si8445. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V. 6. "Unpowered" state (UP) is defined as VDD = 0 V. 7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled (EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See "3. Errata and Design Migration Guidelines" on page 24 for more details. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 19 Rev. 1.7 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 11, 2021 Si8440/41/42/45 Table 13. Enable Input Truth Table1 Si8440 Si8441 Si8442 Si8445 EN11,2 EN21,2 Operation — H Outputs B1, B2, B3, B4 are enabled and follow the input state. — L Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.3 H X Output A4 enabled and follows the input state. L X Output A4 disabled and Logic Low or in high impedance state.3 X H Outputs B1, B2, B3 are enabled and follow the input state. X L Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.3 H X Outputs A3 and A4 are enabled and follow the input state. L X Outputs A3 and A4 are disabled and Logic Low or in high impedance state.3 X H Outputs B1 and B2 are enabled and follow the input state. X L Outputs B1 and B2 are disabled and Logic Low or in high impedance state.3 — — Outputs B1, B2, B3, B4 are enabled and follow the input state. N ot fo R r N ec ew om m D e es n d ig e ns d P/N Notes: 1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by a 3 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si84xx is operating in a noisy environment. 2. X = not applicable; H = Logic High; L = Logic Low. 3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled (EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See "3. Errata and Design Migration Guidelines" on page 24 for more details. 20 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.7 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 11, 2021 Si8440/41/42/45 2.4. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with