74GTL1655A

74GTL1655A 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION s s s s s s s s s s s HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER: tPD = 4.6 ns (MAX.) A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN TRANSPARENT, LATCHED, OR CLOCKED MODE OPERATING VOLTAGE RANGE: VCC(OPR) = 3.0V to 3.6V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT) OUTPUT IMPEDANCE: IOL = 100mA (MIN) at VCC = 3V (B PORT) HIGH-IMPEDANCE STATE DURING POWER UP AND POWER DOWN up to VCC=BIASVCC=1.5V PERMITT LIVE INSERTION B-PORT PRECHARGED BY BIASVCC R EDUCE NOISE ON THE LINE DURING LIVE INSERTION EDGE RATE-CONTROL INPUT CONFIGURES THE B-PORT OUTPUT RISE AND FALL TIMES BUS HOLD ON DATA INPUTS ELIMINATES THE NEED FOR EXTERNAL PULL-UP/ PULL-DOWN RESISTORS (A PORT) DISTRIBUTED VCC AND GND PIN CONFIGURATION MINIMIZES HIGH-SPEED SWITCHING NOISE IN PARALLEL COMUNICATIONS PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 1655 TSSOP Table 1: Order Codes PACKAGE TSSOP T&R 74GTL1655ATTR Figure 1: Pin Connection bs O DESCRIPTION The 74GTL1655A devices are 16-bit high-drive (100mA), low-output-impedance universal bus transceivers designed for backplane applications. The 74GTL1655A devices provide live-insertion capability for backplane applications by tolerating active signals on the data ports when the devices are powered off. In addition, a biasing pin preconditions the GTL/GTL+ port to minimize disruption to an active backplane. The edge rate-control (VERC) input is provided so the rise and fall time of the B outputs can be configured to optimize for various backplane loading conditions. Data flow in each direction is October 2004 Rev. 1 1/16 let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 74GTL1655A controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLK) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLK is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLK. The output enable (OE) is used to disable both ports simultaneously. Figure 2: Input And Output Equivalent Circuit Active bus-hold circuitry is provided on the A port to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5V, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All input and output are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Table 2: Pin Description PIN N° bs O 1, 2 4, 6, 7, 9, 11, 13, 14, 16 17, 19, 20, 22, 23, 25, 27, 29 31, 32 33 34, 35 36 let o Pr e du o (s) ct SYMBOL so Ob - te le ro P uc d s) t( NAME AND FUNCTION Output Enable Input Data Inputs/Outputs LVTTL Data Inputs/Outputs LVTTL Output Enable Input Output Enable Input Latch Enable Pre-Charge Supply Voltage Data Inputs/Outputs GTL/GTL+ GTL Voltage Reference Input Data Inputs/Outputs GTL/GTL+ Edge Rate Control Latch Enable Clock Input (LOW to HIGH edge triggered) Ground (0V) Positive Supply Voltage 1OEAB, 1OEBA 1A1 to 1A8 2A1 to 2A8 2OEAB, 2OEBA OE 2LEBA, 2LEAB BIAS VCC 2B8 to 2B1 VREF 2A1 to 2A8 VERC 1LEBA, 1LEAB CLK GND VCC 37, 38, 40, 42, 43, 45, 46, 48 41 49, 51, 52, 54, 55, 56, 58, 59 61 62, 63 64 5, 8, 10, 12, 18, 21, 24, 26, 30, 39, 44, 47, 53, 57, 60 3, 15, 28, 50 2/16 74GTL1655A Table 3: Function Table (1) INPUTS OEAB H L L L L L L LEAB X H H L L L L H L CLK X X X A X L H L H X X OUTPUT MODE B Z L H L H B0 (2) Isolation Transparent Transparent Registered Registered Previous State Previous State B0(3) 1) A to B data flow is shown. B to A flow is similar, but uses OEBA, LEBA and CLK 2) Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low 3) Output level before the indicated steady-state input conditions were established Table 4: Output Enable Truth Table INPUTS OE L L L L H OEAB L L H H X OEBA L H L H X A PORT OUTPUTS Table 5: B-Port Edge Rate Control (VERC) Truth Table INPUT VERC LOGIC LEVEL H L bs O let o Pr e du o ct (s) NOMINAL VOLTAGE VCC GND so Ob - Pr te le Active Z Active Z Z od uc B PORT Active Active Z Z Z s) t( OUTPUT B PORT EDGE RATE Slow Fast 3/16 74GTL1655A Figure 3: Logic Diagram bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 4/16 74GTL1655A Table 6: Absolute Maximum Ratings Symbol VCC VIA VIB VOA VOB IIK IOK IOA IOB Tstg TL Supply Voltage, Bias VCC DC Input Voltage A Side, Control Input DC Input Voltage B Side, VERC, VREF DC Output Voltage A Side DC Output Voltage B Side DC Input Diode Current DC Output Diode Current DC Output Current A Side DC Output Current B Side in the Low State Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 - 50 - 50 ± 48 200 -65 to +150 300 Unit V V V V V mA mA mA mA °C °C Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied Table 7: Recommended Operating Conditions Symbol VCC VTT VREF VI VIH VIL IIK IOH IOL Supply Voltage Termination Voltage Supply Voltage Input Voltage High Level Input Voltage Low Level Input Voltage Input Clamp Current Parameter Min. GTL GTL+ GTL GTL+ B port other High Level Output Current bs O Top dt/dVCC let o Low Level Output Current Power -up ramp rate Operating Temperature ro P e uc d (s) t so Ob B port other B port other A port A port B port te le 3.0 1.14 1.35 0.74 0.87 0 0 2 ro P Value Typ. 3.3 1.2 1.5 0.8 1 uc d Max. 3.6 1.26 1.65 0.87 1.1 VTT VCC s) t( V V V V V Unit VREF+0.05 VREF-0.05 0.8 -18 -24 24 100 200 -40 85 V mA mA mA µs/V °C 1) VTT and RTT can be adjusted to adapt backplane impedance if DC recommended IOL ratings are not exceeded 2) VREF can be adjusted to optimize noise margin (typ two-thirds VTT) 5/16 74GTL1655A Table 8: DC Specifications Test Condition Symbol Parameter VCC (V) 3 3 to 3.6 3 3 VOLA Low Level Output Voltage A Port 3 to 3.6 3 3 VOLB Low Level Output Voltage B Port 3 3 3 II Ioff II(HOLD) Input Current Control B Port Power Off Leakage Current Bus Hold A Port Input Current 3.6 3.6 0 3 3 3.6 IOZHB IOZLB IOZ (*) IOZPU** IOZPD** ICC ∆ICC CI 3-State Output Current B Port 3-State Output Current B Port 3-State Output Current A Port 3-State Output Current A Port 3-State Output Current A Port Quiescent Supply Current 3.6 3.6 3.6 0 to 1.5 IO=-100µA IO=-12mA IO=-24mA IO=100µA IO=12mA IO=24mA IO=40mA IO=80mA IO=100mA VI = VCC or GND VI = VTT or GND VI or VO = 0 to 3.6V VI = 0.8V VI = 2V VI = 0 to VCC VO = 1.5V VCC-0.2 2.4 2.2 0.2 0.4 0.55 0.2 0.4 0.5 ±10 V µA V V Value -40 to 85 °C Min. Typ. Max. -1.2 V Unit VIK VOHA High Level Input Voltage High Level Output Voltage A Port VO = VCC or GND VO = 0.5 to 3V OE = LOW VO = 0.5 to 3V OE = LOW VI = VCC or GND IO=0 O bs CO let o ∆ Supply Current except B port Control Input Capacitance Input Capacitance A Port Input Capacitance B Port Pr e od ct u 1.5 to 0 3.6 (s) so Ob VO = 0.4V eP let -75 75 od r uc 20 10 ±10 ±100 s) t( µA µA µA ± 500 µA µA µA µA µA mA -10 ±10 ±50 ±50 10 40 3.6 VIN = VCC or GND One input VCC =0.6V VIN = VCC or GND VO = VCC or GND 3 5 6 1 5 6 8 mA pF pF (*) For I/O ports, the parameter IOZ includes the input leakage current (**) Is also guaranteed when connecting BiasVCC with VCC. 6/16 74GTL1655A Table 9: Live Insertion Specifications Test Condition Symbol Parameter VCC (V) 0 to 3.0 3 to 3.6 0 0 0 to 3.6 0 to 1.5 VO(Bport) = 0 to 1.2V VI(Bias Vcc) = 3 to 3.6V VI(Bias Vcc) = 3.3V VO(Bport) = 0.4V VI(Bias Vcc) = 3 to 3.6V OE = 3.3V OE = 0 to 3.3V 1 -1 100 100 Value -40 to 85 °C Min. Typ. Max. 5 10 1.2 mA µA V µA µA µA Unit ICC (Bias Quiescent Bias Current VCC) VO IO Output Voltage B Port Output Current B Port Table 10: AC Electrical Characteristics for GTL (VCC=3.3 ± 0.3V, VTT=1.2V, VREF=0.8V, VERC=VCC or GND) Value Symbol Parameter Test Condition Min. fMAX tPLH tPHL tPLH tPHL tPLH tPHL tEN tDIS tPLH tPHL tPLH tPHL tPLH tPHL tEN Maximum Frequency A to B or B to A Propagation Delay Time A to B Propagation Delay Time CK to B Propagation Delay Time LEAB to B Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time A to B Propagation Delay Time CK to B VERC=VCC R1=12.5Ω CL=30pF VERC=VCC RL=12.5Ω CL=30pF VERC=VCC RL=12.5Ω CL=30pF 160 1.5 -40 to 85 °C Typ. VERC=VCC RL=12.5Ω CL=30pF bs O tDIS tPLH tPLH tPHL tPLH tPHL tPHL let o Propagation Delay Time LEAB to B Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time B to A Propagation Delay Time CK to A Propagation Delay Time LEBA to A od Pr e ct u VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF (s) so Ob - te le 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ro P uc d Max. s) t( Unit MHz ns ns ns 5.2 6.2 5.5 5.8 5.8 6.4 5.4 6.2 4.3 4.6 4.3 4.9 4.9 4.8 4.8 4.2 4.7 4.8 4 4 4 3.7 ns ns ns ns ns RL=500Ω RL=500Ω RL=500Ω CL=50pF CL=50pF CL=50pF 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns 7/16 74GTL1655A Value Symbol Parameter Test Condition Min. tEN tDIS tSU Enable Delay Time OEBA or OE to A Disable Delay Time OEBA or OE to A Set-up Time RL=500Ω R1=500ΩCL=50pF 1 1 Data before clock Data before LE Ck High Ck Low Data after clock Data after LE Ck High or LOW LE High CK High or Low VERC=VCC VERC=GND 2.7 2.8 2.6 0.4 0.9 3 3 1 1 1 1 -40 to 85 °C Typ. Max. 4.6 6.1 ns Unit ns tH tW Hold Time Pulse duration ns ns Slew rate Slew rate B output both transition (0.6 to 1.3V) tsk Skew between drivers (in Switching in the same direction the same package) Switching in any direction Table 11: AC Electrical Characteristics for GTL+ (VCC=3.3 ± 0.3V, VTT=1.5V, VREF=1.0V, VERC=VCC or GND) Symbol Parameter Test Condition fMAX tPLH tPHL tPLH tPHL tPLH tPHL tEN tDIS Maximum Frequency B to A or A to B Propagation Delay Time A to B Propagation Delay Time CK to B Propagation Delay Time LEAB to B Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time A to B Propagation Delay Time CK to B Propagation Delay Time LEAB to B Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B VERC=VCC RL=12.5Ω CL=30pF VERC=VCC RL=12.5Ω CL=30pF VERC=VCC RL=12.5Ω CL=30pF VERC=VCC RL=12.5Ω CL=30pF O bs tPHL tPLH tPLH tPHL tEN tDIS tPHL tPLH let o Pr e du o ct (s) Ob - so te le Min. 160 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ro P Value Typ. uc d s) t( ns/V ns -40 to 85 °C Max. Unit MHz 5.1 6.5 5.4 6.2 5.7 6.7 5.5 5.8 4.3 4.9 4.0 5.5 4.0 5.4 5.1 4.9 ns ns ns ns ns VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ns ns ns 8/16 74GTL1655A Value Symbol Parameter Test Condition Min. tPLH tPHL tPLH tPHL tPLH tPHL tEN Propagation Delay Time B to A Propagation Delay Time CK to A Propagation Delay Time LEBA to A RL=500Ω RL=500Ω RL=500Ω CL=50pF CL=50pF CL=50pF 1.5 1.5 1.5 1.5 1.5 1.5 RL=500Ω R1=500ΩCL=50pF 1 1 VERC=VCC RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF LE High CK High or Low Data before clock Data before LE 3 3 2.7 2.8 2.6 0.4 0.9 -40 to 85 °C Typ. Max. 4.8 4.7 4.4 4.1 4 3.7 4.2 6.1 1 1 ns ns ns ns Unit Enable Delay Time OEBA or OE to A tDIS Disable Delay Time OEBA or OE to A Slew rate Slew rate B output both transition (0.6 to 1.3V) tW tSU Pulse duration Set-up Time Ck High Ck Low tH tsk Hold Time Data after clock Data after LE Ck High or LOW Skew between drivers (in Switching in the same direction the same package) Switching in any direction Figure 4: Test Circuit For "A" Outputs bs O let o Pr e du o (s) ct so Ob - te le ro P uc d 1 1 s) t( ns/V ns ns ns ns Test Switch Open 6V GND tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) tr=tf