74VCXH16374TTR

74VCXH16374 LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS s s s s s s s s s 3.6V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V tPD = 3.9 ns (MAX.) at VCC = 2.3 to 2.7V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3.0V |IOH| = IOL = 18mA (MIN) at VCC = 2.3V OPERATING VOLTAGE RANGE: VCC(OPR) = 2.3V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES H16374 BUS HOLD PROVIDED ON DATA INPUTS LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R 74VCXH16374TTR PIN CONNECTION DESCRIPTION The 74VCXH16374 is a low voltage CMOS 16 BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 2.3 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs. These 16 bit D-TYPE flip-flops are controlled by two clock inputs (nCK) and two output enable inputs (nOE). On the positive transition of the (nCK), the nQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the 8 outputs (nQ) will be in a normal state (HIGH or LOW logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. February 2003 1/12 74VCXH16374 All inputs and outputs are equipped with protection circuits against static discharge, giving INPUT AND OUTPUT EQUIVALENT CIRCUIT them 2KV ESD immunity and transient excess voltage. PIN DESCRIPTION PIN No 1 SYMBOL 1OE NAME AND FUNCTION IEC LOGIC SYMBOLS 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 3 State Output Enable 24 2OE Input (Active LOW) 25 2CK Clock Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L X : Don‘t Care Z : High Impedance OUTPUT D X X L H Q Z NO CHANGE* L H CK X 2/12 74VCXH16374 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage (OFF State) DC Output Voltage (High or Low State) (note 1) DC Input Diode Current DC Output Diode Current (note 2) DC Output Current Parameter Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to VCC + 0.5 - 50 - 50 ± 50 ± 100 400 -65 to +150 300 Unit V V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current per Supply Pin PD Power Dissipation Tstg TL Storage Temperature Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv Supply Voltage Input Voltage Output Voltage (OFF State) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.3 to 2.7V) Operating Temperature Input Rise and Fall Time (note 1) Parameter Value 2.3 to 3.6 -0.3 to 3.6 0 to 3.6 0 to VCC ± 24 ± 18 -55 to 125 0 to 10 Unit V V V V mA mA °C ns/V 1) VIN from 0.8V to 2V at VCC = 3.0V 3/12 74VCXH16374 DC SPECIFICATIONS (2.7V < VCC < 3.6V unless otherwise specified) Test Condition Symbol Parameter VCC (V) -40 to 85 °C Min. 2.0 2.7 to 3.6 0.8 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 II II(HOLD) Input Leakage Current Input Hold Current 2.7 to 3.6 3.0 3.6 Ioff IOZ Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input 0 2.7 to 3.6 IO=-100 µA IO=-12 mA IO=-18 mA IO=-24 mA IO=100 µA IO=12 mA IO=18 mA IO=24 mA VI = 0 to 3.6V VI = 0.8V VI = 2V VI = 0 to 3.6V VI or VO = 0 to 3.6V VI = VIH or VIL VO = 0 to 3.6V VI = VCC or GND 2.7 to 3.6 2.7 to 3.6 VI or VO = VCC to 3.6V VIH = VCC - 0.6V 75 -75 ± 500 10 ± 10 20 ± 20 750 VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 ±5 75 -75 ± 500 10 ± 10 20 ± 20 750 µA µA µA µA µA VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 ±5 µA V V 0.8 Max. Value -55 to 125 °C Min. 2.0 V Max. Unit VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage ICC ∆ICC 4/12 74VCXH16374 DC SPECIFICATIONS (2.3V < VCC < 2.7V unless otherwise specified) Test Condition Symbol Parameter VCC (V) -40 to 85 °C Min. 1.6 2.3 to 2.7 0.7 2.3 to 2.7 2.3 VOL Low Level Output Voltage 2.3 to 2.7 2.3 II II(HOLD) Ioff IOZ Input Leakage Current Input Hold Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 2.3 to 2.7 2.3 0 2.3 to 2.7 IO=-100 µA IO=-6 mA IO=-12 mA IO=-18 mA IO=100 µA IO=12 mA IO=18 mA VI = 0 to 3.6V VI = 0.7V VI = 1.7V VI or VO = 0 to 3.6V VI = VIH or VIL VO = 0 to 3.6V VI = VCC or GND 2.3 to 2.7 VI or VO = VCC to 3.6V 45 -45 10 ± 10 20 ± 20 VCC-0.2 2.0 1.8 1.7 0.2 0.4 0.6 ±5 45 -45 10 ± 10 20 ± 20 µA VCC-0.2 2.0 1.8 1.7 0.2 0.4 0.6 ±5 µA µA µA µA V V 0.7 Max. Value -55 to 125 °C Min. 1.6 V Max. Unit VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage ICC DYNAMIC SWITCHING CHARACTERISTICS (Ta = 25°C, Input tr = tf = 2.0ns, CL = 30pF, RL = 500Ω) Test Condition Symbol Parameter VCC (V) 2.5 3.3 2.5 3.3 2.5 3.3 VIL = 0V VIH = VCC VIL = 0V VIH = VCC VIL = 0V VIH = VCC Value TA = 25 °C Min. Typ. 0.6 0.8 -0.6 -0.8 1.9 2.2 Max. V V V Unit VOLP VOLV VOHV Dynamic Low Voltage Quiet Output (note 1, 3) Dynamic Low Voltage Quiet Output (note 1, 3) Dynamic High Voltage Quiet Output (note 2, 3) 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 2) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the HIGH state. 3) Parameters guaranteed by design. 5/12 74VCXH16374 AC ELECTRICAL CHARACTERISTICS (CL = 30pF, RL = 500Ω, Input tr = tf = 2.0ns) Test Condition Symbol Parameter VCC (V) 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 -40 to 85 °C Min. 1.0 0.8 1.0 0.8 1.0 0.8 1.5 1.5 1.0 1.0 1.5 1.5 200 250 Max. 3.9 3.0 4.6 3.5 3.8 3.5 Value -55 to 125 °C Min. 1.0 0.8 1.0 0.8 1.0 0.8 1.5 1.5 1.0 1.0 1.5 1.5 180 235 Max. 4.7 3.5 5.1 4.3 4.6 4.3 ns ns ns ns ns ns MHz 0.5 0.5 ns Unit tPLH tPHL tPZL tPZH tPLZ tPHZ ts th tw fMAX Propagation Delay Time CK to Qn Output Enable Time Output Disable Time Setup TIme, HIGH or LOW level Dn to CK Hold Time High or LOW level Dn to CK CK Pulse Width, HIGH Clock Pulse Frequency tOSLH tOSHL Output To Output Skew Time (note1, 2) 0.5 0.5 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 2.5 or 3.3 2.5 or 3.3 2.5 or 3.3 VIN = 0 or VCC VIN = 0 or VCC fIN = 10MHz VIN = 0 or VCC Value TA = 25 °C Min. Typ. 6 7 20 Max. pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit) 6/12 74VCXH16374 TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ (VCC = 3.0 to 3.6V) tPZL, tPLZ (VCC = 2.3 to 2.7V) tPZH, tPHZ CL = 30 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open 6V 2VCC GND WAVEFORM SYMBOL VALUES Symbol 3.0 to3.6V VIH VM VX VY 2.7V 1.5V VOL + 0.3V VOH - 0.3V VCC 2.3 to 2.7V VCC VCC/2 VOL + 0.15V VOH - 0.15V 7/12 74VCXH16374 WAVEFORM 1 : nCK TO Qn PROPAGATION DELAYS, nCK MAXIMUM FREQUENCY, Dn TO nCK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 8/12 74VCXH16374 WAVEFORM 3 : nCK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) 9/12 74VCXH16374 TSSOP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.50 6.0 0.5 BSC 8˚ 0.75 0˚ 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8˚ 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7065588C 10/12 74VCXH16374 Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 11/12 74VCXH16374 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 12/12