A6984
36 V, 400 mA automotive synchronous step-down
switching regulator
Datasheet - production data
Applications
Car body and ADAS applications (LCM)
Car audio and low noise applications (LNM)
Description
VFDFPN10 4 x 4 x 1.0 mm
The A6984 is a step-down monolithic switching
regulator able to deliver up to 400 mA DC. The
output voltage adjustability ranges from 0.9 V. The
fixed 3.3 V VOUT requires no external resistor
divider. The “low consumption mode” (LCM) is
designed for applications active during car
parking, so it maximizes the efficiency at light load
with controlled output voltage ripple. The “low
noise mode” (LNM) makes the switching
frequency almost constant over the load current
range, serving low noise application
specifications such as car audio/sensors. The
PGOOD open collector output can implement
output voltage sequencing during the power-up
phase. The synchronous rectification, designed
for high efficiency at medium-heavy load, and the
high switching frequency capability make the size
of the application compact. Pulse-by-pulse
current sensing on the low-side power element
implements effective constant current protection.
The package lead finishing guarantees side
solderability, thus allowing visual inspection
during manufacturing.
Features
AEC-Q100 qualified
400 mA DC output current
4.5 V to 36 V operating input voltage
Synchronous rectification
Low consumption mode or low noise mode
75 µA IQ at light load (LCM VOUT = 3.3 V)
13 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 600 kHz)
Output voltage adjustable from 0.9 V
No resistor divider required for 3.3 V VOUT
VBIAS maximizes efficiency at light load
350 mA valley current limit
Constant on-time control scheme
PGOOD open collector
Thermal shutdown
Figure 1. Application schematic
/ A6984
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Contents
A6984
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 10
4
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1
Maximum output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.2
Leading network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2
Control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
Optional virtual ESR network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output voltage accuracy and optimized resistor divider. . . . . . . . . . . . . . . . . . . . . 24
4.4
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5
Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6
5
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4.5.1
Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.2
Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6.1
LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6.2
LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.7
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.8
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.9
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.10
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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A6984
Contents
5.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1
Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.2
COUT specification and loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6
Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7
Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1
VFDFPN10 4 x 4 x 1.0 mm package information . . . . . . . . . . . . . . . . . . . 44
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Pin settings
A6984
1
Pin settings
1.1
Pin connection
Figure 2. Pin connection (top view)
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1.2
Pin description
Table 1. Pin description
N°
Pin
1
PGOOD
2
FB
3
TON
4
EN
5
GND
6
LX
Switching node
7
VIN
DC input voltage
8
VCC
Embedded regulator output that supplies the main switching controller.
Connect an external 1 F capacitor for proper operation.
An integrated LDO regulates VCC = 3.3 V if VBIAS voltage is < 2.4 V.
VCC is connected to VBIAS through a MOSFET switch if VBIAS > 3.2 V and the embedded
LDO is disabled to increase the light load efficiency.
9
VBIAS
Typically connected to the regulated output voltage. An external voltage reference can be
used to supply the analog circuitry to increase the efficiency at light load. Connect to GND if
not used.
10
LNM
4/49
Description
The open collector output is driven low when the FB voltage is below the VPGD L threshold
(see Table 5).
Inverting input of the error amplifier
A resistor connected between this pin and VIN sets the switching frequency.
Enable pin. A logical active high signal enables the device. Connect this pin to VIN if not used.
Power GND
Connect to VCC for low noise mode (LNM) / to GND for low consumption mode (LCM)
operation.
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A6984
1.3
Pin settings
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions
above those indicated in Table 5 of this specification is not implied.
Exposure to absolute maximum rating conditions may affect device reliability.
Table 2. Absolute maximum ratings
Symbol
Description
Min.
Max.
Unit
dVIN/dt (1)
Input slew rate
-
0.1
V/µs
VIN
-
38
device ON
VIN + 0.3
device OFF
25
LX
EN
VIN + 0.3
TON
-0.3
VCC
VBIAS
V
6
see Table 1
PGOOD
FB
VCC + 0.3
LNM
TJ
Operating temperature range
-40
150
TSTG
Storage temperature range
-
-55 to 150
TLEAD
Lead temperature (soldering 10 sec.)
-
260
IHS, ILS
High-side / low-side RMS switch current
-
400
°C
mA
1. Maximum slew rate should be limited as detailed in Section 5.1.
1.4
Thermal data
Table 3. Thermal data
Symbol
Rth JA
Parameter
Thermal resistance junction ambient
(device soldered on STMicroelectronics evaluation board)
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Value
Unit
50
C/W
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Pin settings
1.5
A6984
ESD protection
Table 4. ESD protection
Symbol
ESD
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Test condition
Value
Unit
HBM
2
kV
MM
200
CDM non-corner pins
500
CDM corner pins
750
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V
A6984
2
Electrical characteristics
Electrical characteristics
TJ = -40 to 125 °C, VIN = VEN = 12 V, VBIAS = 3.3 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol
VIN
Parameter
Test condition
Typ.
Max. Unit
-
4.5
Rising edge VCC regulator
VBIAS = GND
-
3.1
3.8
4.5
Falling edge VCC regulator
VBIAS = GND
-
2.9
3.6
4.3
Fixed output voltage valley
regulation
FB = VCC, no load
-
3.23
3.3
3.37
Adjustable output voltage
valley regulation
No load
-
0.88
0.9
0.92
RDSON HS High-side RDSON
ISW = 0.1 A
-
0.6
1.3
2.2
RDSON LS Low-side RDSON
ISW = 0.1 A
-
0.4
1.0
1.9
VIN = VEN = 4.5 V
-
100
200
400
-
350
400
470
(1)
12
27
46
VIN_UVLO
VOUT
VFB
TOFF
Operating input voltage range
Min.
UVLO thresholds
Minimum Low-side conduction
time
36
V
ns
Current limit and zero crossing comparator
IVY
IZCD
Valley current limit
-
Zero crossing current threshold -
mA
VCC regulator
VCC
VBIAS
VCC voltage
VFB = 1 V, VBIAS = GND
-
3
3.8
4.6
VBIAS falling threshold
-
-
2.4
2.6
2.8
VBIAS rising threshold
-
-
2.6
2.9
3.2
EN = GND
-
3
13
22
V
Power consumption
ISHTDWN
Shutdown current from VIN
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Electrical characteristics
A6984
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
11
26
41
(2)
90
160
230
LNM - SWO
VREF < VFB < VOVP
VBIAS = 3.3 V
-
11
26
42
LNM - NO SWO
VREF < VFB < VOVP
VBIAS = GND
-
200
320
440
(2)
80
150
200
-
180
300
390
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
IQ OPVIN
Quiescent current from VIN
IQ OPVBIAS Quiescent current from VBIAS
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
LNM - SWO
VREF < VFB < VOVP
VBIAS = 3.3 V
(2)
Max. Unit
A
Enable
EN
EN thresholds
EN hysteresis
Device inhibited
- 1.1
-
-
Device enabled
-
-
-
2.6
(3)
-
650
-
mV
%
-
V
Overvoltage protection
VOVP
Overvoltage trip (VOVP/VREF)
Rising edge
18
23
28
PGOOD
VPGD L
VPGD H
VPGOOD
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Power good LOW threshold
Power good HIGH threshold
PGOOD open collector output
VFB rising edge
(PGOOD high impedance)
(3)
-
90
-
VFB falling edge
(PGOOD low impedance)
-
84
88
92
Internal FB rising edge
(PGOOD low impedance)
VFB = VCC
-
118
123
128
(3)
-
100
-
VIN > VIN_UVLO_H,
VFB=GND
4 mA sinking load
-
-
-
0.6
V
2.9 < VIN < VIN_UVLO_H
100 A sinking load
-
-
-
0.6
V
Internal FB falling edge
(PGOOD high impedance)
VFB = VCC
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A6984
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
Thermal shutdown
TSHDWN
Thermal shutdown temperature -
(3)
-
150
-
C
THYS
Thermal shutdown hysteresis
(3)
-
20
-
C
-
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. LCM enables SLEEP mode (part of the internal circuitry is disabled) at light load.
3. Not tested in production.
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Datasheet parameters over the temperature range
3
A6984
Datasheet parameters over the temperature range
100% of the population in the production flow is tested at three different ambient
temperatures (-40 °C; 25 °C, 125 °C) to guarantee datasheet parameters within the junction
temperature range (-40 °C to 125 °C).
Device operation is guaranteed when the junction temperature is within the -40 °C to 150 °C
temperature range. The designer can estimate the silicon temperature increase with respect
to the ambient temperature evaluating the internal power losses generated during the
device operation.
However, the embedded thermal protection disables the switching activity to protect the
device in case the junction temperature reaches the TSHTDWN (+150 °C min) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+125 °C to avoid triggering the thermal shutdown protection during the testing phase due to
self-heating.
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A6984
4
Device description
Device description
The A6984 device is based on a “Constant On-Time” (COT) control scheme with frequency
feed-forward correction over the VIN range. As a consequence the device features fast load
transient response, almost constant switching frequency operation over the input voltage
range and simple stability control.
The switching frequency can be adjusted in the 250 kHz - 600 kHz range.
The LNM (low noise mode) implements constant PWM control to minimize the voltage ripple
over the load range, the LCM (low consumption mode) pulse skipping technique to increase
the efficiency at the light load.
No external resistor divider is required to regulate fixed 3.3 V output voltage, connecting FB
to the VCC pin and VBIAS to the regulated output voltage (see Figure 1 on page 1). An
external voltage divider implements the output voltage adjustability.
The switchover capability of the internal regulator derives a portion of the quiescent current
from an external voltage source (VBIAS pin is typically connected to the regulated output
voltage) to maximize the efficiency at the light load.
The device main internal blocks are shown in the block diagram in Figure 6 on page 15:
The bandgap reference voltage
The on-time controller
A “pulse width modulation” (PWM) comparator and the driving circuitry of the
embedded power elements
The SMPS controller block
The soft-start block to ramp the current limitation
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The current limitation circuit to implement the constant current protection, sensing
pulse-by-pulse low-side switch current.
A circuit to implement the thermal protection function
LNM pin strapping sets the LNM/LCM mode
The PG (“Power Good”) open collector output
The thermal protection circuitry
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Device description
A6984
Figure 3. A6984 block diagram
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A6984
Device description
4.1
Output voltage adjustment
No external resistor divider is required to regulate fixed 3.3 V output voltage, connecting FB
to the VCC pin and VBIAS to the regulated output voltage (see Figure 1 on page 1). An
external voltage divider otherwise implements the output voltage adjustability.
Figure 4. Internal voltage divider for 3.3 V output voltage
A6984
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The error amplifier reference voltage is 0.9 V typical.
The output voltage is adjusted accordingly with the following formula (see Figure 6):
Equation 1
R3
V OUT = 0.9 1 + -------
R2
4.1.1
Maximum output voltage
The constant on-time control scheme naturally requires a minimum cycle-by-cycle off time
to sense the feedback voltage and properly driving the switching activity.
The A6984 minimum off time, as reported in Table 2 on page 5, is 300 nsec typical and
400 nsec max.
The control loop generates the proper PWM signal to regulate the programmed output
voltage over the application conditions. Since the power losses are proportional to the
delivered output power, the duty cycle increases with the load current request.
The fixed minimum off time limits the maximum duty cycle, so the maximum output voltage,
depending on the selected switching frequency (see Section 4.2).
Figure 5 shows the worst case scenario for maximum output voltage limitation over the input
voltage range, that happens at the maximum current request and considering the upper
datasheet limit time for the minimum off time parameter.
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Device description
A6984
Figure 5. Maximum output voltage vs. input voltage range at ILOAD = 400 mA
4.1.2
Leading network
The small signal contribution of a simple voltage divider is:
Equation 2
R2
G DIV s = -------------------R2 + R3
A small signal capacitor in parallel to the upper resistor (see C3 in Figure 6) of the voltage
divider implements a leading network (fzero < fpole) that can improve the dynamic regulation
for boundary application conditions (high fSW / high duty cycle conversion) and improves the
SNR for the feedback comparator operation, entirely coupling the high frequency output
voltage ripple without the resistive divider attenuation.
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A6984
Device description
Figure 6. A6984 application circuit
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Laplace transformer of the leading network:
Equation 3
R2
1 + s R 3 C R3
G DIV s = -------------------- ----------------------------------------------------------R2 R3
R2 + R3
1 s
- C R3
+ ------------------R2 + R3
where:
Equation 4
1
f Z = -------------------------------------2 R 3 C R3
1
f P = --------------------------------------------------R2 R3
2 -------------------- C R3
R2 + R3
fZ fP
The R2, R3 compose the voltage divider. CR3 is calculated as (see Section 5.3.2: COUT
specification and loop stability on page 39 for COUT selection):
Equation 5
C R3 = 28 10
–3
V OUT C OUT
---------------------------------R3
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Device description
4.2
A6984
Control loop
The A6984 device is based on a constant on-time control loop with frequency feed-forward
correction over the input voltage range. As a consequence the on-time generator
compensates the input voltage variations in order to adapt the duty cycle and so keeping the
switching frequency almost constant over the input voltage range.
The general constraint for converters based on the COT architecture is the selection of the
output capacitor with an ESR high enough to guarantee a proper output voltage ripple for
the noiseless operation of the internal PWM comparator. The A6984 innovative control loop
otherwise supports the output ceramic capacitors with the negligible ESR.
The device generates a TON duration switching pulse as soon as the voltage ripple drops
below the valley voltage threshold.
The A6984 on-time is internally generated as shown in Figure 7.
Figure 7. TON generator
where RTON represents the external resistor connected between the VIN and TON pins, CINT
is the integrated capacitor, CPAR the pin parasitic capacitor of the board trace at the pin 3.
The overall contribution of the CPAR and CINT for the A6984 device soldered on the
STMicroelectronics evaluation board is 7.5 pF typical but the precise value depends on the
parasitic capacitance connected at the pin 3 (TON) that may depend on the implemented
board layouts.
As a consequence, a further fine tune of the RTON value with the direct scope measurement
is required for precise fSW adjustment accordingly with the designed board layout.
The ON time can be calculated as:
Equation 6
0.9 R TON C TON 0.9 R TON C INT + C PAR 0.9 R TON 7.5pF
T ON = ----------------------------------------------- = ----------------------------------------------------------------------- -----------------------------------------------V IN
V IN
V IN
The natural feedforward of the generator in Figure 7 corrects the fixed TON time with the
input voltage to achieve almost constant switching frequency over the input voltage range.
On the other hand, the PWM comparator (see Figure 3 on page 12) in the closed loop
operation modulates the TOFF time, given the programmed TON, to compensate conversion
losses (i.e. conduction, switching, inductor losses, etc.) that are proportional to the output
current.
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A6984
Device description
As a consequence the switching frequency slightly depends on the conversion losses:
Equation 7
D REAL I OUT
f SW I OUT = ---------------------------------T ON
where DREAL is the real duty cycle accounting conduction losses:
Equation 8
V OUT + R ON_LS + DCR I OUT
D REAL I OUT = -----------------------------------------------------------------------------------V IN + R ON_LS – R ON_HS I OUT
RON_HS and RON_LS represent the RDSON value of the embedded power elements (see
Table 5 on page 7) and DCR the equivalent series resistor of the selected inductor.
Finally from Equation 7 and Equation 8:
Equation 9
1 V IN D REAL I OUT
R TON = -------- -----------------------------------------------f SW C TON
0.9
where fSW is the desired switching frequency at a certain IOUT load current level.
Figure 8 shows the estimated fSW variation over the load range assuming the typical
RDSON of the power elements, DCR = 420 m (see Section 6 on page 40 for details on the
selected inductor for the reference application board.) and RTON = 1 M.
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Device description
A6984
Figure 8. fSW variation over the load range
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A general requirement for applications compatible with humid environments, is to limit the
maximum resistor value to minimize the resistor variation determined by the leakage path.
An optional external capacitor CTON >> (CINT + CPAR) connected as shown in Figure 9 helps
to limit the RTON value and also minimizes the fSW variation with the p.c.b. parasitic
components CPAR.
Figure 9. TON generator with optional capacitor
Figure 10, Figure 11, Figure 12, and Figure 13 show the numeric example to program the
switching frequency accordingly with the RTON, CTON pair selection.
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Device description
The eDesignSuite online tool supports the A6984 and RTON, CTON dimensioning for proper
switching frequency selection, see
http://www.st.com/content/st_com/en/support/resources/edesign.html).
Figure 10. Example to select RTON, CTON for VOUT = 1.8 V
Figure 11. Example to select RTON, CTON for VOUT = 3.3 V
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Device description
A6984
Figure 12. Example to select RTON, CTON for VOUT = 5 V
Figure 13. Example to select RTON, CTON for VOUT = 12 V
4.3
Optional virtual ESR network
A standard COT loop requires a high ESR output capacitor to generate a proper PWM
signal.
The A6984 architecture naturally supports output ceramic capacitors with the negligible
ESR generating an internal voltage ramp proportional to the inductor current to emulate
a high ESR output capacitor for the proper PWM comparator operation.
The control scheme is designed to guarantee the minimum signal for the PWM comparator
cycle-by-cycle operation with controlled duty cycle jitter, that is a natural duty cycle dithering
that helps to reduce the switching noise emission for EMC.
If required, an optional external virtual ESR network (see Figure 14 can be designed to
generate a higher signal for the PWM comparator operation and remove the duty cycle
dithering. This network requires the external voltage divider to set the output voltage and
supports the LNM and LCM device operation.
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Device description
Figure 14. Virtual ESR network
The CDC capacitor decouples the feedback DC path through the RCOT so the output voltage
is adjusted accordingly with Section 4.1 on page 13.
Basically the network RCOT, CCOT generates a voltage signal proportional to the inductor
current ripple and superimposed with the real partitioned output voltage that increases the
SNR at the input of the PWM comparator. As a consequence the PWM converter
commutation is clean, removing the duty cycle dithering.
For the purpose of the signal generated by the RCOT and CCOT the output capacitor
represents a virtual ground so the equivalent small signal circuit of the output of the virtual
ESR network is shown in Figure 15.
Figure 15. Virtual ESR equivalent circuit
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Device description
A6984
The switching activity drives the inductor voltage so the small signal transfer function can be
calculated as:
Equation 10
1
---------------------1
1
------- + ------R
R
2
3
1
vFB(s)
s L + DCR
H(s) = ------------------- = ----------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- -------------------------------------------------1
1
1
1
iL(s)
R COT + ----------------------------------------------------------------------------------- s C COT + -------------------------------------------------- --------------------- + ---------------------sC
1
1
1
1
1
DC ------- + --------------------------- + ---------------------+ -------------------------------------------------sC
COT
R
R
1
sC
1
1
1
2
3
DC ------- + --------------------------- + ---------------------R
R
1
1
sC
3
2
DC ------- + ------R
R
2
3
Equation 10 can be simplified as follows:
Equation 11
C DC
vFB(s)
s L + DCR s
H(s) = ------------------ = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------iL(s)
1
1
------- + ------
1
1
R2 R3
1 + s R COT + --------------------- C DC 1 + s ------------------------------------------ C COT
1
1
1
1
1
------------ + -------
- + ------- + ---------------
R 2 R 3 R COT
R 2 R 3
The pole splitting is guaranteed by the condition:
Equation 12
C DC 10 C COT
R 2 xR 3
R COT 10 --------------------
R 2 + R 3
In case:
Equation 13
f PL
1
L
f z = ----------- ------------- « fsw
2 DCR
1
= -------------------------------------------------------------------------- « fsw
1
2 R COT + --------------------- C DC
1
1
------- + ------R2 R3
1
f PH = ----------------------------------------------------------------------------------- « fsw
1
2 ------------------------------------------ C COT
1
1
1
------ + ------- + -------------- R 2 R 3 R COT
Equation 10 can be simplified as:
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A6984
Device description
Equation 14
vFB(s)
L
ESR VRT = H(s) s 2 fsw = ------------------
= --------------------------------- iL(s) s 2 fsw
R COT C COT
which represents the virtual ESR of the network in Figure 14.
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Device description
A6984
As a consequence, the injected triangular voltage ripple in the FB is:
Equation 15
V IN – V OUT V OUT 1
VFB RIPPLE V IN = IL RIPPLE ESR VRT = ---------------------------------- -------------- --------R COT C COT V IN fsw
that does not depend on the R2, R3, CDC, L and DCR.
A virtual ESR network able to guarantee a peak-to-peak signal higher than 20 mV at the FB
pin removes any duty cycle dithering at the switching node.
Output voltage accuracy and optimized resistor divider
The constant on-time control scheme implements valley output voltage regulation: the
internal comparator monitors the FB voltage cycle-by-cycle and generates a fixed TON pulse
if the sensed voltage drops below the internal voltage reference (VEAFB = 0.9 V typical).
The virtual ESR network generates a signal proportional to the inductor current that is AC
coupled to the FB pin through the CDC capacitor (refer to Section 4.3 for dimensioning rules)
and superimposed on the voltage divider contribution as shown in Figure 16.
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Device description
Figure 16. Virtual ESR signal generation in CCM operation
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Device description
A6984
In the CCM operation, the average value for the triangular signal in Equation 15 is:
Equation 16
1 V IN – V OUT V OUT 1
VFB AVG V IN = --- ---------------------------------- -------------- --------2 R COT C COT V IN fsw
so the output voltage is calculated as:
Equation 17
R3
V OUT = 0.9 + VFB AVG V IN 1 + -------
R 2
that shows the average injected ripple entered in the divider calculation.
In addition, since the virtual FB ripple depends on the input voltage (the switching frequency
is almost constant, see Section 4.2 on page 16) its contribution affects the average output
voltage regulation.
In the low noise mode (for LNM operation refer to Section 4.6.2 on page 32) the regulator
operates in the forced PWM over the load range so:
Equation 18
R 3
V
OUTMIN = 0.9 + VFB AVG V INMIN 1 + -----R 2
R3
V
= 0.9 + VFB AVG V INMAX 1 + -------
OUTMAX
R2
and the accuracy can be estimated as:
Equation 19
R3
V INMAX – V OUT V INMIN – V OUT
V OUT
1
V OUT – LNM = --- ------------------------------------------------ --------------------------------------- – ------------------------------------- 1 + -------
2 fsw R COT C COT
V INMAX
V INMIN
R2
In the low consumption mode (for LCM operation refer to Section 4.6.1 on page 32) the
regulator skips pulses at light load to increase the efficiency.
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Device description
Figure 17. Virtual ESR signal generation in LCM operation at light load
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In LCM operation the virtual ripple contributes to the regulated output voltage as follows:
Equation 20
T PULSE
R3
R3
1
V
- 1 + ------- 0.9 1 + -------
OUTMIN = 0.9 + --2- VFB RIPPLE V IN -------------------
T BURST
R 2
R 2
R3
V
= 0.9 + VFB AVG V INMAX 1 + -------
OUTMAX
R2
since TPULSE 3.2 V and the embedded
LDO is disabled to increase the light load efficiency.
4.6.1
LCM
LCM operation satisfies the requirements of battery-powered applications where it is crucial
to increase efficiency at the light load.
In order to minimize the regulator quiescent current request from the input voltage, the
VBIAS pin can be connected to an external voltage source in the range 3 V < VBIAS < 5.5 V.
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current
drawn from the input voltage can be calculated as:
Equation 23
V BIAS
1
I Q VIN = I Q OP VIN + ----------------- -------------- I Q OP VBIAS
A6984 V IN
where IQ OP VIN, IQ OP VBIAS are defined in Table 5: Electrical characteristics on page 7 and
A6984 is the efficiency of the conversion in the working point.
4.6.2
LNM
Equation 23 is also valid when the device works in LNM and it can boost the efficiency at
medium load since the regulator always operates in continuous conduction mode.
4.7
Overcurrent protection
The current protection circuitry features a constant current protection, so the device limits
the maximum current (see Table 5: Electrical characteristics on page 7) in overcurrent
condition.
The low-side switch pulse-by-pulse current sensing, called “valley”, implements the constant
current protection. In overcurrent condition the internal logic keeps the low-side switch
conducting as long as the switch current is higher than the valley current threshold.
As a consequence, the maximum DC output current is:
Equation 24
I RIPPLE
V IN – V OUT
I MAX = I VALLEY_TH + -------------------- = I VALLEY_TH + ------------------------------ T ON
L
2
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Device description
Figure 24. Constant current operation in dynamic short-circuit
Figure 25. Valley current sense implements constant current protection
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Device description
4.8
A6984
PGOOD
The internal circuitry monitors the regulated output voltage and keeps the PGOOD open
collector output in low impedance as long as the feedback voltage is below the VPGD L
threshold (see Table 5 on page 7).
Figure 26. PGOOD behavior during soft-start time with electronic load
The PGOOD is driven low impedance if VFB = VCC (internal voltage divider, see Section 4.1
on page 13) and VBIAS > VPGD H threshold (see Table 5).
The VPGD H threshold has no effect on PGOOD behavior in case the external voltage divider
is being used.
4.9
Overvoltage protection
The overvoltage protection monitors the FB pin and enables the low-side MOSFET to
discharge the output capacitor if the output voltage is 20% over the nominal value. A new
soft-start takes place after the OVP event ends.
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Device description
Figure 27. Overvoltage operation
The OVP feature is a second level protection and should never be triggered in normal
operating conditions if the system is properly dimensioned. In other words, the selection of
the external power components and the dynamic performance should guarantee an output
voltage regulation within the overvoltage threshold even during the worst case scenario in
term of load transitions.
The protection is reliable and also able to operate even during normal load transitions for
a system whose dynamic performance is not in line with the load dynamic request. As
a consequence the output voltage regulation would be affected.
In Figure 27 the PGOOD output is driven in low impedance (refer to Section 4.8) as long as
the OVP event is present (VFB = VCC, that is an internal resistor divider for VOUT = 3.3 V).
4.10
Thermal shutdown
The shutdown block disables the switching activity if the junction temperature is higher than
a fixed internal threshold (150 °C typical). The thermal sensing element is close to the
power elements, ensuring fast and accurate temperature detection. A hysteresis of
approximately 20 °C prevents the device from turning ON and OFF continuously. When the
thermal protection runs away a new soft-start cycle will take place.
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Design of the power components
A6984
5
Design of the power components
5.1
Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depend on the ESR value, so usually low ESR
capacitors (like multilayer ceramic capacitors) have a higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 25
2
2
2D
D
I RMS = I O D – --------------- + ------2
Where IO is the maximum DC output current, D is the duty cycles, is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to IO/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 26
V OUT + V LOW_SIDE
D MAX = -------------------------------------------------------------------------------------------------V INMIN + V LOW_SIDE – V HIGH_SIDE
and
Equation 27
V OUT + V LOW_SIDE
D MIN = ---------------------------------------------------------------------------------------------------V INMAX + V LOW_SIDE – V HIGH_SIDE
Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches.
The input filter value must be dimensioned to safely handle the input RMS current and to
limit the VIN ramp-up slew-rate to 0.1 V/µs maximum.
The peak-to-peak voltage across the input filter can be calculated as:
Equation 28
IO
D
D
V PP = ----------------------- 1 – ---- D + ---- 1 – D + ESR I O
C IN f SW
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
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Design of the power components
Equation 29
IO
D
D
C IN = ------------------------- 1 – ---- D + ---- 1 – D
V PP f SW
Considering this function has its maximum in D = 0.5:
Equation 30
IO
C IN_MIN = ---------------------------------------------2 V PP_MAX f SW
Typically CIN is dimensioned to keep the maximum peak-to-peak voltage across the input
filter in the order of 5% VIN_MAX.
Table 6. Input capacitors
Manufacture
TDK
Taiyo Yuden
5.2
Series
Size
C3225X7S1H106M
1210
C3216X5R1H106M
1206
UMK325BJ106MM-T
1210
Cap value (F)
Rated voltage (V)
10
50
Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 5.3: Output capacitor selection). Usually the inductor value is
selected in order to keep the current ripple lower than 20% - 40% of the output current over
the input voltage range. The inductance value can be calculated by the following equation:
Equation 31
V IN – V OUT
V OUT
I L = ------------------------------ T ON = -------------- T OFF
L
L
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 5.1 to calculate minimum duty). So fixing IL = 20% to 40% of the maximum
output current, the minimum inductance value can be calculated:
Equation 32
V OUT 1 – D MIN
L MIN = ---------------- ----------------------F SW
I MAX
where FSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IO = 0.4 A and FSW = 600 kHz the minimum
inductance value to have IL = 30% of IO is about 33 µH.
The peak current through the inductor is given by:
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Design of the power components
A6984
Equation 33
I L
I L PK = I O + -------2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 7 some inductor part numbers are listed.
Table 7. Inductors
Manufacturer
Coilcraft
Series
Inductor value (H)
Saturation current (A)
LPS6225
47 to 150
0.98 to 0.39
LPS5030
10 to 47
1.4 to 0.5
5.3
Output capacitor selection
5.3.1
Output voltage ripple
The triangular shape current ripple (with zero average value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalent resistive component (ESR). As a consequence the output capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be calculated as:
Equation 34
I MAX
V OUT = ESR I MAX + ------------------------------------8 C OUT f SW
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multilayer ceramic capacitor (MLCC).
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.12 A, fSW = 600 kHz (resulting by the
inductor value) and COUT = 4.7 F MLCC:
Equation 35
V OUT
I MAX
1
1
0.12
5mV
------------------ -------------- ------------------------------------- = -------- ------------------------------------------------- = ------------- = 0.15%
3.3 8 4.7F 600kHz
V OUT V OUT 8 C OUT f SW
3.3
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies a high slew
rate load transient, the system bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
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Design of the power components
In Table 8 some capacitor series are listed.
Table 8. Output capacitors
Manufacturer
Series
Cap value (F)
Rated voltage (V)
ESR (m)
GRM32
22 to 100
6.3 to 25
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