AST1S31HF

AST1S31HF Up to 4 V, 3 A step-down 2.3 MHz switching regulator for automotive applications Datasheet - production data Applications  Designed for automotive systems  Battery powered applications  Car body applications Description Features The AST1S31HF is an internally compensated 2.3 MHz fixed frequency PWM synchronous stepdown regulator. The AST1S31HF operates from 2.8 V to 4 V input, while it regulates an output voltage as low as 0.8 V and up to VIN.  AECQ100 qualified  3 A DC output current  2.8 V to 4 V input voltage The AST1S31HF device integrates a 70 m highside switch and a 55 m synchronous rectifier allowing very high efficiency with very low output voltages.  Output voltage adjustable from 0.8 V  2.3 MHz switching frequency  Internal soft-start and enable  Integrated 70 m and 55 m power MOSFETs  All ceramic capacitor  Power Good (POR) The peak current mode control with internal compensation deliver a very compact solution with a minimum component count. The AST1S31HF is available in a 3 mm x 3 mm, 8-lead VFDFPN package.  Cycle-by-cycle current limiting  Current foldback short-circuit protection  VFDFPN 3 x 3 - 8L package Figure 1. Application circuit / 9,1 9,16: 9287 6: 9,1$ &LQBD (1 5 $676+) 9)% &LQBVZ &RXW 3* *1' 5 August 2020 This is information on a product in full production. DocID026968 Rev 4 1/33 www.st.com Contents AST1S31HF Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Datasheet parameters over the temperature range . . . . . . . . . . . . . . . . 7 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 5.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6 Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/33 DocID026968 Rev 4 AST1S31HF Contents 9.1 VFDFPN8 (3 x 3 x 1.0 mm) package information . . . . . . . . . . . . . . . . . . . 30 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID026968 Rev 4 3/33 33 Pin settings AST1S31HF 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) 1.2 Pin description Table 1. Pin description 4/33 No. Type Description 1 VINA 2 EN Enable input. With EN higher than 1.5 V the device in ON and with EN lower than 0.5 V the device is OFF. 3 FB Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from Vout to the FB pin. 4 AGND Unregulated DC input voltage Ground Open drain Power Good (POR) pin. It is released (open drain) when the output voltage is higher than 0.92 * VOUT with a delay of 170 s. If the output voltage is below 0.92 * VOUT, the POR pin goes to low impedance immediately. If not used, it can be left floating or to GND. 5 PG 6 VINSW 7 SW 8 PGND Power ground 9 ePAD Exposed pad connected to ground Power input voltage Regulator output switching pin DocID026968 Rev 4 AST1S31HF 2 Maximum ratings Maximum ratings Stressing the device above the rating listed in Table 2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute maximum ratings Symbol 2.1 Parameter Value Unit VIN Input voltage VEN Enable voltage VSW Output switching voltage VPG Power-on reset voltage (Power Good) -0.3 to VIN VFB Feedback voltage -0.3 to 1.5 PTOT Power dissipation at TA < 60 °C TOP Tstg -0.3 to 5 -0.3 to VIN V -1 to VIN 2.25 W Operating junction temperature range -40 to 150 °C Storage temperature range -55 to 150 °C Thermal data Table 3. Thermal data Symbol RthJA Parameter Value Unit 50 °C/W Test conditions Value Unit HBM 2 kV CDM corner pins 750 CDM non-corner pins 500 Maximum thermal resistance junction ambient(1) VFDFPN 1. Package mounted on demonstration board. 2.2 ESD performance Table 4. ESD performance Symbol ESD Parameter ESD protection voltage DocID026968 Rev 4 V 5/33 33 Electrical characteristics 3 AST1S31HF Electrical characteristics TJ = -40 °C to 125 °C, VIN = 4 V, unless otherwise specified. Table 5. Electrical characteristics Values Symbol Parameter Test condition Unit Min. VIN Typ. Max. Operating input voltage range 2.8 VINON Turn-on VCC threshold 2.3 2.45 2.6 VINOFF Turn-off VCC threshold 1.85 2.0 2.15 70 110 RDSON-P High-side switch on-resistance RDSON-N Low-side switch on- resistance ILIM ISW = 300 mA, TJ = 25 °C 4 ISW = 300 mA 140 ISW = 300 mA, TJ = 25 °C 55 ISW = 300 mA 90 110 Maximum limiting current 3.6 Switching frequency 1.75 0.79 V m m 6.0 A 2.3 2.5 MHz 0.8 0.81 V 630 1200 A 1 A Oscillator FSW Dynamic characteristics VFB Feedback voltage ILOAD = 0 A DC characteristics IQ IQST-BY Quiescent current Duty cycle = 0, no load VFB = 1.2 V Total standby quiescent current OFF Enable VEN EN threshold voltage IEN EN current Device ON level 1.5 Device OFF level 0.5 V 0.1 A 96 %VFB 400 mV Power Good PG threshold PG PG output voltage low 92 94 Isink = 6 mA open drain PG rise delay 170 s Soft-start duration 400 s Soft-start TSS Protection TSHDN Thermal shutdown (1) 150 Hystereris (1) 20 1. Guaranteed by design. 6/33 DocID026968 Rev 4 °C AST1S31HF 4 Datasheet parameters over the temperature range Datasheet parameters over the temperature range The 100% of the population in the production flow is tested at three different ambient temperatures (-40 °C, +25 °C, +125 °C) to guarantee the datasheet parameters inside the junction temperature range (-40 °C, +125 °C). The device operation is guaranteed when the junction temperature is inside the (-40 °C, +125 °C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the TSHDN (+150 °C typ.) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +125 °C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating. DocID026968 Rev 4 7/33 33 Functional description 5 AST1S31HF Functional description The AST1S31HF device is based on a “peak current mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are:  A fully integrated oscillator that provides the internal clock and the ramp for the slope compensation avoiding sub-harmonic instability  The soft-start circuitry to limit the inrush current during the start-up phase  The transconductance error amplifier  The pulse width modulator and the relative logic circuitry necessary to drive the internal power switches  The drivers for embedded P-channel and N-channel power MOSFET switches  The high-side current sensing block  The low-side current sense to implement diode emulation  The voltage monitor circuitry (UVLO) that checks the input and internal voltages  The thermal shutdown block, to prevent the thermal runaway. Figure 3. Block diagram 8/33 DocID026968 Rev 4 AST1S31HF 5.1 Functional description Output voltage adjustment The error amplifier reference voltage is 0.8 V typical. The output voltage is adjusted according to the following formula (see Figure 1 on page 1): Equation 1 R1 V OUT = 0.8   1 + -------  R 2 The internal architecture of the device requires a minimum off time, cycle by cycle, for the output voltage regulation. The minimum off time is typically equal to 66 ns. The control loop compensates for conversion losses with duty cycle control. Since the power losses are proportional to the delivered output power, the duty cycle increases with the load current request. Figure 4 shows at different loading conditions the maximum regulated output voltage over the input voltage range. Figure 4. Maximum output voltage over loading conditions DocID026968 Rev 4 9/33 33 Functional description 5.2 AST1S31HF Soft-start The soft-start is essential to assure the correct and safe start-up of the step-down converter. It avoids the inrush current surge and makes the output voltage rise monothonically. The soft-start is managed ramping the reference of the error amplifier from 0 V to 0.8 V. The internal soft-start capacitor is charged with a resistor to 0.8 V, then the FB pin follows the reference so that the output voltage is regulated to rise to the set value monothonically. 5.3 Error amplifier and control loop stability The error amplifier provides the error signal to be compared with the high-side switch current through the current sense circuitry. The non-inverting input is connected with the internal 0.8 V reference, whilst the inverting input is the FB pin. The compensation network is internal and connected between the E/A output and GND. The error amplifier of the AST1S31HF is a transconductance operational amplifier, with high bandwidth and high output impedance. Table 6. Characteristics of the uncompensated error amplifier Description Value DC gain 87 dB gm 236 A/V Ro 98 M The AST1S31HF device embeds the compensation network that assures the stability of the loop in the whole operating range. In Section 5.7 on page 17 all the tools needed to check the loop stability are shown. In Figure 5 is shown the simple small signal model for the peak current mode control loop. 10/33 DocID026968 Rev 4 AST1S31HF Functional description Figure 5. Block diagram of the loop for the small signal analysis VIN GCO(s) Slope Compensation High side Switch L Current sense Logic And Driver VOUT GDIV (s) Cout Low side Switch PWM comparator 0.8V R1 VC Rc VFB Error Amp R2 Cc G EA(s) Three main terms can be identified to obtain the loop transfer function: 1. From control (output of E/A) to output, GCO(s) 2. From output (Vout) to the FB pin, GDIV(s) 3. From the FB pin to control (output of E/A), GEA(s). The transfer function from control to output GCO(s) results: Equation 2 s  1 + ----   R LOAD 1 z G CO  s  = ------------------  ---------------------------------------------------------------------------------------------  ----------------------  F H  s  R out  T SW Ri s  ------ 1 + ----------------------------   m C   1 – D  – 0.5   1 +  L p where RLOAD represents the load resistance, Ri the equivalent sensing resistor of the current sense circuitry (0.38 ), p the single pole introduced by the LC filter and z the zero given by the ESR of the output capacitor. FH(s) accounts the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. Equation 3 1  Z = ------------------------------ESR  C OUT DocID026968 Rev 4 11/33 33 Functional description AST1S31HF Equation 4 m C   1 – D  – 0.5 1  p = -------------------------------------- + --------------------------------------------L  C OUT  f SW R LOAD  C OUT where: Equation 5 Se   m C = 1 + -----Sn  S = V  f pp SW  e  V IN – V OUT  S = -----------------------------  Ri  n L Sn represents the ON time slope of the sensed inductor current, Se the slope of the external ramp (VPP peak-to-peak amplitude - 0.55 V) that implements the slope compensation to avoid sub-harmonic oscillations at the duty cycle over 50%. The sampling effect contribution FH(s) is: Equation 6 1 F H  s  = -----------------------------------------2 s s 1 + ------------------- + ------2 n  QP  n where: Equation 7 1 Q P = ---------------------------------------------------------   m C   1 – D  – 0.5  and: Equation 8  n =   f SW The resistor to adjust the output voltage gives the term from output voltage to the FB pin. GDIV(s) is: Equation 9 R2 G DIV  s  = -------------------R1 + R2 The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. In Figure 6 the small signal model of the error amplifier with the internal compensation network is shown. 12/33 DocID026968 Rev 4 AST1S31HF Functional description Figure 6. Small signal model for the error amplifier V FB Ro Vd Co Gm*Vd Rc Cc Cp Cc VREF RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability and can be neglected. So GEA(s) results: Equation 10 G EA0   1 + s  R c  C c  G EA  s  = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s  R0   C0 + Cp   Rc  Cc + s   R0  Cc + R0   C0 + Cp  + Rc  Cc  + 1 Where GEA = Gm ꞏ Ro. The poles of this transfer function are (if Cc >> C0 + CP): Equation 11 1 f P LF = ---------------------------------2    R0  Cc Equation 12 1 f P HF = ---------------------------------------------------2    Rc   C0 + Cp  whereas the zero is defined as: Equation 13 1 f Z = --------------------------------2    Rc  Cc The embedded compensation network is RC = 80 k, CC = 55 pF while CP and CO can be considered as negligible. The error amplifier output resistance is 98 Mso the relevant singularities are: Equation 14 f Z = 36 2 kHz f P LF = 13 6 Hz DocID026968 Rev 4 13/33 33 Functional description AST1S31HF So closing the loop the loop gain GLOOP(s) is: Equation 15 G LOOP  s  = G CO  s   G DIV  s   G EA  s  Example: VIN = 3.3 V, VOUT = 1.2 V, Iomax = 3 A, L = 0.91 H, Cout = 22 F (MLCC), R1 = 100 k, R2 = 200 k(see Section 6.2 on page 19 and Section 6.3 on page 20 for inductor and output capacitor selection guidelines). The module and phase Bode plot are reported in Figure 7. The bandwidth is 230 kHz and the phase margin is 70 degrees. Figure 7. Module and phase Bode plot Module [dB] 120 102 84 66 48 30 12 6  24  42  60 0.1 1 10 110 100 3 4 110 4 110 110 5 110 6 110 7 5 110 6 110 Frequency [Hz] 10  17.5  45 Phase  72.5  100  127.5  155  182.5  210 0.1 1 10 3 110 100 Frequency [Hz] 14/33 DocID026968 Rev 4 110 7 AST1S31HF 5.4 Functional description Overcurrent protection The AST1S31 device implements overcurrent protection sensing the current flowing through the high-side current switch. If the current exceeds the overcurrent threshold the high-side is turned off, implementing cycle-by-cycle current limitation. Since the regulation loop is no more fixing the duty cycle, the output voltage is unregulated and the FB pin falls accordingly to the new duty cycle. The mechanism to adjust the switching under the current foldback condition exploits the low-side current sense circuitry. If FB is lower than 0.2 V, the high-side power MOSFET is turned off after the minimum conduction time (approximately 100 nsec typ.), then, after a proper deadtime that avoids the cross conduction, the low-side is turned on until the low-side current is lower than a valley threshold (1.5 A typ.). Once the low-side is turned off the high-side is immediately turned on. In this way the frequency is adjusted to keep the inductor current ripple between peak current value that could be evaluated with the following equation: Equation 16 V In + V Out –  DCR L + R DS  on HS   I Valley I Peak = I Valley + ----------------------------------------------------------------------------------------------------------------   T Onmin  L where DCRL is the series resistance of the inductor and the measured value of the valley current threshold (1.5 A typ.), so properly limiting the output current in case of the overcurrent or short-circuit . The overcurrent protection is always effective when VFB < 0.2 V thanks to the natural frequency reduction. No frequency foldback is otherwise implemented when VFB > 0.2 V. In this case, when the current ripple during the on phase is bigger than the one during the off phase, there will be a peak current level higher than the current limit threshold. The following equations show the inductor current ripple during the ON and OFF phases in case of overcurrent condition: On phase: Equation 17 V In – V Out –  DCR L + R DS  on HS   I I Ton = -------------------------------------------------------------------------------------------------   T Onmin  L Where: Equation 18 V OUTSet V Out = V FB  ---------------------0.8 DocID026968 Rev 4 15/33 33 Functional description AST1S31HF It’s also possible define the output voltage in function of input voltage, on phase time and switching frequency: Equation 19 T OnMin V OUTSet = V IN  D MIN = V IN  ------------------T SW So the on phase the equation results: Equation 20 V IN  T ONMin V IN – V FB  ----------------------------------- –  DCR L + R DS  ON HighSide   I 0.8  T SW I TON  V FB  = ----------------------------------------------------------------------------------------------------------------------------------------------------------  T ONMin L Off phase: Equation 21 –  R DS  ON LowSide + DCR L   I – V OUT I TOFF = -------------------------------------------------------------------------------------------------------  T SW L It is possible to repeat the considerations realized to the on phase equation. So it's possible to write the off phase equation in the following manner: Equation 22 V IN  T ONMin –  R DS  ON LowSide + DCR L   I – V FB  ----------------------------------0.8  T SW I TOFF  V FB  = --------------------------------------------------------------------------------------------------------------------------------------------  T SW L The peak current escalates over the peak current threshold (called “OCP1”) if : Equation 23 I TON  V FB   I TOFF  V FB  In case the current escalates up to a further current threshold (called “OCP2”), slightly higher than OCP1, the converter stops the switching activity, the reference of the error amplifier is pulled down and then it restarts with a new soft-start procedure. If the overcurrent condition is still active, the current foldback with frequency reduction properly limit the output current. 16/33 DocID026968 Rev 4 AST1S31HF Functional description Figure 8. Overcurrent protection region 5.5 Enable function The enable feature allows to put the device into the standby mode. With the EN pin lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 10 A. With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VIN compatible. 5.6 Light-load operation With the peak current mode control loop the output of the error amplifier is proportional to the load current. The AST1S31HF increases light-load efficiency, when the output of the error amplifier falls below a certain threshold, the high-side turn-on is prevented. This mechanism reduces the switching frequency at the light-load in order to save the switching losses. 5.7 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts into the normal operation. DocID026968 Rev 4 17/33 33 Application information AST1S31HF 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is a subject of a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 24 2 2 2D D I RMS = I O  D – --------------- + ------2  where IO is the maximum DC output current, D is the duty cycle, and is the efficiency. Considering = 1, this function has a maximum at D = 0.5 and is equal to IO/2. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 25 IO D D V PP = -------------------------   1 – ----  D + ----   1 – D  + ESR  I O C IN  F SW    where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of CIN as a function of the target peak-to-peak voltage ripple (VPP) can be written as follows: Equation 26 IO D D C IN = ---------------------------   1 – ----  D + ----   1 – D  V PP  F SW    neglecting the small ESR of ceramic capacitors. Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is: Equation 27 IO C IN_MIN = -----------------------------------------------2  V PP_MAX  F SW Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of VINMAX. 18/33 DocID026968 Rev 4 AST1S31HF Application information The placement of the input capacitor is very important to avoid noise injection and voltage spikes on the input voltage pin. So the CIN must be placed as close as possible to the VIN_SW pin. In Table 7 some multilayer ceramic capacitors suitable for this device are given. Table 7. Input MLCC capacitors Manufacturer Series Cap value (µF) Rated voltage (V) Murata GCM 47 6.3 TDK CGA6 47 6.3 TAIYO YUDEN LMK325 47 10 A ceramic bypass capacitor, as close as possible to the VINA pin so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 µF. 6.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. In the continuous current mode (CCM), the inductance value can be calculated by Equation 28: Equation 28 V IN – V OUT V OUT I L = ------------------------------  T ON = --------------  T OFF L L where TON is the conduction time of the high-side switch and TOFF is the conduction time of the low-side switch [in CCM, FSW = 1 / (TON + TOFF)]. The maximum current ripple, given the VOUT, is obtained at maximum TOFF, that is, at a minimum duty cycle (see previous section to calculate minimum duty). So by fixing IL = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: Equation 29 V OUT 1 – D MIN L MIN = ----------------  ----------------------I MAX F SWMIN where FSWMIN is the minimum switching frequency, according to Table 5 on page 6. The slope compensation, to prevent the sub-harmonic instability in the peak current control loop, is internally managed and so fixed. This implies a further lower limit for the inductor value. To assure sub-harmonic stability: Equation 30 L  V out   2  V pp  f sw  where VPP is the peak-to-peak value of the slope compensation ramp. The inductor value selected based on Equation 29 must satisfy Equation 30. DocID026968 Rev 4 19/33 33 Application information AST1S31HF The peak current through the inductor is given by Equation 31: Equation 31 I L I L PK = I O + -------2 So if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table 8 some inductor part numbers are listed. Table 8. Inductors 6.3 Manufacturer Series Inductor value (µH) Saturation current (A) COILTRONICS DRA73 0.6 to 2.2 5.5 to 7.9 COILCRAFT XAL40XX 0.6 to 2.2 5.4 to 8.35 Output capacitor selection The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 32 I MAX V OUT = ESR  I MAX + ------------------------------------8  C OUT  f SW For a ceramic (MLCC) capacitor, the capacitive component of the ripple dominates the resistive one. While for an electrolytic capacitor the opposite is true. As the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. The equations of Section 5.3 on page 10 help to check loop stability given the application conditions, the value of the inductor and of the output capacitor. In Table 9 some capacitor series are listed. Table 9. Output capacitors 20/33 Manufacturer Series Cap value (µF) Rated voltage (V) ESR (m) MURATA GCM 22 to 470 10 5 TDK CGA6 22 to 470 16 10 DocID026968 Rev 4 AST1S31HF 6.4 Application information Thermal dissipation The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) Conduction losses due to the on-resistance of the high-side switch (RHS) and lowside switch (RLS); these are equal to: Equation 33 2 2 P COND = R HS  I OUT  D + R LS  I OUT   1 – D  where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but it is actually slightly higher to compensate the losses of the regulator. b) Switching losses due to the high-side power MOSFET turn-on and turn-off; these can be calculated as: Equation 34  T RISE + T FALL  P SW = V IN  I OUT  -------------------------------------------  Fsw = V IN  I OUT  T SW  F SW 2 where TRISE and TFALL are the overlap times of the voltage across the high-side power switch (VDS) and the current flowing into it during the turn-on and turn-off phases, as shown in Figure 9. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 20 ns. c) Quiescent current losses, calculated as: Equation 35 P Q = V IN  I Q where IQ is the quiescent current (IQ = 1.2 mA maximum). The junction temperature TJ can be calculated as: Equation 36 T J = T A + Rth JA  P TOT where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured on the demonstration board (see Figure 12 on page 25) is about 50 °C/W. DocID026968 Rev 4 21/33 33 Application information AST1S31HF Figure 9. Switching losses VIN VSW ISW,HS VDS,HS PSW PCOND,HS PCOND,LS TFALL TRISE AM11422v1 6.5 Layout consideration The PC board layout of the switching DC-DC regulator is very important to minimize the noise injected in high impedance nodes, to reduce interference generated by the high switching current loops and to optimize the reliability of the device. In order to avoid EMC problems, the high switching current loops must be as short as possible. In the buck converter there are two high switching current loops: during the ontime, the pulsed current flows through the input capacitor, the high-side power switch, the inductor and the output capacitor; during the off-time through the low-side power switch, the inductor and the output capacitor. The input capacitor connected to VINSW must be placed as close as possible to the device, to avoid spikes on VINSW due to the stray inductance and the pulsed input current. In order to prevent the dynamic unbalance between VINSW and VINA, the trace connecting the VINA pin to the input must be derived from VINSW. The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference can be minimized by routing the feedback node with a very short trace and as far as possible from the high current paths. A single point connection from signal ground to power ground is suggested. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. 22/33 DocID026968 Rev 4 AST1S31HF Application information Figure 10. PCB layout example Via to connect the thermal pad To bottom or inner ground plane Star center for common ground Short high switching current loop Input cap as close as possible to VINSW pin Short FB trace VINA derived from Cin To avoid dynamic voltage drop Between VINA and VINSW AM11423v1 DocID026968 Rev 4 23/33 33 Demonstration board 7 AST1S31HF Demonstration board Figure 11. Demonstration board schematic VIN U1 2 3 PGND EN SW FB VIN_SW AGND PGOOD 8 L1 7 VOUT 0.91uH 6 5 C1 47uF C2 22uF 9 4 VIN_A ePAD 1 C3 1uF AST1S31HF R3 R1 10K 100K R2 200K Table 10. Component list 24/33 Reference Part number Description Manufacturer U1 AST1S31HF L1 DRA73 1R0 R 0.91 µH, Isat = 8.22 A Coiltronics C1 GCM32ER70J476ME16 47 µF 6.3 V X7R MURATA C2 GCM32ER71A226KE12 22 µF 10 V X7R MURATA STM C3 1 µF 25 V X7R C4 NC R1 100 k1% R2 200 k 1% R3 10 k 1% DocID026968 Rev 4 AST1S31HF Demonstration board Figure 12. Demonstration board PCB top and bottom, DFN package DocID026968 Rev 4 25/33 33 Typical characteristics 8 AST1S31HF Typical characteristics Figure 13. Efficiency curves: VIN = 4.0 V Figure 14. Efficiency curves: VIN = 4.0 V (log scale) 26/33 DocID026968 Rev 4 AST1S31HF Typical characteristics Figure 15. Load regulation (VIN = 4 V) Figure 16. Efficiency curves: VIN = 3.3 V DocID026968 Rev 4 27/33 33 Typical characteristics AST1S31HF Figure 17. Efficiency curves: VIN = 3.3 V (log scale) Figure 18. Load regulation (VIN = 3.3 V) 28/33 DocID026968 Rev 4 AST1S31HF 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID026968 Rev 4 29/33 33 Package information 9.1 AST1S31HF VFDFPN8 (3 x 3 x 1.0 mm) package information Figure 19. VFDFPN8 (3 x 3 x 1.0 mm) package outline Table 11. VFDFPN8 (3 x 3 x 1.0 mm) package mechanical data Dimensions (mm) Dimensions (inch) Symbol Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.0 0.05 0.0 b 0.25 0.35 0.0098 D D2 3.00 2.234 E E2 30/33 2.384 1.496 1.646 2.484 0.0878 0.40 0.0138 0.0937 0.0976 0.1181 1.746 0.0589 0.65 0.30 0.0118 0.1181 3.00 e L 0.30 0.0020 0.0648 0.0687 0.0256 0.50 DocID026968 Rev 4 0.0118 0.0157 0.0197 AST1S31HF 10 Order codes Order codes Table 12. Ordering information Order code Package AST1S31HF VFDFPN 3 x 3 8L DocID026968 Rev 4 31/33 33 Revision history 11 AST1S31HF Revision history Table 13. Document revision history 32/33 Date Revision Changes 30-Sep-2014 1 Initial release. 03-Mar-2016 2 Updated value in Table 3 on page 6 and Section 7.4 on page 22 (replaced 60 °C/W by 50 °C/W). Updated Section 6.1 on page 10 (added text and Figure 4). Added Section 9 on page 27. Minor modifications throughout document 03-Aug-2018 3 Updated Figure 1: Application circuit on the cover page. 31-Aug-2020 4 Added Section 2.2: ESD performance. DocID026968 Rev 4 AST1S31HF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DocID026968 Rev 4 33/33 33